STLUR Store-release register (unscaled) This instruction calculates an address from a base register value and an immediate offset, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release For information about addressing modes, see Load/Store addressing modes. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 1 x 0 1 1 0 0 1 0 0 0 0 0 0 STLUR <Wt>, [<Xn|SP>{, #<simm>}] 1 STLUR <Xt>, [<Xn|SP>{, #<simm>}] if !IsFeatureImplemented(FEAT_LRCPC2) then UNDEFINED; constant integer scale = UInt(size); constant bits(64) offset = SignExtend(imm9, 64); <Wt> Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <simm> Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field. <Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. constant integer n = UInt(Rn); constant integer t = UInt(Rt); constant integer datasize = 8 << scale; constant boolean tagchecked = n != 31; bits(64) address; constant AccessDescriptor accdesc = CreateAccDescAcqRel(MemOp_STORE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); Mem[address, datasize DIV 8, accdesc] = X[t, datasize];