STNP Store pair of registers, with non-temporal hint This instruction calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about addressing modes, see Load/Store addressing modes. For information about non-temporal pair instructions, see Load/Store non-temporal pair. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. x 0 1 0 1 0 0 0 0 0 0 STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] 1 STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] // Empty. <Wt1> Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. <Wt2> Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4. <imm> For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8. <Xt1> Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. <Xt2> Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. if opc<0> == '1' then UNDEFINED; constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean nontemporal = TRUE; constant integer scale = 2 + UInt(opc<1>); constant integer datasize = 8 << scale; constant bits(64) offset = LSL(SignExtend(imm7, 64), scale); constant boolean tagchecked = n != 31; bits(64) address; bits(64) address2; constant integer dbytes = datasize DIV 8; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, nontemporal, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); address2 = AddressIncrement(address, dbytes, accdesc); Mem[address , dbytes, accdesc] = X[t, datasize]; Mem[address2, dbytes, accdesc] = X[t2, datasize];