STSET, STSETL Atomic bit set on word or doubleword in memory, without return This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. STSET does not have release semantics. STSETL stores to memory with release semantics, as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. LDSET, LDSETA, LDSETAL, LDSETL 1 x 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 0 STSET <Ws>, [<Xn|SP>] LDSET <Ws>, WZR, [<Xn|SP>] Unconditionally 0 1 STSETL <Ws>, [<Xn|SP>] LDSETL <Ws>, WZR, [<Xn|SP>] Unconditionally 1 0 STSET <Xs>, [<Xn|SP>] LDSET <Xs>, XZR, [<Xn|SP>] Unconditionally 1 1 STSETL <Xs>, [<Xn|SP>] LDSETL <Xs>, XZR, [<Xn|SP>] Unconditionally <Ws> Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xs> Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.