STZGM Store Allocation Tag and zero multiple This instruction writes a naturally aligned block of N Allocation Tags and stores zero to the associated data locations, where the size of N is identified in DCZID_EL0.BS, and the Allocation Tag is taken from the source register bits<3:0>. This instruction is UNDEFINED at EL0. This instruction generates an Unchecked access. 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 STZGM <Xt>, [<Xn|SP>] if !IsFeatureImplemented(FEAT_MTE2) then UNDEFINED; constant integer t = UInt(Xt); constant integer n = UInt(Xn); <Xt> Is the 64-bit name of the general-purpose source register, encoded in the "Xt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field. if PSTATE.EL == EL0 then UNDEFINED; constant bits(64) data = X[t, 64]; constant bits(4) tag = data<3:0>; bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; constant integer size = 4 * (2 ^ (UInt(DCZID_EL0.BS))); address = Align(address, size); constant integer count = size >> LOG2_TAG_GRANULE; constant boolean devstoreunpred = TRUE; constant AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_STORE, devstoreunpred); for i = 0 to count-1 AArch64.MemTag[address, accdesc] = tag; Mem[address, TAG_GRANULE, accdesc] = Zeros(8*TAG_GRANULE); address = AddressIncrement(address, TAG_GRANULE, accdesc);