SUB (array results, multiple vectors)
Subtract multi-vector from multi-vector with ZA array vector results
Subtract all corresponding elements of the two or four second source vectors from first source vectors and place the results in the corresponding elements of the ZA single-vector groups.
The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.
Green
False
True
SM_1_only
It has encodings from 2 classes:
Two ZA single-vectors
and
Four ZA single-vectors
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SUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED;
constant integer v = UInt('010':Rv);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn:'0');
constant integer m = UInt(Zm:'0');
constant integer offset = UInt(off3);
constant integer nreg = 2;
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SUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED;
constant integer v = UInt('010':Rv);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn:'00');
constant integer m = UInt(Zm:'00');
constant integer offset = UInt(off3);
constant integer nreg = 4;
<T>
Is the size specifier,
<Wv>
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.
<offs>
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.
<Zn1>
For the two ZA single-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
<Zn1>
For the four ZA single-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.
<Zn4>
Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.
<Zn2>
Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.
<Zm1>
For the two ZA single-vectors variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.
<Zm1>
For the four ZA single-vectors variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.
<Zm4>
Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.
<Zm2>
Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.
CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant integer vectors = VL DIV 8;
constant integer vstride = vectors DIV nreg;
constant bits(32) vbase = X[v, 32];
integer vec = (UInt(vbase) + offset) MOD vstride;
bits(VL) result;
for r = 0 to nreg-1
constant bits(VL) operand1 = Z[n+r, VL];
constant bits(VL) operand2 = Z[m+r, VL];
for e = 0 to elements-1
constant bits(esize) element1 = Elem[operand1, e, esize];
constant bits(esize) element2 = Elem[operand2, e, esize];
Elem[result, e, esize] = element1 - element2;
ZAvector[vec, VL] = result;
vec = vec + vstride;