SUBHN, SUBHN2 Subtract returning high narrow This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see RSUBHN. The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half. The SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 0 0 1 1 1 0 1 0 1 1 0 0 0 SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta> if size == '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer esize = 8 << UInt(size); constant integer datasize = 64; constant integer part = UInt(Q); constant integer elements = datasize DIV esize; constant boolean round = FALSE; 2 Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is Q 2 0 [absent] 1 [present] <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Tb> Is an arrangement specifier, size Q <Tb> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 x RESERVED <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Ta> Is an arrangement specifier, size <Ta> 00 8H 01 4S 10 2D 11 RESERVED <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPAdvSIMDEnabled64(); constant bits(2*datasize) operand1 = V[n, 2*datasize]; constant bits(2*datasize) operand2 = V[m, 2*datasize]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = UInt(Elem[operand1, e, 2*esize]); element2 = UInt(Elem[operand2, e, 2*esize]); sum = element1 - element2; sum = RShr(sum, esize, round); Elem[result, e, esize] = sum<esize-1:0>; Vpart[d, part, datasize] = result;