SUNPK Unpack and sign-extend multi-vector elements Unpack elements from one or two source vectors and then sign-extend them to place in elements of twice their size within the two or four destination vectors. This instruction is unpredicated. Green False True SM_1_only It has encodings from 2 classes: Two registers and Four registers 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 SUNPK { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<Tb> if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer d = UInt(Zd:'0'); constant integer nreg = 2; constant boolean unsigned = FALSE; 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 SUNPK { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<Tb>-<Zn2>.<Tb> } if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd:'00'); constant integer nreg = 4; constant boolean unsigned = FALSE; <Zd1> For the two registers variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. <Zd1> For the four registers variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4. <T> Is the size specifier, size <T> 00 RESERVED 01 H 10 S 11 D <Zd4> Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. <Zn1> Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. <Zd2> Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. <Tb> Is the size specifier, size <Tb> 00 RESERVED 01 B 10 H 11 S <Zn2> Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer hsize = esize DIV 2; constant integer sreg = nreg DIV 2; array [0..3] of bits(VL) results; for r = 0 to sreg-1 constant bits(VL) operand = Z[n+r, VL]; for i = 0 to 1 for e = 0 to elements-1 constant bits(hsize) element = Elem[operand, i*elements + e, hsize]; Elem[results[2*r+i], e, esize] = Extend(element, esize, unsigned); for r = 0 to nreg-1 Z[d+r, VL] = results[r];