SUQADD Signed saturating accumulate of unsigned value This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. It has encodings from 2 classes: Scalar and Vector 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 SUQADD <V><d>, <V><n> constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = esize; constant integer elements = 1; constant boolean unsigned = FALSE; 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 SUQADD <Vd>.<T>, <Vn>.<T> if size:Q == '110' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; constant boolean unsigned = FALSE; <V> Is a width specifier, size <V> 00 B 01 H 10 S 11 D <d> Is the number of the SIMD&FP destination register, encoded in the "Rd" field. <n> Is the number of the SIMD&FP source register, encoded in the "Rn" field. <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 0 RESERVED 11 1 2D <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; bits(datasize) result; constant bits(datasize) operand2 = V[d, datasize]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = UInt(Elem[operand, e, esize]); op2 = SInt(Elem[operand2, e, esize]); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d, datasize] = result;