SUQADD Signed saturating addition of unsigned value Add active unsigned elements of the source vector to the corresponding signed elements of the addend vector, and destructively place the results in the corresponding elements of the addend vector. Each result element is saturated to the N-bit element's signed integer range -2^(N-1) to (2^(N-1) )-1. Inactive elements in the destination vector register remain unmodified. Green True True True 0 1 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 SUQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant integer m = UInt(Zm); <Zdn> Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 constant bits(esize) element1 = Elem[operand1, e, esize]; constant bits(esize) element2 = Elem[operand2, e, esize]; if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = SignedSat(SInt(element1) + UInt(element2), esize); else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn, VL] = result;