TRN1, TRN2 (vectors) Interleave even or odd elements from two vectors Interleave alternating even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated. The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled. Green False True SM_0_only It has encodings from 4 classes: Even , Even (quadwords) , Odd and Odd (quadwords) 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0 TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 0; 0 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 TRN1 <Zd>.Q, <Zn>.Q, <Zm>.Q if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_F64MM) then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 0; 0 0 0 0 0 1 0 1 1 0 1 1 1 0 1 TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 1; 0 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 TRN2 <Zd>.Q, <Zn>.Q, <Zm>.Q if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_F64MM) then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 1; <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 2 then UNDEFINED; constant integer pairs = VL DIV (esize * 2); constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result = Zeros(VL); for p = 0 to pairs-1 Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize]; Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize]; Z[d, VL] = result;