TST (shifted register) Test (shifted register) This instruction performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. ANDS (shifted register) 1 1 0 1 0 1 0 0 1 1 1 1 1 0 TST <Wn>, <Wm>{, <shift> #<amount>} ANDS WZR, <Wn>, <Wm>{, <shift> #<amount>} Unconditionally 1 TST <Xn>, <Xm>{, <shift> #<amount>} ANDS XZR, <Xn>, <Xm>{, <shift> #<amount>} Unconditionally <Wn> Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. <Wm> Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field. <shift> Is the optional shift to be applied to the final source, defaulting to LSL and shift <shift> 00 LSL 01 LSR 10 ASR 11 ROR <amount> For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field. <amount> For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field, <Xn> Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. <Xm> Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.