UADDLP Unsigned add long pairwise This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 UADDLP <Vd>.<Ta>, <Vn>.<Tb> if size == '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV (2 * esize); <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Ta> Is an arrangement specifier, size Q <Ta> 00 0 4H 00 1 8H 01 0 2S 01 1 4S 10 0 1D 10 1 2D 11 x RESERVED <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <Tb> Is an arrangement specifier, size Q <Tb> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 x RESERVED CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; bits(datasize) result; bits(2*esize) sum; integer op1; integer op2; for e = 0 to elements-1 op1 = UInt(Elem[operand, 2*e+0, esize]); op2 = UInt(Elem[operand, 2*e+1, esize]); sum = (op1+op2)<2*esize-1:0>; Elem[result, e, 2*esize] = sum; V[d, datasize] = result;