UDOT (4-way, vectors)
Unsigned integer dot product
The unsigned integer dot product instruction computes the dot product of a group of four unsigned 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four unsigned 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector.
This instruction is unpredicated.
Green
False
True
True
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
if size IN {'0x'} then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer da = UInt(Zda);
<Zda>
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
<T>
Is the size specifier,
<Zn>
Is the name of the first source scalable vector register, encoded in the "Zn" field.
<Tb>
Is the size specifier,
<Zm>
Is the name of the second source scalable vector register, encoded in the "Zm" field.
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(VL) operand1 = Z[n, VL];
constant bits(VL) operand2 = Z[m, VL];
constant bits(VL) operand3 = Z[da, VL];
bits(VL) result;
for e = 0 to elements-1
bits(esize) res = Elem[operand3, e, esize];
for i = 0 to 3
constant integer element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]);
constant integer element2 = UInt(Elem[operand2, 4 * e + i, esize DIV 4]);
res = res + element1 * element2;
Elem[result, e, esize] = res;
Z[da, VL] = result;