UDOT (4-way, multiple and single vector)
Multi-vector unsigned integer dot-product by vector
The unsigned integer dot product instruction computes the dot product of four unsigned 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the two or four first source vectors and four unsigned 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the second source vector. The widened dot product result is destructively added to the corresponding 32-bit or 64-bit element of the ZA single-vector groups.
The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.
Green
False
True
SM_1_only
It has encodings from 2 classes:
Two ZA single-vectors
and
Four ZA single-vectors
1
1
0
0
0
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0
1
0
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UDOT ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED;
constant integer v = UInt('010':Rv);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn);
constant integer m = UInt('0':Zm);
constant integer offset = UInt(off3);
constant integer nreg = 2;
1
1
0
0
0
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UDOT ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED;
constant integer v = UInt('010':Rv);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn);
constant integer m = UInt('0':Zm);
constant integer offset = UInt(off3);
constant integer nreg = 4;
<T>
Is the size specifier,
<Wv>
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.
<offs>
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.
<Zn1>
Is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn".
<Tb>
Is the size specifier,
<Zn4>
Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" plus 3 modulo 32.
<Zn2>
Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" plus 1 modulo 32.
<Zm>
Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant integer vectors = VL DIV 8;
constant integer vstride = vectors DIV nreg;
constant bits(32) vbase = X[v, 32];
integer vec = (UInt(vbase) + offset) MOD vstride;
bits(VL) result;
for r = 0 to nreg-1
constant bits(VL) operand1 = Z[(n+r) MOD 32, VL];
constant bits(VL) operand2 = Z[m, VL];
constant bits(VL) operand3 = ZAvector[vec, VL];
for e = 0 to elements-1
bits(esize) sum = Elem[operand3, e, esize];
for i = 0 to 3
constant integer element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]);
constant integer element2 = UInt(Elem[operand2, 4 * e + i, esize DIV 4]);
sum = sum + element1 * element2;
Elem[result, e, esize] = sum;
ZAvector[vec, VL] = result;
vec = vec + vstride;