UMOV Unsigned move vector element to general-purpose register This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. This instruction is used by the alias MOV (to general) imm5 IN {'xx100'} imm5 IN {'x1000'} See below for details of when the alias is preferred. 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 UMOV <Wd>, <Vn>.<Ts>[<index>] 1 1 0 0 0 UMOV <Xd>, <Vn>.D[<index>] if imm5 IN 'x0000' then UNDEFINED; constant integer size = LowestSetBitNZ(imm5<3:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << size; constant integer datasize = 32 << UInt(Q); if datasize == 64 && esize < 64 then UNDEFINED; if datasize == 32 && esize >= 64 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>); <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <Ts> Is an element size specifier, imm5 <Ts> xx000 RESERVED xxxx1 B xxx10 H xx100 S <index> For the 32-bit variant: is the element index imm5 <index> xx000 RESERVED xxxx1 UInt(imm5<4:1>) xxx10 UInt(imm5<4:2>) xx100 UInt(imm5<4:3>) <index> For the 64-bit variant: is the element index encoded in "imm5<4>". <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. Alias Conditions if index == 0 then CheckFPEnabled64(); else CheckFPAdvSIMDEnabled64(); constant bits(idxdsize) operand = V[n, idxdsize]; X[d, datasize] = ZeroExtend(Elem[operand, index, esize], datasize);