UMULH (predicated) Unsigned multiply returning high half (predicated) Widening multiply unsigned integer values in active elements of the first source vector by corresponding elements of the second source vector and destructively place the high half of the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. Green True True True True 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 UMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant integer m = UInt(Zm); constant boolean unsigned = TRUE; <Zdn> Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 constant integer element1 = Int(Elem[operand1, e, esize], unsigned); constant integer element2 = Int(Elem[operand2, e, esize], unsigned); if ActivePredicateElement(mask, e, esize) then constant integer product = (element1 * element2) >> esize; Elem[result, e, esize] = product<esize-1:0>; else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn, VL] = result;