UQINCP (vector) Unsigned saturating increment vector by count of true predicate elements Counts the number of true elements in the source predicate and then uses the result to increment all destination vector elements. The results are saturated to the element unsigned integer range. The predicate size specifier may be omitted in assembler source code, but this is deprecated and will be prohibited in a future release of the architecture. Green False True 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 UQINCP <Zdn>.<T>, <Pm>.<T> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer m = UInt(Pm); constant integer dn = UInt(Zdn); constant boolean unsigned = TRUE; <Zdn> Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, size <T> 00 RESERVED 01 H 10 S 11 D <Pm> Is the name of the source scalable predicate register, encoded in the "Pm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[dn, VL]; constant bits(PL) operand2 = P[m, PL]; bits(VL) result; integer count = 0; for e = 0 to elements-1 if ActivePredicateElement(operand2, e, esize) then count = count + 1; for e = 0 to elements-1 constant integer element = Int(Elem[operand1, e, esize], unsigned); (Elem[result, e, esize], -) = SatQ(element + count, esize, unsigned); Z[dn, VL] = result;