UQRSHL
Unsigned saturating rounding shift left by vector (predicated)
Shift active unsigned elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
Green
True
True
True
0
1
0
0
0
1
0
0
0
0
1
0
1
1
1
0
0
UQRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer g = UInt(Pg);
constant integer m = UInt(Zm);
constant integer dn = UInt(Zdn);
<Zdn>
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
<T>
Is the size specifier,
size
<T>
00
B
01
H
10
S
11
D
<Pg>
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Zm>
Is the name of the second source scalable vector register, encoded in the "Zm" field.
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(PL) mask = P[g, PL];
constant bits(VL) operand1 = Z[dn, VL];
constant bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
constant integer element = UInt(Elem[operand1, e, esize]);
integer shift = ShiftSat(SInt(Elem[operand2, e, esize]), esize);
integer res;
if shift >= 0 then
res = element << shift;
else
shift = -shift;
res = (element + (1 << (shift - 1))) >> shift;
Elem[result, e, esize] = UnsignedSat(res, esize);
else
Elem[result, e, esize] = Elem[operand1, e, esize];
Z[dn, VL] = result;