URSHR Unsigned rounding shift right by immediate Shift right by immediate each active unsigned element of the source vector, and destructively place the rounded results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified. Green True True True 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 URSHR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant bits(4) tsize = tszh:tszl; if tsize == '0000' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant integer shift = (2 * esize) - UInt(tsize:imm3); <Zdn> Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, tszh tszl <T> 00 00 RESERVED 00 01 B 00 1x H 01 xx S 1x xx D <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <const> Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[dn, VL]; constant bits(PL) mask = P[g, PL]; bits(VL) result; for e = 0 to elements-1 constant integer element1 = UInt(Elem[operand1, e, esize]); if ActivePredicateElement(mask, e, esize) then constant integer res = (element1 + (1 << (shift - 1))) >> shift; Elem[result, e, esize] = res<esize-1:0>; else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn, VL] = result;