USHL Unsigned shift left (register) This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. It has encodings from 2 classes: Scalar and Vector 0 1 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 USHL D<d>, D<n>, D<m> if S == '0' && size != '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant boolean rounding = FALSE; constant integer esize = 8 << UInt(size); constant integer datasize = esize; constant integer elements = 1; 0 1 0 1 1 1 0 1 0 1 0 0 0 1 USHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> if size:Q == '110' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant boolean rounding = FALSE; constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; <d> Is the number of the SIMD&FP destination register, in the "Rd" field. <n> Is the number of the first SIMD&FP source register, encoded in the "Rn" field. <m> Is the number of the second SIMD&FP source register, encoded in the "Rm" field. <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 0 RESERVED 11 1 2D <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand1 = V[n, datasize]; constant bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; for e = 0 to elements-1 integer element = UInt(Elem[operand1, e, esize]); integer shift = SInt(Elem[operand2, e, esize]<7:0>); if shift >= 0 then // left shift element = element << shift; else // right shift shift = -shift; element = RShr(element, shift, rounding); Elem[result, e, esize] = element<esize-1:0>; V[d, datasize] = result;