USMLALL (multiple and single vector) Multi-vector unsigned by signed integer multiply-add long-long by vector This unsigned by signed integer multiply-add long-long instruction multiplies each unsigned 8-bit element in the one, two, or four first source vectors with each signed 8-bit element in the second source vector, widens each product to 32-bits and destructively adds these values to the corresponding 32-bit elements of the ZA quad-vector groups. The quad-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors. The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code. This instruction is unpredicated. Green False True SM_1_only It has encodings from 3 classes: One ZA quad-vector , Two ZA quad-vectors and Four ZA quad-vectors 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 USMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 32; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn); constant integer m = UInt('0':Zm); constant integer offset = UInt(off2:'00'); constant integer nreg = 1; 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 32; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer nreg = 2; 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 32; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer nreg = 4; <Wv> Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. <offs1> For the one ZA quad-vector variant: is the first vector select offset, encoded as "off2" field times 4. <offs1> For the four ZA quad-vectors and two ZA quad-vectors variant: is the first vector select offset, encoded as "o1" field times 4. <offs4> For the one ZA quad-vector variant: is the fourth vector select offset, encoded as "off2" field times 4 plus 3. <offs4> For the four ZA quad-vectors and two ZA quad-vectors variant: is the fourth vector select offset, encoded as "o1" field times 4 plus 3. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zn1> Is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn". <Zn4> Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" plus 3 modulo 32. <Zn2> Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" plus 1 modulo 32. <Zm> Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer vectors = VL DIV 8; constant integer vstride = vectors DIV nreg; constant bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; vec = vec - (vec MOD 4); for r = 0 to nreg-1 constant bits(VL) operand1 = Z[(n+r) MOD 32, VL]; constant bits(VL) operand2 = Z[m, VL]; for i = 0 to 3 constant bits(VL) operand3 = ZAvector[vec + i, VL]; for e = 0 to elements-1 constant integer element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]); constant integer element2 = SInt(Elem[operand2, 4 * e + i, esize DIV 4]); constant bits(esize) product = (element1 * element2)<esize-1:0>; Elem[result, e, esize] = Elem[operand3, e, esize] + product; ZAvector[vec + i, VL] = result; vec = vec + vstride;