USMMLA (vector)
Unsigned and signed 8-bit integer matrix multiply-accumulate (vector)
This instruction multiplies the
2x8 matrix of unsigned 8-bit integer values in the first source vector by the
8x2 matrix of signed 8-bit integer values in the second source vector. The
resulting 2x2 32-bit integer matrix product is destructively added to
the 32-bit integer matrix accumulator in the destination vector. This
is equivalent to performing an 8-way dot product per destination element.
From Armv8.2 to Armv8.5, this is an OPTIONAL instruction.
From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it.
ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
Arm expects that the USMMLA (vector) instruction will deliver a peak integer multiply throughput that is at
least as high as can be achieved using two USDOT (vector) instructions, with a goal that it should
have significantly higher throughput.
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USMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B
if !IsFeatureImplemented(FEAT_I8MM) then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant boolean op1_unsigned = TRUE;
constant boolean op2_unsigned = FALSE;
<Vd>
Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
CheckFPAdvSIMDEnabled64();
constant bits(128) operand1 = V[n, 128];
constant bits(128) operand2 = V[m, 128];
constant bits(128) addend = V[d, 128];
V[d, 128] = MatMulAdd(addend, operand1, operand2, op1_unsigned, op2_unsigned);