USMOPA
Unsigned by signed integer sum of outer products and accumulate
The 8-bit integer variant works with a 32-bit element ZA tile.
The 16-bit integer variant works with a 64-bit element ZA tile.
The unsigned by signed integer sum of outer products and accumulate instructions multiply the sub-matrix in the first source vector by the sub-matrix in the second source vector. In case of the 8-bit integer variant, the first source holds SVLS×4 sub-matrix of unsigned 8-bit integer values, and the second source holds 4×SVLS sub-matrix of signed 8-bit integer values. In case of the 16-bit integer variant, the first source holds SVLD×4 sub-matrix of unsigned 16-bit integer values, and the second source holds 4×SVLD sub-matrix of signed 16-bit integer values.
Each source vector is independently predicated by a corresponding governing predicate. When an 8-bit source element in case of 8-bit integer variant or a 16-bit source element in case of 16-bit integer variant is Inactive, it is treated as having the value 0.
The resulting SVLS×SVLS widened 32-bit integer or SVLD×SVLD widened 64-bit integer sum of outer products is then destructively added to the 32-bit integer or 64-bit integer destination tile, respectively for 8-bit integer and 16-bit integer instruction variants. This is equivalent to performing a 4-way dot product and accumulate to each of the destination tile elements.
In case of the 8-bit integer variant, each 32-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLS×4 sub-matrix, and each 32-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLS sub-matrix. In case of the 16-bit integer variant, each 64-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLD×4 sub-matrix, and each 64-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLD sub-matrix.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.
Green
True
True
SM_1_only
True
It has encodings from 2 classes:
32-bit
and
64-bit
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0
1
0
0
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0
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1
0
0
0
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0
USMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
if !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
constant integer esize = 32;
constant integer a = UInt(Pn);
constant integer b = UInt(Pm);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer da = UInt(ZAda);
constant boolean op1_unsigned = TRUE;
constant boolean op2_unsigned = FALSE;
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0
1
0
0
0
0
1
1
1
0
0
0
USMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
if !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED;
constant integer esize = 64;
constant integer a = UInt(Pn);
constant integer b = UInt(Pm);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer da = UInt(ZAda);
constant boolean op1_unsigned = TRUE;
constant boolean op2_unsigned = FALSE;
<ZAda>
For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.
<ZAda>
For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.
<Pn>
Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.
<Pm>
Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.
<Zn>
Is the name of the first source scalable vector register, encoded in the "Zn" field.
<Zm>
Is the name of the second source scalable vector register, encoded in the "Zm" field.
CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer dim = VL DIV esize;
constant bits(PL) mask1 = P[a, PL];
constant bits(PL) mask2 = P[b, PL];
constant bits(VL) operand1 = Z[n, VL];
constant bits(VL) operand2 = Z[m, VL];
constant bits(dim*dim*esize) operand3 = ZAtile[da, esize, dim*dim*esize];
bits(dim*dim*esize) result;
integer prod;
for row = 0 to dim-1
for col = 0 to dim-1
bits(esize) sum = Elem[operand3, row*dim+col, esize];
for k = 0 to 3
if (ActivePredicateElement(mask1, 4*row + k, esize DIV 4) &&
ActivePredicateElement(mask2, 4*col + k, esize DIV 4)) then
prod = (Int(Elem[operand1, 4*row + k, esize DIV 4], op1_unsigned) *
Int(Elem[operand2, 4*col + k, esize DIV 4], op2_unsigned));
sum = sum + prod;
Elem[result, row*dim+col, esize] = sum;
ZAtile[da, esize, dim*dim*esize] = result;