UZP1 Unzip vectors (primary) This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register. This instruction can be used with UZP2 to de-interleave two vectors. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 0 0 1 1 1 0 0 0 0 0 1 1 0 UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> if size:Q == '110' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; constant integer part = UInt(op); <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 0 RESERVED 11 1 2D <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operandl = V[n, datasize]; constant bits(datasize) operandh = V[m, datasize]; bits(datasize) result; constant bits(datasize*2) zipped = operandh:operandl; for e = 0 to elements-1 Elem[result, e, esize] = Elem[zipped, 2*e+part, esize]; V[d, datasize] = result;