UZP (two registers) Concatenate elements from two vectors Concatenate every second element from each of the first and second source vectors and place them in the corresponding elements of the two destination vectors. This instruction is unpredicated. Green False True SM_1_only It has encodings from 2 classes: 8-bit to 64-bit elements and 128-bit element 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 UZP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd:'0'); 1 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 UZP { <Zd1>.Q-<Zd2>.Q }, <Zn>.Q, <Zm>.Q if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if MaxImplementedSVL() < 256 then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd:'0'); <Zd1> Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <Zd2> Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 2 then UNDEFINED; constant integer pairs = VL DIV (esize * 2); bits(VL) result0; bits(VL) result1; for r = 0 to 1 constant integer base = r * pairs; constant bits(VL) operand = if r == 0 then Z[n, VL] else Z[m, VL]; for p = 0 to pairs-1 Elem[result0, base+p, esize] = Elem[operand, 2*p+0, esize]; Elem[result1, base+p, esize] = Elem[operand, 2*p+1, esize]; Z[d+0, VL] = result0; Z[d+1, VL] = result1;