swAStore 32-bit, values from the low bits of register rs2 to memory.sw rs2,offset(rs1) amoswap.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, swap the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amoswap.w rd,rs2,(rs1)fmin.d@Write the smaller of single precision data in rs1 and rs2 to rd.fmin.d rd,rs1,rs2 fcvt.wu.dConverts a double-precision floating-point number in floating-point register rs1 to a unsigned 32-bit integer, in integer register rd.fcvt.wu.d rd,rs1orGPerforms bitwise OR on registers rs1 and rs2 and place the result in rdor rd,rs1,rs2fsgnj.dnProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is rs2’s sign bit.fsgnj.d rd,rs1,rs2addiadd immediate Adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudo-instruction.addi rd,rs1,imm amomaxu.watomically load a 32-bit unsigned data value from the address in rs1, place the value into register rd, apply unsigned max the loaded value and the original 32-bit unsigned value in rs2, then store the result back to the address in rs1.amomaxu.w rd,rs2,(rs1)c.sdStore a 64-bit value in register rs2\' to memory.It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1\'.c.sd rd\',uimm(rs1\')c.lwLoad a 32-bit value from memory into register rd\'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'.c.lw rd\',uimm(rs1\')uretKReturn from traps in U-mode, and URET copies UPIE into UIE, then sets UPIE.uretc.flwspLoad a single-precision floating-point value from memory into floating-point register rd.It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.c.flwsp rd,uimm(x2)lwucLoads a 32-bit value from memory and zero-extends this to 64 bits before storing it in register rd.lwu rd,offset(rs1)amomax.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply max the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amomax.d rd,rs2,(rs1)csrrsatomic read and set bits in CSR. Reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR.Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.Other bits in the CSR are unaffected (though CSRs might have side effects when written).csrrs rd,offset,rs1fcvt.l.dfcvt.l.d rd,rs1amoxor.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply xor the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amoxor.d rd,rs2,(rs1)fmadd.s1Perform single-precision fused multiply addition.fmadd.s rd,rs1,rs2,rs3fle.dPerforms a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN.fle.d rd,rs1,rs2 amomaxu.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply unsigned max the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amomaxu.d rd,rs2,(rs1)srlmLogical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2srl rd,rs1,rs2amoor.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply or the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amoor.w rd,rs2,(rs1)c.subnSubtract the value in register rs2\' from the value in register rd\', then writes the result to register rd\'.c.sub rd\',rs2\'csrrciClear CSR bit using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field.csrrci rd,offset,uimmfswJStore a single-precision value from floating-point register rs2 to memory.fsw rs2,offset(rs1)feq.dPerforms a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN.feq.d rd,rs1,rs2fmv.w.xMove the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd.fmv.w.x rd,rs1feq.sPerforms a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN.feq.s rd,rs1,rs2sltiset less than immediate Place the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd.slti rd,rs1,immcsrrwsatomic read/write CSR. Atomically swaps values in the CSRs and integer registers.CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd.The initial value in rs1 is written to the CSR.If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.csrrw rd,offset,rs1lbdLoads a 8-bit value from memory and sign-extends this to XLEN bits before storing it in register rd.lb rd,offset(rs1)bne7Take the branch if registers rs1 and rs2 are not equal.bne rs1,rs2,offsetbgeu\Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison.bgeu rs1,rs2,offsetfmax.s?Write the larger of single precision data in rs1 and rs2 to rd.fmax.s rd,rs1,rs2fsgnjx.d|Produce a result that takes all bits except the sign bit from rs1.The result’s sign bit is XOR of sign bit of rs1 and rs2.fsgnjx.d rd,rs1,rs2addiwcAdds the sign-extended 12-bit immediate to register rs1 and produces the proper sign-extension of a 32-bit result in rd.Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits.Note, ADDIW rd, rs1, 0 writes the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).addiw rd,rs1,immlr.w}load a word from the address in rs1, places the sign-extended value in rd, and registers a reservation on the memory address.lr.w rd,rs1 fcvt.s.wuwConverts a 32-bit unsigned integer, in integer register rs1 into a floating-point number in floating-point register rd.fcvt.s.wu rd,rs1c.swStore a 32-bit value in register rs2\' to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'.c.sw rd\',uimm(rs1\')c.slliPerform a logical left shift of the value in register rd then writes the result to rd.The shift amount is encoded in the shamt field, where shamt[5] must be zero for RV32C.c.slli rd,uimmfmin.s@Write the smaller of single precision data in rs1 and rs2 to rd.fmin.s rd,rs1,rs2fclass.ssExamines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.The format of the mask is described in [classify table]_.The corresponding bit in rd will be set if the property is true and clear otherwise.All other bits in rd are cleared. Note that exactly one bit in rd will be set.fclass.s rd,rs1lhueLoads a 16-bit value from memory and zero-extends this to XLEN bits before storing it in register rd.lhu rd,offset(rs1)jal/Jump to address and place return address in rd.jal rd,offsetbltKTake the branch if registers rs1 is less than rs2, using signed comparison.blt rs1,rs2,offsetremuJperform an XLEN bits by XLEN bits unsigned integer reminder of rs1 by rs2.remu rd,rs1,rs2lweLoads a 32-bit value from memory and sign-extends this to XLEN bits before storing it in register rd.lw rd,offset(rs1)bltuMTake the branch if registers rs1 is less than rs2, using unsigned comparison.bltu rs1,rs2,offsetc.addLAdd the values in registers rd and rs2 and writes the result to register rd.c.add rd,rs2c.lwspLoad a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.c.lwsp rd,uimm(x2)sraiPerforms arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediateIn RV64, bit-25 is used to shamt[5].srai rd,rs1,shamtslliwPerforms logical left shift on the 32-bit of value in register rs1 by the shift amount held in the lower 5 bits of the immediate.Encodings with $imm[5] \neq 0$ are reserved.slliw rd,rs1,shamtc.jalr/Jump to address and place return address in rd. c.jalr rdamoand.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply and the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amoand.w rd,rs2,(rs1)amoand.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply and the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amoand.d rd,rs2,(rs1)c.fldspLoad a double-precision floating-point value from memory into floating-point register rd.It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2.c.fldsp rd,uimm(x2) fcvt.lu.dfcvt.lu.d rd,rs1sb@Store 8-bit, values from the low bits of register rs2 to memory.sb rs2,offset(rs1)divuaperform an XLEN bits by XLEN bits unsigned integer division of rs1 by rs2, rounding towards zero.divu rd,rs1,rs2 amominu.watomically load a 32-bit unsigned data value from the address in rs1, place the value into register rd, apply unsigned min the loaded value and the original 32-bit unsigned value in rs2, then store the result back to the address in rs1.amominu.w rd,rs2,(rs1)fmadd.d1Perform single-precision fused multiply addition.fmadd.d rd,rs1,rs2,rs3 fcvt.s.lufcvt.s.lu rd,rs1fclass.dyExamines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.The format of the mask is described in table [classify table]_.The corresponding bit in rd will be set if the property is true and clear otherwise.All other bits in rd are cleared. Note that exactly one bit in rd will be set.fclass.d rd,rs1csrrsiSet CSR bit using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field.csrrsi rd,offset,uimmmulhperforms an XLEN-bit :math:`\times` XLEN-bit multiplication of signed rs1 by signed rs2 and places the upper XLEN bits in the destination register.mulh rd,rs1,rs2lr.drload a 64-bit data from the address in rs1, places value in rd, and registers a reservation on the memory address.lr.d rd,rs1sd1Store 64-bit, values from register rs2 to memory.sd rs2,offset(rs1)fsub.s5Perform single-precision floating-point substraction.fsub.s rd,rs1,rs2sllvPerforms logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.sll rd,rs1,rs2fsqrt.d%Perform single-precision square root.fsqrt.d rd,rs1fmul.d7Perform single-precision floating-point multiplication.fmul.d rd,rs1,rs2fsgnjn.dzProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is opposite of rs2’s sign bit.fsgnjn.d rd,rs1,rs2jalr/Jump to address and place return address in rd.jalr rd,rs1,offsetc.ebreakBCause control to be transferred back to the debugging environment.c.ebreakaddAdds the registers rs1 and rs2 and stores the result in rd.Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result.add rd,rs1,rs2fmul.s7Perform single-precision floating-point multiplication.fmul.s rd,rs1,rs2mulwmulw rd,rs1,rs2 fcvt.d.wuConverts a 32-bit unsigned integer, in integer register rs1 into a double-precision floating-point number in floating-point register rd.fcvt.d.wu rd,rs1c.fswspStore a single-precision floating-point value in floating-point register rs2 to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.c.fswsp rs2,uimm(rs2)xoriPerforms bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rdNote, "XORI rd, rs1, -1" performs a bitwise logical inversion of register rs1(assembler pseudo-instruction NOT rd, rs)xori rd,rs1,immamoadd.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply add the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amoadd.d rd,rs2,(rs1)divwDperform an 32 bits by 32 bits signed integer division of rs1 by rs2.divw rd,rs1,rs2c.jal/Jump to address and place return address in rd. c.jal offsetsltuPlace the value 1 in register rd if register rs1 is less than register rs2 when both are treated as unsigned numbers, else 0 is written to rd.sltu rd,rs1,rs2fnmsub.s1Perform single-precision fused multiply addition.fnmsub.s rd,rs1,rs2,rs3fmsub.s1Perform single-precision fused multiply addition.fmsub.s rd,rs1,rs2,rs3fsgnj.snProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is rs2’s sign bit.fsgnj.s rd,rs1,rs2fcvt.d.wConverts a 32-bit signed integer, in integer register rs1 into a double-precision floating-point number in floating-point register rd.fcvt.d.w rd,rs1c.addiwAdd the non-zero sign-extended 6-bit immediate to the value in register rd then produce 32-bit result, then sign-extends result to 64 bits.c.addiw rd,immc.xorkCompute the bitwise XOR of the values in registers rd\' and rs2\', then writes the result to register rd\'.c.xor rd\',rs2\'c.bnez;Take the branch if the value in register rs1\' is not zero.c.bnez rs1\',offsetsc.dwrite a 64-bit data in rs2 to the address in rs1, provided a valid reservation still exists on that address.SC writes zero to rd on success or a nonzero code on failure.sc.d rd,rs1,rs2fcvt.l.sfcvt.l.s rd,rs1flwYLoad a single-precision floating-point value from memory into floating-point register rd.flw rd,offset(rs1)fmv.x.dfmv.x.d rd,rs1fmv.d.xfmv.d.x rd,rs1srlwPerforms logical right shift on the low 32-bits value in register rs1 by the shift amount held in the lower 5 bits of register rs2 and produce 32-bit results and written to the destination register rd.srlw rd,rs1,rs2c.fswStore a single-precision floating-point value in floatingpoint register rs2\' to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'.c.fsw rd\',uimm(rs1\')fmax.d?Write the larger of single precision data in rs1 and rs2 to rd.fmax.d rd,rs1,rs2sltiuPlace the value 1 in register rd if register rs1 is less than the immediate when both are treated as unsigned numbers, else 0 is written to rd.sltiu rd,rs1,immoriePerforms bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rdori rd,rs1,immandifPerforms bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rdandi rd,rs1,immsrliPerforms logical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediateIn RV64, bit-25 is used to shamt[5].srli rd,rs1,shamt c.addi4spnAdd a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd\'.This instruction is used to generate pointers to stack-allocated variables, and expands to addi rd\', x2, nzuimm[9:2].c.addi4spn rd\',uimmc.jrJPerforms an unconditional control transfer to the address in register rs1.c.jr rs1fence.ipProvides explicit synchronization between writes to instruction memory and instruction fetches on the same hart.fence.ic.mv0Copy the value in register rs2 into register rd.c.mv rd,rs2csrrcatomic read and clear bits in CSR. Reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR.Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.Other bits in the CSR are unaffected.csrrc rd,offset,rs1mretKReturn from traps in M-mode, and MRET copies MPIE into MIE, then sets MPIE.mretfcvt.s.djConverts double floating-point register in rs1 into a floating-point number in floating-point register rd.fcvt.s.d rd,rs1fcvt.w.dConverts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit integer, in integer register rd.fcvt.w.d rd,rs1ebreakUsed by debuggers to cause control to be transferred back to a debugging environment.It generates a breakpoint exception and performs no other operation.ebreaklheLoads a 16-bit value from memory and sign-extends this to XLEN bits before storing it in register rd.lh rd,offset(rs1)c.orjCompute the bitwise OR of the values in registers rd\' and rs2\', then writes the result to register rd\'.c.or rd\',rs2\'srawPerforms arithmetic right shift on the low 32-bits value in register rs1 by the shift amount held in the lower 5 bits of register rs2 and produce 32-bit results and written to the destination register rd.sraw rd,rs1,rs2amoxor.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply exclusive or the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amoxor.w rd,rs2,(rs1)c.subwSubtract the value in register rs2\' from the value in register rd\', then sign-extends the lower 32 bits of the difference before writing the result to register rd\'.c.subw rd\',rs2\'remHperform an XLEN bits by XLEN bits signed integer reminder of rs1 by rs2.rem rd,rs1,rs2fsqrt.s%Perform single-precision square root.fsqrt.s rd,rs1c.ldLoad a 64-bit value from memory into register rd\'.It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1\'.c.ld rd\',uimm(rs1\')fsdKStore a double-precision value from the floating-point registers to memory.fsd rs2,offset(rs1)subwSubtract the 32-bit of registers rs1 and 32-bit of register rs2 and stores the result in rd.Arithmetic overflow is ignored and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.subw rd,rs1,rs2c.swspStore a 32-bit value in register rs2 to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.c.swsp rs2,uimm(x2)ecallMake a request to the supporting execution environment.When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.ecallc.sdspStore a 64-bit value in register rs2 to memory.It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2.c.sdsp rs2,uimm(x2)c.fsdStore a double-precision floating-point value in floating-point register rs2\' to memory.It computes an effective address by adding the zeroextended offset, scaled by 8, to the base address in register rs1\'.c.fsd rd\',uimm(rs1\')amomin.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply min the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amomin.d rd,rs2,(rs1)csrrwiUpdate the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field.csrrwi rd,offset,uimmfcvt.d.sqConverts single floating-point register in rs1 into a double floating-point number in floating-point register rd.fcvt.d.s rd,rs1flt.sPerforms a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN.flt.s rd,rs1,rs2fsub.d4Perform single-precision floating-point subtraction.fsub.d rd,rs1,rs2 amoswap.datomically load a 64-bit data value from the address in rs1, place the value into register rd, swap the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amoswap.d rd,rs2,(rs1)sretKReturn from traps in S-mode, and SRET copies SPIE into SIE, then sets SPIE.sretlbudLoads a 8-bit value from memory and zero-extends this to XLEN bits before storing it in register rd.lbu rd,offset(rs1)sllwPerforms logical left shift on the low 32-bits value in register rs1 by the shift amount held in the lower 5 bits of register rs2 and produce 32-bit results and written to the destination register rd.sllw rd,rs1,rs2remwDperform an 32 bits by 32 bits signed integer reminder of rs1 by rs2.remw rd,rs1,rs2c.li]Load the sign-extended 6-bit immediate, imm, into register rd.C.LI is only valid when rd!=x0.c.li rd,immfadd.s1Perform single-precision floating-point addition.fadd.s rd,rs1,rs2fmsub.d1Perform single-precision fused multiply addition.fmsub.d rd,rs1,rs2,rs3sltPlace the value 1 in register rd if register rs1 is less than register rs2 when both are treated as signed numbers, else 0 is written to rd.slt rd,rs1,rs2c.srliPerform a logical right shift of the value in register rd\' then writes the result to rd\'.The shift amount is encoded in the shamt field, where shamt[5] must be zero for RV32C.c.srli rd\',uimmmulperforms an XLEN-bit :math:`\times` XLEN-bit multiplication of signed rs1 by signed rs2 and places the lower XLEN bits in the destination register.mul rd,rs1,rs2c.nopDDoes not change any user-visible state, except for advancing the pc.c.nopfnmsub.d1Perform single-precision fused multiply addition.fnmsub.d rd,rs1,rs2,rs3andHPerforms bitwise AND on registers rs1 and rs2 and place the result in rdand rd,rs1,rs2 fcvt.lu.sfcvt.lu.s rd,rs1c.fldLoad a double-precision floating-point value from memory into floating-point register rd\'.It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1\'.c.fld rd\',uimm(rs1\')amoor.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply or the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amoor.d rd,rs2,(rs1)addwAdds the 32-bit of registers rs1 and 32-bit of register rs2 and stores the result in rd.Arithmetic overflow is ignored and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.addw rd,rs1,rs2c.ldspLoad a 64-bit value from memory into register rd.It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2.c.ldsp rd,uimm(x2)remuwFperform an 32 bits by 32 bits unsigned integer reminder of rs1 by rs2.remuw rd,rs1,rs2fmv.x.wMove the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd.fmv.x.w rd,rs1c.addwAdd the value in register rs2\' from the value in register rd\', then sign-extends the lower 32 bits of the difference before writing the result to register rd\'.c.addw rd\',rs2\'subSubs the register rs2 from rs1 and stores the result in rd.Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result.sub rd,rs1,rs2fsgnjx.s|Produce a result that takes all bits except the sign bit from rs1.The result’s sign bit is XOR of sign bit of rs1 and rs2.fsgnjx.s rd,rs1,rs2xorHPerforms bitwise XOR on registers rs1 and rs2 and place the result in rdxor rd,rs1,rs2fenceUsed to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors.Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same.Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE.fence pred, succ sfence.vmaGuarantees that any previous stores already visible to the current RISC-V hart are ordered before all subsequent implicit references from that hart to the memory-management data structures.The SFENCE.VMA is used to flush any local hardware caches related to address translation.It is specified as a fence rather than a TLB flush to provide cleaner semantics with respect to which instructions are affected by the flush operation and to support a wider variety of dynamic caching structures and memory-management schemes.SFENCE.VMA is also used by higher privilege levels to synchronize page table writes and the address translation hardware.sfence.vma rs1,rs2fcvt.s.wuConverts a 32-bit signed integer, in integer register rs1 into a floating-point number in floating-point register rd.fcvt.s.w rd,rs1div_perform an XLEN bits by XLEN bits signed integer division of rs1 by rs2, rounding towards zero.div rd,rs1,rs2 c.addi16spAdd the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496).c.addi16sp immmulhsuperforms an XLEN-bit :math:`\times` XLEN-bit multiplication of signed rs1 by unsigned rs2 and places the upper XLEN bits in the destination register.mulhsu rd,rs1,rs2flt.dPerforms a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN.flt.d rd,rs1,rs2 amominu.datomically load a 64-bit data value from the address in rs1, place the value into register rd, apply unsigned min the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1.amominu.d rd,rs2,(rs1)amomax.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply max operator the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amomax.w rd,rs2,(rs1)auipcadd upper immediate to pc Build pc-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then places the result in register rd.auipc rd,immc.sraiPerform a arithmetic right shift of the value in register rd\' then writes the result to rd\'.The shift amount is encoded in the shamt field, where shamt[5] must be zero for RV32C.c.srai rd\',uimmbgeZTake the branch if registers rs1 is greater than or equal to rs2, using signed comparison.bge rs1,rs2,offsetc.beqz7Take the branch if the value in register rs1\' is zero.c.beqz rs1\',offsetc.addihAdd the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd.c.addi rd,u[12:12]|u[6:2]amoadd.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply add the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amoadd.w rd,rs2,(rs1)c.luic.lui rd,immbeq3Take the branch if registers rs1 and rs2 are equal.beq rs1,rs2,offsetc.andiCompute the bitwise AND of of the value in register rd\' and the sign-extended 6-bit immediate, then writes the result to rd\'.c.andi rd\',immfdiv.s1Perform single-precision floating-point division.fdiv.s rd,rs1,rs2ld<Loads a 64-bit value from memory into register rd for RV64I.ld rd,offset(rs1)divuwFperform an 32 bits by 32 bits unsigned integer division of rs1 by rs2.divuw rd,rs1,rs2srayPerforms arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2sra rd,rs1,rs2mulhuperforms an XLEN-bit :math:`\times` XLEN-bit multiplication of unsigned rs1 by unsigned rs2 and places the upper XLEN bits in the destination register.mulhu rd,rs1,rs2amomin.watomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply min operator the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1.amomin.w rd,rs2,(rs1)fle.sPerforms a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN.fle.s rd,rs1,rs2c.andkCompute the bitwise AND of the values in registers rd\' and rs2\', then writes the result to register rd\'.c.and rd\',rs2\'fcvt.d.lfcvt.d.l rd,rs1 fcvt.d.lufcvt.d.lu rd,rs1fcvt.s.lfcvt.s.l rd,rs1 fcvt.wu.srConvert a floating-point number in floating-point register rs1 to a signed 32-bit in unsigned integer register rd.fcvt.wu.s rd,rs1srliwPerforms logical right shift on the 32-bit of value in register rs1 by the shift amount held in the lower 5 bits of the immediate.Encodings with $imm[5] \neq 0$ are reserved.srliw rd,rs1,shamtsraiwPerforms arithmetic right shift on the 32-bit of value in register rs1 by the shift amount held in the lower 5 bits of the immediate.Encodings with $imm[5] \neq 0$ are reserved.sraiw rd,rs1,shamtsc.wwrite a word in rs2 to the address in rs1, provided a valid reservation still exists on that address.SC writes zero to rd on success or a nonzero code on failure.sc.w rd,rs1,rs2c.fsdspStore a double-precision floating-point value in floating-point register rs2 to memory.It computes an effective address by adding the zeroextended offset, scaled by 8, to the stack pointer, x2.c.fsdsp rs2,uimm(x2)fadd.d1Perform single-precision floating-point addition.fadd.d rd,rs1,rs2wfiwait for interrupt. Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing.Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart.WFI is available in all privileged modes, and optionally available to U-mode.This instruction may raise an illegal instruction exception when TW=1 in mstatus.wfislliPerforms logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediateIn RV64, bit-25 is used to shamt[5].slli rd,rs1,shamtfnmadd.s1Perform single-precision fused multiply addition.fnmadd.s rd,rs1,rs2,rs3fcvt.w.siConvert a floating-point number in floating-point register rs1 to a signed 32-bit in integer register rd.fcvt.w.s rd,rs1fdiv.d1Perform single-precision floating-point division.fdiv.d rd,rs1,rs2fldYLoad a double-precision floating-point value from memory into floating-point register rd.fld rd,rs1,offsetluiload upper immediate. Build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros.lui rd,immc.flwLoad a single-precision floating-point value from memory into floating-point register rd\'.It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'.c.flw rd\',uimm(rs1\')shAStore 16-bit, values from the low bits of register rs2 to memory.sh rs2,offset(rs1)c.jUnconditional control transfer. c.j offsetfnmadd.d1Perform single-precision fused multiply addition.fnmadd.d rd,rs1,rs2,rs3fsgnjn.szProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is opposite of rs2’s sign bit.fsgnjn.s rd,rs1,rs2