ErstRSTrstêReSTart. Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.rstRST 0  4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%200rstRST 8H  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%208HrstRST 10H  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2010HrstRST 18H  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2018HrstRST 20H  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2020HrstRST 28H  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2028HrstRST 30H  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2030HrstRST 38H  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2038HsetSETset/SET bit. Sets the numbered bit on target value.set SET b, (HL)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20%28HL%29set SET b, (IX+o) Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20%28IX%2Bo%29set SET b, (IY+o) Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20%28IY%2Bo%29setSET b, r ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20reiEIeióEnable Interrupts. Enables maskable interrupts (after next instruction, i.e. for example: EI RET - the interrupt may happen only after RET instruction is finished (or EI DI pair of instructions will not allow any maskable interrupt to happen).eiEI/https://www.zilog.com/docs/z80/z80cpu_um.pdf#EIinirINIRinirDINput and Increment Repeated. Loops INI until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.inirINIR  1https://www.zilog.com/docs/z80/z80cpu_um.pdf#INIRrlRLrlgRotate Left. Rotates the target bitwise left by one position. The MSB is copied to Carry. The previous contents of Carry are copied to bit 0. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.rlRL (HL):https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20%28HL%29rl RL (IX+o) >https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20%28IX%2Bo%29rl RL (IY+o) >https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20%28IY%2Bo%29rlRL r 3https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20rxorXORxor"Performs the bitwise XOR operator.xorXOR (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20%28HL%29xor XOR (IX+o)?https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20%28IX%2Bo%29xor XOR (IY+o)?https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20%28IY%2Bo%29xorXOR n4https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20nxorXOR r4https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20rxorXOR IXp 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20IXpxorXOR IYq 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20IYqretRETretsRETurn. POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP. retRET  0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RETretRET C  4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20CretRET M  4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20MretRET NC  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20NCretRET NZ  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20NZretRET P  4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20PretRET PE  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20PEretRET PO  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20POretRET Z  4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20ZsubSUBsubSubtracts a value from A.subSUB (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20%28HL%29sub SUB (IX+o)?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20%28IX%2Bo%29sub SUB (IY+o)?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20%28IY%2Bo%29subSUB n4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20nsubSUB r4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20rsubSUB IXp 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20IXpsubSUB IYq 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20IYqoutdOUTDoutdăOut and Decrement. Behaves like IND, except that it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.outdOUTD  1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OUTDotdrOTDRotdrÚOut and Decrement Repeated. except that it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.otdrOTDR  1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OTDRjpJPjp jpJP nn  4https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20nnjpJP (HL):https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20%28HL%29jpJP (IX) :https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20%28IX%29jpJP (IY) :https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20%28IY%29jpJP C, nn  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20C%2C%20nnjpJP M, nn  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20M%2C%20nnjp JP NC, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20NC%2C%20nnjp JP NZ, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20NZ%2C%20nnjpJP P, nn  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20P%2C%20nnjp JP PE, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20PE%2C%20nnjp JP PO, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20PO%2C%20nnjpJP Z, nn  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20Z%2C%20nnldLDldšLoaD. The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first.Zld LD (BC), AAhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28BC%29%2C%20Ald LD (DE), AAhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28DE%29%2C%20Ald LD (HL), n  Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28HL%29%2C%20nld LD (HL), rAhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28HL%29%2C%20rld LD (IX+o), nEhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IX%2Bo%29%2C%20nld LD (IX+o), rEhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IX%2Bo%29%2C%20rld LD (IY+o), nEhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IY%2Bo%29%2C%20nld LD (IY+o), rEhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IY%2Bo%29%2C%20rld LD (nn), A Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20Ald LD (nn), BCBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20BCld LD (nn), DEBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20DEld LD (nn), HLBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20HLld LD (nn), IXBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20IXld LD (nn), IYBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20IYld LD (nn), SPBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20SPld LD A, (BC)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28BC%29ld LD A, (DE)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28DE%29ld LD A, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28HL%29ld LD A, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28IX%2Bo%29ld LD A, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28IY%2Bo%29ld LD A, (nn) Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28nn%29ldLD A, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20nldLD A, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20rld LD A, IXp <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20IXpld LD A, IYq <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20IYqldLD A, I  :https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20IldLD A, R  :https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20Rld LD B, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20%28HL%29ld LD B, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20%28IX%2Bo%29ld LD B, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20%28IY%2Bo%29ldLD B, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20nldLD B, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20rld LD B, IXp <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20IXpld LD B, IYq <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20IYqld LD BC, (nn)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20BC%2C%20%28nn%29ld LD BC, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20BC%2C%20nnld LD C, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20%28HL%29ld LD C, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20%28IX%2Bo%29ld LD C, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20%28IY%2Bo%29ldLD C, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20nldLD C, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20rld LD C, IXp <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20IXpld LD C, IYq <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20IYqld LD D, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20%28HL%29ld LD D, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20%28IX%2Bo%29ld LD D, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20%28IY%2Bo%29ldLD D, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20nldLD D, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20rld LD D, IXp <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20IXpld LD D, IYq <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20IYqld LD DE, (nn)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20DE%2C%20%28nn%29ld LD DE, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20DE%2C%20nnld LD E, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20%28HL%29ld LD E, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20%28IX%2Bo%29ld LD E, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20%28IY%2Bo%29ldLD E, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20nldLD E, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20rld LD E, IXp <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20IXpld LD E, IYq <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20IYqld LD H, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20%28HL%29ld LD H, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20%28IX%2Bo%29ld LD H, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20%28IY%2Bo%29ldLD H, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20nldLD H, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20rld LD HL, (nn)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20HL%2C%20%28nn%29ld LD HL, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20HL%2C%20nnldLD I, A  :https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20I%2C%20Ald LD IX, (nn)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IX%2C%20%28nn%29ld LD IX, nn<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IX%2C%20nnld LD IXh, n  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXh%2C%20nld LD IXh, p <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXh%2C%20pld LD IXl, n  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXl%2C%20nld LD IXl, p <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXl%2C%20pld LD IY, (nn)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IY%2C%20%28nn%29ld LD IY, nn<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IY%2C%20nnld LD IYh, n  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYh%2C%20nld LD IYh, q <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYh%2C%20qld LD IYl, n  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYl%2C%20nld LD IYl, q <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYl%2C%20qld LD L, (HL)Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20%28HL%29ld LD L, (IX+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20%28IX%2Bo%29ld LD L, (IY+o)Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20%28IY%2Bo%29ldLD L, n:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20nldLD L, r:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20rldLD R, A  :https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20R%2C%20Ald LD SP, (nn)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20%28nn%29ld LD SP, HL<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20HLld LD SP, IX  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20IXld LD SP, IY  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20IYld LD SP, nn  <https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20nnhaltHALThaltÙSuspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.haltHALT1https://www.zilog.com/docs/z80/z80cpu_um.pdf#HALTaddADDaddAdds values together.add ADD A, (HL)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20%28HL%29add ADD A, (IX+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20%28IX%2Bo%29add ADD A, (IY+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20%28IY%2Bo%29addADD A, n;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20naddADD A, r;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20radd ADD A, IXp =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20IXpadd ADD A, IYq =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20IYqadd ADD HL, BC  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20BCadd ADD HL, DE  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20DEadd ADD HL, HL  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20HLadd ADD HL, SP  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20SPadd ADD IX, BC=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20BCadd ADD IX, DE=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20DEadd ADD IX, IX=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20IXadd ADD IX, SP=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20SPadd ADD IY, BC=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20BCadd ADD IY, DE=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20DEadd ADD IY, IY=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20IYadd ADD IY, SP=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20SPiniINIini>INput and Incremenent. Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.iniINI  0https://www.zilog.com/docs/z80/z80cpu_um.pdf#INInopNOPnop€No OPeration. Does 'nothing' (just usual housekeeping like refreshing memory and advancing program counter to next instruction).nopNOP0https://www.zilog.com/docs/z80/z80cpu_um.pdf#NOPmuluwMULUWmuluwMPerform 16-bit multiplication. Introduced as a new instruction with the R800.muluw MULUW HL, BC$$?https://www.zilog.com/docs/z80/z80cpu_um.pdf#MULUW%20HL%2C%20BCmuluw MULUW HL, SP$$?https://www.zilog.com/docs/z80/z80cpu_um.pdf#MULUW%20HL%2C%20SPadcADCadcMADd with Carry. Adds values together, adding an additional 1 if Carry is set. adc ADC A, (HL)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20%28HL%29adc ADC A, (IX+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20%28IX%2Bo%29adc ADC A, (IY+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20%28IY%2Bo%29adcADC A, n;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20nadcADC A, r;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20radc ADC A, IXp =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20IXpadc ADC A, IYq =https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20IYqadc ADC HL, BC=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20BCadc ADC HL, DE=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20DEadc ADC HL, HL=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20HLadc ADC HL, SP=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20SPindrINDRindrEINput and Decrement Repeated. Loops INIR until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.indrINDR  1https://www.zilog.com/docs/z80/z80cpu_um.pdf#INDRotirOTIRotirìOut and Increment Repeated. Behaves like INIR except that it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.otirOTIR  1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OTIRsbcSBCsbcMSuBtract with Carry, er, borrow. Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset. sbc SBC A, (HL)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20%28HL%29sbc SBC A, (IX+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20%28IX%2Bo%29sbc SBC A, (IY+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20%28IY%2Bo%29sbcSBC A, n;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20nsbcSBC A, r;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20rsbc SBC A, IXp =https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20IXpsbc SBC A, IYq =https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20IYqsbc SBC HL, BC=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20BCsbc SBC HL, DE=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20DEsbc SBC HL, HL=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20HLsbc SBC HL, SP=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20SPandANDand"Performs the bitwise AND operator.andAND (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20%28HL%29and AND (IX+o)?https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20%28IX%2Bo%29and AND (IY+o)?https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20%28IY%2Bo%29andAND n4https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20nandAND r4https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20randAND IXp 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20IXpandAND IYq 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20IYqslaSLAslaxShift Left Arithmetic. Shifts the target bitwise left by one position. The MSB is copied to Carry. 0 is copied to bit 0.slaSLA (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20%28HL%29sla SLA (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20%28IX%2Bo%29sla SLA (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20%28IY%2Bo%29slaSLA r 4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20rdjnzDJNZdjnz}Decrement reg. b and Jump if Not Zero. Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.djnzDJNZ o  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DJNZ%20osrlSRLsrl{Shift Right Logical. Shifts the target bitwise right by one position. The LSB is copied to Carry. 0 is copied into the MSB.srlSRL (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20%28HL%29srl SRL (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20%28IX%2Bo%29srl SRL (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20%28IY%2Bo%29srlSRL r 4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20rrlcRLCrlcORotate Left Circular. Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.rlcRLC (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20%28HL%29rlc RLC (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20%28IX%2Bo%29rlc RLC (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20%28IY%2Bo%29rlcRLC r 4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20rdiDIdi1Disable Interrupts. Disables maskable interrupts.diDI/https://www.zilog.com/docs/z80/z80cpu_um.pdf#DIexEXex0EXchange. Exchanges the contents of two sources.ex EX (SP), HLBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20%28SP%29%2C%20HLex EX (SP), IXBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20%28SP%29%2C%20IXex EX (SP), IYBhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20%28SP%29%2C%20IYex EX AF, AF'?https://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20AF%2C%20AF%27ex EX DE, HL<https://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20DE%2C%20HLrrcaRRCArrcaQSame as RRC except it only works on A, is faster, and does not alter S, Z or P/V.rrcaRRCA1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRCAjrJRjr˜Jump Relative. Jumps to an alternate address by adding the parameter to the PC - in other words the parameter is an adjustment, not an absolute address.jrJR o  3https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20ojrJR C, o  :https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20C%2C%20ojrJR NC, o  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20NC%2C%20ojrJR NZ, o  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20NZ%2C%20ojrJR Z, o  :https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20Z%2C%20ocpiCPIcpièCoPare and Increment. Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.cpiCPI0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPIincINCincŃINCrement. ncrements the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.incINC (HL)  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20%28HL%29inc INC (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20%28IX%2Bo%29inc INC (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20%28IY%2Bo%29incINC A4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20AincINC B4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20BincINC BC5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20BCincINC C4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20CincINC D4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20DincINC DE5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20DEincINC E4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20EincINC H4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20HincINC HL5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20HLincINC IX  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IXincINC IY  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IYincINC IXp 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IXpincINC IYq 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IYqincINC L4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20LincINC SP5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20SPretiRETIreti§RETurn from Interrupt. Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).retiRETI1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RETIdecDECdec•DECrment. Decrements the target by one. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.decDEC (HL)  ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20%28HL%29dec DEC (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20%28IX%2Bo%29dec DEC (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20%28IY%2Bo%29decDEC A4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20AdecDEC B4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20BdecDEC BC5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20BCdecDEC C4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20CdecDEC D4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20DdecDEC DE5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20DEdecDEC E4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20EdecDEC H4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20HdecDEC HL5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20HLdecDEC IX  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IXdecDEC IY  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IYdecDEC IXp 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IXpdecDEC IYq 6https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IYqdecDEC L4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20LdecDEC SP5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20SPcpdrCPDRcpdrComPare and Decrement Repeated. Automatically loops CPIR until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0). Flag effects are the same as CPD except that one of the two terminating flag conditions will always be true.cpdrCPDR1https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPDRpopPOPpopPops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2. Popping into AF does set value of flag register F directly to low 8 bits of value from stack.popPOP AF  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20AFpopPOP BC  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20BCpopPOP DE  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20DEpopPOP HL  5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20HLpopPOP IX5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20IXpopPOP IY5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20IYbitBITbit2test Bit. Tests if a bit is set on a target value.bit BIT b, (HL) Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20%28HL%29bit BIT b, (IX+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20%28IX%2Bo%29bit BIT b, (IY+o)Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20%28IY%2Bo%29bitBIT b, r ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20rinINin<Inputs a byte value from the 16-bit port number given in BC. in IN A, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20A%2C%20%28C%29in IN A, (n)    @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20A%2C%20%28n%29in IN B, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20B%2C%20%28C%29in IN C, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20C%2C%20%28C%29in IN D, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20D%2C%20%28C%29in IN E, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20E%2C%20%28C%29in IN H, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20H%2C%20%28C%29in IN L, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20L%2C%20%28C%29in IN F, (C)   @https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20F%2C%20%28C%29rrdRRDrrd–Rotate Right bcd Digit. Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.rrdRRD0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRDcpCPcpÆComPare. Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.cpCP (HL):https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20%28HL%29cp CP (IX+o)>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20%28IX%2Bo%29cp CP (IY+o)>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20%28IY%2Bo%29cpCP n3https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20ncpCP r3https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20rcpCP IXp 5https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20IXpcpCP IYq 5https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20IYqlddLDDldd«LoaD and Decrement. Copies the byte pointed to by HL to the address pointed to by DE, then substracts 1 from DE, HL, and BC. P/V is set to (BC!=0), i.e. set when non zero.lddLDD0https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDDnegNEGnegÎNEGate. Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.negNEG 0https://www.zilog.com/docs/z80/z80cpu_um.pdf#NEGdaaDAAdaaDecimal Adjust Accumulator. Modifies the contents of the accumulator based on the flags left by previous operation to correct for binary coded decimal (BCD).daaDAA0https://www.zilog.com/docs/z80/z80cpu_um.pdf#DAArlaRLArlaPSame as RL except it only works on A, is faster, and does not alter S, Z or P/V.rlaRLA0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLAoutiOUTIoutiȚOut and Increment. Behaves like INI, except it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.outiOUTI  1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OUTIcplCPLcpl4ComPLement. Inverts the contents of the accumulator.cplCPL0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPLimIMim-Interrupt Mode. Sets interrupt handling mode.imIM 0 3https://www.zilog.com/docs/z80/z80cpu_um.pdf#IM%200imIM 1 3https://www.zilog.com/docs/z80/z80cpu_um.pdf#IM%201imIM 2 3https://www.zilog.com/docs/z80/z80cpu_um.pdf#IM%202rrRRrr[Rotate Right. Rotates the target bitwise right by one position. The LSB is copied to Carry.rrRR (HL):https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20%28HL%29rr RR (IX+o) >https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20%28IX%2Bo%29rr RR (IY+o) >https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20%28IY%2Bo%29rrRR r 3https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20rexxEXXexxaEXchange all. Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.exxEXX0https://www.zilog.com/docs/z80/z80cpu_um.pdf#EXXsraSRAsraShift Right Arithmetic. Shifts the target bitwise right by one position. The MSB is copied to itself. Bit 0 is copied to Carry.sraSRA (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20%28HL%29sra SRA (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20%28IX%2Bo%29sra SRA (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20%28IY%2Bo%29sraSRA r 4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20rrldRLDrld–Rotate Left bcd Digit. Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.rldRLD0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLDretnRETNretnZRETurn from Non-maskable interrupt. Returns from a non-maskable interrupt service routine.retnRETN1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RETNoutOUTout=Outputs a byte value from the 16-bit port number given in BC.out OUT (C), A   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Aout OUT (C), B   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Bout OUT (C), C   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Cout OUT (C), D   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Dout OUT (C), E   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Eout OUT (C), H   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Hout OUT (C), L   Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20Lout OUT (n), A    Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28n%29%2C%20AcallCALLcallpLike JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls. callCALL nn6https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20nncall CALL C, nn  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20C%2C%20nncall CALL M, nn  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20M%2C%20nncall CALL NC, nn  >https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20NC%2C%20nncall CALL NZ, nn  >https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20NZ%2C%20nncall CALL P, nn  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20P%2C%20nncall CALL PE, nn  >https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20PE%2C%20nncall CALL PO, nn  >https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20PO%2C%20nncall CALL Z, nn  =https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20Z%2C%20nnlddrLDDRlddr LoaD and Decrement Repeated. Automatically loops LDD until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDDR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).lddrLDDR1https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDDRindINDind<INput and Decrement. Inputs a value from port BC into memory at the address stored in HL, then decrements HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.indIND  0https://www.zilog.com/docs/z80/z80cpu_um.pdf#INDrraRRArraPSame as RR except it only works on A, is faster, and does not alter S, Z or P/V.rraRRA0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRAorORor!Performs the bitwise OR operator.orOR (HL):https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20%28HL%29or OR (IX+o)>https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20%28IX%2Bo%29or OR (IY+o)>https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20%28IY%2Bo%29orOR n3https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20norOR r3https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20rorOR IXp 5https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20IXporOR IYq 5https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20IYqcpirCPIRcpirComPare and Increment Repeated. Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0). Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.cpirCPIR1https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPIRrlcaRLCArlcaQSame as RLC except it only works on A, is faster, and does not alter S, Z or P/V.rlcaRLCA1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLCAmulubMULUBmulubLPerform 8-bit multiplication. Introduced as a new instruction with the R800.mulub MULUB A, r=https://www.zilog.com/docs/z80/z80cpu_um.pdf#MULUB%20A%2C%20rldiLDIldi¶LoaD and Increment. Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.ldiLDI0https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDIcpdCPDcpdÁComPare and Decrement. Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then subtracts 1 from HL and subtracts 1 from BC.cpdCPD0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPDccfCCFccfŽComplement Carry Flag. Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.ccfCCF0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CCFldirLDIRldirPLoaD and Increment Repeated. Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself). Flag effects are the same as LDI except that P/V will always be reset.ldirLDIR1https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDIRpushPUSHpush­Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.pushPUSH AF  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20AFpushPUSH BC  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20BCpushPUSH DE  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20DEpushPUSH HL  6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20HLpushPUSH IX6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20IXpushPUSH IY6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20IYresRESres(Resets the numbered bit on target value.res RES b, (HL)Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20%28HL%29res RES b, (IX+o) Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20%28IX%2Bo%29res RES b, (IY+o) Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20%28IY%2Bo%29resRES b, r ;https://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20rrrcRRCrrcSRotate Right Circular. Rotates the target bitwise right by one position. The LSB is copied to the MSB, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.rrcRRC (HL);https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20%28HL%29rrc RRC (IX+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20%28IX%2Bo%29rrc RRC (IY+o) ?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20%28IY%2Bo%29rrcRRC r 4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20rscfSCFscf$Set Carry Flag. Sets the carry flag.scfSCF0https://www.zilog.com/docs/z80/z80cpu_um.pdf#SCF