Atmel Corporation ATMEL ATSAM4LC4C SAM4L B Atmel ATSAM4LC4C device: Cortex-M4 Microcontroller with 256KB Flash, 32KB SRAM, 100-pin package (refer to http://www.atmel.com/devices/SAM4LC4C.aspx for more) ============================================================================\n Atmel Microcontroller Software Support\n ============================================================================\n Copyright (c) 2016 Atmel Corporation,\n a wholly owned subsidiary of Microchip Technology Inc.\n \n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the Licence at\n \n http://www.apache.org/licenses/LICENSE-2.0\n \n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an "AS IS" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n ============================================================================ CM4 r0p1 little true false 4 false system_sam4l 8 32 32 read-write 0x00000000 0xFFFFFFFF ABDACB 1.0.0 Audio Bitstream DAC ABDACB ABDACB_ 0x40064000 0 0x400 registers ABDACB_INTREQ 72 CR Control Register 0x00 32 EN Enable 0 1 ENSelect 0 Audio DAC is disabled 0x0 1 Audio DAC is enabled 0x1 SWAP Swap Channels 1 1 SWAPSelect 0 The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio DAC Sample Data Register (SDR) 0x0 1 The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio DAC Sample Data Register (SDR) 0x1 ALTUPR Alternative up-sampling ratio 3 1 CMOC Common mode offset control 4 1 MONO Mono mode 5 1 SWRST Software reset 7 1 DATAFORMAT Data word format 16 3 FS Sampling frequency 24 4 SDR0 Sample Data Register 0 0x04 32 DATA Sample Data 0 32 SDR1 Sample Data Register 1 0x08 32 DATA Sample Data 0 32 VCR0 Volume Control Register 0 0x0C 32 VOLUME Volume Control 0 15 MUTE Mute 31 1 VCR1 Volume Control Register 1 0x10 32 VOLUME Volume Control 0 15 MUTE Mute 31 1 IER Interrupt Enable Register 0x14 32 write-only TXRDY Transmit Ready Interrupt Enable 1 1 TXRDYSelect 0 No effect 0x0 1 Enables the Audio DAC TX Ready interrupt 0x1 TXUR Transmit Underrun Interrupt Enable 2 1 TXURSelect 0 No effect 0x0 1 Enables the Audio DAC Underrun interrupt 0x1 IDR Interupt Disable Register 0x18 32 write-only TXRDY Transmit Ready Interrupt Disable 1 1 TXRDYSelect 0 No effect 0x0 1 Disable the Audio DAC TX Ready interrupt 0x1 TXUR Transmit Underrun Interrupt Disable 2 1 TXURSelect 0 No effect 0x0 1 Disable the Audio DAC Underrun interrupt 0x1 IMR Interrupt Mask Register 0x1C 32 read-only TXRDY Transmit Ready Interrupt Mask 1 1 TXRDYSelect 0 The Audio DAC TX Ready interrupt is disabled 0x0 1 The Audio DAC TX Ready interrupt is enabled 0x1 TXUR Transmit Underrun Interrupt Mask 2 1 TXURSelect 0 The Audio DAC Underrun interrupt is disabled 0x0 1 The Audio DAC Underrun interrupt is enabled 0x1 SR Status Register 0x20 32 read-only BUSY ABDACB Busy 0 1 TXRDY Transmit Ready 1 1 TXRDYSelect 0 No Audio DAC TX Ready has occured since the last time ISR was read or since reset 0x0 1 At least one Audio DAC TX Ready has occured since the last time ISR was read or since reset 0x1 TXUR Transmit Underrun 2 1 TXURSelect 0 No Audio DAC Underrun has occured since the last time ISR was read or since reset 0x0 1 At least one Audio DAC Underrun has occured since the last time ISR was read or since reset 0x1 SCR Status Clear Register 0x24 32 write-only TXRDY Transmit Ready Interrupt Clear 1 1 TXRDYSelect 0 No effect 0x0 1 Clear the Audio DAC TX Ready interrupt 0x1 TXUR Transmit Underrun Interrupt Clear 2 1 TXURSelect 0 No effect 0x0 1 Clear the Audio DAC Underrun interrupt 0x1 PARAMETER Parameter Register 0x28 32 read-only VERSION Version Register 0x2C 32 read-only 0x00000100 VERSION Version Number 0 12 VARIANT Variant Number 16 4 ACIFC 1.0.1 Analog Comparator Interface ACIFC ACIFC_ 0x40040000 0 0x400 registers ACIFC_INTREQ 71 CTRL Control Register 0x00 32 EN ACIFC Enable 0 1 EVENTEN Peripheral Event Trigger Enable 1 1 USTART User Start Single Comparison 4 1 ESTART Peripheral Event Start Single Comparison 5 1 ACTEST Analog Comparator Test Mode 7 1 SR Status Register 0x04 32 read-only ACCS0 AC0 Current Comparison Status 0 1 read-only ACRDY0 AC0 Ready 1 1 read-only ACCS1 AC1 Current Comparison Status 2 1 read-only ACRDY1 AC1 Ready 3 1 read-only ACCS2 AC2 Current Comparison Status 4 1 read-only ACRDY2 AC2 Ready 5 1 read-only ACCS3 AC3 Current Comparison Status 6 1 read-only ACRDY3 AC3 Ready 7 1 read-only ACCS4 AC4 Current Comparison Status 8 1 read-only ACRDY4 AC4 Ready 9 1 read-only ACCS5 AC5 Current Comparison Status 10 1 read-only ACRDY5 AC5 Ready 11 1 read-only ACCS6 AC6 Current Comparison Status 12 1 read-only ACRDY6 AC6 Ready 13 1 read-only ACCS7 AC7 Current Comparison Status 14 1 read-only ACRDY7 AC7 Ready 15 1 read-only WFCS0 Window0 Mode Current Status 24 1 read-only WFCS1 Window1 Mode Current Status 25 1 read-only WFCS2 Window2 Mode Current Status 26 1 read-only WFCS3 Window3 Mode Current Status 27 1 read-only IER Interrupt Enable Register 0x10 32 write-only ACINT0 AC0 Interrupt Enable 0 1 write-only SUTINT0 AC0 Startup Time Interrupt Enable 1 1 write-only ACINT1 AC1 Interrupt Enable 2 1 write-only SUTINT1 AC1 Startup Time Interrupt Enable 3 1 write-only ACINT2 AC2 Interrupt Enable 4 1 write-only SUTINT2 AC2 Startup Time Interrupt Enable 5 1 write-only ACINT3 AC3 Interrupt Enable 6 1 write-only SUTINT3 AC3 Startup Time Interrupt Enable 7 1 write-only ACINT4 AC4 Interrupt Enable 8 1 write-only SUTINT4 AC4 Startup Time Interrupt Enable 9 1 write-only ACINT5 AC5 Interrupt Enable 10 1 write-only SUTINT5 AC5 Startup Time Interrupt Enable 11 1 write-only ACINT6 AC6 Interrupt Enable 12 1 write-only SUTINT6 AC6 Startup Time Interrupt Enable 13 1 write-only ACINT7 AC7 Interrupt Enable 14 1 write-only SUTINT7 AC7 Startup Time Interrupt Enable 15 1 write-only WFINT0 Window0 Mode Interrupt Enable 24 1 write-only WFINT1 Window1 Mode Interrupt Enable 25 1 write-only WFINT2 Window2 Mode Interrupt Enable 26 1 write-only WFINT3 Window3 Mode Interrupt Enable 27 1 write-only IDR Interrupt Disable Register 0x14 32 write-only ACINT0 AC0 Interrupt Disable 0 1 write-only SUTINT0 AC0 Startup Time Interrupt Disable 1 1 write-only ACINT1 AC1 Interrupt Disable 2 1 write-only SUTINT1 AC1 Startup Time Interrupt Disable 3 1 write-only ACINT2 AC2 Interrupt Disable 4 1 write-only SUTINT2 AC2 Startup Time Interrupt Disable 5 1 write-only ACINT3 AC3 Interrupt Disable 6 1 write-only SUTINT3 AC3 Startup Time Interrupt Disable 7 1 write-only ACINT4 AC4 Interrupt Disable 8 1 write-only SUTINT4 AC4 Startup Time Interrupt Disable 9 1 write-only ACINT5 AC5 Interrupt Disable 10 1 write-only SUTINT5 AC5 Startup Time Interrupt Disable 11 1 write-only ACINT6 AC6 Interrupt Disable 12 1 write-only SUTINT6 AC6 Startup Time Interrupt Disable 13 1 write-only ACINT7 AC7 Interrupt Disable 14 1 write-only SUTINT7 AC7 Startup Time Interrupt Disable 15 1 write-only WFINT0 Window0 Mode Interrupt Disable 24 1 write-only WFINT1 Window1 Mode Interrupt Disable 25 1 write-only WFINT2 Window2 Mode Interrupt Disable 26 1 write-only WFINT3 Window3 Mode Interrupt Disable 27 1 write-only IMR Interrupt Mask Register 0x18 32 read-only ACINT0 AC0 Interrupt Mask 0 1 read-only SUTINT0 AC0 Startup Time Interrupt Mask 1 1 read-only ACINT1 AC1 Interrupt Mask 2 1 read-only SUTINT1 AC1 Startup Time Interrupt Mask 3 1 read-only ACINT2 AC2 Interrupt Mask 4 1 read-only SUTINT2 AC2 Startup Time Interrupt Mask 5 1 read-only ACINT3 AC3 Interrupt Mask 6 1 read-only SUTINT3 AC3 Startup Time Interrupt Mask 7 1 read-only ACINT4 AC4 Interrupt Mask 8 1 read-only SUTINT4 AC4 Startup Time Interrupt Mask 9 1 read-only ACINT5 AC5 Interrupt Mask 10 1 read-only SUTINT5 AC5 Startup Time Interrupt Mask 11 1 read-only ACINT6 AC6 Interrupt Mask 12 1 read-only SUTINT6 AC6 Startup Time Interrupt Mask 13 1 read-only ACINT7 AC7 Interrupt Mask 14 1 read-only SUTINT7 AC7 Startup Time Interrupt Mask 15 1 read-only WFINT0 Window0 Mode Interrupt Mask 24 1 read-only WFINT1 Window1 Mode Interrupt Mask 25 1 read-only WFINT2 Window2 Mode Interrupt Mask 26 1 read-only WFINT3 Window3 Mode Interrupt Mask 27 1 read-only ISR Interrupt Status Register 0x1C 32 read-only ACINT0 AC0 Interrupt Status 0 1 read-only SUTINT0 AC0 Startup Time Interrupt Status 1 1 read-only ACINT1 AC1 Interrupt Status 2 1 read-only SUTINT1 AC1 Startup Time Interrupt Status 3 1 read-only ACINT2 AC2 Interrupt Status 4 1 read-only SUTINT2 AC2 Startup Time Interrupt Status 5 1 read-only ACINT3 AC3 Interrupt Status 6 1 read-only SUTINT3 AC3 Startup Time Interrupt Status 7 1 read-only ACINT4 AC4 Interrupt Status 8 1 read-only SUTINT4 AC4 Startup Time Interrupt Status 9 1 read-only ACINT5 AC5 Interrupt Status 10 1 read-only SUTINT5 AC5 Startup Time Interrupt Status 11 1 read-only ACINT6 AC6 Interrupt Status 12 1 read-only SUTINT6 AC6 Startup Time Interrupt Status 13 1 read-only ACINT7 AC7 Interrupt Status 14 1 read-only SUTINT7 AC7 Startup Time Interrupt Status 15 1 read-only WFINT0 Window0 Mode Interrupt Status 24 1 read-only WFINT1 Window1 Mode Interrupt Status 25 1 read-only WFINT2 Window2 Mode Interrupt Status 26 1 read-only WFINT3 Window3 Mode Interrupt Status 27 1 read-only ICR Interrupt Status Clear Register 0x20 32 write-only ACINT0 AC0 Interrupt Status Clear 0 1 write-only SUTINT0 AC0 Startup Time Interrupt Status Clear 1 1 write-only ACINT1 AC1 Interrupt Status Clear 2 1 write-only SUTINT1 AC1 Startup Time Interrupt Status Clear 3 1 write-only ACINT2 AC2 Interrupt Status Clear 4 1 write-only SUTINT2 AC2 Startup Time Interrupt Status Clear 5 1 write-only ACINT3 AC3 Interrupt Status Clear 6 1 write-only SUTINT3 AC3 Startup Time Interrupt Status Clear 7 1 write-only ACINT4 AC4 Interrupt Status Clear 8 1 write-only SUTINT4 AC4 Startup Time Interrupt Status Clear 9 1 write-only ACINT5 AC5 Interrupt Status Clear 10 1 write-only SUTINT5 AC5 Startup Time Interrupt Status Clear 11 1 write-only ACINT6 AC6 Interrupt Status Clear 12 1 write-only SUTINT6 AC6 Startup Time Interrupt Status Clear 13 1 write-only ACINT7 AC7 Interrupt Status Clear 14 1 write-only SUTINT7 AC7 Startup Time Interrupt Status Clear 15 1 write-only WFINT0 Window0 Mode Interrupt Status Clear 24 1 write-only WFINT1 Window1 Mode Interrupt Status Clear 25 1 write-only WFINT2 Window2 Mode Interrupt Status Clear 26 1 write-only WFINT3 Window3 Mode Interrupt Status Clear 27 1 write-only TR Test Register 0x24 32 ACTEST0 AC0 Output Override Value 0 1 ACTEST1 AC1 Output Override Value 1 1 ACTEST2 AC2 Output Override Value 2 1 ACTEST3 AC3 Output Override Value 3 1 ACTEST4 AC4 Output Override Value 4 1 ACTEST5 AC5 Output Override Value 5 1 ACTEST6 AC6 Output Override Value 6 1 ACTEST7 AC7 Output Override Value 7 1 PARAMETER Parameter Register 0x30 32 read-only ACIMPL0 Analog Comparator 0 Implemented 0 1 read-only ACIMPL1 Analog Comparator 1 Implemented 1 1 read-only ACIMPL2 Analog Comparator 2 Implemented 2 1 read-only ACIMPL3 Analog Comparator 3 Implemented 3 1 read-only ACIMPL4 Analog Comparator 4 Implemented 4 1 read-only ACIMPL5 Analog Comparator 5 Implemented 5 1 read-only ACIMPL6 Analog Comparator 6 Implemented 6 1 read-only ACIMPL7 Analog Comparator 7 Implemented 7 1 read-only WIMPL0 Window0 Mode Implemented 16 1 read-only WIMPL1 Window1 Mode Implemented 17 1 read-only WIMPL2 Window2 Mode Implemented 18 1 read-only WIMPL3 Window3 Mode Implemented 19 1 read-only VERSION Version Register 0x34 32 read-only 0x00000101 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only 4 0x4 CONFW%s Window configuration Register 0x80 32 WIS Window Mode Interrupt Settings 0 3 WEVSRC Peripheral Event Sourse Selection for Window Mode 8 3 WEVEN Window Peripheral Event Enable 11 1 WFEN Window Mode Enable 16 1 8 0x4 CONF%s AC Configuration Register 0xD0 32 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 INSELN Negative Input Select 8 2 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 HYS Hysteresis Voltage Value 24 2 FAST Fast Mode Enable 26 1 ALWAYSON Always On 27 1 ADCIFE 1.0.0 ADC controller interface ADCIFE ADCIFE_ 0x40038000 0 0x400 registers ADCIFE_INTREQ 69 CR Control Register 0x00 32 write-only SWRST Software reset 0 1 write-only TSTOP Internal timer stop bit 1 1 write-only TSTART Internal timer start bit 2 1 write-only STRIG Sequencer trigger 3 1 write-only REFBUFEN Reference buffer enable 4 1 write-only REFBUFDIS Reference buffer disable 5 1 write-only EN ADCIFD enable 8 1 write-only DIS ADCIFD disable 9 1 write-only BGREQEN Bandgap buffer request enable 10 1 write-only BGREQDIS Bandgap buffer request disable 11 1 write-only CFG Configuration Register 0x04 32 REFSEL ADC Reference Selection 1 3 SPEED ADC current reduction 4 2 CLKSEL Clock Selection for sequencer/ADC cell 6 1 PRESCAL Prescaler Rate Selection 8 3 SR Status Register 0x08 32 read-only SEOC Sequencer end of conversion 0 1 read-only LOVR Sequencer last converted value overrun 1 1 read-only WM Window monitor 2 1 read-only SMTRG Sequencer missed trigger event 3 1 read-only SUTD Start-up time done 4 1 read-only TTO Timer time-out 5 1 read-only EN Enable Status 24 1 read-only TBUSY Timer busy 25 1 read-only SBUSY Sequencer busy 26 1 read-only CBUSY Conversion busy 27 1 read-only REFBUF Reference buffer status 28 1 read-only SCR Status Clear Register 0x0C 32 write-only SEOC Sequencer end of conversion 0 1 write-only LOVR Sequencer last converted value overrun 1 1 write-only WM Window monitor 2 1 write-only SMTRG Sequencer missed trigger event 3 1 write-only SUTD Start-up time done 4 1 write-only TTO Timer time-out 5 1 write-only RTS Resistive Touch Screen Register 0x10 32 SEQCFG Sequencer Configuration Register 0x14 32 HWLA Half word left adjust 0 1 BIPOLAR Bipolar Mode 2 1 GAIN Gain factor 4 3 GCOMP Gain Compensation 7 1 TRGSEL Trigger selection 8 3 RES Resolution 12 1 INTERNAL Internal Voltage Source Selection 14 2 MUXPOS MUX selection on Positive ADC input channel 16 4 MUXNEG MUX selection on Negative ADC input channel 20 3 ZOOMRANGE Zoom shift/unipolar reference source selection 28 3 CDMA_FIRST_DMA_WORD Configuration Direct Memory Access Register CDMA 0x18 32 write-only HWLA Half word left adjust 0 1 write-only BIPOLAR Bipolar Mode 2 1 write-only STRIG Sequencer Trigger Event 3 1 write-only GAIN Gain factor 4 3 write-only GCOMP Gain Compensation 7 1 write-only ENSTUP Enable Start-Up Time 8 1 write-only RES Resolution 12 1 write-only TSS Internal timer start or stop bit 13 1 write-only INTERNAL Internal Voltage Source Selection 14 2 write-only MUXPOS MUX selection on Positive ADC input channel 16 4 write-only MUXNEG MUX selection on Negative ADC input channel 20 3 ZOOMRANGE Zoom shift/unipolar reference source selection 28 3 write-only DW Double Word transmitting 31 1 write-only CDMA_SECOND_DMA_WORD Configuration Direct Memory Access Register CDMA 0x18 32 write-only LT Low Threshold 0 12 write-only WM Window Monitor Mode 12 3 HT High Threshold 16 12 DW Double Word transmitting 31 1 TIM Timing Configuration Register 0x1C 32 STARTUP Startup time 0 5 ENSTUP Enable Startup 8 1 ITIMER Internal Timer Register 0x20 32 ITMC Internal timer max counter 0 16 WCFG Window Monitor Configuration Register 0x24 32 WM Window Monitor Mode 12 3 WTH Window Monitor Threshold Configuration Register 0x28 32 LT Low threshold 0 12 HT High Threshold 16 12 LCV Sequencer Last Converted Value Register 0x2C 32 read-only LCV Last converted value 0 16 read-only LCPC Last converted positive channel 16 4 read-only LCNC Last converted negative channel 20 3 read-only IER Interrupt Enable Register 0x30 32 write-only SEOC Sequencer end of conversion Interrupt Enable 0 1 write-only LOVR Sequencer last converted value overrun Interrupt Enable 1 1 write-only WM Window monitor Interrupt Enable 2 1 write-only SMTRG Sequencer missed trigger event Interrupt Enable 3 1 write-only TTO Timer time-out Interrupt Enable 5 1 write-only IDR Interrupt Disable Register 0x34 32 write-only SEOC Sequencer end of conversion Interrupt Disable 0 1 write-only LOVR Sequencer last converted value overrun Interrupt Disable 1 1 write-only WM Window monitor Interrupt Disable 2 1 write-only SMTRG Sequencer missed trigger event Interrupt Disable 3 1 write-only TTO Timer time-out Interrupt Disable 5 1 write-only IMR Interrupt Mask Register 0x38 32 read-only SEOC Sequencer end of conversion Interrupt Mask 0 1 read-only LOVR Sequencer last converted value overrun Interrupt Mask 1 1 read-only WM Window monitor Interrupt Mask 2 1 read-only SMTRG Sequencer missed trigger event Interrupt Mask 3 1 read-only TTO Timer time-out Interrupt Mask 5 1 read-only CALIB Calibration Register 0x3C 32 CALIB Calibration Value 0 8 BIASSEL Select bias mode 8 1 BIASCAL Bias Calibration 12 4 FCD Flash Calibration Done 16 1 VERSION Version Register 0x40 32 read-only 0x00000100 VERSION Version number 0 12 read-only VARIANT Variant number 16 4 read-only PARAMETER Parameter Register 0x44 32 read-only N Number of channels 0 8 read-only AESA 1.0.2 Advanced Encryption Standard AESA AESA_ 0x400B0000 0 0x100 registers AESA_INTREQ 21 CTRL Control Register 0x00 32 ENABLE Enable Module 0 1 DKEYGEN Decryption Key Generate 1 1 write-only NEWMSG New Message 2 1 write-only SWRST Software Reset 8 1 write-only MODE Mode Register 0x04 32 0x000F0000 ENCRYPT Encryption 0 1 KEYSIZE Key Size 1 2 DMA DMA Mode 3 1 OPMODE Confidentiality Mode of Operation 4 3 CFBS Cipher Feedback Data Segment Size 8 3 CTYPE Countermeasure Type 16 4 DATABUFPTR Data Buffer Pointer Register 0x08 32 IDATAW Input Data Word 0 2 ODATAW Output Data Word 4 2 SR Status Register 0x0C 32 read-only 0x00010000 ODATARDY Output Data Ready 0 1 read-only IBUFRDY Input Buffer Ready 16 1 read-only IER Interrupt Enable Register 0x10 32 write-only ODATARDY Output Data Ready Interrupt Enable 0 1 write-only IBUFRDY Input Buffer Ready Interrupt Enable 16 1 write-only IDR Interrupt Disable Register 0x14 32 write-only ODATARDY Output Data Ready Interrupt Disable 0 1 write-only IBUFRDY Input Buffer Ready Interrupt Disable 16 1 write-only IMR Interrupt Mask Register 0x18 32 read-only ODATARDY Output Data Ready Interrupt Mask 0 1 read-only IBUFRDY Input Buffer Ready Interrupt Mask 16 1 read-only 8 0x4 KEY%s Key Register 0x20 32 write-only KEY0 Key Word 0 0 32 write-only 4 0x4 INITVECT%s Initialization Vector Register 0x40 32 write-only INITVECT0 Initialization Vector Word 0 0 32 write-only IDATA Input Data Register 0x50 32 write-only IDATA Input Data 0 32 write-only ODATA Output Data Register 0x60 32 read-only ODATA Output Data 0 32 read-only DRNGSEED DRNG Seed Register 0x70 32 write-only SEED DRNG Seed 0 32 write-only PARAMETER Parameter Register 0xF8 32 read-only 0x00000112 KEYSIZE Maximum Key Size 0 2 read-only OPMODE Maximum Number of Confidentiality Modes of Operation 2 3 read-only CTRMEAS Countermeasures 8 1 read-only VERSION Version Register 0xFC 32 read-only 0x00000102 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only AST 3.1.1 Asynchronous Timer AST AST_ 0x400F0800 0 0x400 registers AST_INTREQ_0 39 AST_INTREQ_1 40 AST_INTREQ_2 41 AST_INTREQ_3 42 AST_INTREQ_4 43 CR Control Register 0x00 32 EN Enable 0 1 ENSelect 0 The AST is disabled. 0x0 1 The AST is enabled 0x1 PCLR Prescaler Clear 1 1 CAL Calendar mode 2 1 CA0 Clear on Alarm 0 8 1 CA1 Clear on Alarm 1 9 1 PSEL Prescaler Select 16 5 CV Counter Value 0x04 32 VALUE AST Value 0 32 SR Status Register 0x08 32 read-only OVF Overflow 0 1 read-only ALARM0 Alarm 0 8 1 read-only ALARM1 Alarm 1 9 1 read-only PER0 Periodic 0 16 1 read-only PER1 Periodic 1 17 1 read-only BUSY AST Busy 24 1 read-only BUSYSelect 0 The AST accepts writes to CV, WER, DTR, SCR, AR, PIR and CR 0x0 1 The AST is busy and will discard writes to CV, WER, DTR, SCR, AR, PIR and CR 0x1 READY AST Ready 25 1 read-only CLKBUSY Clock Busy 28 1 read-only CLKBUSYSelect 0 The clock is ready and can be changed 0x0 1 CEN has been written and the clock is busy 0x1 CLKRDY Clock Ready 29 1 read-only SCR Status Clear Register 0x0C 32 write-only OVF Overflow 0 1 write-only ALARM0 Alarm 0 8 1 write-only ALARM1 Alarm 1 9 1 write-only PER0 Periodic 0 16 1 write-only PER1 Periodic 1 17 1 write-only READY AST Ready 25 1 write-only CLKRDY Clock Ready 29 1 write-only IER Interrupt Enable Register 0x10 32 write-only OVF Overflow 0 1 write-only OVFSelect 0 No effect 0x0 1 Enable Interrupt. 0x1 ALARM0 Alarm 0 8 1 write-only ALARM0Select 0 No effect 0x0 1 Enable interrupt 0x1 ALARM1 Alarm 1 9 1 write-only ALARM1Select 0 No effect 0x0 1 Enable interrupt 0x1 PER0 Periodic 0 16 1 write-only PER0Select 0 No effect 0x0 1 Enable interrupt 0x1 PER1 Periodic 1 17 1 write-only PER1Select 0 No effect 0x0 1 Enable interrupt 0x1 READY AST Ready 25 1 write-only READYSelect 0 No effect 0x0 1 Enable interrupt 0x1 CLKRDY Clock Ready 29 1 write-only CLKRDYSelect 0 No effect 0x0 1 Enable interrupt 0x1 IDR Interrupt Disable Register 0x14 32 write-only OVF Overflow 0 1 write-only OVFSelect 0 No effect 0x0 1 Disable Interrupt. 0x1 ALARM0 Alarm 0 8 1 write-only ALARM0Select 0 No effect 0x0 1 Disable interrupt 0x1 ALARM1 Alarm 1 9 1 write-only ALARM1Select 0 No effect 0x0 1 Disable interrupt 0x1 PER0 Periodic 0 16 1 write-only PER0Select 0 No effet 0x0 1 Disalbe interrupt 0x1 PER1 Periodic 1 17 1 write-only PER1Select 0 No effect 0x0 1 Disable interrupt 0x1 READY AST Ready 25 1 write-only READYSelect 0 No effect 0x0 1 Disable interrupt 0x1 CLKRDY Clock Ready 29 1 write-only CLKRDYSelect 0 No effect 0x0 1 Disable interrupt 0x1 IMR Interrupt Mask Register 0x18 32 read-only OVF Overflow 0 1 read-only OVFSelect 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 ALARM0 Alarm 0 8 1 read-only ALARM0Select 0 Interupt is disabled 0x0 1 Interrupt is enabled 0x1 ALARM1 Alarm 1 9 1 read-only ALARM1Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 PER0 Periodic 0 16 1 read-only PER0Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 PER1 Periodic 1 17 1 read-only PER1Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 READY AST Ready 25 1 read-only READYSelect 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 CLKRDY Clock Ready 29 1 read-only CLKRDYSelect 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 WER Wake Enable Register 0x1C 32 OVF Overflow 0 1 OVFSelect 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 ALARM0 Alarm 0 8 1 ALARM0Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 ALARM1 Alarm 1 9 1 ALARM1Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 PER0 Periodic 0 16 1 PER0Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 PER1 Periodic 1 17 1 PER1Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 AR0 Alarm Register 0 0x20 32 VALUE Alarm Value 0 32 AR1 Alarm Register 1 0x24 32 VALUE Alarm Value 0 32 PIR0 Periodic Interval Register 0 0x30 32 INSEL Interval Select 0 5 PIR1 Periodic Interval Register 1 0x34 32 INSEL Interval Select 0 5 CLOCK Clock Control Register 0x40 32 CEN Clock Enable 0 1 CENSelect 0 The clock is disabled 0x0 1 The clock is enabled 0x1 CSSEL Clock Source Selection 8 3 CSSELSelect SLOWCLOCK Slow clock 0x0 32KHZCLK 32 kHz clock 0x1 PBCLOCK PB clock 0x2 GCLK Generic clock 0x3 1KHZCLK 1kHz clock from 32 kHz oscillator 0x4 DTR Digital Tuner Register 0x44 32 EXP EXP 0 5 ADD ADD 5 1 VALUE VALUE 8 8 EVE Event Enable Register 0x48 32 write-only OVF Overflow 0 1 write-only ALARM0 Alarm 0 8 1 write-only ALARM1 Alarm 1 9 1 write-only PER0 Perioidc 0 16 1 write-only PER1 Periodic 1 17 1 write-only EVD Event Disable Register 0x4C 32 write-only OVF Overflow 0 1 write-only ALARM0 Alarm 0 8 1 write-only ALARM1 Alarm 1 9 1 write-only PER0 Perioidc 0 16 1 write-only PER1 Periodic 1 17 1 write-only EVM Event Mask Register 0x50 32 read-only OVF Overflow 0 1 read-only ALARM0 Alarm 0 8 1 read-only ALARM1 Alarm 1 9 1 read-only PER0 Perioidc 0 16 1 read-only PER1 Periodic 1 17 1 read-only CALV Calendar Value 0x54 32 SEC Second 0 6 MIN Minute 6 6 HOUR Hour 12 5 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 PARAMETER Parameter Register 0xF0 32 read-only DT Digital Tuner 0 1 read-only DTSelect OFF Digital tuner off 0x0 ON Digital tuner on 0x1 DTEXPWA Digital Tuner Exponent Writeable 1 1 read-only DTEXPWASelect 0 Digital tuner exponent is a constant value. Writes to EXP bitfield in DTR will be discarded. 0x0 1 Digital tuner exponent is chosen by writing to EXP bitfield in DTR 0x1 DTEXPVALUE Digital Tuner Exponent Value 2 5 read-only NUMAR Number of alarm comparators 8 2 read-only NUMARSelect ZERO No alarm comparators 0x0 ONE One alarm comparator 0x1 TWO Two alarm comparators 0x2 NUMPIR Number of periodic comparators 12 1 read-only NUMPIRSelect ONE One periodic comparator 0x0 TWO Two periodic comparators 0x1 PIR0WA Periodic Interval 0 Writeable 14 1 read-only PIR0WASelect 0 Periodic alarm prescaler 0 tapping is a constant value. Writes to INSEL bitfield in PIR0 will be discarded. 0x0 1 Periodic alarm prescaler 0 tapping is chosen by writing to INSEL bitfield in PIR0 0x1 PIR1WA Periodic Interval 1 Writeable 15 1 read-only PIR1WASelect 0 Writes to PIR1 will be discarded 0x0 1 PIR1 can be written 0x1 PER0VALUE Periodic Interval 0 Value 16 5 read-only PER1VALUE Periodic Interval 1 Value 24 5 read-only VERSION Version Register 0xFC 32 read-only 0x00000311 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only BPM 1.2.0 Backup Power Manager BPM BPM_ 0x400F0000 0 0x400 registers BPM_INTREQ 37 IER Interrupt Enable Register 0x00 32 write-only PSOK Power Scaling OK Interrupt Enable 0 1 write-only AE Access Error Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x04 32 write-only PSOK Power Scaling OK Interrupt Disable 0 1 write-only AE Access Error Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x08 32 read-only PSOK Power Scaling OK Interrupt Mask 0 1 read-only AE Access Error Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0C 32 read-only PSOK Power Scaling OK Interrupt Status 0 1 read-only AE Access Error Interrupt Status 31 1 read-only ICR Interrupt Clear Register 0x10 32 write-only PSOK Power Scaling OK Interrupt Status Clear 0 1 write-only AE Access Error Interrupt Status Clear 31 1 write-only SR Status Register 0x14 32 read-only PSOK Power Scaling OK Status 0 1 read-only AE Access Error 31 1 UNLOCK Unlock Register 0x18 32 write-only ADDR Unlock Address 0 10 write-only KEY Unlock Key 24 8 write-only PMCON Power Mode Control Register 0x1C 32 PS Power Scaling Configuration Value 0 2 PSCREQ Power Scaling Change Request 2 1 PSCM Power Scaling Change Mode 3 1 BKUP BACKUP Mode 8 1 RET RETENTION Mode 9 1 SLEEP SLEEP mode Configuration 12 2 CK32S 32Khz-1Khz Clock Source Selection 16 1 FASTWKUP Fast Wakeup 24 1 BKUPWCAUSE Backup Wake up Cause Register 0x28 32 read-only BKUPWEN Backup Wake up Enable Register 0x2C 32 BKUPPMUX Backup Pin Muxing Register 0x30 32 BKUPPMUX Backup Pin Muxing 0 9 IORET Input Output Retention Register 0x34 32 RET Retention on I/O lines after waking up from the BACKUP mode 0 1 BPR Bypass Register 0x40 32 RUNPSPB Run Mode Power Scaling Preset Bypass 0 1 PSMPSPB Power Save Mode Power Scaling Preset Bypass 1 1 SEQSTN Sequencial Startup from ULP (Active Low) 2 1 PSBTD Power Scaling Bias Timing Disable 3 1 PSHFD Power Scaling Halt Flash Until VREGOK Disable 4 1 DLYRSTD Delaying Reset Disable 5 1 BIASSEN Bias Switch Enable 6 1 LATSEN Latdel Switch Enable 7 1 BOD18CONT BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes 8 1 POBS Pico Uart Observability 9 1 FFFW Force Flash Fast Wakeup 10 1 FBRDYEN Flash Bias Ready Enable 11 1 FVREFSEN Flash Vref Switch Enable 12 1 FWRUNPS Factory Word Run PS Register 0x44 32 read-only REGLEVEL Regulator Voltage Level 0 4 REGTYPE Regulator Type 4 2 REGTYPESelect NORMAL 0x0 LP 0x1 XULP 0x2 REFTYPE Reference Type 6 2 REFTYPESelect BOTH 0x0 BG 0x1 LPBG 0x2 INTERNAL 0x3 FLASHLATDEL Flash Latch Delay Value 8 5 FLASHBIAS Flash Bias Value 13 4 FPPW Flash Pico Power Mode 17 1 RC115 RC 115KHZ Calibration Value 18 7 RCFAST RCFAST Calibration Value 25 7 FWPSAVEPS Factory Word Power Save PS Register 0x48 32 read-only WREGLEVEL Wait mode Regulator Level 0 4 read-only WBIAS Bias in wait mode 4 4 read-only WLATDEL Flash Latdel in wait mode 8 5 read-only RREGLEVEL Retention mode Regulator Level 13 4 read-only RBIAS Bias in Retention mode 17 4 read-only RLATDEL Flash Latdel in Retention mode 21 5 read-only BREGLEVEL Backup mode Regulator Level 26 4 read-only POR18DIS POR 18 Disable 30 1 read-only FWSAS Flash Wait State Automatic Switching 31 1 read-only VERSION Version Register 0xFC 32 read-only 0x00000120 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only BSCIF 1.0.0 Backup System Control Interface BSCIF BSCIF_ 0x400F0400 0 0x400 registers BSCIF_INTREQ 38 IER Interrupt Enable Register 0x000 32 write-only OSC32RDY 32kHz Oscillator Ready 0 1 write-only RC32KRDY 32kHz RC Oscillator Ready 1 1 write-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 write-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 write-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 write-only BOD33DET BOD33 Detected 5 1 write-only BOD18DET BOD18 Detected 6 1 write-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 write-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 write-only SSWRDY VREG Stop Switching Ready 9 1 write-only VREGOK Main VREG OK 10 1 write-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 write-only AE Access Error 31 1 write-only IDR Interrupt Disable Register 0x004 32 write-only OSC32RDY 32kHz Oscillator Ready 0 1 write-only RC32KRDY 32kHz RC Oscillator Ready 1 1 write-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 write-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 write-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 write-only BOD33DET BOD33 Detected 5 1 write-only BOD18DET BOD18 Detected 6 1 write-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 write-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 write-only SSWRDY VREG Stop Switching Ready 9 1 write-only VREGOK Mai n VREG OK 10 1 write-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 write-only AE Access Error 31 1 write-only IMR Interrupt Mask Register 0x008 32 read-only OSC32RDY 32kHz Oscillator Ready 0 1 read-only RC32KRDY 32kHz RC Oscillator Ready 1 1 read-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 read-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 read-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 read-only BOD33DET BOD33 Detected 5 1 read-only BOD18DET BOD18 Detected 6 1 read-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 read-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 read-only SSWRDY VREG Stop Switching Ready 9 1 read-only VREGOK Main VREG OK 10 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 read-only AE Access Error 31 1 read-only ISR Interrupt Status Register 0x00C 32 read-only OSC32RDY 32kHz Oscillator Ready 0 1 read-only RC32KRDY 32kHz RC Oscillator Ready 1 1 read-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 read-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 read-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 read-only BOD33DET BOD33 Detected 5 1 read-only BOD18DET BOD18 Detected 6 1 read-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 read-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 read-only SSWRDY VREG Stop Switching Ready 9 1 read-only VREGOK Main VREG OK 10 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 read-only AE Access Error 31 1 read-only ICR Interrupt Clear Register 0x010 32 write-only OSC32RDY 32kHz Oscillator Ready 0 1 write-only RC32KRDY 32kHz RC Oscillator Ready 1 1 write-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 write-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 write-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 write-only BOD33DET BOD33 Detected 5 1 write-only BOD18DET BOD18 Detected 6 1 write-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 write-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 write-only SSWRDY VREG Stop Switching Ready 9 1 write-only VREGOK Main VREG OK 10 1 write-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 write-only AE Access Error 31 1 write-only PCLKSR Power and Clocks Status Register 0x014 32 read-only OSC32RDY 32kHz Oscillator Ready 0 1 read-only RC32KRDY 32kHz RC Oscillator Ready 1 1 read-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 read-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 read-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 read-only BOD33DET BOD33 Detected 5 1 read-only BOD18DET BOD18 Detected 6 1 read-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 read-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 read-only SSWRDY VREG Stop Switching Ready 9 1 read-only VREGOK Main VREG OK 10 1 read-only RC1MRDY RC 1MHz Oscillator Ready 11 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 read-only UNLOCK Unlock Register 0x018 32 write-only ADDR Unlock Address 0 10 write-only KEY Unlock Key 24 8 write-only KEYSelect VALID Valid Key to Unlock register 0xaa CSCR Chip Specific Configuration Register 0x01C 32 OSCCTRL32 Oscillator 32 Control Register 0x020 32 0x00000004 OSC32EN 32 KHz Oscillator Enable 0 1 PINSEL Pins Select 1 1 EN32K 32 KHz output Enable 2 1 EN1K 1 KHz output Enable 3 1 MODE Oscillator Mode 8 3 SELCURR Current selection 12 4 STARTUP Oscillator Start-up Time 16 3 RC32KCR 32 kHz RC Oscillator Control Register 0x024 32 EN Enable as Generic clock source 0 1 TCEN Temperature Compensation Enable 1 1 EN32K Enable 32 KHz output 2 1 EN1K Enable 1 kHz output 3 1 MODE Mode Selection 4 1 REF Reference select 5 1 FCD Flash calibration done 7 1 RC32KTUNE 32kHz RC Oscillator Tuning Register 0x028 32 FINE Fine value 0 6 COARSE Coarse Value 16 7 BOD33CTRL BOD33 Control Register 0x02C 32 EN Enable 0 1 HYST BOD Hysteresis 1 1 ACTION Action 8 2 MODE Operation modes 16 1 FCD BOD Fuse Calibration Done 30 1 SFV BOD Control Register Store Final Value 31 1 BOD33LEVEL BOD33 Level Register 0x030 32 VAL BOD Value 0 6 BOD33SAMPLING BOD33 Sampling Control Register 0x034 32 CEN Clock Enable 0 1 CSSEL Clock Source Select 1 1 PSEL Prescaler Select 8 4 BOD18CTRL BOD18 Control Register 0x038 32 EN Enable 0 1 HYST BOD Hysteresis 1 1 ACTION Action 8 2 MODE Operation modes 16 1 FCD BOD Fuse Calibration Done 30 1 SFV BOD Control Register Store Final Value 31 1 BOD18LEVEL BOD18 Level Register 0x03C 32 VAL BOD Value 0 6 RANGE BOD Threshold Range 31 1 VREGCR Voltage Regulator Configuration Register 0x044 32 DIS Voltage Regulator disable 0 1 SSG Spread Spectrum Generator Enable 8 1 SSW Stop Switching 9 1 SSWEVT Stop Switching On Event Enable 10 1 SFV Store Final Value 31 1 VREGNCSR Normal Mode Control and Status Register 0x04C 32 VREGLPCSR LP Mode Control and Status Register 0x050 32 RC1MCR 1MHz RC Clock Configuration Register 0x058 32 0x00000F00 CLKOE 1MHz RC Osc Clock Output Enable 0 1 FCD Flash Calibration Done 7 1 CLKCAL 1MHz RC Osc Calibration 8 5 BGCR Bandgap Calibration Register 0x05C 32 BGCTRL Bandgap Control Register 0x060 32 ADCISEL ADC Input Selection 0 2 ADCISELSelect DIS 0x0 VTEMP 0x1 VREF 0x2 TSEN Temperature Sensor Enable 8 1 BGSR Bandgap Status Register 0x064 32 read-only BGBUFRDY Bandgap Buffer Ready 0 8 read-only BGBUFRDYSelect FLASH 0x1 PLL 0x2 VREG 0x4 BUFRR 0x8 ADC 0x10 LCD 0x20 BGRDY Bandgap Voltage Reference Ready 16 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 17 1 read-only VREF Voltage Reference Used by the System 18 2 read-only 4 0x4 BR%s Backup Register 0x078 32 BRIFBVERSION Backup Register Interface Version Register 0x3E4 32 read-only 0x00000100 VERSION Version Number 0 12 VARIANT Variant Number 16 4 BGREFIFBVERSION BGREFIFB Version Register 0x3E8 32 read-only 0x00000110 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only VREGIFGVERSION VREGIFA Version Register 0x3EC 32 read-only 0x00000110 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only BODIFCVERSION BODIFC Version Register 0x3F0 32 read-only 0x00000110 VERSION Version Number 0 12 VARIANT Variant Number 16 4 RC32KIFBVERSION 32 kHz RC Oscillator Version Register 0x3F4 32 read-only 0x00000100 VERSION Version number 0 12 read-only VARIANT Variant number 16 4 read-only OSC32IFAVERSION 32 KHz Oscillator Version Register 0x3F8 32 read-only 0x00000200 VERSION Version number 0 12 VARIANT Variant nubmer 16 4 VERSION BSCIF Version Register 0x3FC 32 read-only 0x00000100 VERSION Version Number 0 12 VARIANT Variant Number 16 4 CATB 1.0.0 Capacitive Touch Module B CATB CATB_ 0x40070000 0 0x400 registers CATB_INTREQ 75 CR Control Register 0x00 32 EN Module Enable 0 1 RUN Start Operation 1 1 IIDLE Initialize Idle Value 2 1 ETRIG Event Triggered Operation 3 1 INTRES Internal Resistors 4 1 CKSEL Clock Select 5 1 DIFF Differential Mode 6 1 DMAEN DMA Enable 7 1 ESAMPLES Number of Event Samples 8 7 CHARGET Charge Time 16 4 SWRST Software Reset 31 1 CNTCR Counter Control Register 0x04 32 TOP Counter Top Value 0 24 SPREAD Spread Spectrum 24 4 REPEAT Repeat Measurements 28 3 IDLE Sensor Idle Level 0x08 32 FIDLE Fractional Sensor Idle 0 12 RIDLE Integer Sensor Idle 12 16 LEVEL Sensor Relative Level 0x0C 32 read-only FLEVEL Fractional Sensor Level 0 12 read-only RLEVEL Integer Sensor Level 12 8 read-only RAW Sensor Raw Value 0x10 32 read-only RAWA Current Sensor Raw Value 16 8 read-only RAWB Last Sensor Raw Value 24 8 read-only TIMING Filter Timing Register 0x14 32 TLEVEL Relative Level Smoothing 0 12 TIDLE Idle Smoothening 16 12 THRESH Threshold Register 0x18 32 FTHRESH Fractional part of Threshold Value 0 12 RTHRESH Rational part of Threshold Value 12 8 DIR Threshold Direction 23 1 LENGTH Threshold Length 24 5 PINSEL Pin Selection Register 0x1C 32 PINSEL Pin Select 0 8 DMA Direct Memory Access Register 0x20 32 DMA Direct Memory Access 0 32 ISR Interrupt Status Register 0x24 32 read-only SAMPLE Sample Ready Interrupt Status 0 1 read-only INTCH In-touch Interrupt Status 1 1 read-only OUTTCH Out-of-Touch Interrupt Status 2 1 read-only IER Interrupt Enable Register 0x28 32 write-only SAMPLE Sample Ready Interrupt Enable 0 1 write-only INTCH In-touch Interrupt Enable 1 1 write-only OUTTCH Out-of-Touch Interrupt Enable 2 1 write-only IDR Interrupt Disable Register 0x2C 32 write-only SAMPLE Sample Ready Interrupt Disable 0 1 write-only INTCH In-touch Interrupt Disable 1 1 write-only OUTTCH Out-of-Touch Interrupt Disable 2 1 write-only IMR Interrupt Mask Register 0x30 32 read-only SAMPLE Sample Ready Interrupt Mask 0 1 read-only INTCH In-touch Interrupt Mask 1 1 read-only OUTTCH Out-of-Touch Interrupt Mask 2 1 read-only SCR Status Clear Register 0x34 32 write-only SAMPLE Sample Ready 0 1 write-only INTCH In-touch 1 1 write-only OUTTCH Out-of-Touch 2 1 write-only 1 0x4 INTCH%s In-Touch Status Register 0x40 32 read-only INTCH In-Touch 0 32 read-only 1 0x4 INTCHCLR%s In-Touch Status Clear Register 0x50 32 write-only INTCHCLR In-Touch Clear 0 32 write-only 1 0x4 OUTTCH%s Out-of-Touch Status Register 0x60 32 read-only OUTTCH Out-of-Touch 0 32 read-only 1 0x4 OUTTCHCLR%s Out-of-Touch Status Clear Register 0x70 32 write-only OUTTCHCLR Out of Touch 0 32 write-only PARAMETER Parameter Register 0xF8 32 read-only NPINS Number of Pins 0 8 read-only NSTATUS Number of Status bits 8 8 read-only FRACTIONAL Number of Fractional bits 16 4 read-only VERSION Version Register 0xFC 32 read-only 0x00000100 VERSION Version number 0 12 read-only VARIANT Variant number 16 4 read-only CHIPID 1.0.0 Chip ID Registers CHIPID CHIPID_ 0x400E0400 0 0x400 registers CIDR Chip ID Register 0x340 32 read-only 0xAB0A09E0 EXID Chip ID Extension Register 0x344 32 read-only 0x0400000F CRCCU 2.0.2 CRC Calculation Unit CRCCU CRCCU_ 0x400A4000 0 0x400 registers CRCCU_INTREQ 17 DSCR Descriptor Base Register 0x00 32 DSCR Description Base Address 9 23 DMAEN DMA Enable Register 0x08 32 write-only DMAEN DMA Enable 0 1 write-only DMADIS DMA Disable Register 0x0C 32 write-only DMADIS DMA Disable 0 1 write-only DMASR DMA Status Register 0x10 32 read-only DMASR DMA Channel Status 0 1 read-only DMAIER DMA Interrupt Enable Register 0x14 32 write-only DMAIER DMA Interrupt Enable 0 1 write-only DMAIDR DMA Interrupt Disable Register 0x18 32 write-only DMAIDR DMA Interrupt Disable 0 1 write-only DMAIMR DMA Interrupt Mask Register 0x1C 32 read-only DMAIMR DMA Interrupt Mask 0 1 write-only DMAISR DMA Interrupt Status Register 0x20 32 read-only DMAISR DMA Interrupt Status 0 1 read-only CR Control Register 0x34 32 write-only RESET Reset CRCComputation 0 1 write-only MR Mode Register 0x38 32 ENABLE CRC Computation Enable 0 1 COMPARE CRC Compare 1 1 PTYPE Polynomial Type 2 2 PTYPESelect CCITT8023 0x0 CASTAGNOLI 0x1 CCITT16 0x2 DIVIDER Bandwidth Divider 4 4 SR Status Register 0x3C 32 read-only 0xFFFFFFFF CRC Cyclic Redundancy Check Value 0 32 read-only IER Interrupt Enable Register 0x40 32 write-only ERRIER CRC Error Interrupt Enable 0 1 write-only IDR Interrupt Disable Register 0x44 32 write-only ERRIDR CRC Error Interrupt Disable 0 1 write-only IMR Interrupt Mask Register 0x48 32 read-only ERRIMR CRC Error Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x4C 32 read-only ERRISR CRC Error Interrupt Status 0 1 read-only VERSION Version Register 0xFC 32 read-only 0x00000202 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only DACC 1.1.1 DAC Controller DACC DACC_ 0x4003C000 0 0x400 registers DACC_INTREQ 70 CR Control Register 0x00 32 write-only SWRST Software Reset 0 1 write-only MR Mode Register 0x04 32 TRGEN Trigger Enable 0 1 TRGSEL Trigger Selection 1 3 DACEN DAC Enable 4 1 WORD Word Transfer 5 1 STARTUP Startup Time Selection 8 8 CLKDIV Clock Divider for Internal Trigger 16 16 CDR Conversion Data Register 0x08 32 write-only DATA Data to Convert 0 32 write-only IER Interrupt Enable Register 0x0C 32 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only IDR Interrupt Disable Register 0x10 32 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only IMR Interrupt Mask Register 0x14 32 read-only TXRDY Transmit Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x18 32 read-only TXRDY Transmit Ready Interrupt Status 0 1 read-only WPMR Write Protect Mode Register 0xE4 32 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only WPROTERR Write Protection Error 0 1 read-only WPROTADDR Write Protection Error Address 8 8 read-only VERSION Version Register 0xFC 32 read-only 0x00000111 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 3 read-only EIC 3.0.2 External Interrupt Controller EIC EIC_ 0x400F1000 0 0x400 registers EIC_INTREQ_0 45 EIC_INTREQ_1 46 EIC_INTREQ_2 47 EIC_INTREQ_3 48 EIC_INTREQ_4 49 EIC_INTREQ_5 50 EIC_INTREQ_6 51 EIC_INTREQ_7 52 IER Interrupt Enable Register 0x000 32 write-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 IDR Interrupt Disable Register 0x004 32 write-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 IMR Interrupt Mask Register 0x008 32 read-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 ISR Interrupt Status Register 0x00C 32 read-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 ICR Interrupt Clear Register 0x010 32 write-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 MODE Mode Register 0x014 32 NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 EDGE Edge Register 0x018 32 NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT1Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT2 External Interrupt 2 2 1 INT2Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 LEVEL Level Register 0x01C 32 NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 FILTER Filter Register 0x020 32 NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 ASYNC Asynchronous Register 0x028 32 NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 EN Enable Register 0x030 32 write-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 DIS Disable Register 0x034 32 write-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 CTRL Control Register 0x038 32 read-only NMI External Non Maskable CPU interrupt 0 1 INT1 External Interrupt 1 1 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 VERSION Version Register 0x3FC 32 read-only 0x00000302 VERSION Version bits 0 12 HFLASHC 1.1.0 Flash Controller FLASHCALW FLASHCALW_ 0x400A0000 0 0x400 registers HFLASHC_INTREQ 0 FCR Flash Controller Control Register 0x00 32 FRDY Flash Ready Interrupt Enable 0 1 FRDYSelect 0 Flash Ready does not generate an interrupt 0x0 1 Flash Ready generates an interrupt 0x1 LOCKE Lock Error Interrupt Enable 2 1 LOCKESelect 0 Lock Error does not generate an interrupt 0x0 1 Lock Error generates an interrupt 0x1 PROGE Programming Error Interrupt Enable 3 1 PROGESelect 0 Programming Error does not generate an interrupt 0x0 1 Programming Error generates an interrupt 0x1 FWS Flash Wait State 6 1 FWSSelect 0 The flash is read with 0 wait states 0x0 1 The flash is read with 1 wait states 0x1 WS1OPT Wait State 1 Optimization 7 1 FCMD Flash Controller Command Register 0x04 32 CMD Command 0 6 CMDSelect NOP No Operation 0x0 WP Write Page 0x1 EP Erase Page 0x2 CPB Clear Page Buffer 0x3 LP Lock Region containing page 0x4 UP Unlock Region containing page 0x5 EA Erase All, including secuity and fuse bits 0x6 WGPB Write General-Purpose fuse Bit 0x7 EGPB Erase General-Purpose fuse Bit 0x8 SSB Set Security Bit 0x9 PGPFB Program GPFuse Byte 0xa EAGPF Erase All GP Fuses 0xb QPR Quick Page Read 0xc WUP Write User Page 0xd EUP Erase User Page 0xe QPRUP Quick Page Read User Page 0xf HSEN High Speed Mode Enable 0x10 HSDIS High Speed Mode Disable 0x11 PAGEN Page number 8 16 KEY Write protection key 24 8 KEYSelect KEY 0xa5 FSR Flash Controller Status Register 0x08 32 FRDY Flash Ready Status 0 1 read-only LOCKE Lock Error Status 2 1 read-only PROGE Programming Error Status 3 1 read-only SECURITY Security Bit Status 4 1 read-only QPRR Quick Page Read Result 5 1 read-only HSMODE High Speed Mode 6 1 read-only ECCERR ECC Error Status 8 2 read-only ECCERRSelect NOERROR no error 0x0 ONEECCERR one ECC error detected 0x1 TWOECCERR two ECC errors detected 0x2 LOCK0 Lock Region 0 Lock Status 16 1 read-only LOCK1 Lock Region 1 Lock Status 17 1 read-only LOCK2 Lock Region 2 Lock Status 18 1 read-only LOCK3 Lock Region 3 Lock Status 19 1 read-only LOCK4 Lock Region 4 Lock Status 20 1 read-only LOCK5 Lock Region 5 Lock Status 21 1 read-only LOCK6 Lock Region 6 Lock Status 22 1 read-only LOCK7 Lock Region 7 Lock Status 23 1 read-only LOCK8 Lock Region 8 Lock Status 24 1 read-only LOCK9 Lock Region 9 Lock Status 25 1 read-only LOCK10 Lock Region 10 Lock Status 26 1 read-only LOCK11 Lock Region 11 Lock Status 27 1 read-only LOCK12 Lock Region 12 Lock Status 28 1 read-only LOCK13 Lock Region 13 Lock Status 29 1 read-only LOCK14 Lock Region 14 Lock Status 30 1 read-only LOCK15 Lock Region 15 Lock Status 31 1 read-only FPR Flash Controller Parameter Register 0x0C 32 read-only FSZ Flash Size 0 4 read-only PSZ Page Size 8 3 read-only VERSION Flash Controller Version Register 0x10 32 read-only 0x00000110 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only FGPFRHI Flash Controller General Purpose Fuse Register High 0x14 32 GPF32 General Purpose Fuse 32 0 1 read-only GPF33 General Purpose Fuse 33 1 1 read-only GPF34 General Purpose Fuse 34 2 1 read-only GPF35 General Purpose Fuse 35 3 1 read-only GPF36 General Purpose Fuse 36 4 1 read-only GPF37 General Purpose Fuse 37 5 1 read-only GPF38 General Purpose Fuse 38 6 1 read-only GPF39 General Purpose Fuse 39 7 1 read-only GPF40 General Purpose Fuse 40 8 1 read-only GPF41 General Purpose Fuse 41 9 1 read-only GPF42 General Purpose Fuse 42 10 1 read-only GPF43 General Purpose Fuse 43 11 1 read-only GPF44 General Purpose Fuse 44 12 1 read-only GPF45 General Purpose Fuse 45 13 1 read-only GPF46 General Purpose Fuse 46 14 1 read-only GPF47 General Purpose Fuse 47 15 1 read-only GPF48 General Purpose Fuse 48 16 1 read-only GPF49 General Purpose Fuse 49 17 1 read-only GPF50 General Purpose Fuse 50 18 1 read-only GPF51 General Purpose Fuse 51 19 1 read-only GPF52 General Purpose Fuse 52 20 1 read-only GPF53 General Purpose Fuse 53 21 1 read-only GPF54 General Purpose Fuse 54 22 1 read-only GPF55 General Purpose Fuse 55 23 1 read-only GPF56 General Purpose Fuse 56 24 1 read-only GPF57 General Purpose Fuse 57 25 1 read-only GPF58 General Purpose Fuse 58 26 1 read-only GPF59 General Purpose Fuse 59 27 1 read-only GPF60 General Purpose Fuse 60 28 1 read-only GPF61 General Purpose Fuse 61 29 1 read-only GPF62 General Purpose Fuse 62 30 1 read-only GPF63 General Purpose Fuse 63 31 1 read-only FGPFRLO Flash Controller General Purpose Fuse Register Low 0x18 32 LOCK0 Lock Bit 0 0 1 read-only LOCK1 Lock Bit 1 1 1 read-only LOCK2 Lock Bit 2 2 1 read-only LOCK3 Lock Bit 3 3 1 read-only LOCK4 Lock Bit 4 4 1 read-only LOCK5 Lock Bit 5 5 1 read-only LOCK6 Lock Bit 6 6 1 read-only LOCK7 Lock Bit 7 7 1 read-only LOCK8 Lock Bit 8 8 1 read-only LOCK9 Lock Bit 9 9 1 read-only LOCK10 Lock Bit 10 10 1 read-only LOCK11 Lock Bit 11 11 1 read-only LOCK12 Lock Bit 12 12 1 read-only LOCK13 Lock Bit 13 13 1 read-only LOCK14 Lock Bit 14 14 1 read-only LOCK15 Lock Bit 15 15 1 read-only GPF16 General Purpose Fuse 16 16 1 read-only GPF17 General Purpose Fuse 17 17 1 read-only GPF18 General Purpose Fuse 18 18 1 read-only GPF19 General Purpose Fuse 19 19 1 read-only GPF20 General Purpose Fuse 20 20 1 read-only GPF21 General Purpose Fuse 21 21 1 read-only GPF22 General Purpose Fuse 22 22 1 read-only GPF23 General Purpose Fuse 23 23 1 read-only GPF24 General Purpose Fuse 24 24 1 read-only GPF25 General Purpose Fuse 25 25 1 read-only GPF26 General Purpose Fuse 26 26 1 read-only GPF27 General Purpose Fuse 27 27 1 read-only GPF28 General Purpose Fuse 28 28 1 read-only GPF29 General Purpose Fuse 29 29 1 read-only GPF30 General Purpose Fuse 30 30 1 read-only GPF31 General Purpose Fuse 31 31 1 read-only FREQM 3.1.1 Frequency Meter FREQM FREQM_ 0x400E0C00 0 0x400 registers FREQM_INTREQ 24 CTRL Control register 0x000 32 write-only START Start frequency measurement 0 1 write-only MODE Mode register 0x004 32 REFSEL Reference Clock Selection 0 2 REFNUM Number of Reference CLock Cycles 8 8 CLKSEL Clock Source Selection 16 5 REFCEN Reference Clock Enable 31 1 STATUS Status register 0x008 32 read-only BUSY Frequency measurement on-going 0 1 RCLKBUSY Reference Clock busy 1 1 VALUE Value register 0x00C 32 read-only VALUE Measured frequency 0 24 IER Interrupt Enable Register 0x010 32 write-only DONE Frequency measurment done 0 1 write-only RCLKRDY Reference Clock ready 1 1 IDR Interrupt Diable Register 0x014 32 write-only DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 IMR Interrupt Mask Register 0x018 32 read-only DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 ISR Interrupt Status Register 0x01C 32 read-only DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 ICR Interrupt Clear Register 0x020 32 write-only DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 VERSION Version Register 0x3FC 32 read-only 0x00000311 VERSION Version number 0 12 VARIANT Variant number 16 4 GLOC 1.0.2 Glue Logic Controller GLOC GLOC_ 0x40060000 0 0x400 registers 2 0x8 CR%s Control Register 0x00 32 AEN Input mask 0 4 FILTEN Filter enable 31 1 2 0x8 TRUTH%s Truth Register 0x04 32 TRUTH Truth 0 16 PARAMETER Parameter Register 0x38 32 read-only LUTS LUTs 0 8 VERSION Version Register 0x3C 32 read-only 0x00000102 VERSION Version 0 12 VARIANT Variant 16 4 GPIO 2.1.5 General-Purpose Input/Output Controller GPIO GPIO_ 0x400E1000 0 0x1000 registers GPIO_INTREQ_0 25 GPIO_INTREQ_1 26 GPIO_INTREQ_2 27 GPIO_INTREQ_3 28 GPIO_INTREQ_4 29 GPIO_INTREQ_5 30 GPIO_INTREQ_6 31 GPIO_INTREQ_7 32 GPIO_INTREQ_8 33 GPIO_INTREQ_9 34 GPIO_INTREQ_10 35 GPIO_INTREQ_11 36 3 0x200 GPER%s GPIO Enable Register 0x000 32 P0 GPIO Enable 0 1 P1 GPIO Enable 1 1 P2 GPIO Enable 2 1 P3 GPIO Enable 3 1 P4 GPIO Enable 4 1 P5 GPIO Enable 5 1 P6 GPIO Enable 6 1 P7 GPIO Enable 7 1 P8 GPIO Enable 8 1 P9 GPIO Enable 9 1 P10 GPIO Enable 10 1 P11 GPIO Enable 11 1 P12 GPIO Enable 12 1 P13 GPIO Enable 13 1 P14 GPIO Enable 14 1 P15 GPIO Enable 15 1 P16 GPIO Enable 16 1 P17 GPIO Enable 17 1 P18 GPIO Enable 18 1 P19 GPIO Enable 19 1 P20 GPIO Enable 20 1 P21 GPIO Enable 21 1 P22 GPIO Enable 22 1 P23 GPIO Enable 23 1 P24 GPIO Enable 24 1 P25 GPIO Enable 25 1 P26 GPIO Enable 26 1 P27 GPIO Enable 27 1 P28 GPIO Enable 28 1 P29 GPIO Enable 29 1 P30 GPIO Enable 30 1 P31 GPIO Enable 31 1 3 0x200 GPERS%s GPIO Enable Register - Set 0x004 32 write-only P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P2 GPIO Enable 2 1 write-only P3 GPIO Enable 3 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only 3 0x200 GPERC%s GPIO Enable Register - Clear 0x008 32 write-only P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P2 GPIO Enable 2 1 write-only P3 GPIO Enable 3 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only 3 0x200 GPERT%s GPIO Enable Register - Toggle 0x00C 32 write-only P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P2 GPIO Enable 2 1 write-only P3 GPIO Enable 3 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only 3 0x200 PMR0%s Peripheral Mux Register 0 0x010 32 P0 Peripheral Multiplexer Select bit 0 0 1 P1 Peripheral Multiplexer Select bit 0 1 1 P2 Peripheral Multiplexer Select bit 0 2 1 P3 Peripheral Multiplexer Select bit 0 3 1 P4 Peripheral Multiplexer Select bit 0 4 1 P5 Peripheral Multiplexer Select bit 0 5 1 P6 Peripheral Multiplexer Select bit 0 6 1 P7 Peripheral Multiplexer Select bit 0 7 1 P8 Peripheral Multiplexer Select bit 0 8 1 P9 Peripheral Multiplexer Select bit 0 9 1 P10 Peripheral Multiplexer Select bit 0 10 1 P11 Peripheral Multiplexer Select bit 0 11 1 P12 Peripheral Multiplexer Select bit 0 12 1 P13 Peripheral Multiplexer Select bit 0 13 1 P14 Peripheral Multiplexer Select bit 0 14 1 P15 Peripheral Multiplexer Select bit 0 15 1 P16 Peripheral Multiplexer Select bit 0 16 1 P17 Peripheral Multiplexer Select bit 0 17 1 P18 Peripheral Multiplexer Select bit 0 18 1 P19 Peripheral Multiplexer Select bit 0 19 1 P20 Peripheral Multiplexer Select bit 0 20 1 P21 Peripheral Multiplexer Select bit 0 21 1 P22 Peripheral Multiplexer Select bit 0 22 1 P23 Peripheral Multiplexer Select bit 0 23 1 P24 Peripheral Multiplexer Select bit 0 24 1 P25 Peripheral Multiplexer Select bit 0 25 1 P26 Peripheral Multiplexer Select bit 0 26 1 P27 Peripheral Multiplexer Select bit 0 27 1 P28 Peripheral Multiplexer Select bit 0 28 1 P29 Peripheral Multiplexer Select bit 0 29 1 P30 Peripheral Multiplexer Select bit 0 30 1 P31 Peripheral Multiplexer Select bit 0 31 1 3 0x200 PMR0S%s Peripheral Mux Register 0 - Set 0x014 32 write-only P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only 3 0x200 PMR0C%s Peripheral Mux Register 0 - Clear 0x018 32 write-only P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only 3 0x200 PMR0T%s Peripheral Mux Register 0 - Toggle 0x01C 32 write-only P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only 3 0x200 PMR1%s Peripheral Mux Register 1 0x020 32 P0 Peripheral Multiplexer Select bit 1 0 1 P1 Peripheral Multiplexer Select bit 1 1 1 P2 Peripheral Multiplexer Select bit 1 2 1 P3 Peripheral Multiplexer Select bit 1 3 1 P4 Peripheral Multiplexer Select bit 1 4 1 P5 Peripheral Multiplexer Select bit 1 5 1 P6 Peripheral Multiplexer Select bit 1 6 1 P7 Peripheral Multiplexer Select bit 1 7 1 P8 Peripheral Multiplexer Select bit 1 8 1 P9 Peripheral Multiplexer Select bit 1 9 1 P10 Peripheral Multiplexer Select bit 1 10 1 P11 Peripheral Multiplexer Select bit 1 11 1 P12 Peripheral Multiplexer Select bit 1 12 1 P13 Peripheral Multiplexer Select bit 1 13 1 P14 Peripheral Multiplexer Select bit 1 14 1 P15 Peripheral Multiplexer Select bit 1 15 1 P16 Peripheral Multiplexer Select bit 1 16 1 P17 Peripheral Multiplexer Select bit 1 17 1 P18 Peripheral Multiplexer Select bit 1 18 1 P19 Peripheral Multiplexer Select bit 1 19 1 P20 Peripheral Multiplexer Select bit 1 20 1 P21 Peripheral Multiplexer Select bit 1 21 1 P22 Peripheral Multiplexer Select bit 1 22 1 P23 Peripheral Multiplexer Select bit 1 23 1 P24 Peripheral Multiplexer Select bit 1 24 1 P25 Peripheral Multiplexer Select bit 1 25 1 P26 Peripheral Multiplexer Select bit 1 26 1 P27 Peripheral Multiplexer Select bit 1 27 1 P28 Peripheral Multiplexer Select bit 1 28 1 P29 Peripheral Multiplexer Select bit 1 29 1 P30 Peripheral Multiplexer Select bit 1 30 1 P31 Peripheral Multiplexer Select bit 1 31 1 3 0x200 PMR1S%s Peripheral Mux Register 1 - Set 0x024 32 write-only P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only 3 0x200 PMR1C%s Peripheral Mux Register 1 - Clear 0x028 32 write-only P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only 3 0x200 PMR1T%s Peripheral Mux Register 1 - Toggle 0x02C 32 write-only P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only 3 0x200 PMR2%s Peripheral Mux Register 2 0x030 32 P0 Peripheral Multiplexer Select bit 2 0 1 P1 Peripheral Multiplexer Select bit 2 1 1 P2 Peripheral Multiplexer Select bit 2 2 1 P3 Peripheral Multiplexer Select bit 2 3 1 P4 Peripheral Multiplexer Select bit 2 4 1 P5 Peripheral Multiplexer Select bit 2 5 1 P6 Peripheral Multiplexer Select bit 2 6 1 P7 Peripheral Multiplexer Select bit 2 7 1 P8 Peripheral Multiplexer Select bit 2 8 1 P9 Peripheral Multiplexer Select bit 2 9 1 P10 Peripheral Multiplexer Select bit 2 10 1 P11 Peripheral Multiplexer Select bit 2 11 1 P12 Peripheral Multiplexer Select bit 2 12 1 P13 Peripheral Multiplexer Select bit 2 13 1 P14 Peripheral Multiplexer Select bit 2 14 1 P15 Peripheral Multiplexer Select bit 2 15 1 P16 Peripheral Multiplexer Select bit 2 16 1 P17 Peripheral Multiplexer Select bit 2 17 1 P18 Peripheral Multiplexer Select bit 2 18 1 P19 Peripheral Multiplexer Select bit 2 19 1 P20 Peripheral Multiplexer Select bit 2 20 1 P21 Peripheral Multiplexer Select bit 2 21 1 P22 Peripheral Multiplexer Select bit 2 22 1 P23 Peripheral Multiplexer Select bit 2 23 1 P24 Peripheral Multiplexer Select bit 2 24 1 P25 Peripheral Multiplexer Select bit 2 25 1 P26 Peripheral Multiplexer Select bit 2 26 1 P27 Peripheral Multiplexer Select bit 2 27 1 P28 Peripheral Multiplexer Select bit 2 28 1 P29 Peripheral Multiplexer Select bit 2 29 1 P30 Peripheral Multiplexer Select bit 2 30 1 P31 Peripheral Multiplexer Select bit 2 31 1 3 0x200 PMR2S%s Peripheral Mux Register 2 - Set 0x034 32 write-only P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only 3 0x200 PMR2C%s Peripheral Mux Register 2 - Clear 0x038 32 write-only P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only 3 0x200 PMR2T%s Peripheral Mux Register 2 - Toggle 0x03C 32 write-only P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only 3 0x200 ODER%s Output Driver Enable Register 0x040 32 P0 Output Driver Enable 0 1 P1 Output Driver Enable 1 1 P2 Output Driver Enable 2 1 P3 Output Driver Enable 3 1 P4 Output Driver Enable 4 1 P5 Output Driver Enable 5 1 P6 Output Driver Enable 6 1 P7 Output Driver Enable 7 1 P8 Output Driver Enable 8 1 P9 Output Driver Enable 9 1 P10 Output Driver Enable 10 1 P11 Output Driver Enable 11 1 P12 Output Driver Enable 12 1 P13 Output Driver Enable 13 1 P14 Output Driver Enable 14 1 P15 Output Driver Enable 15 1 P16 Output Driver Enable 16 1 P17 Output Driver Enable 17 1 P18 Output Driver Enable 18 1 P19 Output Driver Enable 19 1 P20 Output Driver Enable 20 1 P21 Output Driver Enable 21 1 P22 Output Driver Enable 22 1 P23 Output Driver Enable 23 1 P24 Output Driver Enable 24 1 P25 Output Driver Enable 25 1 P26 Output Driver Enable 26 1 P27 Output Driver Enable 27 1 P28 Output Driver Enable 28 1 P29 Output Driver Enable 29 1 P30 Output Driver Enable 30 1 P31 Output Driver Enable 31 1 3 0x200 ODERS%s Output Driver Enable Register - Set 0x044 32 write-only P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P2 Output Driver Enable 2 1 write-only P3 Output Driver Enable 3 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only 3 0x200 ODERC%s Output Driver Enable Register - Clear 0x048 32 write-only P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P2 Output Driver Enable 2 1 write-only P3 Output Driver Enable 3 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only 3 0x200 ODERT%s Output Driver Enable Register - Toggle 0x04C 32 write-only P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P2 Output Driver Enable 2 1 write-only P3 Output Driver Enable 3 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only 3 0x200 OVR%s Output Value Register 0x050 32 P0 Output Value 0 1 P1 Output Value 1 1 P2 Output Value 2 1 P3 Output Value 3 1 P4 Output Value 4 1 P5 Output Value 5 1 P6 Output Value 6 1 P7 Output Value 7 1 P8 Output Value 8 1 P9 Output Value 9 1 P10 Output Value 10 1 P11 Output Value 11 1 P12 Output Value 12 1 P13 Output Value 13 1 P14 Output Value 14 1 P15 Output Value 15 1 P16 Output Value 16 1 P17 Output Value 17 1 P18 Output Value 18 1 P19 Output Value 19 1 P20 Output Value 20 1 P21 Output Value 21 1 P22 Output Value 22 1 P23 Output Value 23 1 P24 Output Value 24 1 P25 Output Value 25 1 P26 Output Value 26 1 P27 Output Value 27 1 P28 Output Value 28 1 P29 Output Value 29 1 P30 Output Value 30 1 P31 Output Value 31 1 3 0x200 OVRS%s Output Value Register - Set 0x054 32 write-only P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P2 Output Value 2 1 write-only P3 Output Value 3 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only 3 0x200 OVRC%s Output Value Register - Clear 0x058 32 write-only P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P2 Output Value 2 1 write-only P3 Output Value 3 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only 3 0x200 OVRT%s Output Value Register - Toggle 0x05C 32 write-only P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P2 Output Value 2 1 write-only P3 Output Value 3 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only 3 0x200 PVR%s Pin Value Register 0x060 32 read-only P0 Pin Value 0 1 read-only P1 Pin Value 1 1 read-only P2 Pin Value 2 1 read-only P3 Pin Value 3 1 read-only P4 Pin Value 4 1 read-only P5 Pin Value 5 1 read-only P6 Pin Value 6 1 read-only P7 Pin Value 7 1 read-only P8 Pin Value 8 1 read-only P9 Pin Value 9 1 read-only P10 Pin Value 10 1 read-only P11 Pin Value 11 1 read-only P12 Pin Value 12 1 read-only P13 Pin Value 13 1 read-only P14 Pin Value 14 1 read-only P15 Pin Value 15 1 read-only P16 Pin Value 16 1 read-only P17 Pin Value 17 1 read-only P18 Pin Value 18 1 read-only P19 Pin Value 19 1 read-only P20 Pin Value 20 1 read-only P21 Pin Value 21 1 read-only P22 Pin Value 22 1 read-only P23 Pin Value 23 1 read-only P24 Pin Value 24 1 read-only P25 Pin Value 25 1 read-only P26 Pin Value 26 1 read-only P27 Pin Value 27 1 read-only P28 Pin Value 28 1 read-only P29 Pin Value 29 1 read-only P30 Pin Value 30 1 read-only P31 Pin Value 31 1 read-only 3 0x200 PUER%s Pull-up Enable Register 0x070 32 P0 Pull-up Enable 0 1 P1 Pull-up Enable 1 1 P2 Pull-up Enable 2 1 P3 Pull-up Enable 3 1 P4 Pull-up Enable 4 1 P5 Pull-up Enable 5 1 P6 Pull-up Enable 6 1 P7 Pull-up Enable 7 1 P8 Pull-up Enable 8 1 P9 Pull-up Enable 9 1 P10 Pull-up Enable 10 1 P11 Pull-up Enable 11 1 P12 Pull-up Enable 12 1 P13 Pull-up Enable 13 1 P14 Pull-up Enable 14 1 P15 Pull-up Enable 15 1 P16 Pull-up Enable 16 1 P17 Pull-up Enable 17 1 P18 Pull-up Enable 18 1 P19 Pull-up Enable 19 1 P20 Pull-up Enable 20 1 P21 Pull-up Enable 21 1 P22 Pull-up Enable 22 1 P23 Pull-up Enable 23 1 P24 Pull-up Enable 24 1 P25 Pull-up Enable 25 1 P26 Pull-up Enable 26 1 P27 Pull-up Enable 27 1 P28 Pull-up Enable 28 1 P29 Pull-up Enable 29 1 P30 Pull-up Enable 30 1 P31 Pull-up Enable 31 1 3 0x200 PUERS%s Pull-up Enable Register - Set 0x074 32 write-only P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P2 Pull-up Enable 2 1 write-only P3 Pull-up Enable 3 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only 3 0x200 PUERC%s Pull-up Enable Register - Clear 0x078 32 write-only P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P2 Pull-up Enable 2 1 write-only P3 Pull-up Enable 3 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only 3 0x200 PUERT%s Pull-up Enable Register - Toggle 0x07C 32 write-only P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P2 Pull-up Enable 2 1 write-only P3 Pull-up Enable 3 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only 3 0x200 PDER%s Pull-down Enable Register 0x080 32 P0 Pull-down Enable 0 1 P1 Pull-down Enable 1 1 P2 Pull-down Enable 2 1 P3 Pull-down Enable 3 1 P4 Pull-down Enable 4 1 P5 Pull-down Enable 5 1 P6 Pull-down Enable 6 1 P7 Pull-down Enable 7 1 P8 Pull-down Enable 8 1 P9 Pull-down Enable 9 1 P10 Pull-down Enable 10 1 P11 Pull-down Enable 11 1 P12 Pull-down Enable 12 1 P13 Pull-down Enable 13 1 P14 Pull-down Enable 14 1 P15 Pull-down Enable 15 1 P16 Pull-down Enable 16 1 P17 Pull-down Enable 17 1 P18 Pull-down Enable 18 1 P19 Pull-down Enable 19 1 P20 Pull-down Enable 20 1 P21 Pull-down Enable 21 1 P22 Pull-down Enable 22 1 P23 Pull-down Enable 23 1 P24 Pull-down Enable 24 1 P25 Pull-down Enable 25 1 P26 Pull-down Enable 26 1 P27 Pull-down Enable 27 1 P28 Pull-down Enable 28 1 P29 Pull-down Enable 29 1 P30 Pull-down Enable 30 1 P31 Pull-down Enable 31 1 3 0x200 PDERS%s Pull-down Enable Register - Set 0x084 32 write-only P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P2 Pull-down Enable 2 1 write-only P3 Pull-down Enable 3 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only 3 0x200 PDERC%s Pull-down Enable Register - Clear 0x088 32 write-only P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P2 Pull-down Enable 2 1 write-only P3 Pull-down Enable 3 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only 3 0x200 PDERT%s Pull-down Enable Register - Toggle 0x08C 32 write-only P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P2 Pull-down Enable 2 1 write-only P3 Pull-down Enable 3 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only 3 0x200 IER%s Interrupt Enable Register 0x090 32 P0 Interrupt Enable 0 1 P1 Interrupt Enable 1 1 P2 Interrupt Enable 2 1 P3 Interrupt Enable 3 1 P4 Interrupt Enable 4 1 P5 Interrupt Enable 5 1 P6 Interrupt Enable 6 1 P7 Interrupt Enable 7 1 P8 Interrupt Enable 8 1 P9 Interrupt Enable 9 1 P10 Interrupt Enable 10 1 P11 Interrupt Enable 11 1 P12 Interrupt Enable 12 1 P13 Interrupt Enable 13 1 P14 Interrupt Enable 14 1 P15 Interrupt Enable 15 1 P16 Interrupt Enable 16 1 P17 Interrupt Enable 17 1 P18 Interrupt Enable 18 1 P19 Interrupt Enable 19 1 P20 Interrupt Enable 20 1 P21 Interrupt Enable 21 1 P22 Interrupt Enable 22 1 P23 Interrupt Enable 23 1 P24 Interrupt Enable 24 1 P25 Interrupt Enable 25 1 P26 Interrupt Enable 26 1 P27 Interrupt Enable 27 1 P28 Interrupt Enable 28 1 P29 Interrupt Enable 29 1 P30 Interrupt Enable 30 1 P31 Interrupt Enable 31 1 3 0x200 IERS%s Interrupt Enable Register - Set 0x094 32 write-only P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P2 Interrupt Enable 2 1 write-only P3 Interrupt Enable 3 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only 3 0x200 IERC%s Interrupt Enable Register - Clear 0x098 32 write-only P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P2 Interrupt Enable 2 1 write-only P3 Interrupt Enable 3 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only 3 0x200 IERT%s Interrupt Enable Register - Toggle 0x09C 32 write-only P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P2 Interrupt Enable 2 1 write-only P3 Interrupt Enable 3 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only 3 0x200 IMR0%s Interrupt Mode Register 0 0x0A0 32 P0 Interrupt Mode Bit 0 0 1 P1 Interrupt Mode Bit 0 1 1 P2 Interrupt Mode Bit 0 2 1 P3 Interrupt Mode Bit 0 3 1 P4 Interrupt Mode Bit 0 4 1 P5 Interrupt Mode Bit 0 5 1 P6 Interrupt Mode Bit 0 6 1 P7 Interrupt Mode Bit 0 7 1 P8 Interrupt Mode Bit 0 8 1 P9 Interrupt Mode Bit 0 9 1 P10 Interrupt Mode Bit 0 10 1 P11 Interrupt Mode Bit 0 11 1 P12 Interrupt Mode Bit 0 12 1 P13 Interrupt Mode Bit 0 13 1 P14 Interrupt Mode Bit 0 14 1 P15 Interrupt Mode Bit 0 15 1 P16 Interrupt Mode Bit 0 16 1 P17 Interrupt Mode Bit 0 17 1 P18 Interrupt Mode Bit 0 18 1 P19 Interrupt Mode Bit 0 19 1 P20 Interrupt Mode Bit 0 20 1 P21 Interrupt Mode Bit 0 21 1 P22 Interrupt Mode Bit 0 22 1 P23 Interrupt Mode Bit 0 23 1 P24 Interrupt Mode Bit 0 24 1 P25 Interrupt Mode Bit 0 25 1 P26 Interrupt Mode Bit 0 26 1 P27 Interrupt Mode Bit 0 27 1 P28 Interrupt Mode Bit 0 28 1 P29 Interrupt Mode Bit 0 29 1 P30 Interrupt Mode Bit 0 30 1 P31 Interrupt Mode Bit 0 31 1 3 0x200 IMR0S%s Interrupt Mode Register 0 - Set 0x0A4 32 write-only P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only 3 0x200 IMR0C%s Interrupt Mode Register 0 - Clear 0x0A8 32 write-only P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only 3 0x200 IMR0T%s Interrupt Mode Register 0 - Toggle 0x0AC 32 write-only P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only 3 0x200 IMR1%s Interrupt Mode Register 1 0x0B0 32 P0 Interrupt Mode Bit 1 0 1 P1 Interrupt Mode Bit 1 1 1 P2 Interrupt Mode Bit 1 2 1 P3 Interrupt Mode Bit 1 3 1 P4 Interrupt Mode Bit 1 4 1 P5 Interrupt Mode Bit 1 5 1 P6 Interrupt Mode Bit 1 6 1 P7 Interrupt Mode Bit 1 7 1 P8 Interrupt Mode Bit 1 8 1 P9 Interrupt Mode Bit 1 9 1 P10 Interrupt Mode Bit 1 10 1 P11 Interrupt Mode Bit 1 11 1 P12 Interrupt Mode Bit 1 12 1 P13 Interrupt Mode Bit 1 13 1 P14 Interrupt Mode Bit 1 14 1 P15 Interrupt Mode Bit 1 15 1 P16 Interrupt Mode Bit 1 16 1 P17 Interrupt Mode Bit 1 17 1 P18 Interrupt Mode Bit 1 18 1 P19 Interrupt Mode Bit 1 19 1 P20 Interrupt Mode Bit 1 20 1 P21 Interrupt Mode Bit 1 21 1 P22 Interrupt Mode Bit 1 22 1 P23 Interrupt Mode Bit 1 23 1 P24 Interrupt Mode Bit 1 24 1 P25 Interrupt Mode Bit 1 25 1 P26 Interrupt Mode Bit 1 26 1 P27 Interrupt Mode Bit 1 27 1 P28 Interrupt Mode Bit 1 28 1 P29 Interrupt Mode Bit 1 29 1 P30 Interrupt Mode Bit 1 30 1 P31 Interrupt Mode Bit 1 31 1 3 0x200 IMR1S%s Interrupt Mode Register 1 - Set 0x0B4 32 write-only P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only 3 0x200 IMR1C%s Interrupt Mode Register 1 - Clear 0x0B8 32 write-only P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only 3 0x200 IMR1T%s Interrupt Mode Register 1 - Toggle 0x0BC 32 write-only P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only 3 0x200 GFER%s Glitch Filter Enable Register 0x0C0 32 P0 Glitch Filter Enable 0 1 P1 Glitch Filter Enable 1 1 P2 Glitch Filter Enable 2 1 P3 Glitch Filter Enable 3 1 P4 Glitch Filter Enable 4 1 P5 Glitch Filter Enable 5 1 P6 Glitch Filter Enable 6 1 P7 Glitch Filter Enable 7 1 P8 Glitch Filter Enable 8 1 P9 Glitch Filter Enable 9 1 P10 Glitch Filter Enable 10 1 P11 Glitch Filter Enable 11 1 P12 Glitch Filter Enable 12 1 P13 Glitch Filter Enable 13 1 P14 Glitch Filter Enable 14 1 P15 Glitch Filter Enable 15 1 P16 Glitch Filter Enable 16 1 P17 Glitch Filter Enable 17 1 P18 Glitch Filter Enable 18 1 P19 Glitch Filter Enable 19 1 P20 Glitch Filter Enable 20 1 P21 Glitch Filter Enable 21 1 P22 Glitch Filter Enable 22 1 P23 Glitch Filter Enable 23 1 P24 Glitch Filter Enable 24 1 P25 Glitch Filter Enable 25 1 P26 Glitch Filter Enable 26 1 P27 Glitch Filter Enable 27 1 P28 Glitch Filter Enable 28 1 P29 Glitch Filter Enable 29 1 P30 Glitch Filter Enable 30 1 P31 Glitch Filter Enable 31 1 3 0x200 GFERS%s Glitch Filter Enable Register - Set 0x0C4 32 write-only P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P2 Glitch Filter Enable 2 1 write-only P3 Glitch Filter Enable 3 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only 3 0x200 GFERC%s Glitch Filter Enable Register - Clear 0x0C8 32 write-only P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P2 Glitch Filter Enable 2 1 write-only P3 Glitch Filter Enable 3 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only 3 0x200 GFERT%s Glitch Filter Enable Register - Toggle 0x0CC 32 write-only P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P2 Glitch Filter Enable 2 1 write-only P3 Glitch Filter Enable 3 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only 3 0x200 IFR%s Interrupt Flag Register 0x0D0 32 read-only P0 Interrupt Flag 0 1 read-only P1 Interrupt Flag 1 1 read-only P2 Interrupt Flag 2 1 read-only P3 Interrupt Flag 3 1 read-only P4 Interrupt Flag 4 1 read-only P5 Interrupt Flag 5 1 read-only P6 Interrupt Flag 6 1 read-only P7 Interrupt Flag 7 1 read-only P8 Interrupt Flag 8 1 read-only P9 Interrupt Flag 9 1 read-only P10 Interrupt Flag 10 1 read-only P11 Interrupt Flag 11 1 read-only P12 Interrupt Flag 12 1 read-only P13 Interrupt Flag 13 1 read-only P14 Interrupt Flag 14 1 read-only P15 Interrupt Flag 15 1 read-only P16 Interrupt Flag 16 1 read-only P17 Interrupt Flag 17 1 read-only P18 Interrupt Flag 18 1 read-only P19 Interrupt Flag 19 1 read-only P20 Interrupt Flag 20 1 read-only P21 Interrupt Flag 21 1 read-only P22 Interrupt Flag 22 1 read-only P23 Interrupt Flag 23 1 read-only P24 Interrupt Flag 24 1 read-only P25 Interrupt Flag 25 1 read-only P26 Interrupt Flag 26 1 read-only P27 Interrupt Flag 27 1 read-only P28 Interrupt Flag 28 1 read-only P29 Interrupt Flag 29 1 read-only P30 Interrupt Flag 30 1 read-only P31 Interrupt Flag 31 1 read-only 3 0x200 IFRC%s Interrupt Flag Register - Clear 0x0D8 32 write-only P0 Interrupt Flag 0 1 write-only P1 Interrupt Flag 1 1 write-only P2 Interrupt Flag 2 1 write-only P3 Interrupt Flag 3 1 write-only P4 Interrupt Flag 4 1 write-only P5 Interrupt Flag 5 1 write-only P6 Interrupt Flag 6 1 write-only P7 Interrupt Flag 7 1 write-only P8 Interrupt Flag 8 1 write-only P9 Interrupt Flag 9 1 write-only P10 Interrupt Flag 10 1 write-only P11 Interrupt Flag 11 1 write-only P12 Interrupt Flag 12 1 write-only P13 Interrupt Flag 13 1 write-only P14 Interrupt Flag 14 1 write-only P15 Interrupt Flag 15 1 write-only P16 Interrupt Flag 16 1 write-only P17 Interrupt Flag 17 1 write-only P18 Interrupt Flag 18 1 write-only P19 Interrupt Flag 19 1 write-only P20 Interrupt Flag 20 1 write-only P21 Interrupt Flag 21 1 write-only P22 Interrupt Flag 22 1 write-only P23 Interrupt Flag 23 1 write-only P24 Interrupt Flag 24 1 write-only P25 Interrupt Flag 25 1 write-only P26 Interrupt Flag 26 1 write-only P27 Interrupt Flag 27 1 write-only P28 Interrupt Flag 28 1 write-only P29 Interrupt Flag 29 1 write-only P30 Interrupt Flag 30 1 write-only P31 Interrupt Flag 31 1 write-only 3 0x200 ODMER%s Open Drain Mode Register 0x0E0 32 P0 Open Drain Mode Enable 0 1 P1 Open Drain Mode Enable 1 1 P2 Open Drain Mode Enable 2 1 P3 Open Drain Mode Enable 3 1 P4 Open Drain Mode Enable 4 1 P5 Open Drain Mode Enable 5 1 P6 Open Drain Mode Enable 6 1 P7 Open Drain Mode Enable 7 1 P8 Open Drain Mode Enable 8 1 P9 Open Drain Mode Enable 9 1 P10 Open Drain Mode Enable 10 1 P11 Open Drain Mode Enable 11 1 P12 Open Drain Mode Enable 12 1 P13 Open Drain Mode Enable 13 1 P14 Open Drain Mode Enable 14 1 P15 Open Drain Mode Enable 15 1 P16 Open Drain Mode Enable 16 1 P17 Open Drain Mode Enable 17 1 P18 Open Drain Mode Enable 18 1 P19 Open Drain Mode Enable 19 1 P20 Open Drain Mode Enable 20 1 P21 Open Drain Mode Enable 21 1 P22 Open Drain Mode Enable 22 1 P23 Open Drain Mode Enable 23 1 P24 Open Drain Mode Enable 24 1 P25 Open Drain Mode Enable 25 1 P26 Open Drain Mode Enable 26 1 P27 Open Drain Mode Enable 27 1 P28 Open Drain Mode Enable 28 1 P29 Open Drain Mode Enable 29 1 P30 Open Drain Mode Enable 30 1 P31 Open Drain Mode Enable 31 1 3 0x200 ODMERS%s Open Drain Mode Register - Set 0x0E4 32 write-only P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P2 Open Drain Mode Enable 2 1 write-only P3 Open Drain Mode Enable 3 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only 3 0x200 ODMERC%s Open Drain Mode Register - Clear 0x0E8 32 write-only P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P2 Open Drain Mode Enable 2 1 write-only P3 Open Drain Mode Enable 3 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only 3 0x200 ODMERT%s Open Drain Mode Register - Toggle 0x0EC 32 write-only P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P2 Open Drain Mode Enable 2 1 write-only P3 Open Drain Mode Enable 3 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only 3 0x200 ODCR0%s Output Driving Capability Register 0 0x100 32 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P2 Output Driving Capability Register Bit 0 2 1 P3 Output Driving Capability Register Bit 0 3 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 3 0x200 ODCR0S%s Output Driving Capability Register 0 - Set 0x104 32 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P2 Output Driving Capability Register Bit 0 2 1 P3 Output Driving Capability Register Bit 0 3 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 3 0x200 ODCR0C%s Output Driving Capability Register 0 - Clear 0x108 32 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P2 Output Driving Capability Register Bit 0 2 1 P3 Output Driving Capability Register Bit 0 3 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 3 0x200 ODCR0T%s Output Driving Capability Register 0 - Toggle 0x10C 32 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P2 Output Driving Capability Register Bit 0 2 1 P3 Output Driving Capability Register Bit 0 3 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 3 0x200 ODCR1%s Output Driving Capability Register 1 0x110 32 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P2 Output Driving Capability Register Bit 1 2 1 P3 Output Driving Capability Register Bit 1 3 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 3 0x200 ODCR1S%s Output Driving Capability Register 1 - Set 0x114 32 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P2 Output Driving Capability Register Bit 1 2 1 P3 Output Driving Capability Register Bit 1 3 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 3 0x200 ODCR1C%s Output Driving Capability Register 1 - Clear 0x118 32 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P2 Output Driving Capability Register Bit 1 2 1 P3 Output Driving Capability Register Bit 1 3 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 3 0x200 ODCR1T%s Output Driving Capability Register 1 - Toggle 0x11C 32 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P2 Output Driving Capability Register Bit 1 2 1 P3 Output Driving Capability Register Bit 1 3 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 3 0x200 OSRR0%s Output Slew Rate Register 0 0x130 32 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P2 Output Slew Rate Control Enable 2 1 P3 Output Slew Rate Control Enable 3 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 3 0x200 OSRR0S%s Output Slew Rate Register 0 - Set 0x134 32 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P2 Output Slew Rate Control Enable 2 1 P3 Output Slew Rate Control Enable 3 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 3 0x200 OSRR0C%s Output Slew Rate Register 0 - Clear 0x138 32 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P2 Output Slew Rate Control Enable 2 1 P3 Output Slew Rate Control Enable 3 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 3 0x200 OSRR0T%s Output Slew Rate Register 0 - Toggle 0x13C 32 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P2 Output Slew Rate Control Enable 2 1 P3 Output Slew Rate Control Enable 3 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 3 0x200 STER%s Schmitt Trigger Enable Register 0x160 32 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P2 Schmitt Trigger Enable 2 1 P3 Schmitt Trigger Enable 3 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 3 0x200 STERS%s Schmitt Trigger Enable Register - Set 0x164 32 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P2 Schmitt Trigger Enable 2 1 P3 Schmitt Trigger Enable 3 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 3 0x200 STERC%s Schmitt Trigger Enable Register - Clear 0x168 32 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P2 Schmitt Trigger Enable 2 1 P3 Schmitt Trigger Enable 3 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 3 0x200 STERT%s Schmitt Trigger Enable Register - Toggle 0x16C 32 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P2 Schmitt Trigger Enable 2 1 P3 Schmitt Trigger Enable 3 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 3 0x200 EVER%s Event Enable Register 0x180 32 P0 Event Enable 0 1 P1 Event Enable 1 1 P2 Event Enable 2 1 P3 Event Enable 3 1 P4 Event Enable 4 1 P5 Event Enable 5 1 P6 Event Enable 6 1 P7 Event Enable 7 1 P8 Event Enable 8 1 P9 Event Enable 9 1 P10 Event Enable 10 1 P11 Event Enable 11 1 P12 Event Enable 12 1 P13 Event Enable 13 1 P14 Event Enable 14 1 P15 Event Enable 15 1 P16 Event Enable 16 1 P17 Event Enable 17 1 P18 Event Enable 18 1 P19 Event Enable 19 1 P20 Event Enable 20 1 P21 Event Enable 21 1 P22 Event Enable 22 1 P23 Event Enable 23 1 P24 Event Enable 24 1 P25 Event Enable 25 1 P26 Event Enable 26 1 P27 Event Enable 27 1 P28 Event Enable 28 1 P29 Event Enable 29 1 P30 Event Enable 30 1 P31 Event Enable 31 1 3 0x200 EVERS%s Event Enable Register - Set 0x184 32 write-only P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P2 Event Enable 2 1 write-only P3 Event Enable 3 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only 3 0x200 EVERC%s Event Enable Register - Clear 0x188 32 write-only P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P2 Event Enable 2 1 write-only P3 Event Enable 3 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only 3 0x200 EVERT%s Event Enable Register - Toggle 0x18C 32 write-only P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P2 Event Enable 2 1 write-only P3 Event Enable 3 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only 3 0x200 LOCK%s Lock Register 0x1A0 32 P0 Lock State 0 1 P1 Lock State 1 1 P2 Lock State 2 1 P3 Lock State 3 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P30 Lock State 30 1 P31 Lock State 31 1 3 0x200 LOCKS%s Lock Register - Set 0x1A4 32 write-only P0 Lock State 0 1 P1 Lock State 1 1 P2 Lock State 2 1 P3 Lock State 3 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P30 Lock State 30 1 P31 Lock State 31 1 3 0x200 LOCKC%s Lock Register - Clear 0x1A8 32 write-only P0 Lock State 0 1 P1 Lock State 1 1 P2 Lock State 2 1 P3 Lock State 3 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P30 Lock State 30 1 P31 Lock State 31 1 3 0x200 LOCKT%s Lock Register - Toggle 0x1AC 32 write-only P0 Lock State 0 1 P1 Lock State 1 1 P2 Lock State 2 1 P3 Lock State 3 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P30 Lock State 30 1 P31 Lock State 31 1 3 0x200 UNLOCK%s Unlock Register 0x1E0 32 write-only ADDR Offset Register 0 10 write-only KEY Unlocking Key 24 8 3 0x200 ASR%s Access Status Register 0x1E4 32 AR Access Error 0 1 3 0x200 PARAMETER%s Parameter Register 0x1F8 32 read-only PARAMETER Parameter 0 32 3 0x200 VERSION%s Version Register 0x1FC 32 read-only 0x00000215 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only HCACHE 1.0.1 Cortex M I&D Cache Controller HCACHE HCACHE_ 0x400A0400 0 0x100 registers CTRL Control Register 0x08 32 write-only CEN Cache Enable 0 1 write-only CENSelect NO Disable Cache Controller 0x0 YES Enable Cache Controller 0x1 SR Status Register 0x0C 32 CSTS Cache Controller Status 0 1 read-only CSTSSelect DIS Cache Controller Disabled 0x0 EN Cache Controller Enabled 0x1 MAINT0 Maintenance Register 0 0x20 32 write-only INVALL Cache Controller Invalidate All 0 1 write-only INVALLSelect NO No effect 0x0 YES Invalidate all cache entries 0x1 MAINT1 Maintenance Register 1 0x24 32 write-only INDEX Invalidate Index 4 4 write-only MCFG Monitor Configuration Register 0x28 32 MODE Cache Controller Monitor Counter Mode 0 2 MODESelect CYCLE Cycle Counter 0x0 IHIT Instruction Hit Counter 0x1 DHIT Data Hit Counter 0x2 MEN Monitor Enable Register 0x2C 32 MENABLE Monitor Enable 0 1 write-only MENABLESelect DIS Disable Monitor Counter 0x0 EN Enable Monitor Counter 0x1 MCTRL Monitor Control Register 0x30 32 write-only SWRST Monitor Software Reset 0 1 write-only SWRSTSelect NO No effect 0x0 YES Reset event counter register 0x1 MSR Monitor Status Register 0x34 32 read-only EVENTCNT Monitor Event Counter 0 32 read-only VERSION Version Register 0xFC 32 read-only 0x00000101 VERSION VERSION 0 12 read-only MFN MFN 16 4 read-only HMATRIX 1.3.0 HSB Matrix HMATRIXB HMATRIXB_ 0x400A1000 0 0x400 registers 16 0x4 MCFG%s Master Configuration Register 0x000 32 0x00000002 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 16 0x4 SCFG%s Slave Configuration Register 0x040 32 0x00000010 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 16 0x8 PRAS%s Priority Register A for Slave 0x080 32 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 16 0x8 PRBS%s Priority Register B for Slave 0x084 32 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 MRCR Master Remap Control Register 0x100 32 RCB0 Remap Command bit for Master 0 0 1 RCB0Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB1 Remap Command bit for Master 1 1 1 RCB1Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB2 Remap Command bit for Master 2 2 1 RCB2Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB3 Remap Command bit for Master 3 3 1 RCB3Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB4 Remap Command bit for Master 4 4 1 RCB4Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB5 Remap Command bit for Master 5 5 1 RCB5Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB6 Remap Command bit for Master 6 6 1 RCB6Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB7 Remap Command bit for Master 7 7 1 RCB7Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB8 Remap Command bit for Master 8 8 1 RCB8Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB9 Remap Command bit for Master 9 9 1 RCB9Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB10 Remap Command bit for Master 10 10 1 RCB10Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB11 Remap Command bit for Master 11 11 1 RCB11Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB12 Remap Command bit for Master 12 12 1 RCB12Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB13 Remap Command bit for Master 13 13 1 RCB13Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB14 Remap Command bit for Master 14 14 1 RCB14Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB15 Remap Command bit for Master 15 15 1 RCB15Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 16 0x4 SFR%s Special Function Register 0x110 32 SFR Special Function Register 0 32 IISC 1.0.0 Inter-IC Sound (I2S) Controller IISC IISC_ 0x40004000 0 0x400 registers IISC_INTREQ 53 CR Control Register 0x00 32 write-only RXEN Receive Enable 0 1 RXENSelect OFF No effect 0x0 ON Enables Data Receive if RXDIS is not set 0x1 RXDIS Receive Disable 1 1 RXDISSelect OFF No effect 0x0 ON Disables Data Receive 0x1 CKEN Clocks Enable 2 1 CKENSelect OFF No effect 0x0 ON Enables clocks if CKDIS is not set 0x1 CKDIS Clocks Disable 3 1 CKDISSelect OFF No effect 0x0 ON Disables clocks 0x1 TXEN Transmit Enable 4 1 TXENSelect OFF No effect 0x0 ON Enables Data Transmit if TXDIS is not set 0x1 TXDIS Transmit Disable 5 1 TXDISSelect OFF No effect 0x0 ON Disables Data Transmit 0x1 SWRST Software Reset 7 1 SWRSTSelect OFF No effect 0x0 ON Performs a software reset. Has priority on any other bit in CR 0x1 MR Mode Register 0x04 32 MODE Master/Slave/Controller Mode 0 1 MODESelect SLAVE Slave mode (only serial data handled, clocks received from external master or controller) 0x0 MASTER Master mode (clocks generated and output by IISC, serial data handled if CR.RXEN and/or CR.TXEN written to 1) 0x1 DATALENGTH Data Word Length 2 3 DATALENGTHSelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 RXMONO Receiver Mono 8 1 RXMONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 RXDMA Single or Multiple DMA Channels for Receiver 9 1 RXDMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 RXLOOP Loop-back Test Mode 10 1 RXLOOPSelect OFF Normal mode 0x0 ON ISDO internally connected to ISDI 0x1 TXMONO Transmitter Mono 12 1 TXMONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 TXDMA Single or Multiple DMA Channels for Transmitter 13 1 TXDMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 TXSAME Transmit Data when Underrun 14 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0x0 SAME Last data transmitted in case of underrun 0x1 IMCKFS Master Clock to fs Ratio 24 6 IMCKFSSelect 16 16 fs 0x0 32 32 fs 0x1 64 64 fs 0x3 128 128 fs 0x7 256 256 fs 0xf 384 384 fs 0x17 512 512 fs 0x1f 768 768 fs 0x2f 1024 1024 fs 0x3f IMCKMODE Master Clock Mode 30 1 IMCKMODESelect NO_IMCK No IMCK generated 0x0 IMCK IMCK generated 0x1 IWS24 IWS Data Slot Width 31 1 IWS24Select 32 IWS Data Slot is 32-bit wide for DATALENGTH=18/20/24-bit 0x0 24 IWS Data Slot is 24-bit wide for DATALENGTH=18/20/24-bit 0x1 SR Status Register 0x08 32 read-only RXEN Receive Enable 0 1 RXENSelect OFF Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request 0x0 ON Receiver is effectively enabled, following a CR.RXEN request 0x1 RXRDY Receive Ready 1 1 RXRDYSelect EMPTY The register RHR is empty and can't be read 0x0 FULL The register RHR is full and is ready to be read 0x1 RXOR Receive Overrun 2 1 RXORSelect NO No overrun 0x0 YES The previous received data has not been read. This data is lost 0x1 TXEN Transmit Enable 4 1 TXENSelect OFF Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request 0x0 ON Transmitter is effectively enabled, following a CR.TXEN request 0x1 TXRDY Transmit Ready 5 1 TXRDYSelect FULL The register THR is full and can't be written 0x0 EMPTY The register THR is empty and is ready to be written 0x1 TXUR Transmit Underrun 6 1 TXURSelect NO No underrun 0x0 YES The last bit of the last data written to the register THR has been set. Until the next write to THR, data will be sent according to MR.TXSAME field 0x1 RXORCH Receive Overrun Channels 8 2 RXORCHSelect LEFT Overrun first occurred on left channel 0x0 RIGHT Overrun first occurred on right channel 0x1 TXURCH Transmit Underrun Channels 20 2 TXURCHSelect LEFT Underrun first occurred on left channel 0x0 RIGHT Underrun first occurred on right channel 0x1 SCR Status Clear Register 0x0C 32 write-only RXOR Receive Overrun 2 1 RXORSelect NO No effect 0x0 CLEAR Clears the corresponding SR bit 0x1 TXUR Transmit Underrun 6 1 TXURSelect NO No effect 0x0 CLEAR Clears the corresponding SR bit 0x1 RXORCH Receive Overrun Channels 8 2 TXURCH Transmit Underrun Channels 20 2 SSR Status Set Register 0x10 32 write-only RXOR Receive Overrun 2 1 RXORSelect NO No effect 0x0 SET Sets corresponding SR bit 0x1 TXUR Transmit Underrun 6 1 TXURSelect NO No effect 0x0 SET Sets corresponding SR bit 0x1 RXORCH Receive Overrun Channels 8 2 TXURCH Transmit Underrun Channels 20 2 IER Interrupt Enable Register 0x14 32 write-only RXRDY Receiver Ready Interrupt Enable 1 1 RXRDYSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 RXOR Receive Overrun Interrupt Enable 2 1 RXORSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 TXRDY Transmit Ready Interrupt Enable 5 1 TXRDYSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 TXUR Transmit Underrun Interrupt Enable 6 1 TXURSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 IDR Interrupt Disable Register 0x18 32 write-only RXRDY Receive Ready Interrupt Disable 1 1 RXRDYSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 RXOR Receive Overrun Interrupt Disable 2 1 RXORSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 TXRDY Transmit Ready Interrupt Disable 5 1 TXRDYSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 TXUR Transmit Underrun Interrupt Disable 6 1 TXURSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 IMR Interrupt Mask Register 0x1C 32 read-only RXRDY Receive Ready Interrupt Mask 1 1 RXRDYSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 RXOR Receive Overrun Interrupt Mask 2 1 RXORSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 TXRDY Transmit Ready Interrupt Mask 5 1 TXRDYSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 TXUR Transmit Underrun Interrupt Mask 6 1 TXURSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 RHR Receive Holding Register 0x20 32 read-only RDAT Receive Data 0 32 THR Transmit Holding Register 0x24 32 write-only TDAT Transmit Data 0 32 VERSION Version Register 0x28 32 read-only 0x00000100 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 PARAMETER Parameter Register 0x2C 32 read-only 0x00010000 FORMAT Data protocol format 7 1 FORMATSelect I2S I2S format, stereo with IWS low for left channel 0x0 NBCHAN Maximum number of channels - 1 16 5 LCDCA 1.0.0 LCD Controller LCDCA LCDCA_ 0x40080000 0 0x400 registers LCDCA_INTREQ 79 CR Control Register 0x00 32 write-only DIS Disable 0 1 write-only EN Enable 1 1 write-only FC0DIS Frame Counter 0 Disable 2 1 write-only FC0EN Frame Counter 0 Enable 3 1 write-only FC1DIS Frame Counter 1 Disable 4 1 write-only FC1EN Frame Counter 1 Enable 5 1 write-only FC2DIS Frame Counter 2 Disable 6 1 write-only FC2EN Frame Counter 2 Enable 7 1 write-only CDM Clear Display Memory 8 1 write-only WDIS Wake up Disable 9 1 write-only WEN Wake up Enable 10 1 write-only BSTART Blinking Start 11 1 write-only BSTOP Blinking Stop 12 1 write-only CSTART Circular Shift Start 13 1 write-only CSTOP Circular Shift Stop 14 1 write-only CFG Configuration Register 0x04 32 XBIAS External Bias Generation 0 1 WMOD Waveform Mode 1 1 BLANK Blank LCD 2 1 LOCK Lock 3 1 DUTY Duty Select 8 2 FCST Fine Contrast 16 6 NSU Number of Segment Terminals in Use 24 6 TIM Timing Register 0x08 32 PRESC LCD Prescaler Select 0 1 CLKDIV LCD Clock Division 1 3 FC0 Frame Counter 0 8 5 FC0PB Frame Counter 0 Prescaler Bypass 13 1 FC1 Frame Counter 1 16 5 FC2 Frame Counter 2 24 5 SR Status Register 0x0C 32 read-only FC0R Frame Counter 0 Rollover 0 1 read-only FC0S Frame Counter 0 Status 1 1 read-only FC1S Frame Counter 1 Status 2 1 read-only FC2S Frame Counter 2 Status 3 1 read-only EN LCDCA Status 4 1 read-only WEN Wake up Status 5 1 read-only BLKS Blink Status 6 1 read-only CSRS Circular Shift Register Status 7 1 read-only CPS Charge Pump Status 8 1 read-only SCR Status Clear Register 0x10 32 write-only FC0R Frame Counter 0 Rollover 0 1 write-only DRL0 Data Register Low 0 0x14 32 DATA Segments Value 0 32 DRH0 Data Register High 0 0x18 32 DATA Segments Value 0 8 DRL1 Data Register Low 1 0x1C 32 DATA Segments Value 0 32 DRH1 Data Register High 1 0x20 32 DATA Segments Value 0 8 DRL2 Data Register Low 2 0x24 32 DATA Segments Value 0 32 DRH2 Data Register High 2 0x28 32 DATA Segments Value 0 8 DRL3 Data Register Low 3 0x2C 32 DATA Segments Value 0 32 DRH3 Data Register High 3 0x30 32 DATA Segments Value 0 8 IADR Indirect Access Data Register 0x34 32 write-only DATA Segments Value 0 8 write-only DMASK Data Mask 8 8 write-only OFF Byte Offset 16 5 write-only BCFG Blink Configuration Register 0x38 32 MODE Blinking Mode 0 1 FCS Frame Counter Selection 1 2 BSS0 Blink Segment Selection 0 8 4 BSS1 Blink Segment Selection 1 12 4 CSRCFG Circular Shift Register Configuration 0x3C 32 DIR Direction 0 1 FCS Frame Counter Selection 1 2 SIZE Size 3 3 DATA Circular Shift Register Value 8 8 CMCFG Character Mapping Configuration Register 0x40 32 DREV Digit Reverse Mode 0 1 TDG Type of Digit 1 2 STSEG Start Segment 8 6 CMDR Character Mapping Data Register 0x44 32 write-only ASCII ASCII Code 0 7 write-only ACMCFG Automated Character Mapping Configuration Register 0x48 32 EN Enable 0 1 FCS Frame Counter Selection 1 2 MODE Mode (sequential or scrolling) 3 1 DREV Digit Reverse 4 1 TDG Type of Digit 5 2 STSEG Start Segment 8 6 STEPS Scrolling Steps 16 8 DIGN Digit Number 24 4 ACMDR Automated Character Mapping Data Register 0x4C 32 write-only ASCII ASCII Code 0 7 write-only ABMCFG Automated Bit Mapping Configuration Register 0x50 32 EN Enable 0 1 FCS Frame Counter Selection 1 2 SIZE Size 8 5 ABMDR Automated Bit Mapping Data Register 0x54 32 write-only DATA Segments Value 0 8 write-only DMASK Data Mask 8 8 write-only OFF Byte Offset 16 5 write-only IER Interrupt Enable Register 0x58 32 write-only FC0R Frame Counter 0 Rollover 0 1 write-only IDR Interrupt Disable Register 0x5C 32 write-only FC0R Frame Counter 0 Rollover 0 1 write-only IMR Interrupt Mask Register 0x60 32 read-only FC0R Frame Counter 0 Rollover 0 1 read-only VERSION Version Register 0x64 32 read-only 0x00000100 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only PARC 1.0.0 Parallel Capture PARC PARC_ 0x4006C000 0 0x400 registers PARC_INTREQ 74 CFG Configuration Register 0x00 32 DSIZE Data Size 0 2 SMODE Sampling Mode 2 2 EMODE Events Mode 4 1 EDGE Sampling Edge Select 5 1 HALF Half Capture 6 1 ODD Odd Capture 7 1 CR Control Register 0x04 32 EN Enable 0 1 DIS Disable 1 1 write-only START Start Capture 2 1 write-only STOP Stop Capture 3 1 IER Interrupt Enable Register 0x08 32 write-only DRDY Data Ready Interrupt Enable 2 1 write-only OVR Overrun Interrupt Enable 3 1 write-only IDR Interrupt Disable Register 0x0C 32 write-only DRDY Data Ready Interrupt Disable 2 1 write-only OVR Overrun Interrupt Disable 3 1 write-only IMR Interrupt Mask Register 0x10 32 read-only DRDY Data Ready Interrupt Mask 2 1 read-only OVR Overrun Interrupt Mask 3 1 read-only SR Status Register 0x14 32 read-only EN Enable Status 0 1 read-only CS Capture Status 1 1 read-only DRDY Data Ready Interrupt Status 2 1 read-only OVR Overrun Interrupt Status 3 1 read-only ICR Interrupt Status Clear Register 0x18 32 write-only DRDY Data Ready Interrupt Status Clear 2 1 write-only OVR Overrun Interrupt Status Clear 3 1 write-only RHR Receive Holding Register 0x1C 32 read-only CDATA Captured Data 0 32 read-only VERSION Version Register 0x20 32 read-only 0x00000100 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only PDCA 1.2.4 Peripheral DMA Controller PDCA PDCA_ 0x400A2000 0 0x1000 registers PDCA_INTREQ_0 1 PDCA_INTREQ_1 2 PDCA_INTREQ_2 3 PDCA_INTREQ_3 4 PDCA_INTREQ_4 5 PDCA_INTREQ_5 6 PDCA_INTREQ_6 7 PDCA_INTREQ_7 8 PDCA_INTREQ_8 9 PDCA_INTREQ_9 10 PDCA_INTREQ_10 11 PDCA_INTREQ_11 12 PDCA_INTREQ_12 13 PDCA_INTREQ_13 14 PDCA_INTREQ_14 15 PDCA_INTREQ_15 16 16 0x40 MAR%s Memory Address Register 0x000 32 MADDR Memory Address 0 32 16 0x40 PSR%s Peripheral Select Register 0x004 32 PID Peripheral Identifier 0 8 16 0x40 TCR%s Transfer Counter Register 0x008 32 TCV Transfer Counter Value 0 16 16 0x40 MARR%s Memory Address Reload Register 0x00C 32 MARV Memory Address Reload Value 0 32 16 0x40 TCRR%s Transfer Counter Reload Register 0x010 32 TCRV Transfer Counter Reload Value 0 16 16 0x40 CR%s Control Register 0x014 32 write-only TEN Transfer Enable 0 1 TDIS Transfer Disable 1 1 ECLR Error Clear 8 1 16 0x40 MR%s Mode Register 0x018 32 SIZE Transfer size 0 2 SIZESelect Byte 0x0 Half_Word 0x1 Word 0x2 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 16 0x40 SR%s Status Register 0x01C 32 read-only TEN Transfer Enabled 0 1 16 0x40 IER%s Interrupt Enable Register 0x020 32 write-only RCZ Reload Counter Zero 0 1 TRC Transfer Complete 1 1 TERR Transfer Error 2 1 16 0x40 IDR%s Interrupt Disable Register 0x024 32 write-only RCZ Reload Counter Zero 0 1 TRC Transfer Complete 1 1 TERR Transfer Error 2 1 16 0x40 IMR%s Interrupt Mask Register 0x028 32 read-only RCZ Reload Counter Zero 0 1 TRC Transfer Complete 1 1 TERR Transfer Error 2 1 16 0x40 ISR%s Interrupt Status Register 0x02C 32 read-only RCZ Reload Counter Zero 0 1 TRC Transfer Complete 1 1 TERR Transfer Error 2 1 PCONTROL Performance Control Register 0x800 32 CH0EN Channel 0 Enabled 0 1 CH1EN Channel 1 Enabled. 1 1 CH0OF Channel 0 Overflow Freeze 4 1 CH1OF Channel 1 overflow freeze 5 1 CH0RES Channel 0 counter reset 8 1 CH1RES Channel 1 counter reset 9 1 MON0CH PDCA Channel to monitor with counter 0 16 6 MON1CH PDCA Channel to monitor with counter 1 24 6 PRDATA0 Channel 0 Read Data Cycles 0x804 32 read-only DATA Data Cycles Counted Since Last reset 0 32 PRSTALL0 Channel 0 Read Stall Cycles 0x808 32 read-only STALL Stall Cycles counted since last reset 0 32 PRLAT0 Channel 0 Read Max Latency 0x80C 32 read-only LAT Maximum Transfer Initiation cycles counted since last reset 0 16 PWDATA0 Channel 0 Write Data Cycles 0x810 32 read-only DATA Data Cycles Counted since last Reset 0 32 PWSTALL0 Channel 0 Write Stall Cycles 0x814 32 read-only STALL Stall cycles counted since last reset 0 32 PWLAT0 Channel0 Write Max Latency 0x818 32 read-only LAT Maximum transfer initiation cycles counted since last reset 0 16 PRDATA1 Channel 1 Read Data Cycles 0x81C 32 read-only DATA Data Cycles Counted Since Last reset 0 32 PRSTALL1 Channel Read Stall Cycles 0x820 32 read-only STALL Stall Cycles Counted since last reset 0 32 PRLAT1 Channel 1 Read Max Latency 0x824 32 read-only LAT Maximum Transfer initiation cycles counted since last reset 0 16 PWDATA1 Channel 1 Write Data Cycles 0x828 32 read-only DATA Data cycles Counted Since last reset 0 32 PWSTALL1 Channel 1 Write stall Cycles 0x82C 32 read-only STALL Stall cycles counted since last reset 0 32 PWLAT1 Channel 1 Read Max Latency 0x830 32 read-only LAT Maximum transfer initiation cycles counted since last reset 0 16 VERSION Version Register 0x834 32 read-only 0x00000124 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only PEVC 2.0.0 Peripheral Event Controller PEVC PEVC_ 0x400A6000 0 0x400 registers PEVC_INTREQ_0 19 PEVC_INTREQ_1 20 CHSR Channel Status Register 0x000 32 read-only CHS Channel Status 0 32 CHSSelect 0 Channel j Disabled 0x0 1 Channel j Enabled 0x1 CHER Channel Enable Register 0x004 32 write-only CHE Channel Enable 0 32 CHESelect 0 No Action 0x0 1 Enable Channel j 0x1 CHDR Channel Disable Register 0x008 32 write-only CHD Channel Disable 0 32 CHDSelect 0 No Action 0x0 1 Disable Channel j 0x1 SEV Software Event 0x010 32 write-only SEV Software Event 0 32 SEVSelect 0 No Action 0x0 1 CPU forces software event to channel j 0x1 BUSY Channel / User Busy 0x014 32 read-only BUSY Channel Status 0 32 BUSYSelect 0 No Action 0x0 1 Channel j or User j is Busy 0x1 TRIER Trigger Interrupt Mask Enable Register 0x020 32 write-only TRIE Trigger Interrupt Enable 0 32 TRIESelect 0 No Action 0x0 1 Enable Trigger j Interrupt 0x1 TRIDR Trigger Interrupt Mask Disable Register 0x024 32 write-only TRID Trigger Interrupt Disable 0 32 TRIDSelect 0 No Action 0x0 1 Disable Trigger j Interrupt 0x1 TRIMR Trigger Interrupt Mask Register 0x028 32 read-only TRIM Trigger Interrupt Mask 0 32 TRIMSelect 0 Trigger j Interrupt Disabled 0x0 1 Trigger j Interrupt Enabled 0x1 TRSR Trigger Status Register 0x030 32 read-only TRS Trigger Interrupt Status 0 32 TRSSelect 0 Channel j did not send out an Event in the past 0x0 1 Channel j did send out an Event in the past 0x1 TRSCR Trigger Status Clear Register 0x034 32 write-only TRSC Trigger Interrupt Status Clear 0 32 TRSCSelect 0 No Action 0x0 1 Clear TRSR[j] 0x1 OVIER Overrun Interrupt Mask Enable Register 0x040 32 write-only OVIE Overrun Interrupt Enable 0 32 OVIESelect 0 No Action 0x0 1 Enable Overrun Interrupt for Channel j 0x1 OVIDR Overrun Interrupt Mask Disable Register 0x044 32 write-only OVID Overrun Interrupt Disable 0 32 OVIDSelect 0 No Action 0x0 1 Enable Overrun Interrupt for Channel j 0x1 OVIMR Overrun Interrupt Mask Register 0x048 32 read-only OVIM Overrun Interrupt Mask 0 32 OVIMSelect 0 Overrun Interrupt for Channel j Disabled 0x0 1 Overrun Interrupt for Channel j Enabled 0x1 OVSR Overrun Status Register 0x050 32 read-only OVS Overrun Interrupt Status 0 32 OVSSelect 0 No Overrun occured on Channel j 0x0 1 Overrun occured on Channel j 0x1 OVSCR Overrun Status Clear Register 0x054 32 write-only OVSC Overrun Interrupt Status Clear 0 32 OVSCSelect 0 No Action 0x0 1 Clear Overrun Status Bit j 0x1 19 0x4 CHMX%s Channel Multiplexer 0x100 32 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 31 0x4 EVS%s Event Shaper 0x200 32 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFDR Input Glitch Filter Divider Register 0x300 32 IGFDR Input Glitch Filter Divider Register 0 4 PARAMETER Parameter 0x3F8 32 read-only 0x14061824 IGF_COUNT Number of Input Glitch Filters 0 8 EVS_COUNT Number of Event Shapers 8 8 EVIN Number of Event Inputs / Generators 16 8 TRIGOUT Number of Trigger Outputs / Channels / Users 24 8 VERSION Version 0x3FC 32 read-only 0x00000200 VERSION Version Number 0 12 VARIANT Variant Number 16 4 PICOUART 1.0.1 Pico UART PICOUART PICOUART_ 0x400F1400 0 0x400 registers CR Control Register 0x00 32 write-only EN Enable 0 1 DIS Disable 1 1 write-only CFG Configuration Register 0x04 32 SOURCE Source Enable Mode 0 2 ACTION Action to perform 2 1 MATCH Data Match 8 8 SR Status Register 0x08 32 read-only EN Enable Interrupt Status 0 1 read-only DRDY Data Ready Interrupt Status 1 1 read-only RHR Receive Holding Register 0x0C 32 read-only CDATA Received Data 0 32 read-only VERSION Version Register 0x20 32 read-only 0x00000101 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 4 read-only PM 4.4.1 Power Manager PM PM_ 0x400E0000 0 0x400 registers PM_INTREQ 22 MCCTRL Main Clock Control 0x000 32 MCSEL Main Clock Select 0 3 CPUSEL CPU Clock Select 0x004 32 CPUSEL CPU Clock Select 0 3 CPUSELSelect 0 fCPU:fmain. CPUDIV: 0x0 1 fCPU:fmain / 2^(CPUSEL+1) 0x1 CPUDIV CPU Division 7 1 PBASEL PBA Clock Select 0x00C 32 PBSEL PBA Clock Select 0 3 PBDIV PBA Division Select 7 1 PBBSEL PBB Clock Select 0x010 32 PBSEL PBB Clock Select 0 3 PBDIV PBB Division Select 7 1 PBCSEL PBC Clock Select 0x014 32 PBSEL PBC Clock Select 0 3 PBDIV PBC Division Select 7 1 PBDSEL PBD Clock Select 0x018 32 PBSEL PBD Clock Select 0 3 PBDIV PBD Division Select 7 1 CPUMASK CPU Mask 0x020 32 0x00000001 OCD OCD CPU Clock Mask 0 1 HSBMASK HSB Mask 0x024 32 0x000001E2 PDCA_ PDCA HSB Clock Mask 0 1 HFLASHC_ HFLASHC HSB Clock Mask 1 1 HRAMC1_ HRAMC1 HSB Clock Mask 2 1 USBC_ USBC HSB Clock Mask 3 1 CRCCU_ CRCCU HSB Clock Mask 4 1 HTOP0_ HTOP0 HSB Clock Mask 5 1 HTOP1_ HTOP1 HSB Clock Mask 6 1 HTOP2_ HTOP2 HSB Clock Mask 7 1 HTOP3_ HTOP3 HSB Clock Mask 8 1 AESA_ AESA HSB Clock Mask 9 1 PBAMASK PBA Mask 0x028 32 IISC_ IISC APB Clock Enable 0 1 SPI_ SPI APB Clock Enable 1 1 TC0_ TC0 APB Clock Enable 2 1 TC1_ TC1 APB Clock Enable 3 1 TWIM0_ TWIM0 APB Clock Enable 4 1 TWIS0_ TWIS0 APB Clock Enable 5 1 TWIM1_ TWIM1 APB Clock Enable 6 1 TWIS1_ TWIS1 APB Clock Enable 7 1 USART0_ USART0 APB Clock Enable 8 1 USART1_ USART1 APB Clock Enable 9 1 USART2_ USART2 APB Clock Enable 10 1 USART3_ USART3 APB Clock Enable 11 1 ADCIFE_ ADCIFE APB Clock Enable 12 1 DACC_ DACC APB Clock Enable 13 1 ACIFC_ ACIFC APB Clock Enable 14 1 GLOC_ GLOC APB Clock Enable 15 1 ABDACB_ ABDACB APB Clock Enable 16 1 TRNG_ TRNG APB Clock Enable 17 1 PARC_ PARC APB Clock Enable 18 1 CATB_ CATB APB Clock Enable 19 1 TWIM2_ TWIM2 APB Clock Enable 21 1 TWIM3_ TWIM3 APB Clock Enable 22 1 LCDCA_ LCDCA APB Clock Enable 23 1 PBBMASK PBB Mask 0x02C 32 0x00000001 HFLASHC_ HFLASHC APB Clock Enable 0 1 HCACHE_ HCACHE APB Clock Enable 1 1 HMATRIX_ HMATRIX APB Clock Enable 2 1 PDCA_ PDCA APB Clock Enable 3 1 CRCCU_ CRCCU APB Clock Enable 4 1 USBC_ USBC APB Clock Enable 5 1 PEVC_ PEVC APB Clock Enable 6 1 PBCMASK PBC Mask 0x030 32 0x0000001F PM_ PM APB Clock Enable 0 1 CHIPID_ CHIPID APB Clock Enable 1 1 SCIF_ SCIF APB Clock Enable 2 1 FREQM_ FREQM APB Clock Enable 3 1 GPIO_ GPIO APB Clock Enable 4 1 PBDMASK PBD Mask 0x034 32 0x0000003F BPM_ BPM APB Clock Enable 0 1 BSCIF_ BSCIF APB Clock Enable 1 1 AST_ AST APB Clock Enable 2 1 WDT_ WDT APB Clock Enable 3 1 EIC_ EIC APB Clock Enable 4 1 PICOUART_ PICOUART APB Clock Enable 5 1 PBADIVMASK PBA Divided Clock Mask 0x040 32 CFDCTRL Clock Failure Detector Control 0x054 32 CFDEN Clock Failure Detection Enable 0 1 SFV Store Final Value 31 1 UNLOCK Unlock Register 0x058 32 write-only ADDR Unlock Address 0 10 KEY Unlock Key 24 8 IER Interrupt Enable Register 0x0C0 32 write-only CFD Clock Failure Detected Interrupt Enable 0 1 CKRDY Clock Ready Interrupt Enable 5 1 WAKE Wake up Interrupt Enable 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 AE Access Error Interrupt Enable 31 1 IDR Interrupt Disable Register 0x0C4 32 write-only CFD Clock Failure Detected Interrupt Disable 0 1 CKRDY Clock Ready Interrupt Disable 5 1 WAKE Wake up Interrupt Disable 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 AE Access Error Interrupt Disable 31 1 IMR Interrupt Mask Register 0x0C8 32 read-only CFD Clock Failure Detected Interrupt Mask 0 1 CKRDY Clock Ready Interrupt Mask 5 1 WAKE Wake up Interrupt Mask 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 AE Access Error Interrupt Mask 31 1 ISR Interrupt Status Register 0x0CC 32 read-only CFD Clock Failure Detected Interrupt Status 0 1 CKRDY Clock Ready Interrupt Status 5 1 WAKE Wake up Interrupt Status 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 AE Access Error Interrupt Status 31 1 ICR Interrupt Clear Register 0x0D0 32 write-only CFD Clock Failure Detected Interrupt Status Clear 0 1 CKRDY Clock Ready Interrupt Status Clear 5 1 WAKE Wake up Interrupt Status Clear 8 1 AE Access Error Interrupt Status Clear 31 1 SR Status Register 0x0D4 32 read-only CFD Clock Failure Detected 0 1 OCP Over Clock Detected 1 1 CKRDY Clock Ready 5 1 WAKE Wake up 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 PERRDY Peripheral Ready 28 1 AE Access Error 31 1 PPCR Peripheral Power Control Register 0x160 32 0x000001FE RSTPUN Reset Pullup 0 1 CATBRCMASK CAT Request Clock Mask 1 1 ACIFCRCMASK ACIFC Request Clock Mask 2 1 ASTRCMASK AST Request Clock Mask 3 1 TWIS0RCMASK TWIS0 Request Clock Mask 4 1 TWIS1RCMASK TWIS1 Request Clock Mask 5 1 PEVCRCMASK PEVC Request Clock Mask 6 1 ADCIFERCMASK ADCIFE Request Clock Mask 7 1 VREGRCMASK VREG Request Clock Mask 8 1 FWBGREF Flash Wait BGREF 9 1 FWBOD18 Flash Wait BOD18 10 1 RCAUSE Reset Cause Register 0x180 32 read-only POR Power-on Reset 0 1 BOD Brown-out Reset 1 1 EXT External Reset Pin 2 1 WDT Watchdog Reset 3 1 OCDRST OCD Reset 8 1 POR33 Power-on Reset 10 1 BOD33 Brown-out 3.3V Reset 13 1 WCAUSE Wake Cause Register 0x184 32 read-only TWI_SLAVE_0 Two-wire Slave Interface 0 0 1 read-only TWI_SLAVE_1 Two-wire Slave Interface 1 1 1 read-only USBC USB Device and Embedded Host Interface 2 1 read-only PSOK Power Scaling OK 3 1 read-only BOD18_IRQ BOD18 Interrupt 4 1 read-only BOD33_IRQ BOD33 Interrupt 5 1 read-only PICOUART Picopower UART 6 1 read-only LCDCA LCD Controller 7 1 read-only EIC External Interrupt Controller 16 1 read-only AST Asynchronous Timer 17 1 read-only AWEN Asynchronous Wake Enable 0x188 32 AWEN Asynchronous Wake Up 0 32 OBS Obsvervability 0x190 32 FASTSLEEP Fast Sleep Register 0x194 32 OSC Oscillator 0 1 PLL PLL 8 1 FASTRCOSC RC80 or FLO 16 5 DFLL DFLL 24 1 CONFIG Configuration Register 0x3F8 32 read-only 0x0000000F PBA APBA Implemented 0 1 PBB APBB Implemented 1 1 PBC APBC Implemented 2 1 PBD APBD Implemented 3 1 HSBPEVC HSB PEVC Clock Implemented 7 1 VERSION Version Register 0x3FC 32 read-only 0x00000441 VERSION Version number 0 12 read-only VARIANT Variant number 16 4 read-only SCIF 1.3.0 System Control Interface SCIF SCIF_ 0x400E0800 0 0x400 registers SCIF_INTREQ 23 IER Interrupt Enable Register 0x000 32 write-only OSC0RDY OSC0 Ready 0 1 write-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 write-only DFLL0LOCKF DFLL0 Lock Fine 2 1 write-only DFLL0RDY DFLL0 Ready 3 1 write-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 write-only DFLL0OOB DFLL0 Out Of Bounds 5 1 write-only PLL0LOCK PLL0 Lock 6 1 write-only PLL0LOCKLOST PLL0 Lock Lost 7 1 write-only RCFASTLOCK RCFAST Lock 13 1 write-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 write-only AE Access Error 31 1 write-only IDR Interrupt Disable Register 0x004 32 write-only OSC0RDY OSC0 Ready 0 1 write-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 write-only DFLL0LOCKF DFLL0 Lock Fine 2 1 write-only DFLL0RDY DFLL0 Ready 3 1 write-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 write-only DFLL0OOB DFLL0 Out Of Bounds 5 1 write-only PLL0LOCK PLL0 Lock 6 1 write-only PLL0LOCKLOST PLL0 Lock Lost 7 1 write-only RCFASTLOCK RCFAST Lock 13 1 write-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 write-only AE Access Error 31 1 write-only IMR Interrupt Mask Register 0x008 32 read-only OSC0RDY OSC0 Ready 0 1 read-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 read-only DFLL0LOCKF DFLL0 Lock Fine 2 1 read-only DFLL0RDY DFLL0 Ready 3 1 read-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 read-only DFLL0OOB DFLL0 Out Of Bounds 5 1 read-only PLL0LOCK PLL0 Lock 6 1 read-only PLL0LOCKLOST PLL0 Lock Lost 7 1 read-only RCFASTLOCK RCFAST Lock 13 1 read-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 read-only AE Access Error 31 1 read-only ISR Interrupt Status Register 0x00C 32 read-only OSC0RDY OSC0 Ready 0 1 read-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 read-only DFLL0LOCKF DFLL0 Lock Fine 2 1 read-only DFLL0RDY DFLL0 Ready 3 1 read-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 read-only DFLL0OOB DFLL0 Out Of Bounds 5 1 read-only PLL0LOCK PLL0 Lock 6 1 read-only PLL0LOCKLOST PLL0 Lock Lost 7 1 read-only RCFASTLOCK RCFAST Lock 13 1 read-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 read-only AE Access Error 31 1 read-only ICR Interrupt Clear Register 0x010 32 write-only OSC0RDY OSC0 Ready 0 1 write-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 write-only DFLL0LOCKF DFLL0 Lock Fine 2 1 write-only DFLL0RDY DFLL0 Ready 3 1 write-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 write-only DFLL0OOB DFLL0 Out Of Bounds 5 1 write-only PLL0LOCK PLL0 Lock 6 1 write-only PLL0LOCKLOST PLL0 Lock Lost 7 1 write-only RCFASTLOCK RCFAST Lock 13 1 write-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 write-only AE Access Error 31 1 write-only PCLKSR Power and Clocks Status Register 0x014 32 read-only OSC0RDY OSC0 Ready 0 1 read-only DFLL0LOCKC DFLL0 Locked on Coarse Value 1 1 read-only DFLL0LOCKF DFLL0 Locked on Fine Value 2 1 read-only DFLL0RDY DFLL0 Synchronization Ready 3 1 read-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 read-only DFLL0OOB DFLL0 Track Out Of Bounds 5 1 read-only PLL0LOCK PLL0 Locked on Accurate value 6 1 read-only PLL0LOCKLOST PLL0 lock lost value 7 1 read-only RCFASTLOCK RCFAST Locked on Accurate value 13 1 read-only RCFASTLOCKLOST RCFAST lock lost value 14 1 read-only UNLOCK Unlock Register 0x018 32 write-only ADDR Unlock Address 0 10 write-only KEY Unlock Key 24 8 write-only CSCR Chip Specific Configuration Register 0x01C 32 OSCCTRL0 Oscillator Control Register 0x020 32 MODE Oscillator Mode 0 1 GAIN Gain 1 2 AGC Automatic Gain Control 3 1 STARTUP Oscillator Start-up Time 8 4 OSCEN Oscillator Enable 16 1 PLL PLL0 Control Register 0x024 32 PLLEN PLL Enable 0 1 PLLOSC PLL Oscillator Select 1 2 PLLOPT PLL Option 3 3 PLLDIV PLL Division Factor 8 4 PLLMUL PLL Multiply Factor 16 4 PLLCOUNT PLL Count 24 6 DFLL0CONF DFLL0 Config Register 0x028 32 EN Enable 0 1 MODE Mode Selection 1 1 STABLE Stable DFLL Frequency 2 1 LLAW Lose Lock After Wake 3 1 CCDIS Chill Cycle Disable 5 1 QLDIS Quick Lock Disable 6 1 RANGE Range Value 16 2 FCD Fuse Calibration Done 23 1 CALIB Calibration Value 24 4 DFLL0VAL DFLL Value Register 0x02C 32 FINE Fine Value 0 8 COARSE Coarse Value 16 5 DFLL0MUL DFLL0 Multiplier Register 0x030 32 MUL DFLL Multiply Factor 0 16 DFLL0STEP DFLL0 Step Register 0x034 32 FSTEP Fine Maximum Step 0 8 CSTEP Coarse Maximum Step 16 5 DFLL0SSG DFLL0 Spread Spectrum Generator Control Register 0x038 32 EN Enable 0 1 write-only PRBS Pseudo Random Bit Sequence 1 1 write-only AMPLITUDE SSG Amplitude 8 5 write-only STEPSIZE SSG Step Size 16 5 write-only DFLL0RATIO DFLL0 Ratio Registe 0x03C 32 read-only RATIODIFF Multiplication Ratio Difference 0 16 read-only DFLL0SYNC DFLL0 Synchronization Register 0x040 32 write-only SYNC Synchronization 0 1 write-only RCCR System RC Oscillator Calibration Register 0x044 32 CALIB Calibration Value 0 10 FCD Flash Calibration Done 16 1 RCFASTCFG 4/8/12 MHz RC Oscillator Configuration Register 0x048 32 EN Oscillator Enable 0 1 TUNEEN Tuner Enable 1 1 JITMODE Jitter Mode 2 1 NBPERIODS Number of 32kHz Periods 4 3 FCD RCFAST Fuse Calibration Done 7 1 FRANGE Frequency Range 8 2 LOCKMARGIN Accepted Count Error for Lock 12 4 CALIB Oscillator Calibration Value 16 7 RCFASTSR 4/8/12 MHz RC Oscillator Status Register 0x04C 32 CURTRIM Current Trim Value 0 7 CNTERR Current Count Error 16 5 SIGN Sign of Current Count Error 21 1 LOCK Lock 24 1 LOCKLOST Lock Lost 25 1 UPDATED Current Trim Value Updated 31 1 RC80MCR 80 MHz RC Oscillator Register 0x050 32 EN Enable 0 1 FCD Flash Calibration Done 7 1 CALIB Calibration Value 16 2 HRPCR High Resolution Prescaler Control Register 0x064 32 HRPEN High Resolution Prescaler Enable 0 1 CKSEL Clock Input Selection 1 3 HRCOUNT High Resolution Counter 8 24 FPCR Fractional Prescaler Control Register 0x068 32 FPEN High Resolution Prescaler Enable 0 1 CKSEL Clock Input Selection 1 3 FPMUL Fractional Prescaler Multiplier Register 0x06C 32 FPMUL Fractional Prescaler Multiplication Factor 0 16 FPDIV Fractional Prescaler DIVIDER Register 0x070 32 FPDIV Fractional Prescaler Division Factor 0 16 12 0x4 GCCTRL%s Generic Clock Control 0x074 32 CEN Clock Enable 0 1 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 DIV Division Factor 16 16 RCFASTVERSION 4/8/12 MHz RC Oscillator Version Register 0x3D8 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 GCLKPRESCVERSION Generic Clock Prescaler Version Register 0x3DC 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 PLLIFAVERSION PLL Version Register 0x3E0 32 read-only VERSION Version number 0 12 VARIANT Variant nubmer 16 4 OSCIFAVERSION Oscillator 0 Version Register 0x3E4 32 read-only VERSION Version number 0 12 VARIANT Variant nubmer 16 4 DFLLIFBVERSION DFLL Version Register 0x3E8 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 RCOSCIFAVERSION System RC Oscillator Version Register 0x3EC 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 FLOVERSION Frequency Locked Oscillator Version Register 0x3F0 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 RC80MVERSION 80MHz RC Oscillator Version Register 0x3F4 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 GCLKIFVERSION Generic Clock Version Register 0x3F8 32 read-only VERSION Version number 0 12 VARIANT Variant number 16 4 VERSION SCIF Version Register 0x3FC 32 read-only 0x00000130 VERSION Version number 0 12 VARIANT Variant number 16 4 SMAP 1.0.0 System Manager Access Port SMAP SMAP_ 0x400A3000 0 0x400 registers CR Control Register 0x00 32 write-only EN Enable 0 1 write-only DIS Disable 1 1 write-only CRC User Page Read 2 1 write-only FSPR Flash Supplementary Page Read 3 1 write-only CE Chip Erase 4 1 write-only SR Status Register 0x04 32 read-only DONE Operation done 0 1 read-only HCR Hold Core reset 1 1 read-only BERR Bus error 2 1 read-only FAIL Failure 3 1 read-only LCK Lock 4 1 read-only EN Enabled 8 1 read-only PROT Protected 9 1 read-only DBGP Debugger Present 10 1 read-only STATE State 24 3 read-only SCR Status Clear Register 0x08 32 write-only DONE Done 0 1 write-only HCR Hold Core Register 1 1 write-only BERR Bus error 2 1 write-only FAIL Failure 3 1 write-only LCK Lock error 4 1 write-only ADDR Address Register 0x0C 32 ADDR Address Value 2 30 LENGTH Length Register 0x10 32 LENGTH Length Register 2 30 DATA Data Register 0x14 32 DATA Generic data register 0 32 VERSION VERSION register 0x28 32 read-only 0x00000100 VERSION Version number 0 12 read-only VARIANT Variant number 16 4 read-only CIDR Chip ID Register 0xF0 32 read-only VERSION Version of the Device 0 5 read-only EPROC Embedded Processor 5 3 read-only NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 read-only SRAMSIZ Internal SRAM Size 16 5 read-only ARCH Architecture Identifier 21 7 read-only NVPTYP Nonvolatile Program Memory Type 28 3 read-only EXT Extension Flag 31 1 read-only EXID Chip ID Extension Register 0xF4 32 read-only EXID Chip ID Extension 0 32 read-only IDR AP Identification register 0xFC 32 read-only 0x003E0000 APIDV AP Identification Variant 0 4 read-only APID AP Identification 4 4 read-only CLSS Class 16 1 read-only IC JEP-106 Identity Code 17 7 read-only CC JEP-106 Continuation Code 24 4 read-only REVISION Revision 28 4 read-only SPI 2.1.1 Serial Peripheral Interface SPI SPI_ 0x40008000 0 0x400 registers SPI_INTREQ 54 CR Control Register 0x00 32 write-only SPIEN SPI Enable 0 1 SPIENSelect 0 No effect. 0x0 1 Enables the SPI to transfer and receive data. 0x1 SPIDIS SPI Disable 1 1 SPIDISSelect 0 No effect. 0x0 1 Disables the SPI.All pins are set in input mode and no data is received or transmitted.If a transfer is in progress, the transfer is finished before the SPI is disabled.If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. 0x1 SWRST SPI Software Reset 7 1 SWRSTSelect 0 No effect. 0x0 1 Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. 0x1 FLUSHFIFO Flush FIFO command 8 1 LASTXFER Last Transfer 24 1 LASTXFERSelect 0 No effect. 0x0 1 The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed. 0x1 MR Mode Register 0x04 32 MSTR Master/Slave Mode 0 1 MSTRSelect 0 SPI is in Slave mode. 0x0 1 SPI is in Master mode. 0x1 PS Peripheral Select 1 1 PSSelect 0 Fixed Peripheral Select. 0x0 1 Variable Peripheral Select. 0x1 PCSDEC Chip Select Decode 2 1 PCSDECSelect 0 The chip selects are directly connected to a peripheral device. 0x0 1 The four chip select lines are connected to a 4- to 16-bit decoder.When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bitdecoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:CSR0 defines peripheral chip select signals 0 to 3.CSR1 defines peripheral chip select signals 4 to 7.CSR2 defines peripheral chip select signals 8 to 11.CSR3 defines peripheral chip select signals 12 to 15. 0x1 MODFDIS Mode Fault Detection 4 1 MODFDISSelect 0 Mode fault detection is enabled. 0x0 1 Mode fault detection is disabled. 0x1 WDRBT wait data read before transfer 5 1 RXFIFOEN FIFO in Reception Enable 6 1 LLB Local Loopback Enable 7 1 LLBSelect 0 Local loopback path disabled. 0x0 1 Local loopback path enabled.LLB controls the local loopback on the data serializer for testing in Master Mode only. 0x1 PCS Peripheral Chip Select 16 4 DLYBCS Delay Between Chip Selects 24 8 RDR Receive Data Register 0x08 32 read-only RD Receive Data 0 16 PCS Peripheral Chip Select 16 4 TDR Transmit Data Register 0x0C 32 write-only TD Transmit Data 0 16 PCS Peripheral Chip Select 16 4 LASTXFER Last Transfer 24 1 LASTXFERSelect 0 No effect. 0x0 1 The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed. 0x1 SR Status Register 0x10 32 read-only 0x000000F0 RDRF Receive Data Register Full 0 1 RDRFSelect 0 No data has been received since the last read of RDR 0x0 1 Data has been received and the received data has been transferred from the serializer to RDR since the last readof RDR. 0x1 TDRE Transmit Data Register Empty 1 1 TDRESelect 0 Data has been written to TDR and not yet transferred to the serializer. 0x0 1 The last data written in the Transmit Data Register has been transferred to the serializer.TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. 0x1 MODF Mode Fault Error 2 1 MODFSelect 0 No Mode Fault has been detected since the last read of SR. 0x0 1 A Mode Fault occurred since the last read of the SR. 0x1 OVRES Overrun Error Status 3 1 OVRESSelect 0 No overrun has been detected since the last read of SR. 0x0 1 An overrun has occurred since the last read of SR. 0x1 ENDRX End of RX buffer 4 1 ENDRXSelect 0 The Receive Counter Register has not reached 0 since the last write in RCR or RNCR. 0x0 1 The Receive Counter Register has reached 0 since the last write in RCR or RNCR. 0x1 ENDTX End of TX buffer 5 1 ENDTXSelect 0 The Transmit Counter Register has not reached 0 since the last write in TCR or TNCR. 0x0 1 The Transmit Counter Register has reached 0 since the last write in TCR or TNCR. 0x1 RXBUFF RX Buffer Full 6 1 RXBUFFSelect 0 RCR or RNCR has a value other than 0. 0x0 1 Both RCR and RNCR has a value of 0. 0x1 TXBUFE TX Buffer Empty 7 1 TXBUFESelect 0 TCR or TNCR has a value other than 0. 0x0 1 Both TCR and TNCR has a value of 0. 0x1 NSSR NSS Rising 8 1 NSSRSelect 0 No rising edge detected on NSS pin since last read. 0x0 1 A rising edge occurred on NSS pin since last read. 0x1 TXEMPTY Transmission Registers Empty 9 1 TXEMPTYSelect 0 As soon as data is written in TDR. 0x0 1 TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion ofsuch delay. 0x1 UNDES Underrun Error Status (Slave Mode Only) 10 1 SPIENS SPI Enable Status 16 1 SPIENSSelect 0 SPI is disabled. 0x0 1 SPI is enabled. 0x1 IER Interrupt Enable Register 0x14 32 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 RDRFSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 TDRE Transmit Data Register Empty Interrupt Enable 1 1 TDRESelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 MODF Mode Fault Error Interrupt Enable 2 1 MODFSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 OVRES Overrun Error Interrupt Enable 3 1 OVRESSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 ENDRX End of Receive Buffer Interrupt Enable 4 1 ENDRXSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 ENDTX End of Transmit Buffer Interrupt Enable 5 1 ENDTXSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 RXBUFF Receive Buffer Full Interrupt Enable 6 1 RXBUFFSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 TXBUFE Transmit Buffer Empty Interrupt Enable 7 1 TXBUFESelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 NSSR NSS Rising Interrupt Enable 8 1 NSSRSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 TXEMPTY Transmission Registers Empty Enable 9 1 TXEMPTYSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 UNDES Underrun Error Interrupt Enable 10 1 IDR Interrupt Disable Register 0x18 32 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 RDRFSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 TDRE Transmit Data Register Empty Interrupt Disable 1 1 TDRESelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 MODF Mode Fault Error Interrupt Disable 2 1 MODFSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 OVRES Overrun Error Interrupt Disable 3 1 OVRESSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 ENDRX End of Receive Buffer Interrupt Disable 4 1 ENDRXSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 ENDTX End of Transmit Buffer Interrupt Disable 5 1 ENDTXSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 RXBUFF Receive Buffer Full Interrupt Disable 6 1 RXBUFFSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 TXBUFE Transmit Buffer Empty Interrupt Disable 7 1 TXBUFESelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 NSSR NSS Rising Interrupt Disable 8 1 NSSRSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 TXEMPTY Transmission Registers Empty Disable 9 1 TXEMPTYSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 UNDES Underrun Error Interrupt Disable 10 1 IMR Interrupt Mask Register 0x1C 32 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 RDRFSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 TDRE Transmit Data Register Empty Interrupt Mask 1 1 TDRESelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 MODF Mode Fault Error Interrupt Mask 2 1 MODFSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 OVRES Overrun Error Interrupt Mask 3 1 OVRESSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 ENDRX End of Receive Buffer Interrupt Mask 4 1 ENDRXSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 ENDTX End of Transmit Buffer Interrupt Mask 5 1 ENDTXSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 RXBUFF Receive Buffer Full Interrupt Mask 6 1 RXBUFFSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 TXBUFE Transmit Buffer Empty Interrupt Mask 7 1 TXBUFESelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 NSSR NSS Rising Interrupt Mask 8 1 NSSRSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 TXEMPTY Transmission Registers Empty Mask 9 1 TXEMPTYSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 UNDES Underrun Error Interrupt Mask 10 1 4 0x4 CSR%s Chip Select Register 0x30 32 CPOL Clock Polarity 0 1 CPOLSelect 0 The inactive state value of SPCK is logic level zero. 0x0 1 The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. 0x1 NCPHA Clock Phase 1 1 NCPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. 0x1 CSNAAT Chip Select Not Active After Transfer 2 1 CSAAT Chip Select Active After Transfer 3 1 CSAATSelect 0 The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 0x0 1 The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. 0x1 BITS Bits Per Transfer 4 4 BITSSelect 8_BPT 8 bits per transfer 0x0 9_BPT 9 bits per transfer 0x1 10_BPT 10 bits per transfer 0x2 11_BPT 11 bits per transfer 0x3 12_BPT 12 bits per transfer 0x4 13_BPT 13 bits per transfer 0x5 14_BPT 14 bits per transfer 0x6 15_BPT 15 bits per transfer 0x7 16_BPT 16 bits per transfer 0x8 SCBR Serial Clock Baud Rate 8 8 DLYBS Delay Before SPCK 16 8 DLYBCT Delay Between Consecutive Transfers 24 8 WPCR Write Protection control Register 0xE4 32 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key Password 8 24 WPKEYSelect VALUE SPI Write Protection Key Password 0x535049 WPSR Write Protection status Register 0xE8 32 read-only WPVS Write Protection Violation Status 0 3 WPVSSelect WRITE_WITH_WP The Write Protection has blocked a Write access to a protected register (since the last read). 0x1 SWRST_WITH_WP Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). 0x2 UNEXPECTED_WRITE Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select "i" was active) since the last read. 0x4 WPVSRC Write Protection Violation Source 8 8 FEATURES Features Register 0xF8 32 read-only NCS Number of Chip Selects 0 4 PCONF Polarity is Configurable 4 1 PPNCONF Polarity is Positive if Polarity is not Configurable 5 1 PHCONF Phase is Configurable 6 1 PHZNCONF Phase is Zero if Phase is not Configurable 7 1 LENCONF Character Length is Configurable 8 1 LENNCONF Character Length if not Configurable 9 7 EXTDEC External Decoder is True 16 1 CSNAATIMPL CSNAAT Features are Implemented 17 1 BRPBHSB Bridge Type is PB to HSB 18 1 FIFORIMPL FIFO in Reception is Implemented 19 1 SWPIMPL Spurious Write Protection is Implemented 20 1 VERSION Version Register 0xFC 32 read-only 0x00000211 VERSION Version 0 12 MFN mfn 16 3 TC0 4.0.2 Timer/Counter 0 TC TC_ 0x40010000 0 0x400 registers TC0_INTREQ_0 55 TC0_INTREQ_1 56 TC0_INTREQ_2 57 3 0x40 CCR%s Channel Control Register Channel 0x00 32 write-only CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 3 0x40 CMR%s_CAPTURE Channel Mode Register Channel CMR%s 0x04 32 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 3 0x40 CMR%s_WAVEFORM Channel Mode Register Channel CMR%s 0x04 32 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 3 0x40 SMMR%s Stepper Motor Mode Register 0x08 32 GCEN Gray Count Enable 0 1 DOWN Down Count 1 1 3 0x40 CV%s Counter Value Channel 0x10 32 read-only CV Counter Value 0 16 3 0x40 RA%s Register A Channel 0x14 32 RA Register A 0 16 3 0x40 RB%s Register B Channel 0x18 32 RB Register B 0 16 3 0x40 RC%s Register C Channel 0x1C 32 RC Register C 0 16 3 0x40 SR%s Status Register Channel 0x20 32 read-only COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 3 0x40 IER%s Interrupt Enable Register Channel 0x24 32 write-only COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 3 0x40 IDR%s Interrupt Disable Register Channel 0x28 32 write-only COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 3 0x40 IMR%s Interrupt Mask Register Channel 0x2C 32 read-only COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 BCR TC Block Control Register 0xC0 32 write-only SYNC Synchro Command 0 1 SYNCSelect 0 No effect. 0x0 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0x1 BMR TC Block Mode Register 0xC4 32 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Select TCLK0 as clock signal 0. 0x0 NO_CLK Select no clock as clock signal 0. 0x1 TIOA1 Select TIOA1 as clock signal 0. 0x2 TIOA2 Select TIOA2 as clock signal 0. 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Select TCLK1 as clock signal 1. 0x0 NO_CLK Select no clock as clock signal 1. 0x1 TIOA0 Select TIOA0 as clock signal 1. 0x2 TIOA2 Select TIOA2 as clock signal 1. 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Select TCLK2 as clock signal 2. 0x0 NO_CLK Select no clock as clock signal 2. 0x1 TIOA0 Select TIOA0 as clock signal 2. 0x2 TIOA1 Select TIOA1 as clock signal 2. 0x3 WPMR Write Protect Mode Register 0xE4 32 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 FEATURES Features Register 0xF8 32 read-only CTRSIZE Counter Size 0 8 UPDNIMPL Up Down is Implemented 8 1 BRPBHSB Bridge Type is PB to HSB 9 1 VERSION Version Register 0xFC 32 read-only 0x00000402 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 TC1 Timer/Counter 1 0x40014000 TC1_INTREQ_0 58 TC1_INTREQ_1 59 TC1_INTREQ_2 60 TRNG 1.0.3 True Random Number Generator TRNG TRNG_ 0x40068000 0 0x400 registers TRNG_INTREQ 73 CR Control Register 0x00 32 write-only ENABLE Enables the TRNG to provide random values 0 1 write-only KEY Security Key 8 24 IER Interrupt Enable Register 0x10 32 write-only DATRDY Data Ready Interrupt Enable 0 1 write-only IDR Interrupt Disable Register 0x14 32 write-only DATRDY Data Ready Interrupt Disable 0 1 write-only IMR Interrupt Mask Register 0x18 32 read-only DATRDY Data Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x1C 32 read-only DATRDY Data Ready Interrupt Status 0 1 read-only ODATA Output Data Register 0x50 32 read-only ODATA Output Data 0 1 read-only VERSION Version Register 0xFC 32 read-only 0x00000103 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 3 read-only TWIM0 1.2.0 Two-wire Master Interface 0 TWIM TWIM_ 0x40018000 0 0x400 registers TWIM0_INTREQ 61 CR Control Register 0x00 32 write-only MEN Master Enable 0 1 MDIS Master Disable 1 1 SMEN SMBus Enable 4 1 SMDIS SMBus Disable 5 1 SWRST Software Reset 7 1 STOP Stop the current transfer 8 1 CWGR Clock Waveform Generator Register 0x04 32 LOW Clock Low Cycles 0 8 HIGH Clock High Cycles 8 8 STASTO START and STOP Cycles 16 8 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 SMBTR SMBus Timing Register 0x08 32 TLOWS Slave Clock stretch maximum cycles 0 8 TLOWM Master Clock stretch maximum cycles 8 8 THMAX Clock High maximum cycles 16 8 EXP SMBus Timeout Clock prescaler 28 4 CMDR Command Register 0x0C 32 READ Transfer Direction 0 1 SADR Slave Address 1 10 TENBIT Ten Bit Addressing Mode 11 1 REPSAME Transfer is to same address as previous address 12 1 START Send START condition 13 1 STOP Send STOP condition 14 1 VALID CMDR Valid 15 1 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NCMDR Next Command Register 0x10 32 READ Transfer Direction 0 1 SADR Slave Address 1 10 TENBIT Ten Bit Addressing Mode 11 1 REPSAME Transfer is to same address as previous address 12 1 START Send START condition 13 1 STOP Send STOP condition 14 1 VALID CMDR Valid 15 1 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 RHR Receive Holding Register 0x14 32 read-only RXDATA Received Data 0 8 THR Transmit Holding Register 0x18 32 write-only TXDATA Data to Transmit 0 8 SR Status Register 0x1C 32 read-only 0x00000002 RXRDY RHR Data Ready 0 1 TXRDY THR Data Ready 1 1 CRDY Ready for More Commands 2 1 CCOMP Command Complete 3 1 IDLE Master Interface is Idle 4 1 BUSFREE Two-wire Bus is Free 5 1 ANAK NAK in Address Phase Received 8 1 DNAK NAK in Data Phase Received 9 1 ARBLST Arbitration Lost 10 1 SMBALERT SMBus Alert 11 1 TOUT Timeout 12 1 PECERR PEC Error 13 1 STOP Stop Request Accepted 14 1 MENB Master Interface Enable 16 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IER Interrupt Enable Register 0x20 32 write-only RXRDY RHR Data Ready 0 1 TXRDY THR Data Ready 1 1 CRDY Ready for More Commands 2 1 CCOMP Command Complete 3 1 IDLE Master Interface is Idle 4 1 BUSFREE Two-wire Bus is Free 5 1 ANAK NAK in Address Phase Received 8 1 DNAK NAK in Data Phase Received 9 1 ARBLST Arbitration Lost 10 1 SMBALERT SMBus Alert 11 1 TOUT Timeout 12 1 PECERR PEC Error 13 1 STOP Stop Request Accepted 14 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDR Interrupt Disable Register 0x24 32 write-only RXRDY RHR Data Ready 0 1 TXRDY THR Data Ready 1 1 CRDY Ready for More Commands 2 1 CCOMP Command Complete 3 1 IDLE Master Interface is Idle 4 1 BUSFREE Two-wire Bus is Free 5 1 ANAK NAK in Address Phase Received 8 1 DNAK NAK in Data Phase Received 9 1 ARBLST Arbitration Lost 10 1 SMBALERT SMBus Alert 11 1 TOUT Timeout 12 1 PECERR PEC Error 13 1 STOP Stop Request Accepted 14 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IMR Interrupt Mask Register 0x28 32 read-only RXRDY RHR Data Ready 0 1 TXRDY THR Data Ready 1 1 CRDY Ready for More Commands 2 1 CCOMP Command Complete 3 1 IDLE Master Interface is Idle 4 1 BUSFREE Two-wire Bus is Free 5 1 ANAK NAK in Address Phase Received 8 1 DNAK NAK in Data Phase Received 9 1 ARBLST Arbitration Lost 10 1 SMBALERT SMBus Alert 11 1 TOUT Timeout 12 1 PECERR PEC Error 13 1 STOP Stop Request Accepted 14 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 SCR Status Clear Register 0x2C 32 write-only CCOMP Command Complete 3 1 ANAK NAK in Address Phase Received 8 1 DNAK NAK in Data Phase Received 9 1 ARBLST Arbitration Lost 10 1 SMBALERT SMBus Alert 11 1 TOUT Timeout 12 1 PECERR PEC Error 13 1 STOP Stop Request Accepted 14 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PR Parameter Register 0x30 32 read-only 0x00000001 HS HS-mode 0 1 VR Version Register 0x34 32 read-only 0x00000120 VERSION Version number 0 12 VARIANT Variant number 16 4 HSCWGR HS-mode Clock Waveform Generator 0x38 32 LOW Clock Low Cycles 0 8 HIGH Clock High Cycles 8 8 STASTO START and STOP Cycles 16 8 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 SRR Slew Rate Register 0x3C 32 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 FILTER Input Spike Filter Control 28 2 HSSRR HS-mode Slew Rate Register 0x40 32 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLDRIVEH Clock Drive Strength HIGH 20 2 CLSLEW Clock Slew Limit 24 2 FILTER Input Spike Filter Control 28 2 TWIM1 Two-wire Master Interface 1 0x4001C000 TWIM1_INTREQ 63 TWIM2 Two-wire Master Interface 2 0x40078000 TWIM2_INTREQ 77 TWIM3 Two-wire Master Interface 3 0x4007C000 TWIM3_INTREQ 78 TWIS0 1.4.0 Two-wire Slave Interface 0 TWIS TWIS_ 0x40018400 0 0x400 registers TWIS0_INTREQ 62 CR Control Register 0x00 32 SEN Slave Enable 0 1 SMEN SMBus Mode Enable 1 1 SMATCH Slave Address Match 2 1 GCMATCH General Call Address Match 3 1 STREN Clock Stretch Enable 4 1 SWRST Software Reset 7 1 SMBALERT SMBus Alert 8 1 SMDA SMBus Default Address 9 1 SMHH SMBus Host Header 10 1 PECEN Packet Error Checking Enable 11 1 ACK Slave Receiver Data Phase ACK Value 12 1 CUP NBYTES Count Up 13 1 SOAM Stretch Clock on Address Match 14 1 SODR Stretch Clock on Data Byte Reception 15 1 ADR Slave Address 16 10 TENBIT Ten Bit Address Match 26 1 BRIDGE Bridge Control Enable 27 1 NBYTES NBYTES Register 0x04 32 NBYTES Number of Bytes to Transfer 0 8 TR Timing Register 0x08 32 TLOWS SMBus Tlow:sext Cycles 0 8 TTOUT SMBus Ttimeout Cycles 8 8 SUDAT Data Setup Cycles 16 8 EXP Clock Prescaler 28 4 RHR Receive Holding Register 0x0C 32 read-only RXDATA Received Data Byte 0 8 THR Transmit Holding Register 0x10 32 write-only TXDATA Data Byte to Transmit 0 8 PECR Packet Error Check Register 0x14 32 read-only PEC Calculated PEC Value 0 8 SR Status Register 0x18 32 read-only 0x00000002 RXRDY RX Buffer Ready 0 1 TXRDY TX Buffer Ready 1 1 SEN Slave Enabled 2 1 TCOMP Transmission Complete 3 1 TRA Transmitter Mode 5 1 URUN Underrun 6 1 ORUN Overrun 7 1 NAK NAK Received 8 1 SMBTOUT SMBus Timeout 12 1 SMBPECERR SMBus PEC Error 13 1 BUSERR Bus Error 14 1 SAM Slave Address Match 16 1 GCM General Call Match 17 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBHHM SMBus Host Header Address Match 19 1 SMBDAM SMBus Default Address Match 20 1 STO Stop Received 21 1 REP Repeated Start Received 22 1 BTF Byte Transfer Finished 23 1 IER Interrupt Enable Register 0x1C 32 write-only RXRDY RX Buffer Ready 0 1 TXRDY TX Buffer Ready 1 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 ORUN Overrun 7 1 NAK NAK Received 8 1 SMBTOUT SMBus Timeout 12 1 SMBPECERR SMBus PEC Error 13 1 BUSERR Bus Error 14 1 SAM Slave Address Match 16 1 GCM General Call Match 17 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBHHM SMBus Host Header Address Match 19 1 SMBDAM SMBus Default Address Match 20 1 STO Stop Received 21 1 REP Repeated Start Received 22 1 BTF Byte Transfer Finished 23 1 IDR Interrupt Disable Register 0x20 32 write-only RXRDY RX Buffer Ready 0 1 TXRDY TX Buffer Ready 1 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 ORUN Overrun 7 1 NAK NAK Received 8 1 SMBTOUT SMBus Timeout 12 1 SMBPECERR SMBus PEC Error 13 1 BUSERR Bus Error 14 1 SAM Slave Address Match 16 1 GCM General Call Match 17 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBHHM SMBus Host Header Address Match 19 1 SMBDAM SMBus Default Address Match 20 1 STO Stop Received 21 1 REP Repeated Start Received 22 1 BTF Byte Transfer Finished 23 1 IMR Interrupt Mask Register 0x24 32 read-only RXRDY RX Buffer Ready 0 1 TXRDY TX Buffer Ready 1 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 ORUN Overrun 7 1 NAK NAK Received 8 1 SMBTOUT SMBus Timeout 12 1 SMBPECERR SMBus PEC Error 13 1 BUSERR Bus Error 14 1 SAM Slave Address Match 16 1 GCM General Call Match 17 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBHHM SMBus Host Header Address Match 19 1 SMBDAM SMBus Default Address Match 20 1 STO Stop Received 21 1 REP Repeated Start Received 22 1 BTF Byte Transfer Finished 23 1 SCR Status Clear Register 0x28 32 write-only TCOMP Transmission Complete 3 1 URUN Underrun 6 1 ORUN Overrun 7 1 NAK NAK Received 8 1 SMBTOUT SMBus Timeout 12 1 SMBPECERR SMBus PEC Error 13 1 BUSERR Bus Error 14 1 SAM Slave Address Match 16 1 GCM General Call Match 17 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBHHM SMBus Host Header Address Match 19 1 SMBDAM SMBus Default Address Match 20 1 STO Stop Received 21 1 REP Repeated Start Received 22 1 BTF Byte Transfer Finished 23 1 PR Parameter Register 0x2C 32 read-only 0x00000001 HS HS-mode 0 1 read-only VR Version Register 0x30 32 read-only 0x00000140 VERSION Version Number 0 12 VARIANT Variant Number 16 4 HSTR HS-mode Timing Register 0x34 32 HDDAT Data Hold Cycles 16 8 SRR Slew Rate Register 0x38 32 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 HSSRR HS-mode Slew Rate Register 0x3C 32 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIS1 Two-wire Slave Interface 1 0x4001C400 TWIS1_INTREQ 64 USART0 6.0.2.1 Universal Synchronous Asynchronous Receiver Transmitter 0 USART USART_ 0x40024000 0 0x400 registers USART0_INTREQ 65 CR_LIN_MODE Control Register CR 0x00 32 write-only RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 CR_SPI_MASTER_MODE Control Register CR 0x00 32 write-only RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 FCS Force SPI Chip Select 18 1 FCSSelect 0 No effect 0x0 1 Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) 0x1 RCS Release SPI Chip Select 19 1 RCSSelect 0 No effect 0x0 1 Releases the Slave Select Line NSS (RTS pin) 0x1 CR_USART_MODE Control Register CR 0x00 32 write-only RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 MR_SPI_MODE Mode Register MR 0x04 32 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 INVDATA Inverted data 23 1 MAX_ITERATION Max interation 24 3 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 MR_USART_MODE Mode Register MR 0x04 32 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 SYNC Synchronous Mode Select 8 1 SYNCSelect 0 USART operates in Synchronous Mode 0x0 1 USART operates in Asynchronous Mode 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 MSBF Bit Order 16 1 MSBFSelect LSBF Least Significant Bit first 0x0 MSBF Most Significant Bit first 0x1 MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 VAR_SYNC Variable synchronization of command/data sync Start Frame Delimiter 22 1 VAR_SYNCSelect 0 User defined configuration of command or data sync field depending on SYNC value 0x0 1 The sync field is updated when a character is written into THR register 0x1 INVDATA Inverted data 23 1 MAX_ITERATION Max interation 24 3 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 MAN Manchester Encoder/Decoder Enable 29 1 MANSelect 0 Manchester Encoder/Decoder is disabled 0x0 1 Manchester Encoder/Decoder is enabled 0x1 MODSYNC Manchester Synchronization Mode 30 1 MODSYNCSelect 0 The Manchester Start bit is a 0 to 1 transition 0x0 1 The Manchester Start bit is a 1 to 0 transition 0x1 ONEBIT Start Frame Delimiter selector 31 1 ONEBITSelect 0 Start Frame delimiter is COMMAND or DATA SYNC 0x0 1 Start Frame delimiter is One Bit 0x1 IER_LIN_MODE Interrupt Enable Register IER 0x08 32 write-only RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 IER_SPI_SLAVE_MODE Interrupt Enable Register IER 0x08 32 write-only RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Enable 10 1 UNRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 IER_USART_MODE Interrupt Enable Register IER 0x08 32 write-only RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 MANE Manchester Error Interrupt Enable 20 1 MANEA Manchester Error Interrupt Enable 24 1 MANEASelect 0 No effect 0x0 1 Enables the interrupt 0x1 IDR_LIN_MODE Interrupt Disable Register IDR 0x0C 32 write-only RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 IDR_SPI_SLAVE_MODE Interrupt Disable Register IDR 0x0C 32 write-only RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Disable 10 1 UNRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 NACK Non Acknowledge Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 IDR_USART_MODE Interrupt Disable Register IDR 0x0C 32 write-only RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 NACK Non Acknowledge Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 MANE Manchester Error Interrupt Disable 20 1 MANEA Manchester Error Interrupt Disable 24 1 MANEASelect 0 No effect 0x0 1 Disables the corresponding interrupt 0x1 IMR_LIN_MODE Interrupt Mask Register IMR 0x10 32 read-only RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 IMR_SPI_SLAVE_MODE Interrupt Mask Register IMR 0x10 32 read-only RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 UNRE SPI Underrun Error Interrupt Mask 10 1 UNRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 IMR_USART_MODE Interrupt Mask Register IMR 0x10 32 read-only RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 MANE Manchester Error Interrupt Mask 20 1 MANEA Manchester Error Interrupt Mask 24 1 MANEASelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 CSR_LIN_MODE Channel Status Register CSR 0x14 32 read-only RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINTC LIN Transfer Conpleted 15 1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINBE LIN Bit Error 25 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINIPE LIN Identifier Parity Error 27 1 LINCE LIN Checksum Error 28 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 CSR_SPI_SLAVE_MODE Channel Status Register CSR 0x14 32 read-only RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 UNRE SPI Underrun Error 10 1 UNRESelect 0 No SPI underrun error has occurred since the last RSTSTA 0x0 1 At least one SPI underrun error has occurred since the last RSTSTA 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 NACK Non Acknowledge 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 CTS Image of CTS Input 23 1 CTSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 CSR_USART_MODE Channel Status Register CSR 0x14 32 read-only RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 NACK Non Acknowledge 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 CTS Image of CTS Input 23 1 CTSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 MANERR Manchester Error 24 1 MANERRSelect 0 No Manchester error has been detected since the last RSTSTA 0x0 1 At least one Manchester error has been detected since the last RSTSTA 0x1 RHR Receiver Holding Register 0x18 32 read-only RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 THR Transmitter Holding Register 0x1C 32 write-only TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 BRGR Baud Rate Generator Register 0x20 32 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 RTOR Receiver Time-out Register 0x24 32 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 TTGR Transmitter Timeguard Register 0x28 32 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 FIDI FI DI Ratio Register 0x40 32 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 NER Number of Errors Register 0x44 32 read-only NB_ERRORS Error number during ISO7816 transfers 0 8 IFR IrDA Filter Register 0x4C 32 IRDA_FILTER Irda filter 0 8 MAN Manchester Configuration Register 0x50 32 0x30011004 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 LINMR LIN Mode Register 0x54 32 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 WKUPTYP Wakeup Signal Type 7 1 DLC Data Length Control 8 8 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 LINIR LIN Identifier Register 0x58 32 IDCHR Identifier Character 0 8 LINBRR LIN Baud Rate Register 0x5C 32 read-only LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 WPMR Write Protect Mode Register 0xE4 32 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 VERSION Version Register 0xFC 32 read-only 0x00000602 VERSION Version 0 12 MFN MFN 16 4 USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 0x40028000 USART1_INTREQ 66 USART2 Universal Synchronous Asynchronous Receiver Transmitter 2 0x4002C000 USART2_INTREQ 67 USART3 Universal Synchronous Asynchronous Receiver Transmitter 3 0x40030000 USART3_INTREQ 68 USBC 3.1.0 USB 2.0 Interface USBC USBC_ 0x400A5000 0 0x1000 registers USBC_INTREQ 18 UDCON Device General Control Register 0x000 32 0x00000100 UADD USB Address 0 7 ADDEN Address Enable 7 1 DETACH Detach 8 1 RMWKUP Remote Wake-Up 9 1 SPDCONF Speed configuration 10 2 LS Low Speed Mode Force 12 1 TSTJ Test mode J 13 1 TSTK Test mode K 14 1 TSTPCKT Test Packet mode 15 1 OPMODE2 Specific Operational mode 16 1 GNAK Global NAK 17 1 UDINT Device Global Interupt Register 0x004 32 read-only SUSP Suspend Interrupt 0 1 read-only MSOF Micro Start of Frame Interrupt 1 1 read-only SOF Start of Frame Interrupt 2 1 read-only EORST End of Reset Interrupt 3 1 read-only WAKEUP Wake-Up Interrupt 4 1 read-only EORSM End Of Resume Interrupt 5 1 read-only UPRSM Upstream Resume Interrupt 6 1 read-only EP0INT Endpoint 0 Interrupt 12 1 read-only EP1INT Endpoint 1 Interrupt 13 1 read-only EP2INT Endpoint 2 Interrupt 14 1 read-only EP3INT Endpoint 3 Interrupt 15 1 read-only EP4INT Endpoint 4 Interrupt 16 1 read-only EP5INT Endpoint 5 Interrupt 17 1 read-only EP6INT Endpoint 6 Interrupt 18 1 read-only EP7INT Endpoint 7 Interrupt 19 1 read-only UDINTCLR Device Global Interrupt Clear Register 0x008 32 write-only SUSPC SUSP Interrupt Clear 0 1 write-only MSOFC MSOF Interrupt Clear 1 1 write-only SOFC SOF Interrupt Clear 2 1 write-only EORSTC EORST Interrupt Clear 3 1 write-only WAKEUPC WAKEUP Interrupt Clear 4 1 write-only EORSMC EORSM Interrupt Clear 5 1 write-only UPRSMC UPRSM Interrupt Clear 6 1 write-only UDINTSET Device Global Interrupt Set Regsiter 0x00C 32 write-only SUSPS SUSP Interrupt Set 0 1 write-only MSOFS MSOF Interrupt Set 1 1 write-only SOFS SOF Interrupt Set 2 1 write-only EORSTS EORST Interrupt Set 3 1 write-only WAKEUPS WAKEUP Interrupt Set 4 1 write-only EORSMS EORSM Interrupt Set 5 1 write-only UPRSMS UPRSM Interrupt Set 6 1 write-only UDINTE Device Global Interrupt Enable Register 0x010 32 read-only SUSPE SUSP Interrupt Enable 0 1 read-only MSOFE MSOF Interrupt Enable 1 1 read-only SOFE SOF Interrupt Enable 2 1 read-only EORSTE EORST Interrupt Enable 3 1 read-only WAKEUPE WAKEUP Interrupt Enable 4 1 read-only EORSME EORSM Interrupt Enable 5 1 read-only UPRSME UPRSM Interrupt Enable 6 1 read-only EP0INTE EP0INT Interrupt Enable 12 1 read-only EP1INTE EP1INT Interrupt Enable 13 1 read-only EP2INTE EP2INT Interrupt Enable 14 1 read-only EP3INTE EP3INT Interrupt Enable 15 1 read-only EP4INTE EP4INT Interrupt Enable 16 1 read-only EP5INTE EP5INT Interrupt Enable 17 1 read-only EP6INTE EP6INT Interrupt Enable 18 1 read-only EP7INTE EP7INT Interrupt Enable 19 1 read-only UDINTECLR Device Global Interrupt Enable Clear Register 0x014 32 write-only SUSPEC SUSP Interrupt Enable Clear 0 1 write-only MSOFEC MSOF Interrupt Enable Clear 1 1 write-only SOFEC SOF Interrupt Enable Clear 2 1 write-only EORSTEC EORST Interrupt Enable Clear 3 1 write-only WAKEUPEC WAKEUP Interrupt Enable Clear 4 1 write-only EORSMEC EORSM Interrupt Enable Clear 5 1 write-only UPRSMEC UPRSM Interrupt Enable Clear 6 1 write-only EP0INTEC EP0INT Interrupt Enable Clear 12 1 write-only EP1INTEC EP1INT Interrupt Enable Clear 13 1 write-only EP2INTEC EP2INT Interrupt Enable Clear 14 1 write-only EP3INTEC EP3INT Interrupt Enable Clear 15 1 write-only EP4INTEC EP4INT Interrupt Enable Clear 16 1 write-only EP5INTEC EP5INT Interrupt Enable Clear 17 1 write-only EP6INTEC EP6INT Interrupt Enable Clear 18 1 write-only EP7INTEC EP7INT Interrupt Enable Clear 19 1 write-only UDINTESET Device Global Interrupt Enable Set Register 0x018 32 write-only SUSPES SUSP Interrupt Enable Set 0 1 write-only MSOFES MSOF Interrupt Enable Set 1 1 write-only SOFES SOF Interrupt Enable Set 2 1 write-only EORSTES EORST Interrupt Enable Set 3 1 write-only WAKEUPES WAKEUP Interrupt Enable Set 4 1 write-only EORSMES EORSM Interrupt Enable Set 5 1 write-only UPRSMES UPRSM Interrupt Enable Set 6 1 write-only EP0INTES EP0INT Interrupt Enable Set 12 1 write-only EP1INTES EP1INT Interrupt Enable Set 13 1 write-only EP2INTES EP2INT Interrupt Enable Set 14 1 write-only EP3INTES EP3INT Interrupt Enable Set 15 1 write-only EP4INTES EP4INT Interrupt Enable Set 16 1 write-only EP5INTES EP5INT Interrupt Enable Set 17 1 write-only EP6INTES EP6INT Interrupt Enable Set 18 1 write-only EP7INTES EP7INT Interrupt Enable Set 19 1 write-only UERST Endpoint Enable/Reset Register 0x01C 32 EPEN0 Endpoint0 Enable 0 1 EPEN1 Endpoint1 Enable 1 1 EPEN2 Endpoint2 Enable 2 1 EPEN3 Endpoint3 Enable 3 1 EPEN4 Endpoint4 Enable 4 1 EPEN5 Endpoint5 Enable 5 1 EPEN6 Endpoint6 Enable 6 1 EPEN7 Endpoint7 Enable 7 1 UDFNUM Device Frame Number Register 0x020 32 read-only MFNUM Micro Frame Number 0 3 read-only FNUM Frame Number 3 11 read-only FNCERR Frame Number CRC Error 15 1 read-only UECFG0 Endpoint Configuration Register 0x100 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG1 Endpoint Configuration Register 0x104 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG2 Endpoint Configuration Register 0x108 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG3 Endpoint Configuration Register 0x10C 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG4 Endpoint Configuration Register 0x110 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG5 Endpoint Configuration Register 0x114 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG6 Endpoint Configuration Register 0x118 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UECFG7 Endpoint Configuration Register 0x11C 32 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE 0x0 DOUBLE 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT 0x0 IN 0x1 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 REPNB Redirected Endpoint Number 16 4 UESTA0 Endpoint Status Register 0x130 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA1 Endpoint Status Register 0x134 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA2 Endpoint Status Register 0x138 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA3 Endpoint Status Register 0x13C 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA4 Endpoint Status Register 0x140 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA5 Endpoint Status Register 0x144 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA6 Endpoint Status Register 0x148 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA7 Endpoint Status Register 0x14C 32 read-only 0x00000100 TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only STALLEDI STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only CURRBK Current Bank 14 2 read-only CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT 0x0 IN 0x1 UESTA0CLR Endpoint Status Clear Register 0x160 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA1CLR Endpoint Status Clear Register 0x164 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA2CLR Endpoint Status Clear Register 0x168 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA3CLR Endpoint Status Clear Register 0x16C 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA4CLR Endpoint Status Clear Register 0x170 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA5CLR Endpoint Status Clear Register 0x174 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA6CLR Endpoint Status Clear Register 0x178 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA7CLR Endpoint Status Clear Register 0x17C 32 write-only TXINIC TXINI Clear 0 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only NAKINIC NAKINI Clear 4 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only UESTA0SET Endpoint Status Set Register 0x190 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA1SET Endpoint Status Set Register 0x194 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA2SET Endpoint Status Set Register 0x198 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA3SET Endpoint Status Set Register 0x19C 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA4SET Endpoint Status Set Register 0x1A0 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA5SET Endpoint Status Set Register 0x1A4 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA6SET Endpoint Status Set Register 0x1A8 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UESTA7SET Endpoint Status Set Register 0x1AC 32 write-only TXINIS TXINI Set 0 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NAKINIS NAKINI Set 4 1 write-only STALLEDIS STALLEDI Set 6 1 write-only RAMACERIS RAMACERI Set 11 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only UECON0 Endpoint Control Register 0x1C0 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET token disable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON1 Endpoint Control Register 0x1C4 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON2 Endpoint Control Register 0x1C8 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON3 Endpoint Control Register 0x1CC 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON4 Endpoint Control Register 0x1D0 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON5 Endpoint Control Register 0x1D4 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON6 Endpoint Control Register 0x1D8 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON7 Endpoint Control Register 0x1DC 32 read-only TXINE TXIN Interrupt Enable 0 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only NREPLY No Reply 8 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only NYETDIS NYET Token Enable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only UECON0SET Endpoint Control Set Register 0x1F0 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON1SET Endpoint Control Set Register 0x1F4 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON2SET Endpoint Control Set Register 0x1F8 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON3SET Endpoint Control Set Register 0x1FC 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON4SET Endpoint Control Set Register 0x200 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON5SET Endpoint Control Set Register 0x204 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON6SET Endpoint Control Set Register 0x208 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON7SET Endpoint Control Set Register 0x20C 32 write-only TXINES TXINE Set 0 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NAKINES NAKINE Set 4 1 write-only STALLEDES STALLEDE Set 6 1 write-only NREPLYS NREPLY Set 8 1 write-only RAMACERES RAMACERE Set 11 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only KILLBKS KILLBK Set 13 1 write-only NYETDISS NYETDIS Set 17 1 write-only RSTDTS RSTDT Set 18 1 write-only STALLRQS STALLRQ Set 19 1 write-only BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only UECON0CLR Endpoint Control Clear Register 0x220 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXSTPE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC STALLEDE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLRQ Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON1CLR TXINE Clear 0x224 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON2CLR TXINE Clear 0x228 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON3CLR TXINE Clear 0x22C 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON4CLR TXINE Clear 0x230 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON5CLR TXINE Clear 0x234 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON6CLR TXINE Clear 0x238 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UECON7CLR TXINE Clear 0x23C 32 write-only TXINEC TXINE Clear 0 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NAKINEC NAKINE Clear 4 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only NREPLYC NREPLY Clear 8 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NYETDISC NYETDIS Clear 17 1 write-only STALLRQC STALLEDE Clear 19 1 write-only BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only UHCON Host General Control Register 0x400 32 SOFE SOF Enable 8 1 RESET Send USB Reset 9 1 RESUME Send USB Resume 10 1 SPDCONF Speed Configuration 12 2 TSTJ Test J 16 1 TSTK Test K 17 1 UHINT Host Global Interrupt Register 0x404 32 read-only DCONNI Device Connection Interrupt 0 1 read-only DDISCI Device Disconnection Interrupt 1 1 read-only RSTI USB Reset Sent Interrupt 2 1 read-only RSMEDI Downstream Resume Sent Interrupt 3 1 read-only RXRSMI Upstream Resume Received Interrupt 4 1 read-only HSOFI Host SOF Interrupt 5 1 read-only HWUPI Host Wake-Up Interrupt 6 1 read-only P0INT Pipe 0 Interrupt 8 1 read-only P1INT Pipe 1 Interrupt 9 1 read-only P2INT Pipe 2 Interrupt 10 1 read-only P3INT Pipe 3 Interrupt 11 1 read-only P4INT Pipe 4 Interrupt 12 1 read-only P5INT Pipe 5 Interrupt 13 1 read-only P6INT Pipe 6 Interrupt 14 1 read-only UHINTCLR Host Global Interrrupt Clear Register 0x408 32 write-only DCONNIC DCONNI Clear 0 1 write-only DDISCIC DDISCI Clear 1 1 write-only RSTIC RSTI Clear 2 1 write-only RSMEDIC RSMEDI Clear 3 1 write-only RXRSMIC RXRSMI Clear 4 1 write-only HSOFIC HSOFI Clear 5 1 write-only HWUPIC HWUPI Clear 6 1 write-only UHINTSET Host Global Interrupt Set Register 0x40C 32 write-only DCONNIS DCONNI Set 0 1 write-only DDISCIS DDISCI Set 1 1 write-only RSTIS RSTI Set 2 1 write-only RSMEDIS RSMEDI Set 3 1 write-only RXRSMIS RXRSMI Set 4 1 write-only HSOFIS HSOFI Set 5 1 write-only HWUPIS HWUPI Set 6 1 write-only UHINTE Host Global Interrupt Enable Register 0x410 32 read-only DCONNIE DCONNI Enable 0 1 read-only DDISCIE DDISCI Enable 1 1 read-only RSTIE RSTI Enable 2 1 read-only RSMEDIE RSMEDI Enable 3 1 read-only RXRSMIE RXRSMI Enable 4 1 read-only HSOFIE HSOFI Enable 5 1 read-only HWUPIE HWUPI Enable 6 1 read-only P0INTE P0INT Enable 8 1 read-only P1INTE P1INT Enable 9 1 read-only P2INTE P2INT Enable 10 1 read-only P3INTE P3INT Enable 11 1 read-only P4INTE P4INT Enable 12 1 read-only P5INTE P5INT Enable 13 1 read-only P6INTE P6INT Enable 14 1 read-only P7INTE P7INT Enable 15 1 read-only UHINTECLR Host Global Interrupt Enable Clear Register 0x414 32 write-only DCONNIEC DCONNIE Clear 0 1 write-only DDISCIEC DDISCIE Clear 1 1 write-only RSTIEC RSTIE Clear 2 1 write-only RSMEDIEC RSMEDIE Clear 3 1 write-only RXRSMIEC RXRSMIE Clear 4 1 write-only HSOFIEC HSOFIE Clear 5 1 write-only HWUPIEC HWUPIE Clear 6 1 write-only P0INTEC P0INTE Clear 8 1 write-only P1INTEC P1INTE Clear 9 1 write-only P2INTEC P2INTE Clear 10 1 write-only P3INTEC P3INTE Clear 11 1 write-only P4INTEC P4INTE Clear 12 1 write-only P5INTEC P5INTE Clear 13 1 write-only P6INTEC P6INTE Clear 14 1 write-only P7INTEC P7INTE Clear 15 1 write-only UHINTESET Host Global Interrupt Enable Set Register 0x418 32 write-only DCONNIES DCONNIE Set 0 1 write-only DDISCIES DDISCIE Set 1 1 write-only RSTIES RSTIE Set 2 1 write-only RSMEDIES RSMEDIE Set 3 1 write-only RXRSMIES RXRSMIE Set 4 1 write-only HSOFIES HSOFIE Set 5 1 write-only HWUPIES HWUPIE Set 6 1 write-only P0INTES P0INTE Set 8 1 write-only P1INTES P1INTE Set 9 1 write-only P2INTES P2INTE Set 10 1 write-only P3INTES P3INTE Set 11 1 write-only P4INTES P4INTE Set 12 1 write-only P5INTES P5INTE Set 13 1 write-only P6INTES P6INTE Set 14 1 write-only P7INTES P7INTE Set 15 1 write-only UPRST Pipe Reset Register 0x41C 32 PEN0 Pipe0 Enable 0 1 PEN1 Pipe1 Enable 1 1 PEN2 Pipe2 Enable 2 1 PEN3 Pipe3 Enable 3 1 PEN4 Pipe4 Enable 4 1 PEN5 Pipe5 Enable 5 1 PEN6 Pipe6 Enable 6 1 PEN7 Pipe7 Enable 7 1 UHFNUM Host Frame Number Register 0x420 32 MFNUM Micro Frame Number 0 3 read-only FNUM Frame Number 3 11 FLENHIGH Frame Length 16 8 read-only UHSOFC Host Start of Frame Control Register 0x424 32 FLENC Frame Length Control 0 14 FLENCE Frame Length Control Enable 16 1 UPCFG0 Pipe Configuration Register 0x500 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG1 Pipe Configuration Register 0x504 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG2 Pipe Configuration Register 0x508 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG3 Pipe Configuration Register 0x50C 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG4 Pipe Configuration Register 0x510 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG5 Pipe Configuration Register 0x514 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG6 Pipe Configuration Register 0x518 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPCFG7 Pipe Configuration Register 0x51C 32 PBK Pipe Banks 2 1 PBKSelect SINGLE 0x0 DOUBLE 0x1 PSIZE Pipe Size 4 3 PSIZESelect 8 0x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP 0x0 IN 0x1 OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 PINGEN Ping Enable 20 1 BINTERVAL binterval parameter 24 8 UPSTA0 Pipe Status Register 0x530 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA1 Pipe Status Register 0x534 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA2 Pipe Status Register 0x538 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA3 Pipe Status Register 0x53C 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA4 Pipe Status Register 0x540 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA5 Pipe Status Register 0x544 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA6 Pipe Status Register 0x548 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA7 Pipe Status Register 0x54C 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only ERRORFI Errorflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only CURRBK Current Bank 14 2 read-only UPSTA0CLR Pipe Status Clear Register 0x560 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA1CLR Pipe Status Clear Register 0x564 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA2CLR Pipe Status Clear Register 0x568 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA3CLR Pipe Status Clear Register 0x56C 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA4CLR Pipe Status Clear Register 0x570 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA5CLR Pipe Status Clear Register 0x574 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA6CLR Pipe Status Clear Register 0x578 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA7CLR Pipe Status Clear Register 0x57C 32 write-only RXINIC RXINI Clear 0 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only PERRIC PERRI Clear 3 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only ERRORFIC ERRORFI Clear 5 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only UPSTA0SET Pipe Status Set Register 0x590 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA1SET Pipe Status Set Register 0x594 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA2SET Pipe Status Set Register 0x598 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA3SET Pipe Status Set Register 0x59C 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA4SET Pipe Status Set Register 0x5A0 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA5SET Pipe Status Set Register 0x5A4 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA6SET Pipe Status Set Register 0x5A8 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPSTA7SET Pipe Status Set Register 0x5AC 32 write-only RXINIS RXINI Set 0 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only PERRIS PERRI Set 3 1 write-only NAKEDIS NAKEDI Set 4 1 write-only ERRORFIS ERRORFI Set 5 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only RAMACERIS RAMACERI Set 10 1 write-only UPCON0 Pipe Control Register 0x5C0 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON1 Pipe Control Register 0x5C4 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON2 Pipe Control Register 0x5C8 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON3 Pipe Control Register 0x5CC 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON4 Pipe Control Register 0x5D0 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON5 Pipe Control Register 0x5D4 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON6 Pipe Control Register 0x5D8 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON7 Pipe Control Register 0x5DC 32 read-only RXINE RXIN Interrupt Enable 0 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only PERRE PERR Interrupt Enable 3 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only ERRORFIE ERRORFI Interrupt Enable 5 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PFREEZE Pipe Freeze 17 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only INITBK Bank Initialization 19 1 read-only UPCON0SET Pipe Control Set Register 0x5F0 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON1SET Pipe Control Set Register 0x5F4 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON2SET Pipe Control Set Register 0x5F8 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON3SET Pipe Control Set Register 0x5FC 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON4SET Pipe Control Set Register 0x600 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON5SET Pipe Control Set Register 0x604 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON6SET Pipe Control Set Register 0x608 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON7SET Pipe Control Set Register 0x60C 32 write-only RXINES RXINE Set 0 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only PERRES PERRE Set 3 1 write-only NAKEDES NAKEDE Set 4 1 write-only ERRORFIES ERRORFIE Set 5 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only RAMACERES RAMACERE Set 10 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only FIFOCONS FIFOCON Set 14 1 write-only PFREEZES PFREEZE Set 17 1 write-only INITDTGLS INITDTGL Set 18 1 write-only INITBKS INITBK Set 19 1 write-only UPCON0CLR Pipe Control Clear Register 0x620 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON1CLR Pipe Control Clear Register 0x624 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON2CLR Pipe Control Clear Register 0x628 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON3CLR Pipe Control Clear Register 0x62C 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON4CLR Pipe Control Clear Register 0x630 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON5CLR Pipe Control Clear Register 0x634 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON6CLR Pipe Control Clear Register 0x638 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPCON7CLR Pipe Control Clear Register 0x63C 32 write-only RXINEC RXINE Clear 0 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only PERREC PERRE Clear 3 1 write-only NAKEDEC NAKEDE Clear 4 1 write-only ERRORFIEC ERRORFIE Clear 5 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only INITBKC INITBK Clear 19 1 write-only UPINRQ0 Pipe In Request 0x650 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ1 Pipe In Request 0x654 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ2 Pipe In Request 0x658 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ3 Pipe In Request 0x65C 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ4 Pipe In Request 0x660 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ5 Pipe In Request 0x664 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ6 Pipe In Request 0x668 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 UPINRQ7 Pipe In Request 0x66C 32 0x00000001 INRQ IN Request Number before Freeze 0 8 INMODE IN Request Mode 8 1 USBCON General Control Register 0x800 32 0x01004000 FRZCLK Freeze USB Clock 14 1 USBE USBC Enable 15 1 UIMOD USBC Mode 24 1 USBSTA General Status Register 0x804 32 read-only 0x00010000 VBUSRQ VBus Request 9 1 read-only SPEED Speed Status 12 2 read-only SPEEDSelect FULL 0x0 HIGH 0x1 LOW 0x2 CLKUSABLE USB Clock Usable 14 1 read-only SUSPEND Suspend module state 16 1 read-only USBSTACLR General Status Clear Register 0x808 32 write-only RAMACERIC RAMACERI Clear 8 1 write-only VBUSRQC VBUSRQ Clear 9 1 write-only USBSTASET General Status Set Register 0x80C 32 write-only RAMACERIS RAMACERI Set 8 1 write-only VBUSRQS VBUSRQ Set 9 1 write-only UVERS IP Version Register 0x818 32 read-only 0x00000310 VERSION Version Number 0 12 read-only VARIANT Variant Number 16 3 read-only UFEATURES IP Features Register 0x81C 32 read-only 0x00000007 EPTNBRMAX Maximum Number of Pipes/Endpints 0 4 read-only UTMIMODE UTMI Mode 8 1 read-only UADDRSIZE IP PB address size Register 0x820 32 read-only 0x00001000 UADDRSIZE IP PB Address Size 0 32 UNAME1 IP Name Part One: HUSB 0x824 32 read-only 0x48555342 UNAME1 IP Name Part One 0 32 UNAME2 IP Name Part Two: HOST 0x828 32 read-only 0x484F5354 UNAME2 IP Name Part Two 0 32 USBFSM USB internal finite state machine 0x82C 32 read-only 0x00000009 DRDSTATE DualRoleDevice state 0 4 read-only DRDSTATESelect A_IDLE 0x0 A_WAIT_VRISE 0x1 A_WAIT_BCON 0x2 A_HOST 0x3 A_SUSPEND 0x4 A_PERIPHERAL 0x5 A_WAIT_VFALL 0x6 A_VBUS_ERR 0x7 A_WAIT_DISCHARGE 0x8 B_IDLE 0x9 B_PERIPHERAL 0xa B_WAIT_BEGIN_HNP 0xb B_WAIT_DISCHARGE 0xc B_WAIT_ACON 0xd B_HOST 0xe B_SRP_INIT 0xf UDESC Endpoint descriptor table 0x830 32 UDESCA USB Descriptor Address 0 32 WDT 5.0.1 Watchdog Timer WDT WDT_ 0x400F0C00 0 0x400 registers WDT_INTREQ 44 CTRL Control Register 0x000 32 0x00010080 EN WDT Enable 0 1 ENSelect 0 WDT is disabled. 0x0 1 WDT is enabled 0x1 DAR WDT Disable After Reset 1 1 MODE WDT Mode 2 1 SFV WDT Store Final Value 3 1 IM WDT Interruput Mode 4 1 FCD WDT Fuse Calibration Done 7 1 PSEL Timeout Prescale Select 8 5 CSSEL1 Clock Source Selection1 14 1 CEN Clock Enable 16 1 CSSEL Clock Source Selection0 17 1 TBAN TBAN Prescale Select 18 5 KEY Key 24 8 CLR Clear Register 0x004 32 write-only WDTCLR Clear WDT counter 0 1 write-only KEY Key 24 8 write-only SR Status Register 0x008 32 read-only 0x00000003 WINDOW WDT in window 0 1 read-only CLEARED WDT cleared 1 1 read-only IER Interrupt Enable Register 0x00C 32 write-only WINT Watchdog Interrupt 2 1 IDR Interrupt Disable Register 0x010 32 write-only WINT Watchdog Interrupt 2 1 IMR Interrupt Mask Register 0x014 32 read-only WINT Watchdog Interrupt 2 1 ISR Interrupt Status Register 0x018 32 read-only WINT Watchdog Interrupt 2 1 ICR Interrupt Clear Register 0x01C 32 write-only WINT Watchdog Interrupt 2 1 VERSION Version Register 0x3FC 32 read-only 0x00000501 VERSION Version number 0 12 VARIANT Variant number 16 4