Microchip Technology
MCHP
ATSAME70N19B
SAME70
0
Microchip ATSAME70N19B Microcontroller
CM7
r1p1
little
true
true
true
true
true
true
true
3
false
74
8
32
32
read-write
0x00000000
0xFFFFFFFF
ACC
6490J
Analog Comparator Controller
0x40044000
0
0xEC
registers
ACC
33
CR
Control Register
0x00
32
write-only
SWRST
Software Reset
0
1
MR
Mode Register
0x04
32
SELMINUS
Selection for Minus Comparator Input
0
3
SELMINUSSelect
TS
Select TS
0x0
VREFP
Select VREFP
0x1
DAC0
Select DAC0
0x2
DAC1
Select DAC1
0x3
AFE0_AD0
Select AFE0_AD0
0x4
AFE0_AD1
Select AFE0_AD1
0x5
AFE0_AD2
Select AFE0_AD2
0x6
AFE0_AD3
Select AFE0_AD3
0x7
SELPLUS
Selection For Plus Comparator Input
4
3
SELPLUSSelect
AFE0_AD0
Select AFE0_AD0
0x0
AFE0_AD1
Select AFE0_AD1
0x1
AFE0_AD2
Select AFE0_AD2
0x2
AFE0_AD3
Select AFE0_AD3
0x3
AFE0_AD4
Select AFE0_AD4
0x4
AFE0_AD5
Select AFE0_AD5
0x5
AFE1_AD0
Select AFE1_AD0
0x6
AFE1_AD1
Select AFE1_AD1
0x7
ACEN
Analog Comparator Enable
8
1
ACENSelect
DIS
Analog comparator disabled.
0
EN
Analog comparator enabled.
1
EDGETYP
Edge Type
9
2
EDGETYPSelect
RISING
Only rising edge of comparator output
0x0
FALLING
Falling edge of comparator output
0x1
ANY
Any edge of comparator output
0x2
INV
Invert Comparator Output
12
1
INVSelect
DIS
Analog comparator output is directly processed.
0
EN
Analog comparator output is inverted prior to being processed.
1
SELFS
Selection Of Fault Source
13
1
SELFSSelect
CE
The CE flag is used to drive the FAULT output.
0
OUTPUT
The output of the analog comparator flag is used to drive the FAULT output.
1
FE
Fault Enable
14
1
FESelect
DIS
The FAULT output is tied to 0.
0
EN
The FAULT output is driven by the signal defined by SELFS.
1
IER
Interrupt Enable Register
0x24
32
write-only
CE
Comparison Edge
0
1
IDR
Interrupt Disable Register
0x28
32
write-only
CE
Comparison Edge
0
1
IMR
Interrupt Mask Register
0x2C
32
read-only
CE
Comparison Edge
0
1
ISR
Interrupt Status Register
0x30
32
read-only
CE
Comparison Edge (cleared on read)
0
1
SCO
Synchronized Comparator Output
1
1
MASK
Flag Mask
31
1
ACR
Analog Control Register
0x94
32
ISEL
Current Selection
0
1
ISELSelect
LOPW
Low-power option.
0
HISP
High-speed option.
1
HYST
Hysteresis Selection
1
2
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x414343
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
AES
6149W
Advanced Encryption Standard
0x4006C000
0
0xAC
registers
AES
56
CR
Control Register
0x00
32
write-only
START
Start Processing
0
1
SWRST
Software Reset
8
1
LOADSEED
Random Number Generator Seed Loading
16
1
MR
Mode Register
0x04
32
CIPHER
Processing Mode
0
1
GTAGEN
GCM Automatic Tag Generation Enable
1
1
DUALBUFF
Dual Input Buffer
3
1
DUALBUFFSelect
INACTIVE
AES_IDATARx cannot be written during processing of previous block.
0
ACTIVE
AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files.
1
PROCDLY
Processing Delay
4
4
SMOD
Start Mode
8
2
SMODSelect
MANUAL_START
Manual Mode
0x0
AUTO_START
Auto Mode
0x1
IDATAR0_START
AES_IDATAR0 access only Auto Mode (DMA)
0x2
KEYSIZE
Key Size
10
2
KEYSIZESelect
AES128
AES Key Size is 128 bits
0x0
AES192
AES Key Size is 192 bits
0x1
AES256
AES Key Size is 256 bits
0x2
OPMOD
Operating Mode
12
3
OPMODSelect
ECB
ECB: Electronic Code Book mode
0x0
CBC
CBC: Cipher Block Chaining mode
0x1
OFB
OFB: Output Feedback mode
0x2
CFB
CFB: Cipher Feedback mode
0x3
CTR
CTR: Counter mode (16-bit internal counter)
0x4
GCM
GCM: Galois/Counter mode
0x5
LOD
Last Output Data Mode
15
1
CFBS
Cipher Feedback Data Size
16
3
CFBSSelect
SIZE_128BIT
128-bit
0x0
SIZE_64BIT
64-bit
0x1
SIZE_32BIT
32-bit
0x2
SIZE_16BIT
16-bit
0x3
SIZE_8BIT
8-bit
0x4
CKEY
Countermeasure Key
20
4
CKEYSelect
PASSWD
This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0.
0xE
IER
Interrupt Enable Register
0x10
32
write-only
DATRDY
Data Ready Interrupt Enable
0
1
URAD
Unspecified Register Access Detection Interrupt Enable
8
1
TAGRDY
GCM Tag Ready Interrupt Enable
16
1
IDR
Interrupt Disable Register
0x14
32
write-only
DATRDY
Data Ready Interrupt Disable
0
1
URAD
Unspecified Register Access Detection Interrupt Disable
8
1
TAGRDY
GCM Tag Ready Interrupt Disable
16
1
IMR
Interrupt Mask Register
0x18
32
read-only
DATRDY
Data Ready Interrupt Mask
0
1
URAD
Unspecified Register Access Detection Interrupt Mask
8
1
TAGRDY
GCM Tag Ready Interrupt Mask
16
1
ISR
Interrupt Status Register
0x1C
32
read-only
DATRDY
Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)
0
1
URAD
Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)
8
1
URAT
Unspecified Register Access (cleared by writing SWRST in AES_CR)
12
4
URATSelect
IDR_WR_PROCESSING
Input Data Register written during the data processing when SMOD = 0x2 mode.
0x0
ODR_RD_PROCESSING
Output Data Register read during the data processing.
0x1
MR_WR_PROCESSING
Mode Register written during the data processing.
0x2
ODR_RD_SUBKGEN
Output Data Register read during the sub-keys generation.
0x3
MR_WR_SUBKGEN
Mode Register written during the sub-keys generation.
0x4
WOR_RD_ACCESS
Write-only register read access.
0x5
TAGRDY
GCM Tag Ready
16
1
8
4
KEYWR[%s]
Key Word Register
0x20
32
write-only
KEYW
Key Word
0
32
4
4
IDATAR[%s]
Input Data Register
0x40
32
write-only
IDATA
Input Data Word
0
32
4
4
ODATAR[%s]
Output Data Register
0x50
32
read-only
ODATA
Output Data
0
32
4
4
IVR[%s]
Initialization Vector Register
0x60
32
write-only
IV
Initialization Vector
0
32
AADLENR
Additional Authenticated Data Length Register
0x70
32
AADLEN
Additional Authenticated Data Length
0
32
CLENR
Plaintext/Ciphertext Length Register
0x74
32
CLEN
Plaintext/Ciphertext Length
0
32
4
4
GHASHR[%s]
GCM Intermediate Hash Word Register
0x78
32
GHASH
Intermediate GCM Hash Word x
0
32
4
4
TAGR[%s]
GCM Authentication Tag Word Register
0x88
32
read-only
TAG
GCM Authentication Tag x
0
32
CTRR
GCM Encryption Counter Value Register
0x98
32
read-only
CTR
GCM Encryption Counter
0
32
4
4
GCMHR[%s]
GCM H Word Register
0x9C
32
H
GCM H Word x
0
32
AFEC0
11147S
Analog Front-End Controller
AFEC
AFEC_
0x4003C000
0
0xEC
registers
AFEC0
29
CR
AFEC Control Register
0x00
32
write-only
SWRST
Software Reset
0
1
START
Start Conversion
1
1
MR
AFEC Mode Register
0x04
32
TRGEN
Trigger Enable
0
1
TRGENSelect
DIS
Hardware triggers are disabled. Starting a conversion is only possible by software.
0
EN
Hardware trigger selected by TRGSEL field is enabled.
1
TRGSEL
Trigger Selection
1
3
TRGSELSelect
AFEC_TRIG0
AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1
0x0
AFEC_TRIG1
TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1
0x1
AFEC_TRIG2
TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1
0x2
AFEC_TRIG3
TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1
0x3
AFEC_TRIG4
PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1
0x4
AFEC_TRIG5
PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1
0x5
AFEC_TRIG6
Analog Comparator
0x6
SLEEP
Sleep Mode
5
1
SLEEPSelect
NORMAL
Normal mode: The AFE and reference voltage circuitry are kept ON between conversions.
0
SLEEP
Sleep mode: The AFE and reference voltage circuitry are OFF between conversions.
1
FWUP
Fast Wake-up
6
1
FWUPSelect
OFF
Normal Sleep mode: The sleep mode is defined by the SLEEP bit.
0
ON
Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF.
1
FREERUN
Free Run Mode
7
1
FREERUNSelect
OFF
Normal mode
0
ON
Free Run mode: Never wait for any trigger.
1
PRESCAL
Prescaler Rate Selection
8
8
STARTUP
Start-up Time
16
4
STARTUPSelect
SUT0
0 periods of AFE clock
0x0
SUT8
8 periods of AFE clock
0x1
SUT16
16 periods of AFE clock
0x2
SUT24
24 periods of AFE clock
0x3
SUT64
64 periods of AFE clock
0x4
SUT80
80 periods of AFE clock
0x5
SUT96
96 periods of AFE clock
0x6
SUT112
112 periods of AFE clock
0x7
SUT512
512 periods of AFE clock
0x8
SUT576
576 periods of AFE clock
0x9
SUT640
640 periods of AFE clock
0xA
SUT704
704 periods of AFE clock
0xB
SUT768
768 periods of AFE clock
0xC
SUT832
832 periods of AFE clock
0xD
SUT896
896 periods of AFE clock
0xE
SUT960
960 periods of AFE clock
0xF
ONE
One
23
1
TRACKTIM
Tracking Time
24
4
TRANSFER
Transfer Period
28
2
USEQ
User Sequence Enable
31
1
USEQSelect
NUM_ORDER
Normal mode: The controller converts channels in a simple numeric order.
0
REG_ORDER
User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R.
1
EMR
AFEC Extended Mode Register
0x08
32
CMPMODE
Comparison Mode
0
2
CMPMODESelect
LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x0
HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x1
IN
Generates an event when the converted data is in the comparison window.
0x2
OUT
Generates an event when the converted data is out of the comparison window.
0x3
CMPSEL
Comparison Selected Channel
3
5
CMPALL
Compare All Channels
9
1
CMPFILTER
Compare Event Filtering
12
2
RES
Resolution
16
3
RESSelect
NO_AVERAGE
12-bit resolution, AFE sample rate is maximum (no averaging).
0x0
OSR4
13-bit resolution, AFE sample rate divided by 4 (averaging).
0x2
OSR16
14-bit resolution, AFE sample rate divided by 16 (averaging).
0x3
OSR64
15-bit resolution, AFE sample rate divided by 64 (averaging).
0x4
OSR256
16-bit resolution, AFE sample rate divided by 256 (averaging).
0x5
TAG
TAG of the AFEC_LDCR
24
1
STM
Single Trigger Mode
25
1
SIGNMODE
Sign Mode
28
2
SIGNMODESelect
SE_UNSG_DF_SIGN
Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.
0x0
SE_SIGN_DF_UNSG
Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.
0x1
ALL_UNSIGNED
All channels: Unsigned conversions.
0x2
ALL_SIGNED
All channels: Signed conversions.
0x3
SEQ1R
AFEC Channel Sequence 1 Register
0x0C
32
USCH0
User Sequence Number 0
0
4
USCH1
User Sequence Number 1
4
4
USCH2
User Sequence Number 2
8
4
USCH3
User Sequence Number 3
12
4
USCH4
User Sequence Number 4
16
4
USCH5
User Sequence Number 5
20
4
USCH6
User Sequence Number 6
24
4
USCH7
User Sequence Number 7
28
4
SEQ2R
AFEC Channel Sequence 2 Register
0x10
32
USCH8
User Sequence Number 8
0
4
USCH9
User Sequence Number 9
4
4
USCH10
User Sequence Number 10
8
4
USCH11
User Sequence Number 11
12
4
CHER
AFEC Channel Enable Register
0x14
32
write-only
CH0
Channel 0 Enable
0
1
CH1
Channel 1 Enable
1
1
CH2
Channel 2 Enable
2
1
CH3
Channel 3 Enable
3
1
CH4
Channel 4 Enable
4
1
CH5
Channel 5 Enable
5
1
CH6
Channel 6 Enable
6
1
CH7
Channel 7 Enable
7
1
CH8
Channel 8 Enable
8
1
CH9
Channel 9 Enable
9
1
CH10
Channel 10 Enable
10
1
CH11
Channel 11 Enable
11
1
CHDR
AFEC Channel Disable Register
0x18
32
write-only
CH0
Channel 0 Disable
0
1
CH1
Channel 1 Disable
1
1
CH2
Channel 2 Disable
2
1
CH3
Channel 3 Disable
3
1
CH4
Channel 4 Disable
4
1
CH5
Channel 5 Disable
5
1
CH6
Channel 6 Disable
6
1
CH7
Channel 7 Disable
7
1
CH8
Channel 8 Disable
8
1
CH9
Channel 9 Disable
9
1
CH10
Channel 10 Disable
10
1
CH11
Channel 11 Disable
11
1
CHSR
AFEC Channel Status Register
0x1C
32
read-only
CH0
Channel 0 Status
0
1
CH1
Channel 1 Status
1
1
CH2
Channel 2 Status
2
1
CH3
Channel 3 Status
3
1
CH4
Channel 4 Status
4
1
CH5
Channel 5 Status
5
1
CH6
Channel 6 Status
6
1
CH7
Channel 7 Status
7
1
CH8
Channel 8 Status
8
1
CH9
Channel 9 Status
9
1
CH10
Channel 10 Status
10
1
CH11
Channel 11 Status
11
1
LCDR
AFEC Last Converted Data Register
0x20
32
read-only
LDATA
Last Data Converted
0
16
CHNB
Channel Number
24
4
IER
AFEC Interrupt Enable Register
0x24
32
write-only
EOC0
End of Conversion Interrupt Enable 0
0
1
EOC1
End of Conversion Interrupt Enable 1
1
1
EOC2
End of Conversion Interrupt Enable 2
2
1
EOC3
End of Conversion Interrupt Enable 3
3
1
EOC4
End of Conversion Interrupt Enable 4
4
1
EOC5
End of Conversion Interrupt Enable 5
5
1
EOC6
End of Conversion Interrupt Enable 6
6
1
EOC7
End of Conversion Interrupt Enable 7
7
1
EOC8
End of Conversion Interrupt Enable 8
8
1
EOC9
End of Conversion Interrupt Enable 9
9
1
EOC10
End of Conversion Interrupt Enable 10
10
1
EOC11
End of Conversion Interrupt Enable 11
11
1
DRDY
Data Ready Interrupt Enable
24
1
GOVRE
General Overrun Error Interrupt Enable
25
1
COMPE
Comparison Event Interrupt Enable
26
1
TEMPCHG
Temperature Change Interrupt Enable
30
1
IDR
AFEC Interrupt Disable Register
0x28
32
write-only
EOC0
End of Conversion Interrupt Disable 0
0
1
EOC1
End of Conversion Interrupt Disable 1
1
1
EOC2
End of Conversion Interrupt Disable 2
2
1
EOC3
End of Conversion Interrupt Disable 3
3
1
EOC4
End of Conversion Interrupt Disable 4
4
1
EOC5
End of Conversion Interrupt Disable 5
5
1
EOC6
End of Conversion Interrupt Disable 6
6
1
EOC7
End of Conversion Interrupt Disable 7
7
1
EOC8
End of Conversion Interrupt Disable 8
8
1
EOC9
End of Conversion Interrupt Disable 9
9
1
EOC10
End of Conversion Interrupt Disable 10
10
1
EOC11
End of Conversion Interrupt Disable 11
11
1
DRDY
Data Ready Interrupt Disable
24
1
GOVRE
General Overrun Error Interrupt Disable
25
1
COMPE
Comparison Event Interrupt Disable
26
1
TEMPCHG
Temperature Change Interrupt Disable
30
1
IMR
AFEC Interrupt Mask Register
0x2C
32
read-only
EOC0
End of Conversion Interrupt Mask 0
0
1
EOC1
End of Conversion Interrupt Mask 1
1
1
EOC2
End of Conversion Interrupt Mask 2
2
1
EOC3
End of Conversion Interrupt Mask 3
3
1
EOC4
End of Conversion Interrupt Mask 4
4
1
EOC5
End of Conversion Interrupt Mask 5
5
1
EOC6
End of Conversion Interrupt Mask 6
6
1
EOC7
End of Conversion Interrupt Mask 7
7
1
EOC8
End of Conversion Interrupt Mask 8
8
1
EOC9
End of Conversion Interrupt Mask 9
9
1
EOC10
End of Conversion Interrupt Mask 10
10
1
EOC11
End of Conversion Interrupt Mask 11
11
1
DRDY
Data Ready Interrupt Mask
24
1
GOVRE
General Overrun Error Interrupt Mask
25
1
COMPE
Comparison Event Interrupt Mask
26
1
TEMPCHG
Temperature Change Interrupt Mask
30
1
ISR
AFEC Interrupt Status Register
0x30
32
read-only
EOC0
End of Conversion 0 (cleared by reading AFEC_CDRx)
0
1
EOC1
End of Conversion 1 (cleared by reading AFEC_CDRx)
1
1
EOC2
End of Conversion 2 (cleared by reading AFEC_CDRx)
2
1
EOC3
End of Conversion 3 (cleared by reading AFEC_CDRx)
3
1
EOC4
End of Conversion 4 (cleared by reading AFEC_CDRx)
4
1
EOC5
End of Conversion 5 (cleared by reading AFEC_CDRx)
5
1
EOC6
End of Conversion 6 (cleared by reading AFEC_CDRx)
6
1
EOC7
End of Conversion 7 (cleared by reading AFEC_CDRx)
7
1
EOC8
End of Conversion 8 (cleared by reading AFEC_CDRx)
8
1
EOC9
End of Conversion 9 (cleared by reading AFEC_CDRx)
9
1
EOC10
End of Conversion 10 (cleared by reading AFEC_CDRx)
10
1
EOC11
End of Conversion 11 (cleared by reading AFEC_CDRx)
11
1
DRDY
Data Ready (cleared by reading AFEC_LCDR)
24
1
GOVRE
General Overrun Error (cleared by reading AFEC_ISR)
25
1
COMPE
Comparison Error (cleared by reading AFEC_ISR)
26
1
TEMPCHG
Temperature Change (cleared on read)
30
1
OVER
AFEC Overrun Status Register
0x4C
32
read-only
OVRE0
Overrun Error 0
0
1
OVRE1
Overrun Error 1
1
1
OVRE2
Overrun Error 2
2
1
OVRE3
Overrun Error 3
3
1
OVRE4
Overrun Error 4
4
1
OVRE5
Overrun Error 5
5
1
OVRE6
Overrun Error 6
6
1
OVRE7
Overrun Error 7
7
1
OVRE8
Overrun Error 8
8
1
OVRE9
Overrun Error 9
9
1
OVRE10
Overrun Error 10
10
1
OVRE11
Overrun Error 11
11
1
CWR
AFEC Compare Window Register
0x50
32
LOWTHRES
Low Threshold
0
16
HIGHTHRES
High Threshold
16
16
CGR
AFEC Channel Gain Register
0x54
32
GAIN0
Gain for Channel 0
0
2
GAIN1
Gain for Channel 1
2
2
GAIN2
Gain for Channel 2
4
2
GAIN3
Gain for Channel 3
6
2
GAIN4
Gain for Channel 4
8
2
GAIN5
Gain for Channel 5
10
2
GAIN6
Gain for Channel 6
12
2
GAIN7
Gain for Channel 7
14
2
GAIN8
Gain for Channel 8
16
2
GAIN9
Gain for Channel 9
18
2
GAIN10
Gain for Channel 10
20
2
GAIN11
Gain for Channel 11
22
2
DIFFR
AFEC Channel Differential Register
0x60
32
DIFF0
Differential inputs for channel 0
0
1
DIFF1
Differential inputs for channel 1
1
1
DIFF2
Differential inputs for channel 2
2
1
DIFF3
Differential inputs for channel 3
3
1
DIFF4
Differential inputs for channel 4
4
1
DIFF5
Differential inputs for channel 5
5
1
DIFF6
Differential inputs for channel 6
6
1
DIFF7
Differential inputs for channel 7
7
1
DIFF8
Differential inputs for channel 8
8
1
DIFF9
Differential inputs for channel 9
9
1
DIFF10
Differential inputs for channel 10
10
1
DIFF11
Differential inputs for channel 11
11
1
CSELR
AFEC Channel Selection Register
0x64
32
CSEL
Channel Selection
0
4
CDR
AFEC Channel Data Register
0x68
32
read-only
DATA
Converted Data
0
16
COCR
AFEC Channel Offset Compensation Register
0x6C
32
AOFF
Analog Offset
0
10
TEMPMR
AFEC Temperature Sensor Mode Register
0x70
32
RTCT
Temperature Sensor RTC Trigger Mode
0
1
TEMPCMPMOD
Temperature Comparison Mode
4
2
TEMPCMPMODSelect
LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x0
HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x1
IN
Generates an event when the converted data is in the comparison window.
0x2
OUT
Generates an event when the converted data is out of the comparison window.
0x3
TEMPCWR
AFEC Temperature Compare Window Register
0x74
32
TLOWTHRES
Temperature Low Threshold
0
16
THIGHTHRES
Temperature High Threshold
16
16
ACR
AFEC Analog Control Register
0x94
32
PGA0EN
PGA0 Enable
2
1
PGA1EN
PGA1 Enable
3
1
IBCTL
AFE Bias Current Control
8
2
SHMR
AFEC Sample & Hold Mode Register
0xA0
32
DUAL0
Dual Sample & Hold for channel 0
0
1
DUAL1
Dual Sample & Hold for channel 1
1
1
DUAL2
Dual Sample & Hold for channel 2
2
1
DUAL3
Dual Sample & Hold for channel 3
3
1
DUAL4
Dual Sample & Hold for channel 4
4
1
DUAL5
Dual Sample & Hold for channel 5
5
1
DUAL6
Dual Sample & Hold for channel 6
6
1
DUAL7
Dual Sample & Hold for channel 7
7
1
DUAL8
Dual Sample & Hold for channel 8
8
1
DUAL9
Dual Sample & Hold for channel 9
9
1
DUAL10
Dual Sample & Hold for channel 10
10
1
DUAL11
Dual Sample & Hold for channel 11
11
1
COSR
AFEC Correction Select Register
0xD0
32
CSEL
Sample & Hold unit Correction Select
0
1
CVR
AFEC Correction Values Register
0xD4
32
OFFSETCORR
Offset Correction
0
16
GAINCORR
Gain Correction
16
16
CECR
AFEC Channel Error Correction Register
0xD8
32
ECORR0
Error Correction Enable for channel 0
0
1
ECORR1
Error Correction Enable for channel 1
1
1
ECORR2
Error Correction Enable for channel 2
2
1
ECORR3
Error Correction Enable for channel 3
3
1
ECORR4
Error Correction Enable for channel 4
4
1
ECORR5
Error Correction Enable for channel 5
5
1
ECORR6
Error Correction Enable for channel 6
6
1
ECORR7
Error Correction Enable for channel 7
7
1
ECORR8
Error Correction Enable for channel 8
8
1
ECORR9
Error Correction Enable for channel 9
9
1
ECORR10
Error Correction Enable for channel 10
10
1
ECORR11
Error Correction Enable for channel 11
11
1
WPMR
AFEC Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protect KEY
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x414443
WPSR
AFEC Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protect Violation Status
0
1
WPVSRC
Write Protect Violation Source
8
16
AFEC1
0x40064000
AFEC1
40
CHIPID
6417ZK
Chip Identifier
0x400E0940
0
0x8
registers
CIDR
Chip ID Register
0x0
32
read-only
VERSION
Version of the Device
0
5
EPROC
Embedded Processor
5
3
EPROCSelect
SAMx7
Cortex-M7
0x0
ARM946ES
ARM946ES
0x1
ARM7TDMI
ARM7TDMI
0x2
CM3
Cortex-M3
0x3
ARM920T
ARM920T
0x4
ARM926EJS
ARM926EJS
0x5
CA5
Cortex-A5
0x6
CM4
Cortex-M4
0x7
NVPSIZ
Nonvolatile Program Memory Size
8
4
NVPSIZSelect
NONE
None
0x0
_8K
8 Kbytes
0x1
_16K
16 Kbytes
0x2
_32K
32 Kbytes
0x3
_64K
64 Kbytes
0x5
_128K
128 Kbytes
0x7
_160K
160 Kbytes
0x8
_256K
256 Kbytes
0x9
_512K
512 Kbytes
0xA
_1024K
1024 Kbytes
0xC
_2048K
2048 Kbytes
0xE
NVPSIZ2
Second Nonvolatile Program Memory Size
12
4
NVPSIZ2Select
NONE
None
0x0
_8K
8 Kbytes
0x1
_16K
16 Kbytes
0x2
_32K
32 Kbytes
0x3
_64K
64 Kbytes
0x5
_128K
128 Kbytes
0x7
_256K
256 Kbytes
0x9
_512K
512 Kbytes
0xA
_1024K
1024 Kbytes
0xC
_2048K
2048 Kbytes
0xE
SRAMSIZ
Internal SRAM Size
16
4
SRAMSIZSelect
_48K
48 Kbytes
0x0
_192K
192 Kbytes
0x1
_384K
384 Kbytes
0x2
_6K
6 Kbytes
0x3
_24K
24 Kbytes
0x4
_4K
4 Kbytes
0x5
_80K
80 Kbytes
0x6
_160K
160 Kbytes
0x7
_8K
8 Kbytes
0x8
_16K
16 Kbytes
0x9
_32K
32 Kbytes
0xA
_64K
64 Kbytes
0xB
_128K
128 Kbytes
0xC
_256K
256 Kbytes
0xD
_96K
96 Kbytes
0xE
_512K
512 Kbytes
0xF
ARCH
Architecture Identifier
20
8
ARCHSelect
SAME70
SAM E70
0x10
SAMS70
SAM S70
0x11
SAMV71
SAM V71
0x12
SAMV70
SAM V70
0x13
NVPTYP
Nonvolatile Program Memory Type
28
3
NVPTYPSelect
ROM
ROM
0x0
ROMLESS
ROMless or on-chip Flash
0x1
FLASH
Embedded Flash Memory
0x2
ROM_FLASH
ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size
0x3
SRAM
SRAM emulating ROM
0x4
EXT
Extension Flag
31
1
EXID
Chip ID Extension Register
0x4
32
read-only
EXID
Chip ID Extension
0
32
DACC
11246E
Digital-to-Analog Converter Controller
0x40040000
0
0xEC
registers
DACC
30
CR
Control Register
0x00
32
write-only
SWRST
Software Reset
0
1
MR
Mode Register
0x04
32
MAXS0
Max Speed Mode for Channel 0
0
1
MAXS0Select
TRIG_EVENT
External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)
0
MAXIMUM
Max speed mode enabled.
1
MAXS1
Max Speed Mode for Channel 1
1
1
MAXS1Select
TRIG_EVENT
External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)
0
MAXIMUM
Max speed mode enabled.
1
WORD
Word Transfer Mode
4
1
WORDSelect
DISABLED
One data to convert is written to the FIFO per access to DACC.
0
ENABLED
Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses).
1
ZERO
Must always be written to 0.
5
1
DIFF
Differential Mode
23
1
DIFFSelect
DISABLED
DAC0 and DAC1 are single-ended outputs.
0
ENABLED
DACP and DACN are differential outputs. The differential level is configured by the channel 0 value.
1
PRESCALER
Peripheral Clock to DAC Clock Ratio
24
4
TRIGR
Trigger Register
0x08
32
TRGEN0
Trigger Enable of Channel 0
0
1
TRGEN0Select
DIS
External trigger mode disabled. DACC is in Free-running mode or Max speed mode.
0
EN
External trigger mode enabled.
1
TRGEN1
Trigger Enable of Channel 1
1
1
TRGEN1Select
DIS
External trigger mode disabled. DACC is in Free-running mode or Max speed mode.
0
EN
External trigger mode enabled.
1
TRGSEL0
Trigger Selection of Channel 0
4
3
TRGSEL0Select
TRGSEL0
DAC External Trigger Input (DATRG)
0x0
TRGSEL1
TC0 Channel 0 Output (TIOA0)
0x1
TRGSEL2
TC0 Channel 1 Output (TIOA1)
0x2
TRGSEL3
TC0 Channel 2 Output (TIOA2)
0x3
TRGSEL4
PWM0 Event Line 0
0x4
TRGSEL5
PWM0 Event Line 1
0x5
TRGSEL6
PWM1 Event Line 0
0x6
TRGSEL7
PWM1 Event Line 1
0x7
TRGSEL1
Trigger Selection of Channel 1
8
3
TRGSEL1Select
TRGSEL0
DAC External Trigger Input (DATRG)
0x0
TRGSEL1
TC0 Channel 0 Output (TIOA0)
0x1
TRGSEL2
TC0 Channel 1 Output (TIOA1)
0x2
TRGSEL3
TC0 Channel 2 Output (TIOA2)
0x3
TRGSEL4
PWM0 Event Line 0
0x4
TRGSEL5
PWM0 Event Line 1
0x5
TRGSEL6
PWM1 Event Line 0
0x6
TRGSEL7
PWM1 Event Line 1
0x7
OSR0
Over Sampling Ratio of Channel 0
16
3
OSR0Select
OSR_1
OSR = 1
0x0
OSR_2
OSR = 2
0x1
OSR_4
OSR = 4
0x2
OSR_8
OSR = 8
0x3
OSR_16
OSR = 16
0x4
OSR_32
OSR = 32
0x5
OSR1
Over Sampling Ratio of Channel 1
20
3
OSR1Select
OSR_1
OSR = 1
0x0
OSR_2
OSR = 2
0x1
OSR_4
OSR = 4
0x2
OSR_8
OSR = 8
0x3
OSR_16
OSR = 16
0x4
OSR_32
OSR = 32
0x5
CHER
Channel Enable Register
0x10
32
write-only
CH0
Channel 0 Enable
0
1
CH1
Channel 1 Enable
1
1
CHDR
Channel Disable Register
0x14
32
write-only
CH0
Channel 0 Disable
0
1
CH1
Channel 1 Disable
1
1
CHSR
Channel Status Register
0x18
32
read-only
CH0
Channel 0 Status
0
1
CH1
Channel 1 Status
1
1
DACRDY0
DAC Ready Flag
8
1
DACRDY1
DAC Ready Flag
9
1
2
4
CDR[%s]
Conversion Data Register 0
0x1C
32
write-only
DATA0
Data to Convert for channel 0
0
16
DATA1
Data to Convert for channel 1
16
16
IER
Interrupt Enable Register
0x24
32
write-only
TXRDY0
Transmit Ready Interrupt Enable of channel 0
0
1
TXRDY1
Transmit Ready Interrupt Enable of channel 1
1
1
EOC0
End of Conversion Interrupt Enable of channel 0
4
1
EOC1
End of Conversion Interrupt Enable of channel 1
5
1
IDR
Interrupt Disable Register
0x28
32
write-only
TXRDY0
Transmit Ready Interrupt Disable of channel 0
0
1
TXRDY1
Transmit Ready Interrupt Disable of channel 1
1
1
EOC0
End of Conversion Interrupt Disable of channel 0
4
1
EOC1
End of Conversion Interrupt Disable of channel 1
5
1
IMR
Interrupt Mask Register
0x2C
32
read-only
TXRDY0
Transmit Ready Interrupt Mask of channel 0
0
1
TXRDY1
Transmit Ready Interrupt Mask of channel 1
1
1
EOC0
End of Conversion Interrupt Mask of channel 0
4
1
EOC1
End of Conversion Interrupt Mask of channel 1
5
1
ISR
Interrupt Status Register
0x30
32
read-only
TXRDY0
Transmit Ready Interrupt Flag of channel 0
0
1
TXRDY1
Transmit Ready Interrupt Flag of channel 1
1
1
EOC0
End of Conversion Interrupt Flag of channel 0
4
1
EOC1
End of Conversion Interrupt Flag of channel 1
5
1
ACR
Analog Current Register
0x94
32
IBCTLCH0
Analog Output Current Control
0
2
IBCTLCH1
Analog Output Current Control
2
2
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protect Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0.
0x444143
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
8
EFC
6450Y
Embedded Flash Controller
0x400E0C00
0
0xE8
registers
EFC
6
EEFC_FMR
EEFC Flash Mode Register
0x00
32
FRDY
Flash Ready Interrupt Enable
0
1
FWS
Flash Wait State
8
4
SCOD
Sequential Code Optimization Disable
16
1
CLOE
Code Loop Optimization Enable
26
1
EEFC_FCR
EEFC Flash Command Register
0x04
32
write-only
FCMD
Flash Command
0
8
FCMDSelect
GETD
Get Flash descriptor
0x00
WP
Write page
0x01
WPL
Write page and lock
0x02
EWP
Erase page and write page
0x03
EWPL
Erase page and write page then lock
0x04
EA
Erase all
0x05
EPA
Erase pages
0x07
SLB
Set lock bit
0x08
CLB
Clear lock bit
0x09
GLB
Get lock bit
0x0A
SGPB
Set GPNVM bit
0x0B
CGPB
Clear GPNVM bit
0x0C
GGPB
Get GPNVM bit
0x0D
STUI
Start read unique identifier
0x0E
SPUI
Stop read unique identifier
0x0F
GCALB
Get CALIB bit
0x10
ES
Erase sector
0x11
WUS
Write user signature
0x12
EUS
Erase user signature
0x13
STUS
Start read user signature
0x14
SPUS
Stop read user signature
0x15
FARG
Flash Command Argument
8
16
FKEY
Flash Writing Protection Key
24
8
FKEYSelect
PASSWD
The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.
0x5A
EEFC_FSR
EEFC Flash Status Register
0x08
32
read-only
FRDY
Flash Ready Status (cleared when Flash is busy)
0
1
FCMDE
Flash Command Error Status (cleared on read or by writing EEFC_FCR)
1
1
FLOCKE
Flash Lock Error Status (cleared on read)
2
1
FLERR
Flash Error Status (cleared when a programming operation starts)
3
1
UECCELSB
Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
16
1
MECCELSB
Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
17
1
UECCEMSB
Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
18
1
MECCEMSB
Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
19
1
EEFC_FRR
EEFC Flash Result Register
0x0C
32
read-only
FVALUE
Flash Result Value
0
32
EEFC_WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
0x454643
GMAC
11046S
Gigabit Ethernet MAC
0x40050000
0
0x820
registers
GMAC
39
GMAC_Q1
66
GMAC_Q2
67
GMAC_Q3
71
GMAC_Q4
72
GMAC_Q5
73
NCR
Network Control Register
0x000
32
LBL
Loop Back Local
1
1
RXEN
Receive Enable
2
1
TXEN
Transmit Enable
3
1
MPE
Management Port Enable
4
1
CLRSTAT
Clear Statistics Registers
5
1
INCSTAT
Increment Statistics Registers
6
1
WESTAT
Write Enable for Statistics Registers
7
1
BP
Back pressure
8
1
TSTART
Start Transmission
9
1
THALT
Transmit Halt
10
1
TXPF
Transmit Pause Frame
11
1
TXZQPF
Transmit Zero Quantum Pause Frame
12
1
SRTSM
Store Receive Time Stamp to Memory
15
1
ENPBPR
Enable PFC Priority-based Pause Reception
16
1
TXPBPF
Transmit PFC Priority-based Pause Frame
17
1
FNP
Flush Next Packet
18
1
TXLPIEN
Enable LPI Transmission
19
1
NCFGR
Network Configuration Register
0x004
32
SPD
Speed
0
1
FD
Full Duplex
1
1
DNVLAN
Discard Non-VLAN FRAMES
2
1
JFRAME
Jumbo Frame Size
3
1
CAF
Copy All Frames
4
1
NBC
No Broadcast
5
1
MTIHEN
Multicast Hash Enable
6
1
UNIHEN
Unicast Hash Enable
7
1
MAXFS
1536 Maximum Frame Size
8
1
RTY
Retry Test
12
1
PEN
Pause Enable
13
1
RXBUFO
Receive Buffer Offset
14
2
LFERD
Length Field Error Frame Discard
16
1
RFCS
Remove FCS
17
1
CLK
MDC CLock Division
18
3
CLKSelect
MCK_8
MCK divided by 8 (MCK up to 20 MHz)
0x0
MCK_16
MCK divided by 16 (MCK up to 40 MHz)
0x1
MCK_32
MCK divided by 32 (MCK up to 80 MHz)
0x2
MCK_48
MCK divided by 48 (MCK up to 120 MHz)
0x3
MCK_64
MCK divided by 64 (MCK up to 160 MHz)
0x4
MCK_96
MCK divided by 96 (MCK up to 240 MHz)
0x5
DBW
Data Bus Width
21
2
DCPF
Disable Copy of Pause Frames
23
1
RXCOEN
Receive Checksum Offload Enable
24
1
EFRHD
Enable Frames Received in Half Duplex
25
1
IRXFCS
Ignore RX FCS
26
1
IPGSEN
IP Stretch Enable
28
1
RXBP
Receive Bad Preamble
29
1
IRXER
Ignore IPG GRXER
30
1
NSR
Network Status Register
0x008
32
read-only
MDIO
MDIO Input Status
1
1
IDLE
PHY Management Logic Idle
2
1
RXLPIS
LPI Indication
7
1
UR
User Register
0x00C
32
RMII
Reduced MII Mode
0
1
DCFGR
DMA Configuration Register
0x010
32
FBLDO
Fixed Burst Length for DMA Data Operations:
0
5
FBLDOSelect
SINGLE
00001: Always use SINGLE AHB bursts
0x1
INCR4
001xx: Attempt to use INCR4 AHB bursts (Default)
0x4
INCR8
01xxx: Attempt to use INCR8 AHB bursts
0x8
INCR16
1xxxx: Attempt to use INCR16 AHB bursts
0x10
ESMA
Endian Swap Mode Enable for Management Descriptor Accesses
6
1
ESPA
Endian Swap Mode Enable for Packet Data Accesses
7
1
RXBMS
Receiver Packet Buffer Memory Size Select
8
2
RXBMSSelect
EIGHTH
4/8 Kbyte Memory Size
0x0
QUARTER
4/4 Kbytes Memory Size
0x1
HALF
4/2 Kbytes Memory Size
0x2
FULL
4 Kbytes Memory Size
0x3
TXPBMS
Transmitter Packet Buffer Memory Size Select
10
1
TXCOEN
Transmitter Checksum Generation Offload Enable
11
1
DRBS
DMA Receive Buffer Size
16
8
DDRP
DMA Discard Receive Packets
24
1
TSR
Transmit Status Register
0x014
32
UBR
Used Bit Read
0
1
COL
Collision Occurred
1
1
RLE
Retry Limit Exceeded
2
1
TXGO
Transmit Go
3
1
TFC
Transmit Frame Corruption Due to AHB Error
4
1
TXCOMP
Transmit Complete
5
1
HRESP
HRESP Not OK
8
1
RBQB
Receive Buffer Queue Base Address Register
0x018
32
ADDR
Receive Buffer Queue Base Address
2
30
TBQB
Transmit Buffer Queue Base Address Register
0x01C
32
ADDR
Transmit Buffer Queue Base Address
2
30
RSR
Receive Status Register
0x020
32
BNA
Buffer Not Available
0
1
REC
Frame Received
1
1
RXOVR
Receive Overrun
2
1
HNO
HRESP Not OK
3
1
ISR
Interrupt Status Register
0x024
32
read-only
MFS
Management Frame Sent
0
1
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
TXUBR
TX Used Bit Read
3
1
TUR
Transmit Underrun
4
1
RLEX
Retry Limit Exceeded
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
PFNZ
Pause Frame with Non-zero Pause Quantum Received
12
1
PTZ
Pause Time Zero
13
1
PFTR
Pause Frame Transmitted
14
1
DRQFR
PTP Delay Request Frame Received
18
1
SFR
PTP Sync Frame Received
19
1
DRQFT
PTP Delay Request Frame Transmitted
20
1
SFT
PTP Sync Frame Transmitted
21
1
PDRQFR
PDelay Request Frame Received
22
1
PDRSFR
PDelay Response Frame Received
23
1
PDRQFT
PDelay Request Frame Transmitted
24
1
PDRSFT
PDelay Response Frame Transmitted
25
1
SRI
TSU Seconds Register Increment
26
1
RXLPISBC
Receive LPI indication Status Bit Change
27
1
WOL
Wake On LAN
28
1
TSUTIMCOMP
TSU Timer Comparison
29
1
IER
Interrupt Enable Register
0x028
32
write-only
MFS
Management Frame Sent
0
1
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
TXUBR
TX Used Bit Read
3
1
TUR
Transmit Underrun
4
1
RLEX
Retry Limit Exceeded or Late Collision
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
PFNZ
Pause Frame with Non-zero Pause Quantum Received
12
1
PTZ
Pause Time Zero
13
1
PFTR
Pause Frame Transmitted
14
1
EXINT
External Interrupt
15
1
DRQFR
PTP Delay Request Frame Received
18
1
SFR
PTP Sync Frame Received
19
1
DRQFT
PTP Delay Request Frame Transmitted
20
1
SFT
PTP Sync Frame Transmitted
21
1
PDRQFR
PDelay Request Frame Received
22
1
PDRSFR
PDelay Response Frame Received
23
1
PDRQFT
PDelay Request Frame Transmitted
24
1
PDRSFT
PDelay Response Frame Transmitted
25
1
SRI
TSU Seconds Register Increment
26
1
RXLPISBC
Enable RX LPI Indication
27
1
WOL
Wake On LAN
28
1
TSUTIMCOMP
TSU Timer Comparison
29
1
IDR
Interrupt Disable Register
0x02C
32
write-only
MFS
Management Frame Sent
0
1
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
TXUBR
TX Used Bit Read
3
1
TUR
Transmit Underrun
4
1
RLEX
Retry Limit Exceeded or Late Collision
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
PFNZ
Pause Frame with Non-zero Pause Quantum Received
12
1
PTZ
Pause Time Zero
13
1
PFTR
Pause Frame Transmitted
14
1
EXINT
External Interrupt
15
1
DRQFR
PTP Delay Request Frame Received
18
1
SFR
PTP Sync Frame Received
19
1
DRQFT
PTP Delay Request Frame Transmitted
20
1
SFT
PTP Sync Frame Transmitted
21
1
PDRQFR
PDelay Request Frame Received
22
1
PDRSFR
PDelay Response Frame Received
23
1
PDRQFT
PDelay Request Frame Transmitted
24
1
PDRSFT
PDelay Response Frame Transmitted
25
1
SRI
TSU Seconds Register Increment
26
1
RXLPISBC
Enable RX LPI Indication
27
1
WOL
Wake On LAN
28
1
TSUTIMCOMP
TSU Timer Comparison
29
1
IMR
Interrupt Mask Register
0x030
32
MFS
Management Frame Sent
0
1
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
TXUBR
TX Used Bit Read
3
1
TUR
Transmit Underrun
4
1
RLEX
Retry Limit Exceeded
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
PFNZ
Pause Frame with Non-zero Pause Quantum Received
12
1
PTZ
Pause Time Zero
13
1
PFTR
Pause Frame Transmitted
14
1
EXINT
External Interrupt
15
1
DRQFR
PTP Delay Request Frame Received
18
1
SFR
PTP Sync Frame Received
19
1
DRQFT
PTP Delay Request Frame Transmitted
20
1
SFT
PTP Sync Frame Transmitted
21
1
PDRQFR
PDelay Request Frame Received
22
1
PDRSFR
PDelay Response Frame Received
23
1
PDRQFT
PDelay Request Frame Transmitted
24
1
PDRSFT
PDelay Response Frame Transmitted
25
1
SRI
TSU Seconds Register Increment
26
1
RXLPISBC
Enable RX LPI Indication
27
1
WOL
Wake On LAN
28
1
TSUTIMCOMP
TSU Timer Comparison
29
1
MAN
PHY Maintenance Register
0x034
32
DATA
PHY Data
0
16
WTN
Write Ten
16
2
REGA
Register Address
18
5
PHYA
PHY Address
23
5
OP
Operation
28
2
CLTTO
Clause 22 Operation
30
1
WZO
Write ZERO
31
1
RPQ
Received Pause Quantum Register
0x038
32
read-only
RPQ
Received Pause Quantum
0
16
TPQ
Transmit Pause Quantum Register
0x03C
32
TPQ
Transmit Pause Quantum
0
16
TPSF
TX Partial Store and Forward Register
0x040
32
TPB1ADR
Transmit Partial Store and Forward Address
0
12
ENTXP
Enable TX Partial Store and Forward Operation
31
1
RPSF
RX Partial Store and Forward Register
0x044
32
RPB1ADR
Receive Partial Store and Forward Address
0
12
ENRXP
Enable RX Partial Store and Forward Operation
31
1
RJFML
RX Jumbo Frame Max Length Register
0x048
32
FML
Frame Max Length
0
14
HRB
Hash Register Bottom
0x080
32
ADDR
Hash Address
0
32
HRT
Hash Register Top
0x084
32
ADDR
Hash Address
0
32
4
8
1-4
GMAC_SA%s
Specific Address 1 Bottom Register
0x088
SAB
Specific Address 1 Bottom Register
0x00
32
ADDR
Specific Address 1
0
32
SAT
Specific Address 1 Top Register
0x04
32
ADDR
Specific Address 1
0
16
TIDM1
Type ID Match 1 Register
0x0A8
32
TID
Type ID Match 1
0
16
ENID1
Enable Copying of TID Matched Frames
31
1
TIDM2
Type ID Match 2 Register
0x0AC
32
TID
Type ID Match 2
0
16
ENID2
Enable Copying of TID Matched Frames
31
1
TIDM3
Type ID Match 3 Register
0x0B0
32
TID
Type ID Match 3
0
16
ENID3
Enable Copying of TID Matched Frames
31
1
TIDM4
Type ID Match 4 Register
0x0B4
32
TID
Type ID Match 4
0
16
ENID4
Enable Copying of TID Matched Frames
31
1
WOL
Wake on LAN Register
0x0B8
32
IP
ARP Request IP Address
0
16
MAG
Magic Packet Event Enable
16
1
ARP
ARP Request IP Address
17
1
SA1
Specific Address Register 1 Event Enable
18
1
MTI
Multicast Hash Event Enable
19
1
IPGS
IPG Stretch Register
0x0BC
32
FL
Frame Length
0
16
SVLAN
Stacked VLAN Register
0x0C0
32
VLAN_TYPE
User Defined VLAN_TYPE Field
0
16
ESVLAN
Enable Stacked VLAN Processing Mode
31
1
TPFCP
Transmit PFC Pause Register
0x0C4
32
PEV
Priority Enable Vector
0
8
PQ
Pause Quantum
8
8
SAMB1
Specific Address 1 Mask Bottom Register
0x0C8
32
ADDR
Specific Address 1 Mask
0
32
SAMT1
Specific Address 1 Mask Top Register
0x0CC
32
ADDR
Specific Address 1 Mask
0
16
NSC
1588 Timer Nanosecond Comparison Register
0x0DC
32
NANOSEC
1588 Timer Nanosecond Comparison Value
0
22
SCL
1588 Timer Second Comparison Low Register
0x0E0
32
SEC
1588 Timer Second Comparison Value
0
32
SCH
1588 Timer Second Comparison High Register
0x0E4
32
SEC
1588 Timer Second Comparison Value
0
16
EFTSH
PTP Event Frame Transmitted Seconds High Register
0x0E8
32
read-only
RUD
Register Update
0
16
EFRSH
PTP Event Frame Received Seconds High Register
0x0EC
32
read-only
RUD
Register Update
0
16
PEFTSH
PTP Peer Event Frame Transmitted Seconds High Register
0x0F0
32
read-only
RUD
Register Update
0
16
PEFRSH
PTP Peer Event Frame Received Seconds High Register
0x0F4
32
read-only
RUD
Register Update
0
16
OTLO
Octets Transmitted Low Register
0x100
32
read-only
TXO
Transmitted Octets
0
32
OTHI
Octets Transmitted High Register
0x104
32
read-only
TXO
Transmitted Octets
0
16
FT
Frames Transmitted Register
0x108
32
read-only
FTX
Frames Transmitted without Error
0
32
BCFT
Broadcast Frames Transmitted Register
0x10C
32
read-only
BFTX
Broadcast Frames Transmitted without Error
0
32
MFT
Multicast Frames Transmitted Register
0x110
32
read-only
MFTX
Multicast Frames Transmitted without Error
0
32
PFT
Pause Frames Transmitted Register
0x114
32
read-only
PFTX
Pause Frames Transmitted Register
0
16
BFT64
64 Byte Frames Transmitted Register
0x118
32
read-only
NFTX
64 Byte Frames Transmitted without Error
0
32
TBFT127
65 to 127 Byte Frames Transmitted Register
0x11C
32
read-only
NFTX
65 to 127 Byte Frames Transmitted without Error
0
32
TBFT255
128 to 255 Byte Frames Transmitted Register
0x120
32
read-only
NFTX
128 to 255 Byte Frames Transmitted without Error
0
32
TBFT511
256 to 511 Byte Frames Transmitted Register
0x124
32
read-only
NFTX
256 to 511 Byte Frames Transmitted without Error
0
32
TBFT1023
512 to 1023 Byte Frames Transmitted Register
0x128
32
read-only
NFTX
512 to 1023 Byte Frames Transmitted without Error
0
32
TBFT1518
1024 to 1518 Byte Frames Transmitted Register
0x12C
32
read-only
NFTX
1024 to 1518 Byte Frames Transmitted without Error
0
32
GTBFT1518
Greater Than 1518 Byte Frames Transmitted Register
0x130
32
read-only
NFTX
Greater than 1518 Byte Frames Transmitted without Error
0
32
TUR
Transmit Underruns Register
0x134
32
read-only
TXUNR
Transmit Underruns
0
10
SCF
Single Collision Frames Register
0x138
32
read-only
SCOL
Single Collision
0
18
MCF
Multiple Collision Frames Register
0x13C
32
read-only
MCOL
Multiple Collision
0
18
EC
Excessive Collisions Register
0x140
32
read-only
XCOL
Excessive Collisions
0
10
LC
Late Collisions Register
0x144
32
read-only
LCOL
Late Collisions
0
10
DTF
Deferred Transmission Frames Register
0x148
32
read-only
DEFT
Deferred Transmission
0
18
CSE
Carrier Sense Errors Register
0x14C
32
read-only
CSR
Carrier Sense Error
0
10
ORLO
Octets Received Low Received Register
0x150
32
read-only
RXO
Received Octets
0
32
ORHI
Octets Received High Received Register
0x154
32
read-only
RXO
Received Octets
0
16
FR
Frames Received Register
0x158
32
read-only
FRX
Frames Received without Error
0
32
BCFR
Broadcast Frames Received Register
0x15C
32
read-only
BFRX
Broadcast Frames Received without Error
0
32
MFR
Multicast Frames Received Register
0x160
32
read-only
MFRX
Multicast Frames Received without Error
0
32
PFR
Pause Frames Received Register
0x164
32
read-only
PFRX
Pause Frames Received Register
0
16
BFR64
64 Byte Frames Received Register
0x168
32
read-only
NFRX
64 Byte Frames Received without Error
0
32
TBFR127
65 to 127 Byte Frames Received Register
0x16C
32
read-only
NFRX
65 to 127 Byte Frames Received without Error
0
32
TBFR255
128 to 255 Byte Frames Received Register
0x170
32
read-only
NFRX
128 to 255 Byte Frames Received without Error
0
32
TBFR511
256 to 511 Byte Frames Received Register
0x174
32
read-only
NFRX
256 to 511 Byte Frames Received without Error
0
32
TBFR1023
512 to 1023 Byte Frames Received Register
0x178
32
read-only
NFRX
512 to 1023 Byte Frames Received without Error
0
32
TBFR1518
1024 to 1518 Byte Frames Received Register
0x17C
32
read-only
NFRX
1024 to 1518 Byte Frames Received without Error
0
32
TMXBFR
1519 to Maximum Byte Frames Received Register
0x180
32
read-only
NFRX
1519 to Maximum Byte Frames Received without Error
0
32
UFR
Undersize Frames Received Register
0x184
32
read-only
UFRX
Undersize Frames Received
0
10
OFR
Oversize Frames Received Register
0x188
32
read-only
OFRX
Oversized Frames Received
0
10
JR
Jabbers Received Register
0x18C
32
read-only
JRX
Jabbers Received
0
10
FCSE
Frame Check Sequence Errors Register
0x190
32
read-only
FCKR
Frame Check Sequence Errors
0
10
LFFE
Length Field Frame Errors Register
0x194
32
read-only
LFER
Length Field Frame Errors
0
10
RSE
Receive Symbol Errors Register
0x198
32
read-only
RXSE
Receive Symbol Errors
0
10
AE
Alignment Errors Register
0x19C
32
read-only
AER
Alignment Errors
0
10
RRE
Receive Resource Errors Register
0x1A0
32
read-only
RXRER
Receive Resource Errors
0
18
ROE
Receive Overrun Register
0x1A4
32
read-only
RXOVR
Receive Overruns
0
10
IHCE
IP Header Checksum Errors Register
0x1A8
32
read-only
HCKER
IP Header Checksum Errors
0
8
TCE
TCP Checksum Errors Register
0x1AC
32
read-only
TCKER
TCP Checksum Errors
0
8
UCE
UDP Checksum Errors Register
0x1B0
32
read-only
UCKER
UDP Checksum Errors
0
8
TISUBN
1588 Timer Increment Sub-nanoseconds Register
0x1BC
32
LSBTIR
Lower Significant Bits of Timer Increment Register
0
16
TSH
1588 Timer Seconds High Register
0x1C0
32
TCS
Timer Count in Seconds
0
16
TSL
1588 Timer Seconds Low Register
0x1D0
32
TCS
Timer Count in Seconds
0
32
TN
1588 Timer Nanoseconds Register
0x1D4
32
TNS
Timer Count in Nanoseconds
0
30
TA
1588 Timer Adjust Register
0x1D8
32
write-only
ITDT
Increment/Decrement
0
30
ADJ
Adjust 1588 Timer
31
1
TI
1588 Timer Increment Register
0x1DC
32
CNS
Count Nanoseconds
0
8
ACNS
Alternative Count Nanoseconds
8
8
NIT
Number of Increments
16
8
EFTSL
PTP Event Frame Transmitted Seconds Low Register
0x1E0
32
read-only
RUD
Register Update
0
32
EFTN
PTP Event Frame Transmitted Nanoseconds Register
0x1E4
32
read-only
RUD
Register Update
0
30
EFRSL
PTP Event Frame Received Seconds Low Register
0x1E8
32
read-only
RUD
Register Update
0
32
EFRN
PTP Event Frame Received Nanoseconds Register
0x1EC
32
read-only
RUD
Register Update
0
30
PEFTSL
PTP Peer Event Frame Transmitted Seconds Low Register
0x1F0
32
read-only
RUD
Register Update
0
32
PEFTN
PTP Peer Event Frame Transmitted Nanoseconds Register
0x1F4
32
read-only
RUD
Register Update
0
30
PEFRSL
PTP Peer Event Frame Received Seconds Low Register
0x1F8
32
read-only
RUD
Register Update
0
32
PEFRN
PTP Peer Event Frame Received Nanoseconds Register
0x1FC
32
read-only
RUD
Register Update
0
30
RXLPI
Received LPI Transitions
0x270
32
read-only
COUNT
Count of RX LPI transitions (cleared on read)
0
16
RXLPITIME
Received LPI Time
0x274
32
read-only
LPITIME
Time in LPI (cleared on read)
0
24
TXLPI
Transmit LPI Transitions
0x278
32
read-only
COUNT
Count of LPI transitions (cleared on read)
0
16
TXLPITIME
Transmit LPI Time
0x27C
32
read-only
LPITIME
Time in LPI (cleared on read)
0
24
5
4
ISRPQ[%s]
Interrupt Status Register Priority Queue (1..5)
0x400
32
read-only
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
RLEX
Retry Limit Exceeded or Late Collision
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
5
4
TBQBAPQ[%s]
Transmit Buffer Queue Base Address Register Priority Queue (1..5)
0x440
32
TXBQBA
Transmit Buffer Queue Base Address
2
30
5
4
RBQBAPQ[%s]
Receive Buffer Queue Base Address Register Priority Queue (1..5)
0x480
32
RXBQBA
Receive Buffer Queue Base Address
2
30
5
4
RBSRPQ[%s]
Receive Buffer Size Register Priority Queue (1..5)
0x4A0
32
RBS
Receive Buffer Size
0
16
CBSCR
Credit-Based Shaping Control Register
0x4BC
32
QBE
Queue B CBS Enable
0
1
QAE
Queue A CBS Enable
1
1
CBSISQA
Credit-Based Shaping IdleSlope Register for Queue A
0x4C0
32
IS
IdleSlope
0
32
CBSISQB
Credit-Based Shaping IdleSlope Register for Queue B
0x4C4
32
IS
IdleSlope
0
32
4
4
ST1RPQ[%s]
Screening Type 1 Register Priority Queue
0x500
32
QNB
Queue Number (0-5)
0
3
DSTCM
Differentiated Services or Traffic Class Match
4
8
UDPM
UDP Port Match
12
16
DSTCE
Differentiated Services or Traffic Class Match Enable
28
1
UDPE
UDP Port Match Enable
29
1
8
4
ST2RPQ[%s]
Screening Type 2 Register Priority Queue
0x540
32
QNB
Queue Number (0-5)
0
3
VLANP
VLAN Priority
4
3
VLANE
VLAN Enable
8
1
I2ETH
Index of Screening Type 2 EtherType register x
9
3
ETHE
EtherType Enable
12
1
COMPA
Index of Screening Type 2 Compare Word 0/Word 1 register x
13
5
COMPAE
Compare A Enable
18
1
COMPB
Index of Screening Type 2 Compare Word 0/Word 1 register x
19
5
COMPBE
Compare B Enable
24
1
COMPC
Index of Screening Type 2 Compare Word 0/Word 1 register x
25
5
COMPCE
Compare C Enable
30
1
5
4
IERPQ[%s]
Interrupt Enable Register Priority Queue (1..5)
0x600
32
write-only
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
RLEX
Retry Limit Exceeded or Late Collision
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
5
4
IDRPQ[%s]
Interrupt Disable Register Priority Queue (1..5)
0x620
32
write-only
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
RLEX
Retry Limit Exceeded or Late Collision
5
1
TFC
Transmit Frame Corruption Due to AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
5
4
IMRPQ[%s]
Interrupt Mask Register Priority Queue (1..5)
0x640
32
RCOMP
Receive Complete
1
1
RXUBR
RX Used Bit Read
2
1
RLEX
Retry Limit Exceeded or Late Collision
5
1
AHB
AHB Error
6
1
TCOMP
Transmit Complete
7
1
ROVR
Receive Overrun
10
1
HRESP
HRESP Not OK
11
1
4
4
ST2ER[%s]
Screening Type 2 Ethertype Register
0x6E0
32
COMPVAL
Ethertype Compare Value
0
16
24
8
GMAC_ST2CW[%s]
Screening Type 2 Compare Word 0 Register
0x700
ST2CW0
Screening Type 2 Compare Word 0 Register
0x00
32
MASKVAL
Mask Value
0
16
COMPVAL
Compare Value
16
16
ST2CW1
Screening Type 2 Compare Word 1 Register
0x04
32
OFFSVAL
Offset Value in Bytes
0
7
OFFSSTRT
Ethernet Frame Offset Start
7
2
OFFSSTRTSelect
FRAMESTART
Offset from the start of the frame
0x0
ETHERTYPE
Offset from the byte after the EtherType field
0x1
IP
Offset from the byte after the IP header field
0x2
TCP_UDP
Offset from the byte after the TCP/UDP header field
0x3
GPBR
6378J
General Purpose Backup Registers
0x400E1890
0
0x20
registers
8
4
SYS_GPBR[%s]
General Purpose Backup Register 0
0x0
32
GPBR_VALUE
Value of GPBR x
0
32
HSMCI
6449R
High Speed MultiMedia Card Interface
0x40000000
0
0xB58
registers
HSMCI
18
CR
Control Register
0x00
32
write-only
MCIEN
Multi-Media Interface Enable
0
1
MCIDIS
Multi-Media Interface Disable
1
1
PWSEN
Power Save Mode Enable
2
1
PWSDIS
Power Save Mode Disable
3
1
SWRST
Software Reset
7
1
MR
Mode Register
0x04
32
CLKDIV
Clock Divider
0
8
PWSDIV
Power Saving Divider
8
3
RDPROOF
Read Proof Enable
11
1
WRPROOF
Write Proof Enable
12
1
FBYTE
Force Byte Transfer
13
1
PADV
Padding Value
14
1
CLKODD
Clock divider is odd
16
1
DTOR
Data Timeout Register
0x08
32
DTOCYC
Data Timeout Cycle Number
0
4
DTOMUL
Data Timeout Multiplier
4
3
DTOMULSelect
_1
DTOCYC
0x0
_16
DTOCYC x 16
0x1
_128
DTOCYC x 128
0x2
_256
DTOCYC x 256
0x3
_1024
DTOCYC x 1024
0x4
_4096
DTOCYC x 4096
0x5
_65536
DTOCYC x 65536
0x6
_1048576
DTOCYC x 1048576
0x7
SDCR
SD/SDIO Card Register
0x0C
32
SDCSEL
SDCard/SDIO Slot
0
2
SDCSELSelect
SLOTA
Slot A is selected.
0
SDCBUS
SDCard/SDIO Bus Width
6
2
SDCBUSSelect
_1
1 bit
0x0
_4
4 bits
0x2
_8
8 bits
0x3
ARGR
Argument Register
0x10
32
ARG
Command Argument
0
32
CMDR
Command Register
0x14
32
write-only
CMDNB
Command Number
0
6
RSPTYP
Response Type
6
2
RSPTYPSelect
NORESP
No response
0x0
_48_BIT
48-bit response
0x1
_136_BIT
136-bit response
0x2
R1B
R1b response type
0x3
SPCMD
Special Command
8
3
SPCMDSelect
STD
Not a special CMD.
0x0
INIT
Initialization CMD: 74 clock cycles for initialization sequence.
0x1
SYNC
Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.
0x2
CE_ATA
CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.
0x3
IT_CMD
Interrupt command: Corresponds to the Interrupt Mode (CMD40).
0x4
IT_RESP
Interrupt response: Corresponds to the Interrupt Mode (CMD40).
0x5
BOR
Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.
0x6
EBO
End Boot Operation. This command allows the host processor to terminate the boot operation mode.
0x7
OPDCMD
Open Drain Command
11
1
OPDCMDSelect
PUSHPULL
Push pull command.
0
OPENDRAIN
Open drain command.
1
MAXLAT
Max Latency for Command to Response
12
1
MAXLATSelect
_5
5-cycle max latency.
0
_64
64-cycle max latency.
1
TRCMD
Transfer Command
16
2
TRCMDSelect
NO_DATA
No data transfer
0x0
START_DATA
Start data transfer
0x1
STOP_DATA
Stop data transfer
0x2
TRDIR
Transfer Direction
18
1
TRDIRSelect
WRITE
Write.
0
READ
Read.
1
TRTYP
Transfer Type
19
3
TRTYPSelect
SINGLE
MMC/SD Card Single Block
0x0
MULTIPLE
MMC/SD Card Multiple Block
0x1
STREAM
MMC Stream
0x2
BYTE
SDIO Byte
0x4
BLOCK
SDIO Block
0x5
IOSPCMD
SDIO Special Command
24
2
IOSPCMDSelect
STD
Not an SDIO Special Command
0x0
SUSPEND
SDIO Suspend Command
0x1
RESUME
SDIO Resume Command
0x2
ATACS
ATA with Command Completion Signal
26
1
ATACSSelect
NORMAL
Normal operation mode.
0
COMPLETION
This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).
1
BOOT_ACK
Boot Operation Acknowledge
27
1
BLKR
Block Register
0x18
32
BCNT
MMC/SDIO Block Count - SDIO Byte Count
0
16
BLKLEN
Data Block Length
16
16
CSTOR
Completion Signal Timeout Register
0x1C
32
CSTOCYC
Completion Signal Timeout Cycle Number
0
4
CSTOMUL
Completion Signal Timeout Multiplier
4
3
CSTOMULSelect
_1
CSTOCYC x 1
0x0
_16
CSTOCYC x 16
0x1
_128
CSTOCYC x 128
0x2
_256
CSTOCYC x 256
0x3
_1024
CSTOCYC x 1024
0x4
_4096
CSTOCYC x 4096
0x5
_65536
CSTOCYC x 65536
0x6
_1048576
CSTOCYC x 1048576
0x7
4
4
RSPR[%s]
Response Register 0
0x20
32
read-only
RSP
Response
0
32
RDR
Receive Data Register
0x30
32
read-only
DATA
Data to Read
0
32
TDR
Transmit Data Register
0x34
32
write-only
DATA
Data to Write
0
32
SR
Status Register
0x40
32
read-only
CMDRDY
Command Ready (cleared by writing in HSMCI_CMDR)
0
1
RXRDY
Receiver Ready (cleared by reading HSMCI_RDR)
1
1
TXRDY
Transmit Ready (cleared by writing in HSMCI_TDR)
2
1
BLKE
Data Block Ended (cleared on read)
3
1
DTIP
Data Transfer in Progress (cleared at the end of CRC16 calculation)
4
1
NOTBUSY
HSMCI Not Busy
5
1
SDIOIRQA
SDIO Interrupt for Slot A (cleared on read)
8
1
SDIOWAIT
SDIO Read Wait Operation Status
12
1
CSRCV
CE-ATA Completion Signal Received (cleared on read)
13
1
RINDE
Response Index Error (cleared by writing in HSMCI_CMDR)
16
1
RDIRE
Response Direction Error (cleared by writing in HSMCI_CMDR)
17
1
RCRCE
Response CRC Error (cleared by writing in HSMCI_CMDR)
18
1
RENDE
Response End Bit Error (cleared by writing in HSMCI_CMDR)
19
1
RTOE
Response Time-out Error (cleared by writing in HSMCI_CMDR)
20
1
DCRCE
Data CRC Error (cleared on read)
21
1
DTOE
Data Time-out Error (cleared on read)
22
1
CSTOE
Completion Signal Time-out Error (cleared on read)
23
1
BLKOVRE
DMA Block Overrun Error (cleared on read)
24
1
FIFOEMPTY
FIFO empty flag
26
1
XFRDONE
Transfer Done flag
27
1
ACKRCV
Boot Operation Acknowledge Received (cleared on read)
28
1
ACKRCVE
Boot Operation Acknowledge Error (cleared on read)
29
1
OVRE
Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
30
1
UNRE
Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
31
1
IER
Interrupt Enable Register
0x44
32
write-only
CMDRDY
Command Ready Interrupt Enable
0
1
RXRDY
Receiver Ready Interrupt Enable
1
1
TXRDY
Transmit Ready Interrupt Enable
2
1
BLKE
Data Block Ended Interrupt Enable
3
1
DTIP
Data Transfer in Progress Interrupt Enable
4
1
NOTBUSY
Data Not Busy Interrupt Enable
5
1
SDIOIRQA
SDIO Interrupt for Slot A Interrupt Enable
8
1
SDIOWAIT
SDIO Read Wait Operation Status Interrupt Enable
12
1
CSRCV
Completion Signal Received Interrupt Enable
13
1
RINDE
Response Index Error Interrupt Enable
16
1
RDIRE
Response Direction Error Interrupt Enable
17
1
RCRCE
Response CRC Error Interrupt Enable
18
1
RENDE
Response End Bit Error Interrupt Enable
19
1
RTOE
Response Time-out Error Interrupt Enable
20
1
DCRCE
Data CRC Error Interrupt Enable
21
1
DTOE
Data Time-out Error Interrupt Enable
22
1
CSTOE
Completion Signal Timeout Error Interrupt Enable
23
1
BLKOVRE
DMA Block Overrun Error Interrupt Enable
24
1
FIFOEMPTY
FIFO empty Interrupt enable
26
1
XFRDONE
Transfer Done Interrupt enable
27
1
ACKRCV
Boot Acknowledge Interrupt Enable
28
1
ACKRCVE
Boot Acknowledge Error Interrupt Enable
29
1
OVRE
Overrun Interrupt Enable
30
1
UNRE
Underrun Interrupt Enable
31
1
IDR
Interrupt Disable Register
0x48
32
write-only
CMDRDY
Command Ready Interrupt Disable
0
1
RXRDY
Receiver Ready Interrupt Disable
1
1
TXRDY
Transmit Ready Interrupt Disable
2
1
BLKE
Data Block Ended Interrupt Disable
3
1
DTIP
Data Transfer in Progress Interrupt Disable
4
1
NOTBUSY
Data Not Busy Interrupt Disable
5
1
SDIOIRQA
SDIO Interrupt for Slot A Interrupt Disable
8
1
SDIOWAIT
SDIO Read Wait Operation Status Interrupt Disable
12
1
CSRCV
Completion Signal received interrupt Disable
13
1
RINDE
Response Index Error Interrupt Disable
16
1
RDIRE
Response Direction Error Interrupt Disable
17
1
RCRCE
Response CRC Error Interrupt Disable
18
1
RENDE
Response End Bit Error Interrupt Disable
19
1
RTOE
Response Time-out Error Interrupt Disable
20
1
DCRCE
Data CRC Error Interrupt Disable
21
1
DTOE
Data Time-out Error Interrupt Disable
22
1
CSTOE
Completion Signal Time out Error Interrupt Disable
23
1
BLKOVRE
DMA Block Overrun Error Interrupt Disable
24
1
FIFOEMPTY
FIFO empty Interrupt Disable
26
1
XFRDONE
Transfer Done Interrupt Disable
27
1
ACKRCV
Boot Acknowledge Interrupt Disable
28
1
ACKRCVE
Boot Acknowledge Error Interrupt Disable
29
1
OVRE
Overrun Interrupt Disable
30
1
UNRE
Underrun Interrupt Disable
31
1
IMR
Interrupt Mask Register
0x4C
32
read-only
CMDRDY
Command Ready Interrupt Mask
0
1
RXRDY
Receiver Ready Interrupt Mask
1
1
TXRDY
Transmit Ready Interrupt Mask
2
1
BLKE
Data Block Ended Interrupt Mask
3
1
DTIP
Data Transfer in Progress Interrupt Mask
4
1
NOTBUSY
Data Not Busy Interrupt Mask
5
1
SDIOIRQA
SDIO Interrupt for Slot A Interrupt Mask
8
1
SDIOWAIT
SDIO Read Wait Operation Status Interrupt Mask
12
1
CSRCV
Completion Signal Received Interrupt Mask
13
1
RINDE
Response Index Error Interrupt Mask
16
1
RDIRE
Response Direction Error Interrupt Mask
17
1
RCRCE
Response CRC Error Interrupt Mask
18
1
RENDE
Response End Bit Error Interrupt Mask
19
1
RTOE
Response Time-out Error Interrupt Mask
20
1
DCRCE
Data CRC Error Interrupt Mask
21
1
DTOE
Data Time-out Error Interrupt Mask
22
1
CSTOE
Completion Signal Time-out Error Interrupt Mask
23
1
BLKOVRE
DMA Block Overrun Error Interrupt Mask
24
1
FIFOEMPTY
FIFO Empty Interrupt Mask
26
1
XFRDONE
Transfer Done Interrupt Mask
27
1
ACKRCV
Boot Operation Acknowledge Received Interrupt Mask
28
1
ACKRCVE
Boot Operation Acknowledge Error Interrupt Mask
29
1
OVRE
Overrun Interrupt Mask
30
1
UNRE
Underrun Interrupt Mask
31
1
DMA
DMA Configuration Register
0x50
32
CHKSIZE
DMA Channel Read and Write Chunk Size
4
3
CHKSIZESelect
_1
1 data available
0x0
_2
2 data available
0x1
_4
4 data available
0x2
_8
8 data available
0x3
_16
16 data available
0x4
DMAEN
DMA Hardware Handshaking Enable
8
1
CFG
Configuration Register
0x54
32
FIFOMODE
HSMCI Internal FIFO control mode
0
1
FERRCTRL
Flow Error flag reset control mode
4
1
HSMODE
High Speed Mode
8
1
LSYNC
Synchronize on the last block
12
1
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protect Enable
0
1
WPKEY
Write Protect Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x4D4349
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
16
256
4
FIFO[%s]
FIFO Memory Aperture0 0
0x200
32
DATA
Data to Read or Data to Write
0
32
I2SC0
11241N
Inter-IC Sound Controller
I2SC
I2SC_
0x4008C000
0
0x28
registers
I2SC0
69
CR
Control Register
0x00
32
write-only
RXEN
Receiver Enable
0
1
RXDIS
Receiver Disable
1
1
CKEN
Clocks Enable
2
1
CKDIS
Clocks Disable
3
1
TXEN
Transmitter Enable
4
1
TXDIS
Transmitter Disable
5
1
SWRST
Software Reset
7
1
MR
Mode Register
0x04
32
MODE
Inter-IC Sound Controller Mode
0
1
MODESelect
SLAVE
I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization.
0
MASTER
Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set.
1
DATALENGTH
Data Word Length
2
3
DATALENGTHSelect
_32_BITS
Data length is set to 32 bits
0x0
_24_BITS
Data length is set to 24 bits
0x1
_20_BITS
Data length is set to 20 bits
0x2
_18_BITS
Data length is set to 18 bits
0x3
_16_BITS
Data length is set to 16 bits
0x4
_16_BITS_COMPACT
Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
0x5
_8_BITS
Data length is set to 8 bits
0x6
_8_BITS_COMPACT
Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.
0x7
RXMONO
Receive Mono
8
1
RXDMA
Single or Multiple DMA Controller Channels for Receiver
9
1
RXLOOP
Loopback Test Mode
10
1
TXMONO
Transmit Mono
12
1
TXDMA
Single or Multiple DMA Controller Channels for Transmitter
13
1
TXSAME
Transmit Data when Underrun
14
1
IMCKDIV
Selected Clock to I2SC Master Clock Ratio
16
6
IMCKFS
Master Clock to fs Ratio
24
6
IMCKFSSelect
M2SF32
Sample frequency ratio set to 32
0x0
M2SF64
Sample frequency ratio set to 64
0x1
M2SF96
Sample frequency ratio set to 96
0x2
M2SF128
Sample frequency ratio set to 128
0x3
M2SF192
Sample frequency ratio set to 192
0x5
M2SF256
Sample frequency ratio set to 256
0x7
M2SF384
Sample frequency ratio set to 384
0xB
M2SF512
Sample frequency ratio set to 512
0xF
M2SF768
Sample frequency ratio set to 768
0x17
M2SF1024
Sample frequency ratio set to 1024
0x1F
M2SF1536
Sample frequency ratio set to 1536
0x2F
M2SF2048
Sample frequency ratio set to 2048
0x3F
IMCKMODE
Master Clock Mode
30
1
IWS
I2SC_WS Slot Width
31
1
SR
Status Register
0x08
32
read-only
RXEN
Receiver Enabled
0
1
RXRDY
Receive Ready
1
1
RXOR
Receive Overrun
2
1
TXEN
Transmitter Enabled
4
1
TXRDY
Transmit Ready
5
1
TXUR
Transmit Underrun
6
1
RXORCH
Receive Overrun Channel
8
2
TXURCH
Transmit Underrun Channel
20
2
SCR
Status Clear Register
0x0C
32
write-only
RXOR
Receive Overrun Status Clear
2
1
TXUR
Transmit Underrun Status Clear
6
1
RXORCH
Receive Overrun Per Channel Status Clear
8
2
TXURCH
Transmit Underrun Per Channel Status Clear
20
2
SSR
Status Set Register
0x10
32
write-only
RXOR
Receive Overrun Status Set
2
1
TXUR
Transmit Underrun Status Set
6
1
RXORCH
Receive Overrun Per Channel Status Set
8
2
TXURCH
Transmit Underrun Per Channel Status Set
20
2
IER
Interrupt Enable Register
0x14
32
write-only
RXRDY
Receiver Ready Interrupt Enable
1
1
RXOR
Receiver Overrun Interrupt Enable
2
1
TXRDY
Transmit Ready Interrupt Enable
5
1
TXUR
Transmit Underflow Interrupt Enable
6
1
IDR
Interrupt Disable Register
0x18
32
write-only
RXRDY
Receiver Ready Interrupt Disable
1
1
RXOR
Receiver Overrun Interrupt Disable
2
1
TXRDY
Transmit Ready Interrupt Disable
5
1
TXUR
Transmit Underflow Interrupt Disable
6
1
IMR
Interrupt Mask Register
0x1C
32
read-only
RXRDY
Receiver Ready Interrupt Disable
1
1
RXOR
Receiver Overrun Interrupt Disable
2
1
TXRDY
Transmit Ready Interrupt Disable
5
1
TXUR
Transmit Underflow Interrupt Disable
6
1
RHR
Receiver Holding Register
0x20
32
read-only
RHR
Receiver Holding Register
0
32
THR
Transmitter Holding Register
0x24
32
write-only
THR
Transmitter Holding Register
0
32
ICM
11105H
Integrity Check Monitor
0x40048000
0
0x58
registers
ICM
32
CFG
Configuration Register
0x00
32
WBDIS
Write Back Disable
0
1
EOMDIS
End of Monitoring Disable
1
1
SLBDIS
Secondary List Branching Disable
2
1
BBC
Bus Burden Control
4
4
ASCD
Automatic Switch To Compare Digest
8
1
DUALBUFF
Dual Input Buffer
9
1
UIHASH
User Initial Hash Value
12
1
UALGO
User SHA Algorithm
13
3
UALGOSelect
SHA1
SHA1 algorithm processed
0x0
SHA256
SHA256 algorithm processed
0x1
SHA224
SHA224 algorithm processed
0x4
CTRL
Control Register
0x04
32
write-only
ENABLE
ICM Enable
0
1
DISABLE
ICM Disable Register
1
1
SWRST
Software Reset
2
1
REHASH
Recompute Internal Hash
4
4
RMDIS
Region Monitoring Disable
8
4
RMEN
Region Monitoring Enable
12
4
SR
Status Register
0x08
32
read-only
ENABLE
ICM Controller Enable Register
0
1
RAWRMDIS
Region Monitoring Disabled Raw Status
8
4
RMDIS
Region Monitoring Disabled Status
12
4
IER
Interrupt Enable Register
0x10
32
write-only
RHC
Region Hash Completed Interrupt Enable
0
4
RDM
Region Digest Mismatch Interrupt Enable
4
4
RBE
Region Bus Error Interrupt Enable
8
4
RWC
Region Wrap Condition detected Interrupt Enable
12
4
REC
Region End bit Condition Detected Interrupt Enable
16
4
RSU
Region Status Updated Interrupt Disable
20
4
URAD
Undefined Register Access Detection Interrupt Enable
24
1
IDR
Interrupt Disable Register
0x14
32
write-only
RHC
Region Hash Completed Interrupt Disable
0
4
RDM
Region Digest Mismatch Interrupt Disable
4
4
RBE
Region Bus Error Interrupt Disable
8
4
RWC
Region Wrap Condition Detected Interrupt Disable
12
4
REC
Region End bit Condition detected Interrupt Disable
16
4
RSU
Region Status Updated Interrupt Disable
20
4
URAD
Undefined Register Access Detection Interrupt Disable
24
1
IMR
Interrupt Mask Register
0x18
32
read-only
RHC
Region Hash Completed Interrupt Mask
0
4
RDM
Region Digest Mismatch Interrupt Mask
4
4
RBE
Region Bus Error Interrupt Mask
8
4
RWC
Region Wrap Condition Detected Interrupt Mask
12
4
REC
Region End bit Condition Detected Interrupt Mask
16
4
RSU
Region Status Updated Interrupt Mask
20
4
URAD
Undefined Register Access Detection Interrupt Mask
24
1
ISR
Interrupt Status Register
0x1C
32
read-only
RHC
Region Hash Completed
0
4
RDM
Region Digest Mismatch
4
4
RBE
Region Bus Error
8
4
RWC
Region Wrap Condition Detected
12
4
REC
Region End bit Condition Detected
16
4
RSU
Region Status Updated Detected
20
4
URAD
Undefined Register Access Detection Status
24
1
UASR
Undefined Access Status Register
0x20
32
read-only
URAT
Undefined Register Access Trace
0
3
URATSelect
UNSPEC_STRUCT_MEMBER
Unspecified structure member set to one detected when the descriptor is loaded.
0x0
ICM_CFG_MODIFIED
ICM_CFG modified during active monitoring.
0x1
ICM_DSCR_MODIFIED
ICM_DSCR modified during active monitoring.
0x2
ICM_HASH_MODIFIED
ICM_HASH modified during active monitoring
0x3
READ_ACCESS
Write-only register read access
0x4
DSCR
Region Descriptor Area Start Address Register
0x30
32
DASA
Descriptor Area Start Address
6
26
HASH
Region Hash Area Start Address Register
0x34
32
HASA
Hash Area Start Address
7
25
8
4
UIHVAL[%s]
User Initial Hash Value 0 Register 0
0x38
32
write-only
VAL
Initial Hash Value
0
32
ISI
6350K
Image Sensor Interface
0x4004C000
0
0xEC
registers
ISI
59
CFG1
ISI Configuration 1 Register
0x00
32
HSYNC_POL
Horizontal Synchronization Polarity
2
1
VSYNC_POL
Vertical Synchronization Polarity
3
1
PIXCLK_POL
Pixel Clock Polarity
4
1
GRAYLE
Grayscale Little Endian
5
1
EMB_SYNC
Embedded Synchronization
6
1
CRC_SYNC
Embedded Synchronization Correction
7
1
FRATE
Frame Rate [0..7]
8
3
DISCR
Disable Codec Request
11
1
FULL
Full Mode is Allowed
12
1
THMASK
Threshold Mask
13
2
THMASKSelect
BEATS_4
Only 4 beats AHB burst allowed
0x0
BEATS_8
Only 4 and 8 beats AHB burst allowed
0x1
BEATS_16
4, 8 and 16 beats AHB burst allowed
0x2
SLD
Start of Line Delay
16
8
SFD
Start of Frame Delay
24
8
CFG2
ISI Configuration 2 Register
0x04
32
IM_VSIZE
Vertical Size of the Image Sensor [0..2047]
0
11
GS_MODE
Grayscale Pixel Format Mode
11
1
RGB_MODE
RGB Input Mode
12
1
GRAYSCALE
Grayscale Mode Format Enable
13
1
RGB_SWAP
RGB Format Swap Mode
14
1
COL_SPACE
Color Space for the Image Data
15
1
IM_HSIZE
Horizontal Size of the Image Sensor [0..2047]
16
11
YCC_SWAP
YCrCb Format Swap Mode
28
2
YCC_SWAPSelect
DEFAULT
Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1)
0x0
MODE1
Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1)
0x1
MODE2
Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i)
0x2
MODE3
Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i)
0x3
RGB_CFG
RGB Pixel Mapping Configuration
30
2
RGB_CFGSelect
DEFAULT
Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B
0x0
MODE1
Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R
0x1
MODE2
Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB)
0x2
MODE3
Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB)
0x3
PSIZE
ISI Preview Size Register
0x08
32
PREV_VSIZE
Vertical Size for the Preview Path
0
10
PREV_HSIZE
Horizontal Size for the Preview Path
16
10
PDECF
ISI Preview Decimation Factor Register
0x0C
32
DEC_FACTOR
Decimation Factor
0
8
Y2R_SET0
ISI Color Space Conversion YCrCb To RGB Set 0 Register
0x10
32
C0
Color Space Conversion Matrix Coefficient C0
0
8
C1
Color Space Conversion Matrix Coefficient C1
8
8
C2
Color Space Conversion Matrix Coefficient C2
16
8
C3
Color Space Conversion Matrix Coefficient C3
24
8
Y2R_SET1
ISI Color Space Conversion YCrCb To RGB Set 1 Register
0x14
32
C4
Color Space Conversion Matrix Coefficient C4
0
9
Yoff
Color Space Conversion Luminance Default Offset
12
1
Croff
Color Space Conversion Red Chrominance Default Offset
13
1
Cboff
Color Space Conversion Blue Chrominance Default Offset
14
1
R2Y_SET0
ISI Color Space Conversion RGB To YCrCb Set 0 Register
0x18
32
C0
Color Space Conversion Matrix Coefficient C0
0
7
C1
Color Space Conversion Matrix Coefficient C1
8
7
C2
Color Space Conversion Matrix Coefficient C2
16
7
Roff
Color Space Conversion Red Component Offset
24
1
R2Y_SET1
ISI Color Space Conversion RGB To YCrCb Set 1 Register
0x1C
32
C3
Color Space Conversion Matrix Coefficient C3
0
7
C4
Color Space Conversion Matrix Coefficient C4
8
7
C5
Color Space Conversion Matrix Coefficient C5
16
7
Goff
Color Space Conversion Green Component Offset
24
1
R2Y_SET2
ISI Color Space Conversion RGB To YCrCb Set 2 Register
0x20
32
C6
Color Space Conversion Matrix Coefficient C6
0
7
C7
Color Space Conversion Matrix Coefficient C7
8
7
C8
Color Space Conversion Matrix Coefficient C8
16
7
Boff
Color Space Conversion Blue Component Offset
24
1
CR
ISI Control Register
0x24
32
write-only
ISI_EN
ISI Module Enable Request
0
1
ISI_DIS
ISI Module Disable Request
1
1
ISI_SRST
ISI Software Reset Request
2
1
ISI_CDC
ISI Codec Request
8
1
SR
ISI Status Register
0x28
32
read-only
ENABLE
Module Enable
0
1
DIS_DONE
Module Disable Request has Terminated (cleared on read)
1
1
SRST
Module Software Reset Request has Terminated (cleared on read)
2
1
CDC_PND
Pending Codec Request
8
1
VSYNC
Vertical Synchronization (cleared on read)
10
1
PXFR_DONE
Preview DMA Transfer has Terminated (cleared on read)
16
1
CXFR_DONE
Codec DMA Transfer has Terminated (cleared on read)
17
1
SIP
Synchronization in Progress
19
1
P_OVR
Preview Datapath Overflow (cleared on read)
24
1
C_OVR
Codec Datapath Overflow (cleared on read)
25
1
CRC_ERR
CRC Synchronization Error (cleared on read)
26
1
FR_OVR
Frame Rate Overrun (cleared on read)
27
1
IER
ISI Interrupt Enable Register
0x2C
32
write-only
DIS_DONE
Disable Done Interrupt Enable
1
1
SRST
Software Reset Interrupt Enable
2
1
VSYNC
Vertical Synchronization Interrupt Enable
10
1
PXFR_DONE
Preview DMA Transfer Done Interrupt Enable
16
1
CXFR_DONE
Codec DMA Transfer Done Interrupt Enable
17
1
P_OVR
Preview Datapath Overflow Interrupt Enable
24
1
C_OVR
Codec Datapath Overflow Interrupt Enable
25
1
CRC_ERR
Embedded Synchronization CRC Error Interrupt Enable
26
1
FR_OVR
Frame Rate Overflow Interrupt Enable
27
1
IDR
ISI Interrupt Disable Register
0x30
32
write-only
DIS_DONE
Disable Done Interrupt Disable
1
1
SRST
Software Reset Interrupt Disable
2
1
VSYNC
Vertical Synchronization Interrupt Disable
10
1
PXFR_DONE
Preview DMA Transfer Done Interrupt Disable
16
1
CXFR_DONE
Codec DMA Transfer Done Interrupt Disable
17
1
P_OVR
Preview Datapath Overflow Interrupt Disable
24
1
C_OVR
Codec Datapath Overflow Interrupt Disable
25
1
CRC_ERR
Embedded Synchronization CRC Error Interrupt Disable
26
1
FR_OVR
Frame Rate Overflow Interrupt Disable
27
1
IMR
ISI Interrupt Mask Register
0x34
32
read-only
DIS_DONE
Module Disable Operation Completed
1
1
SRST
Software Reset Completed
2
1
VSYNC
Vertical Synchronization
10
1
PXFR_DONE
Preview DMA Transfer Completed
16
1
CXFR_DONE
Codec DMA Transfer Completed
17
1
P_OVR
Preview FIFO Overflow
24
1
C_OVR
Codec FIFO Overflow
25
1
CRC_ERR
CRC Synchronization Error
26
1
FR_OVR
Frame Rate Overrun
27
1
DMA_CHER
DMA Channel Enable Register
0x38
32
write-only
P_CH_EN
Preview Channel Enable
0
1
C_CH_EN
Codec Channel Enable
1
1
DMA_CHDR
DMA Channel Disable Register
0x3C
32
write-only
P_CH_DIS
Preview Channel Disable Request
0
1
C_CH_DIS
Codec Channel Disable Request
1
1
DMA_CHSR
DMA Channel Status Register
0x40
32
read-only
P_CH_S
Preview DMA Channel Status
0
1
C_CH_S
Code DMA Channel Status
1
1
DMA_P_ADDR
DMA Preview Base Address Register
0x44
32
P_ADDR
Preview Image Base Address
2
30
DMA_P_CTRL
DMA Preview Control Register
0x48
32
P_FETCH
Descriptor Fetch Control Bit
0
1
P_WB
Descriptor Writeback Control Bit
1
1
P_IEN
Transfer Done Flag Control
2
1
P_DONE
Preview Transfer Done
3
1
DMA_P_DSCR
DMA Preview Descriptor Address Register
0x4C
32
P_DSCR
Preview Descriptor Base Address
2
30
DMA_C_ADDR
DMA Codec Base Address Register
0x50
32
C_ADDR
Codec Image Base Address
2
30
DMA_C_CTRL
DMA Codec Control Register
0x54
32
C_FETCH
Descriptor Fetch Control Bit
0
1
C_WB
Descriptor Writeback Control Bit
1
1
C_IEN
Transfer Done Flag Control
2
1
C_DONE
Codec Transfer Done
3
1
DMA_C_DSCR
DMA Codec Descriptor Address Register
0x58
32
C_DSCR
Codec Descriptor Base Address
2
30
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key Password
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x495349
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
16
MATRIX
11282L
AHB Bus Matrix
0x40088000
0
0x1EC
registers
13
4
MCFG[%s]
Master Configuration Register 0
0x0
32
ULBT
Undefined Length Burst Type
0
3
ULBTSelect
UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x0
SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x1
_4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x2
_8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x3
_16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x4
_32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x5
_64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x6
_128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
0x7
9
4
SCFG[%s]
Slave Configuration Register 0
0x40
32
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
DEFMSTR_TYPE
Default Master Type
16
2
DEFMSTR_TYPESelect
NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x0
LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x1
FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
0x2
FIXED_DEFMSTR
Fixed Default Master
18
4
9
8
MATRIX_PR[%s]
Priority Register A for Slave 0
0x0080
PRAS
Priority Register A for Slave 0
0x00
32
M0PR
Master 0 Priority
0
2
M1PR
Master 1 Priority
4
2
M2PR
Master 2 Priority
8
2
M3PR
Master 3 Priority
12
2
M4PR
Master 4 Priority
16
2
M5PR
Master 5 Priority
20
2
M6PR
Master 6 Priority
24
2
PRBS
Priority Register B for Slave 0
0x04
32
M8PR
Master 8 Priority
0
2
M9PR
Master 9 Priority
4
2
M10PR
Master 10 Priority
8
2
M11PR
Master 11 Priority
12
2
M12PR
Master 12 Priority
16
2
MRCR
Master Remap Control Register
0x0100
32
RCB0
Remap Command Bit for Master 0
0
1
RCB1
Remap Command Bit for Master 1
1
1
RCB2
Remap Command Bit for Master 2
2
1
RCB3
Remap Command Bit for Master 3
3
1
RCB4
Remap Command Bit for Master 4
4
1
RCB5
Remap Command Bit for Master 5
5
1
RCB6
Remap Command Bit for Master 6
6
1
RCB8
Remap Command Bit for Master 8
8
1
RCB9
Remap Command Bit for Master 9
9
1
RCB10
Remap Command Bit for Master 10
10
1
RCB11
Remap Command Bit for Master 11
11
1
RCB12
Remap Command Bit for Master 12
12
1
CCFG_CAN0
CAN0 Configuration Register
0x0110
32
CAN0DMABA
CAN0 DMA Base Address
16
16
CCFG_SYSIO
System I/O and CAN1 Configuration Register
0x0114
32
SYSIO4
PB4 or TDI Assignment
4
1
SYSIO5
PB5 or TDO/TRACESWO Assignment
5
1
SYSIO6
PB6 or TMS/SWDIO Assignment
6
1
SYSIO7
PB7 or TCK/SWCLK Assignment
7
1
SYSIO12
PB12 or ERASE Assignment
12
1
CAN1DMABA
CAN1 DMA Base Address
16
16
CCFG_PCCR
Peripheral Clock Configuration Register
0x0118
32
TC0CC
TC0 Clock Configuration
20
1
I2SC0CC
I2SC0 Clock Configuration
21
1
I2SC1CC
I2SC1 Clock Configuration
22
1
CCFG_DYNCKG
Dynamic Clock Gating Register
0x011C
32
MATCKG
MATRIX Dynamic Clock Gating
0
1
BRIDCKG
Bridge Dynamic Clock Gating Enable
1
1
EFCCKG
EFC Dynamic Clock Gating Enable
2
1
CCFG_SMCNFCS
SMC NAND Flash Chip Select Configuration Register
0x0124
32
SMC_NFCS0
SMC NAND Flash Chip Select 0 Assignment
0
1
SMC_NFCS1
SMC NAND Flash Chip Select 1 Assignment
1
1
SMC_NFCS2
SMC NAND Flash Chip Select 2 Assignment
2
1
SMC_NFCS3
SMC NAND Flash Chip Select 3 Assignment
3
1
WPMR
Write Protection Mode Register
0x01E4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x4D4154
WPSR
Write Protection Status Register
0x01E8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
16
MCAN0
11273N
Controller Area Network
MCAN
MCAN_
0x40030000
0
0xFC
registers
MCAN0_INT0
35
MCAN0_INT1
36
CREL
Core Release Register
0x00
32
read-only
DAY
Timestamp Day
0
8
MON
Timestamp Month
8
8
YEAR
Timestamp Year
16
4
SUBSTEP
Sub-step of Core Release
20
4
STEP
Step of Core Release
24
4
REL
Core Release
28
4
ENDN
Endian Register
0x04
32
read-only
ETV
Endianness Test Value
0
32
CUST
Customer Register
0x08
32
CSV
Customer-specific Value
0
32
DBTP
Data Bit Timing and Prescaler Register
0x0C
32
DSJW
Data (Re) Synchronization Jump Width
0
3
DTSEG2
Data Time Segment After Sample Point
4
4
DTSEG1
Data Time Segment Before Sample Point
8
5
DBRP
Data Bit Rate Prescaler
16
5
TDC
Transmitter Delay Compensation
23
1
TDCSelect
DISABLED
Transmitter Delay Compensation disabled.
0
ENABLED
Transmitter Delay Compensation enabled.
1
TEST
Test Register
0x10
32
LBCK
Loop Back Mode (read/write)
4
1
LBCKSelect
DISABLED
Reset value. Loop Back mode is disabled.
0
ENABLED
Loop Back mode is enabled (see Section 6.1.9).
1
TX
Control of Transmit Pin (read/write)
5
2
TXSelect
RESET
Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time.
0x0
SAMPLE_POINT_MONITORING
Sample Point can be monitored at pin CANTX.
0x1
DOMINANT
Dominant ('0') level at pin CANTX.
0x2
RECESSIVE
Recessive ('1') at pin CANTX.
0x3
RX
Receive Pin (read-only)
7
1
RWD
RAM Watchdog Register
0x14
32
WDC
Watchdog Configuration (read/write)
0
8
WDV
Watchdog Value (read-only)
8
8
CCCR
CC Control Register
0x18
32
INIT
Initialization (read/write)
0
1
INITSelect
DISABLED
Normal operation.
0
ENABLED
Initialization is started.
1
CCE
Configuration Change Enable (read/write, write protection)
1
1
CCESelect
PROTECTED
The processor has no write access to the protected configuration registers.
0
CONFIGURABLE
The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1').
1
ASM
Restricted Operation Mode (read/write, write protection against '1')
2
1
ASMSelect
NORMAL
Normal CAN operation.
0
RESTRICTED
Restricted Operation mode active.
1
CSA
Clock Stop Acknowledge (read-only)
3
1
CSR
Clock Stop Request (read/write)
4
1
CSRSelect
NO_CLOCK_STOP
No clock stop is requested.
0
CLOCK_STOP
Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle.
1
MON
Bus Monitoring Mode (read/write, write protection against '1')
5
1
MONSelect
DISABLED
Bus Monitoring mode is disabled.
0
ENABLED
Bus Monitoring mode is enabled.
1
DAR
Disable Automatic Retransmission (read/write, write protection)
6
1
DARSelect
AUTO_RETX
Automatic retransmission of messages not transmitted successfully enabled.
0
NO_AUTO_RETX
Automatic retransmission disabled.
1
TEST
Test Mode Enable (read/write, write protection against '1')
7
1
TESTSelect
DISABLED
Normal operation, MCAN_TEST register holds reset values.
0
ENABLED
Test mode, write access to MCAN_TEST register enabled.
1
FDOE
CAN FD Operation Enable (read/write, write protection)
8
1
FDOESelect
DISABLED
FD operation disabled.
0
ENABLED
FD operation enabled.
1
BRSE
Bit Rate Switching Enable (read/write, write protection)
9
1
BRSESelect
DISABLED
Bit rate switching for transmissions disabled.
0
ENABLED
Bit rate switching for transmissions enabled.
1
PXHD
Protocol Exception Event Handling (read/write, write protection)
12
1
EFBI
Edge Filtering during Bus Integration (read/write, write protection)
13
1
TXP
Transmit Pause (read/write, write protection)
14
1
NISO
Non-ISO Operation
15
1
NBTP
Nominal Bit Timing and Prescaler Register
0x1C
32
NTSEG2
Nominal Time Segment After Sample Point
0
7
NTSEG1
Nominal Time Segment Before Sample Point
8
8
NBRP
Nominal Bit Rate Prescaler
16
9
NSJW
Nominal (Re) Synchronization Jump Width
25
7
TSCC
Timestamp Counter Configuration Register
0x20
32
TSS
Timestamp Select
0
2
TSSSelect
ALWAYS_0
Timestamp counter value always 0x0000
0x0
TCP_INC
Timestamp counter value incremented according to TCP
0x1
EXT_TIMESTAMP
External timestamp counter value used
0x2
TCP
Timestamp Counter Prescaler
16
4
TSCV
Timestamp Counter Value Register
0x24
32
TSC
Timestamp Counter (cleared on write)
0
16
TOCC
Timeout Counter Configuration Register
0x28
32
ETOC
Enable Timeout Counter
0
1
ETOCSelect
NO_TIMEOUT
Timeout Counter disabled.
0
TOS_CONTROLLED
Timeout Counter enabled.
1
TOS
Timeout Select
1
2
TOSSelect
CONTINUOUS
Continuous operation
0x0
TX_EV_TIMEOUT
Timeout controlled by Tx Event FIFO
0x1
RX0_EV_TIMEOUT
Timeout controlled by Receive FIFO 0
0x2
RX1_EV_TIMEOUT
Timeout controlled by Receive FIFO 1
0x3
TOP
Timeout Period
16
16
TOCV
Timeout Counter Value Register
0x2C
32
TOC
Timeout Counter (cleared on write)
0
16
ECR
Error Counter Register
0x40
32
read-only
TEC
Transmit Error Counter
0
8
REC
Receive Error Counter
8
7
RP
Receive Error Passive
15
1
CEL
CAN Error Logging (cleared on read)
16
8
PSR
Protocol Status Register
0x44
32
read-only
LEC
Last Error Code (set to 111 on read)
0
3
LECSelect
NO_ERROR
No error occurred since LEC has been reset by successful reception or transmission.
0x0
STUFF_ERROR
More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x1
FORM_ERROR
A fixed format part of a received frame has the wrong format.
0x2
ACK_ERROR
The message transmitted by the MCAN was not acknowledged by another node.
0x3
BIT1_ERROR
During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
0x4
BIT0_ERROR
During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x5
CRC_ERROR
The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data.
0x6
NO_CHANGE
Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register.
0x7
ACT
Activity
3
2
ACTSelect
SYNCHRONIZING
Node is synchronizing on CAN communication
0x0
IDLE
Node is neither receiver nor transmitter
0x1
RECEIVER
Node is operating as receiver
0x2
TRANSMITTER
Node is operating as transmitter
0x3
EP
Error Passive
5
1
EW
Warning Status
6
1
BO
Bus_Off Status
7
1
DLEC
Data Phase Last Error Code (set to 111 on read)
8
3
RESI
ESI Flag of Last Received CAN FD Message (cleared on read)
11
1
RBRS
BRS Flag of Last Received CAN FD Message (cleared on read)
12
1
RFDF
Received a CAN FD Message (cleared on read)
13
1
PXE
Protocol Exception Event (cleared on read)
14
1
TDCV
Transmitter Delay Compensation Value
16
7
TDCR
Transmit Delay Compensation Register
0x48
32
TDCF
Transmitter Delay Compensation Filter
0
7
TDCO
Transmitter Delay Compensation Offset
8
7
IR
Interrupt Register
0x50
32
RF0N
Receive FIFO 0 New Message
0
1
RF0W
Receive FIFO 0 Watermark Reached
1
1
RF0F
Receive FIFO 0 Full
2
1
RF0L
Receive FIFO 0 Message Lost
3
1
RF1N
Receive FIFO 1 New Message
4
1
RF1W
Receive FIFO 1 Watermark Reached
5
1
RF1F
Receive FIFO 1 Full
6
1
RF1L
Receive FIFO 1 Message Lost
7
1
HPM
High Priority Message
8
1
TC
Transmission Completed
9
1
TCF
Transmission Cancellation Finished
10
1
TFE
Tx FIFO Empty
11
1
TEFN
Tx Event FIFO New Entry
12
1
TEFW
Tx Event FIFO Watermark Reached
13
1
TEFF
Tx Event FIFO Full
14
1
TEFL
Tx Event FIFO Element Lost
15
1
TSW
Timestamp Wraparound
16
1
MRAF
Message RAM Access Failure
17
1
TOO
Timeout Occurred
18
1
DRX
Message stored to Dedicated Receive Buffer
19
1
ELO
Error Logging Overflow
22
1
EP
Error Passive
23
1
EW
Warning Status
24
1
BO
Bus_Off Status
25
1
WDI
Watchdog Interrupt
26
1
PEA
Protocol Error in Arbitration Phase
27
1
PED
Protocol Error in Data Phase
28
1
ARA
Access to Reserved Address
29
1
IE
Interrupt Enable Register
0x54
32
RF0NE
Receive FIFO 0 New Message Interrupt Enable
0
1
RF0WE
Receive FIFO 0 Watermark Reached Interrupt Enable
1
1
RF0FE
Receive FIFO 0 Full Interrupt Enable
2
1
RF0LE
Receive FIFO 0 Message Lost Interrupt Enable
3
1
RF1NE
Receive FIFO 1 New Message Interrupt Enable
4
1
RF1WE
Receive FIFO 1 Watermark Reached Interrupt Enable
5
1
RF1FE
Receive FIFO 1 Full Interrupt Enable
6
1
RF1LE
Receive FIFO 1 Message Lost Interrupt Enable
7
1
HPME
High Priority Message Interrupt Enable
8
1
TCE
Transmission Completed Interrupt Enable
9
1
TCFE
Transmission Cancellation Finished Interrupt Enable
10
1
TFEE
Tx FIFO Empty Interrupt Enable
11
1
TEFNE
Tx Event FIFO New Entry Interrupt Enable
12
1
TEFWE
Tx Event FIFO Watermark Reached Interrupt Enable
13
1
TEFFE
Tx Event FIFO Full Interrupt Enable
14
1
TEFLE
Tx Event FIFO Event Lost Interrupt Enable
15
1
TSWE
Timestamp Wraparound Interrupt Enable
16
1
MRAFE
Message RAM Access Failure Interrupt Enable
17
1
TOOE
Timeout Occurred Interrupt Enable
18
1
DRXE
Message stored to Dedicated Receive Buffer Interrupt Enable
19
1
ELOE
Error Logging Overflow Interrupt Enable
22
1
EPE
Error Passive Interrupt Enable
23
1
EWE
Warning Status Interrupt Enable
24
1
BOE
Bus_Off Status Interrupt Enable
25
1
WDIE
Watchdog Interrupt Enable
26
1
PEAE
Protocol Error in Arbitration Phase Enable
27
1
PEDE
Protocol Error in Data Phase Enable
28
1
ARAE
Access to Reserved Address Enable
29
1
ILS
Interrupt Line Select Register
0x58
32
RF0NL
Receive FIFO 0 New Message Interrupt Line
0
1
RF0WL
Receive FIFO 0 Watermark Reached Interrupt Line
1
1
RF0FL
Receive FIFO 0 Full Interrupt Line
2
1
RF0LL
Receive FIFO 0 Message Lost Interrupt Line
3
1
RF1NL
Receive FIFO 1 New Message Interrupt Line
4
1
RF1WL
Receive FIFO 1 Watermark Reached Interrupt Line
5
1
RF1FL
Receive FIFO 1 Full Interrupt Line
6
1
RF1LL
Receive FIFO 1 Message Lost Interrupt Line
7
1
HPML
High Priority Message Interrupt Line
8
1
TCL
Transmission Completed Interrupt Line
9
1
TCFL
Transmission Cancellation Finished Interrupt Line
10
1
TFEL
Tx FIFO Empty Interrupt Line
11
1
TEFNL
Tx Event FIFO New Entry Interrupt Line
12
1
TEFWL
Tx Event FIFO Watermark Reached Interrupt Line
13
1
TEFFL
Tx Event FIFO Full Interrupt Line
14
1
TEFLL
Tx Event FIFO Event Lost Interrupt Line
15
1
TSWL
Timestamp Wraparound Interrupt Line
16
1
MRAFL
Message RAM Access Failure Interrupt Line
17
1
TOOL
Timeout Occurred Interrupt Line
18
1
DRXL
Message stored to Dedicated Receive Buffer Interrupt Line
19
1
ELOL
Error Logging Overflow Interrupt Line
22
1
EPL
Error Passive Interrupt Line
23
1
EWL
Warning Status Interrupt Line
24
1
BOL
Bus_Off Status Interrupt Line
25
1
WDIL
Watchdog Interrupt Line
26
1
PEAL
Protocol Error in Arbitration Phase Line
27
1
PEDL
Protocol Error in Data Phase Line
28
1
ARAL
Access to Reserved Address Line
29
1
ILE
Interrupt Line Enable Register
0x5C
32
EINT0
Enable Interrupt Line 0
0
1
EINT1
Enable Interrupt Line 1
1
1
GFC
Global Filter Configuration Register
0x80
32
RRFE
Reject Remote Frames Extended
0
1
RRFESelect
FILTER
Filter remote frames with 29-bit extended IDs.
0
REJECT
Reject all remote frames with 29-bit extended IDs.
1
RRFS
Reject Remote Frames Standard
1
1
RRFSSelect
FILTER
Filter remote frames with 11-bit standard IDs.
0
REJECT
Reject all remote frames with 11-bit standard IDs.
1
ANFE
Accept Non-matching Frames Extended
2
2
ANFESelect
RX_FIFO_0
Accept in Rx FIFO 0
0
RX_FIFO_1
Accept in Rx FIFO 1
1
ANFS
Accept Non-matching Frames Standard
4
2
ANFSSelect
RX_FIFO_0
Accept in Rx FIFO 0
0
RX_FIFO_1
Accept in Rx FIFO 1
1
SIDFC
Standard ID Filter Configuration Register
0x84
32
FLSSA
Filter List Standard Start Address
2
14
LSS
List Size Standard
16
8
XIDFC
Extended ID Filter Configuration Register
0x88
32
FLESA
Filter List Extended Start Address
2
14
LSE
List Size Extended
16
7
XIDAM
Extended ID AND Mask Register
0x90
32
EIDM
Extended ID Mask
0
29
HPMS
High Priority Message Status Register
0x94
32
read-only
BIDX
Buffer Index
0
6
MSI
Message Storage Indicator
6
2
MSISelect
NO_FIFO_SEL
No FIFO selected.
0x0
LOST
FIFO message lost.
0x1
FIFO_0
Message stored in FIFO 0.
0x2
FIFO_1
Message stored in FIFO 1.
0x3
FIDX
Filter Index
8
7
FLST
Filter List
15
1
NDAT1
New Data 1 Register
0x98
32
ND0
New Data
0
1
ND1
New Data
1
1
ND2
New Data
2
1
ND3
New Data
3
1
ND4
New Data
4
1
ND5
New Data
5
1
ND6
New Data
6
1
ND7
New Data
7
1
ND8
New Data
8
1
ND9
New Data
9
1
ND10
New Data
10
1
ND11
New Data
11
1
ND12
New Data
12
1
ND13
New Data
13
1
ND14
New Data
14
1
ND15
New Data
15
1
ND16
New Data
16
1
ND17
New Data
17
1
ND18
New Data
18
1
ND19
New Data
19
1
ND20
New Data
20
1
ND21
New Data
21
1
ND22
New Data
22
1
ND23
New Data
23
1
ND24
New Data
24
1
ND25
New Data
25
1
ND26
New Data
26
1
ND27
New Data
27
1
ND28
New Data
28
1
ND29
New Data
29
1
ND30
New Data
30
1
ND31
New Data
31
1
NDAT2
New Data 2 Register
0x9C
32
ND32
New Data
0
1
ND33
New Data
1
1
ND34
New Data
2
1
ND35
New Data
3
1
ND36
New Data
4
1
ND37
New Data
5
1
ND38
New Data
6
1
ND39
New Data
7
1
ND40
New Data
8
1
ND41
New Data
9
1
ND42
New Data
10
1
ND43
New Data
11
1
ND44
New Data
12
1
ND45
New Data
13
1
ND46
New Data
14
1
ND47
New Data
15
1
ND48
New Data
16
1
ND49
New Data
17
1
ND50
New Data
18
1
ND51
New Data
19
1
ND52
New Data
20
1
ND53
New Data
21
1
ND54
New Data
22
1
ND55
New Data
23
1
ND56
New Data
24
1
ND57
New Data
25
1
ND58
New Data
26
1
ND59
New Data
27
1
ND60
New Data
28
1
ND61
New Data
29
1
ND62
New Data
30
1
ND63
New Data
31
1
RXF0C
Receive FIFO 0 Configuration Register
0xA0
32
F0SA
Receive FIFO 0 Start Address
2
14
F0S
Receive FIFO 0 Start Address
16
7
F0WM
Receive FIFO 0 Watermark
24
7
F0OM
FIFO 0 Operation Mode
31
1
RXF0S
Receive FIFO 0 Status Register
0xA4
32
read-only
F0FL
Receive FIFO 0 Fill Level
0
7
F0GI
Receive FIFO 0 Get Index
8
6
F0PI
Receive FIFO 0 Put Index
16
6
F0F
Receive FIFO 0 Fill Level
24
1
RF0L
Receive FIFO 0 Message Lost
25
1
RXF0A
Receive FIFO 0 Acknowledge Register
0xA8
32
F0AI
Receive FIFO 0 Acknowledge Index
0
6
RXBC
Receive Rx Buffer Configuration Register
0xAC
32
RBSA
Receive Buffer Start Address
2
14
RXF1C
Receive FIFO 1 Configuration Register
0xB0
32
F1SA
Receive FIFO 1 Start Address
2
14
F1S
Receive FIFO 1 Start Address
16
7
F1WM
Receive FIFO 1 Watermark
24
7
F1OM
FIFO 1 Operation Mode
31
1
RXF1S
Receive FIFO 1 Status Register
0xB4
32
read-only
F1FL
Receive FIFO 1 Fill Level
0
7
F1GI
Receive FIFO 1 Get Index
8
6
F1PI
Receive FIFO 1 Put Index
16
6
F1F
Receive FIFO 1 Fill Level
24
1
RF1L
Receive FIFO 1 Message Lost
25
1
DMS
Debug Message Status
30
2
DMSSelect
IDLE
Idle state, wait for reception of debug messages, DMA request is cleared.
0x0
MSG_A
Debug message A received.
0x1
MSG_AB
Debug messages A, B received.
0x2
MSG_ABC
Debug messages A, B, C received, DMA request is set.
0x3
RXF1A
Receive FIFO 1 Acknowledge Register
0xB8
32
F1AI
Receive FIFO 1 Acknowledge Index
0
6
RXESC
Receive Buffer / FIFO Element Size Configuration Register
0xBC
32
F0DS
Receive FIFO 0 Data Field Size
0
3
F0DSSelect
_8_BYTE
8-byte data field
0x0
_12_BYTE
12-byte data field
0x1
_16_BYTE
16-byte data field
0x2
_20_BYTE
20-byte data field
0x3
_24_BYTE
24-byte data field
0x4
_32_BYTE
32-byte data field
0x5
_48_BYTE
48-byte data field
0x6
_64_BYTE
64-byte data field
0x7
F1DS
Receive FIFO 1 Data Field Size
4
3
F1DSSelect
_8_BYTE
8-byte data field
0x0
_12_BYTE
12-byte data field
0x1
_16_BYTE
16-byte data field
0x2
_20_BYTE
20-byte data field
0x3
_24_BYTE
24-byte data field
0x4
_32_BYTE
32-byte data field
0x5
_48_BYTE
48-byte data field
0x6
_64_BYTE
64-byte data field
0x7
RBDS
Receive Buffer Data Field Size
8
3
RBDSSelect
_8_BYTE
8-byte data field
0x0
_12_BYTE
12-byte data field
0x1
_16_BYTE
16-byte data field
0x2
_20_BYTE
20-byte data field
0x3
_24_BYTE
24-byte data field
0x4
_32_BYTE
32-byte data field
0x5
_48_BYTE
48-byte data field
0x6
_64_BYTE
64-byte data field
0x7
TXBC
Transmit Buffer Configuration Register
0xC0
32
TBSA
Tx Buffers Start Address
2
14
NDTB
Number of Dedicated Transmit Buffers
16
6
TFQS
Transmit FIFO/Queue Size
24
6
TFQM
Tx FIFO/Queue Mode
30
1
TXFQS
Transmit FIFO/Queue Status Register
0xC4
32
read-only
TFFL
Tx FIFO Free Level
0
6
TFGI
Tx FIFO Get Index
8
5
TFQPI
Tx FIFO/Queue Put Index
16
5
TFQF
Tx FIFO/Queue Full
21
1
TXESC
Transmit Buffer Element Size Configuration Register
0xC8
32
TBDS
Tx Buffer Data Field Size
0
3
TBDSSelect
_8_BYTE
8-byte data field
0x0
_12_BYTE
12-byte data field
0x1
_16_BYTE
16-byte data field
0x2
_20_BYTE
20-byte data field
0x3
_24_BYTE
24-byte data field
0x4
_32_BYTE
32-byte data field
0x5
_48_BYTE
48-byte data field
0x6
_64_BYTE
64-byte data field
0x7
TXBRP
Transmit Buffer Request Pending Register
0xCC
32
read-only
TRP0
Transmission Request Pending for Buffer 0
0
1
TRP1
Transmission Request Pending for Buffer 1
1
1
TRP2
Transmission Request Pending for Buffer 2
2
1
TRP3
Transmission Request Pending for Buffer 3
3
1
TRP4
Transmission Request Pending for Buffer 4
4
1
TRP5
Transmission Request Pending for Buffer 5
5
1
TRP6
Transmission Request Pending for Buffer 6
6
1
TRP7
Transmission Request Pending for Buffer 7
7
1
TRP8
Transmission Request Pending for Buffer 8
8
1
TRP9
Transmission Request Pending for Buffer 9
9
1
TRP10
Transmission Request Pending for Buffer 10
10
1
TRP11
Transmission Request Pending for Buffer 11
11
1
TRP12
Transmission Request Pending for Buffer 12
12
1
TRP13
Transmission Request Pending for Buffer 13
13
1
TRP14
Transmission Request Pending for Buffer 14
14
1
TRP15
Transmission Request Pending for Buffer 15
15
1
TRP16
Transmission Request Pending for Buffer 16
16
1
TRP17
Transmission Request Pending for Buffer 17
17
1
TRP18
Transmission Request Pending for Buffer 18
18
1
TRP19
Transmission Request Pending for Buffer 19
19
1
TRP20
Transmission Request Pending for Buffer 20
20
1
TRP21
Transmission Request Pending for Buffer 21
21
1
TRP22
Transmission Request Pending for Buffer 22
22
1
TRP23
Transmission Request Pending for Buffer 23
23
1
TRP24
Transmission Request Pending for Buffer 24
24
1
TRP25
Transmission Request Pending for Buffer 25
25
1
TRP26
Transmission Request Pending for Buffer 26
26
1
TRP27
Transmission Request Pending for Buffer 27
27
1
TRP28
Transmission Request Pending for Buffer 28
28
1
TRP29
Transmission Request Pending for Buffer 29
29
1
TRP30
Transmission Request Pending for Buffer 30
30
1
TRP31
Transmission Request Pending for Buffer 31
31
1
TXBAR
Transmit Buffer Add Request Register
0xD0
32
AR0
Add Request for Transmit Buffer 0
0
1
AR1
Add Request for Transmit Buffer 1
1
1
AR2
Add Request for Transmit Buffer 2
2
1
AR3
Add Request for Transmit Buffer 3
3
1
AR4
Add Request for Transmit Buffer 4
4
1
AR5
Add Request for Transmit Buffer 5
5
1
AR6
Add Request for Transmit Buffer 6
6
1
AR7
Add Request for Transmit Buffer 7
7
1
AR8
Add Request for Transmit Buffer 8
8
1
AR9
Add Request for Transmit Buffer 9
9
1
AR10
Add Request for Transmit Buffer 10
10
1
AR11
Add Request for Transmit Buffer 11
11
1
AR12
Add Request for Transmit Buffer 12
12
1
AR13
Add Request for Transmit Buffer 13
13
1
AR14
Add Request for Transmit Buffer 14
14
1
AR15
Add Request for Transmit Buffer 15
15
1
AR16
Add Request for Transmit Buffer 16
16
1
AR17
Add Request for Transmit Buffer 17
17
1
AR18
Add Request for Transmit Buffer 18
18
1
AR19
Add Request for Transmit Buffer 19
19
1
AR20
Add Request for Transmit Buffer 20
20
1
AR21
Add Request for Transmit Buffer 21
21
1
AR22
Add Request for Transmit Buffer 22
22
1
AR23
Add Request for Transmit Buffer 23
23
1
AR24
Add Request for Transmit Buffer 24
24
1
AR25
Add Request for Transmit Buffer 25
25
1
AR26
Add Request for Transmit Buffer 26
26
1
AR27
Add Request for Transmit Buffer 27
27
1
AR28
Add Request for Transmit Buffer 28
28
1
AR29
Add Request for Transmit Buffer 29
29
1
AR30
Add Request for Transmit Buffer 30
30
1
AR31
Add Request for Transmit Buffer 31
31
1
TXBCR
Transmit Buffer Cancellation Request Register
0xD4
32
CR0
Cancellation Request for Transmit Buffer 0
0
1
CR1
Cancellation Request for Transmit Buffer 1
1
1
CR2
Cancellation Request for Transmit Buffer 2
2
1
CR3
Cancellation Request for Transmit Buffer 3
3
1
CR4
Cancellation Request for Transmit Buffer 4
4
1
CR5
Cancellation Request for Transmit Buffer 5
5
1
CR6
Cancellation Request for Transmit Buffer 6
6
1
CR7
Cancellation Request for Transmit Buffer 7
7
1
CR8
Cancellation Request for Transmit Buffer 8
8
1
CR9
Cancellation Request for Transmit Buffer 9
9
1
CR10
Cancellation Request for Transmit Buffer 10
10
1
CR11
Cancellation Request for Transmit Buffer 11
11
1
CR12
Cancellation Request for Transmit Buffer 12
12
1
CR13
Cancellation Request for Transmit Buffer 13
13
1
CR14
Cancellation Request for Transmit Buffer 14
14
1
CR15
Cancellation Request for Transmit Buffer 15
15
1
CR16
Cancellation Request for Transmit Buffer 16
16
1
CR17
Cancellation Request for Transmit Buffer 17
17
1
CR18
Cancellation Request for Transmit Buffer 18
18
1
CR19
Cancellation Request for Transmit Buffer 19
19
1
CR20
Cancellation Request for Transmit Buffer 20
20
1
CR21
Cancellation Request for Transmit Buffer 21
21
1
CR22
Cancellation Request for Transmit Buffer 22
22
1
CR23
Cancellation Request for Transmit Buffer 23
23
1
CR24
Cancellation Request for Transmit Buffer 24
24
1
CR25
Cancellation Request for Transmit Buffer 25
25
1
CR26
Cancellation Request for Transmit Buffer 26
26
1
CR27
Cancellation Request for Transmit Buffer 27
27
1
CR28
Cancellation Request for Transmit Buffer 28
28
1
CR29
Cancellation Request for Transmit Buffer 29
29
1
CR30
Cancellation Request for Transmit Buffer 30
30
1
CR31
Cancellation Request for Transmit Buffer 31
31
1
TXBTO
Transmit Buffer Transmission Occurred Register
0xD8
32
read-only
TO0
Transmission Occurred for Buffer 0
0
1
TO1
Transmission Occurred for Buffer 1
1
1
TO2
Transmission Occurred for Buffer 2
2
1
TO3
Transmission Occurred for Buffer 3
3
1
TO4
Transmission Occurred for Buffer 4
4
1
TO5
Transmission Occurred for Buffer 5
5
1
TO6
Transmission Occurred for Buffer 6
6
1
TO7
Transmission Occurred for Buffer 7
7
1
TO8
Transmission Occurred for Buffer 8
8
1
TO9
Transmission Occurred for Buffer 9
9
1
TO10
Transmission Occurred for Buffer 10
10
1
TO11
Transmission Occurred for Buffer 11
11
1
TO12
Transmission Occurred for Buffer 12
12
1
TO13
Transmission Occurred for Buffer 13
13
1
TO14
Transmission Occurred for Buffer 14
14
1
TO15
Transmission Occurred for Buffer 15
15
1
TO16
Transmission Occurred for Buffer 16
16
1
TO17
Transmission Occurred for Buffer 17
17
1
TO18
Transmission Occurred for Buffer 18
18
1
TO19
Transmission Occurred for Buffer 19
19
1
TO20
Transmission Occurred for Buffer 20
20
1
TO21
Transmission Occurred for Buffer 21
21
1
TO22
Transmission Occurred for Buffer 22
22
1
TO23
Transmission Occurred for Buffer 23
23
1
TO24
Transmission Occurred for Buffer 24
24
1
TO25
Transmission Occurred for Buffer 25
25
1
TO26
Transmission Occurred for Buffer 26
26
1
TO27
Transmission Occurred for Buffer 27
27
1
TO28
Transmission Occurred for Buffer 28
28
1
TO29
Transmission Occurred for Buffer 29
29
1
TO30
Transmission Occurred for Buffer 30
30
1
TO31
Transmission Occurred for Buffer 31
31
1
TXBCF
Transmit Buffer Cancellation Finished Register
0xDC
32
read-only
CF0
Cancellation Finished for Transmit Buffer 0
0
1
CF1
Cancellation Finished for Transmit Buffer 1
1
1
CF2
Cancellation Finished for Transmit Buffer 2
2
1
CF3
Cancellation Finished for Transmit Buffer 3
3
1
CF4
Cancellation Finished for Transmit Buffer 4
4
1
CF5
Cancellation Finished for Transmit Buffer 5
5
1
CF6
Cancellation Finished for Transmit Buffer 6
6
1
CF7
Cancellation Finished for Transmit Buffer 7
7
1
CF8
Cancellation Finished for Transmit Buffer 8
8
1
CF9
Cancellation Finished for Transmit Buffer 9
9
1
CF10
Cancellation Finished for Transmit Buffer 10
10
1
CF11
Cancellation Finished for Transmit Buffer 11
11
1
CF12
Cancellation Finished for Transmit Buffer 12
12
1
CF13
Cancellation Finished for Transmit Buffer 13
13
1
CF14
Cancellation Finished for Transmit Buffer 14
14
1
CF15
Cancellation Finished for Transmit Buffer 15
15
1
CF16
Cancellation Finished for Transmit Buffer 16
16
1
CF17
Cancellation Finished for Transmit Buffer 17
17
1
CF18
Cancellation Finished for Transmit Buffer 18
18
1
CF19
Cancellation Finished for Transmit Buffer 19
19
1
CF20
Cancellation Finished for Transmit Buffer 20
20
1
CF21
Cancellation Finished for Transmit Buffer 21
21
1
CF22
Cancellation Finished for Transmit Buffer 22
22
1
CF23
Cancellation Finished for Transmit Buffer 23
23
1
CF24
Cancellation Finished for Transmit Buffer 24
24
1
CF25
Cancellation Finished for Transmit Buffer 25
25
1
CF26
Cancellation Finished for Transmit Buffer 26
26
1
CF27
Cancellation Finished for Transmit Buffer 27
27
1
CF28
Cancellation Finished for Transmit Buffer 28
28
1
CF29
Cancellation Finished for Transmit Buffer 29
29
1
CF30
Cancellation Finished for Transmit Buffer 30
30
1
CF31
Cancellation Finished for Transmit Buffer 31
31
1
TXBTIE
Transmit Buffer Transmission Interrupt Enable Register
0xE0
32
TIE0
Transmission Interrupt Enable for Buffer 0
0
1
TIE1
Transmission Interrupt Enable for Buffer 1
1
1
TIE2
Transmission Interrupt Enable for Buffer 2
2
1
TIE3
Transmission Interrupt Enable for Buffer 3
3
1
TIE4
Transmission Interrupt Enable for Buffer 4
4
1
TIE5
Transmission Interrupt Enable for Buffer 5
5
1
TIE6
Transmission Interrupt Enable for Buffer 6
6
1
TIE7
Transmission Interrupt Enable for Buffer 7
7
1
TIE8
Transmission Interrupt Enable for Buffer 8
8
1
TIE9
Transmission Interrupt Enable for Buffer 9
9
1
TIE10
Transmission Interrupt Enable for Buffer 10
10
1
TIE11
Transmission Interrupt Enable for Buffer 11
11
1
TIE12
Transmission Interrupt Enable for Buffer 12
12
1
TIE13
Transmission Interrupt Enable for Buffer 13
13
1
TIE14
Transmission Interrupt Enable for Buffer 14
14
1
TIE15
Transmission Interrupt Enable for Buffer 15
15
1
TIE16
Transmission Interrupt Enable for Buffer 16
16
1
TIE17
Transmission Interrupt Enable for Buffer 17
17
1
TIE18
Transmission Interrupt Enable for Buffer 18
18
1
TIE19
Transmission Interrupt Enable for Buffer 19
19
1
TIE20
Transmission Interrupt Enable for Buffer 20
20
1
TIE21
Transmission Interrupt Enable for Buffer 21
21
1
TIE22
Transmission Interrupt Enable for Buffer 22
22
1
TIE23
Transmission Interrupt Enable for Buffer 23
23
1
TIE24
Transmission Interrupt Enable for Buffer 24
24
1
TIE25
Transmission Interrupt Enable for Buffer 25
25
1
TIE26
Transmission Interrupt Enable for Buffer 26
26
1
TIE27
Transmission Interrupt Enable for Buffer 27
27
1
TIE28
Transmission Interrupt Enable for Buffer 28
28
1
TIE29
Transmission Interrupt Enable for Buffer 29
29
1
TIE30
Transmission Interrupt Enable for Buffer 30
30
1
TIE31
Transmission Interrupt Enable for Buffer 31
31
1
TXBCIE
Transmit Buffer Cancellation Finished Interrupt Enable Register
0xE4
32
CFIE0
Cancellation Finished Interrupt Enable for Transmit Buffer 0
0
1
CFIE1
Cancellation Finished Interrupt Enable for Transmit Buffer 1
1
1
CFIE2
Cancellation Finished Interrupt Enable for Transmit Buffer 2
2
1
CFIE3
Cancellation Finished Interrupt Enable for Transmit Buffer 3
3
1
CFIE4
Cancellation Finished Interrupt Enable for Transmit Buffer 4
4
1
CFIE5
Cancellation Finished Interrupt Enable for Transmit Buffer 5
5
1
CFIE6
Cancellation Finished Interrupt Enable for Transmit Buffer 6
6
1
CFIE7
Cancellation Finished Interrupt Enable for Transmit Buffer 7
7
1
CFIE8
Cancellation Finished Interrupt Enable for Transmit Buffer 8
8
1
CFIE9
Cancellation Finished Interrupt Enable for Transmit Buffer 9
9
1
CFIE10
Cancellation Finished Interrupt Enable for Transmit Buffer 10
10
1
CFIE11
Cancellation Finished Interrupt Enable for Transmit Buffer 11
11
1
CFIE12
Cancellation Finished Interrupt Enable for Transmit Buffer 12
12
1
CFIE13
Cancellation Finished Interrupt Enable for Transmit Buffer 13
13
1
CFIE14
Cancellation Finished Interrupt Enable for Transmit Buffer 14
14
1
CFIE15
Cancellation Finished Interrupt Enable for Transmit Buffer 15
15
1
CFIE16
Cancellation Finished Interrupt Enable for Transmit Buffer 16
16
1
CFIE17
Cancellation Finished Interrupt Enable for Transmit Buffer 17
17
1
CFIE18
Cancellation Finished Interrupt Enable for Transmit Buffer 18
18
1
CFIE19
Cancellation Finished Interrupt Enable for Transmit Buffer 19
19
1
CFIE20
Cancellation Finished Interrupt Enable for Transmit Buffer 20
20
1
CFIE21
Cancellation Finished Interrupt Enable for Transmit Buffer 21
21
1
CFIE22
Cancellation Finished Interrupt Enable for Transmit Buffer 22
22
1
CFIE23
Cancellation Finished Interrupt Enable for Transmit Buffer 23
23
1
CFIE24
Cancellation Finished Interrupt Enable for Transmit Buffer 24
24
1
CFIE25
Cancellation Finished Interrupt Enable for Transmit Buffer 25
25
1
CFIE26
Cancellation Finished Interrupt Enable for Transmit Buffer 26
26
1
CFIE27
Cancellation Finished Interrupt Enable for Transmit Buffer 27
27
1
CFIE28
Cancellation Finished Interrupt Enable for Transmit Buffer 28
28
1
CFIE29
Cancellation Finished Interrupt Enable for Transmit Buffer 29
29
1
CFIE30
Cancellation Finished Interrupt Enable for Transmit Buffer 30
30
1
CFIE31
Cancellation Finished Interrupt Enable for Transmit Buffer 31
31
1
TXEFC
Transmit Event FIFO Configuration Register
0xF0
32
EFSA
Event FIFO Start Address
2
14
EFS
Event FIFO Size
16
6
EFWM
Event FIFO Watermark
24
6
TXEFS
Transmit Event FIFO Status Register
0xF4
32
read-only
EFFL
Event FIFO Fill Level
0
6
EFGI
Event FIFO Get Index
8
5
EFPI
Event FIFO Put Index
16
5
EFF
Event FIFO Full
24
1
TEFL
Tx Event FIFO Element Lost
25
1
TXEFA
Transmit Event FIFO Acknowledge Register
0xF8
32
EFAI
Event FIFO Acknowledge Index
0
5
MCAN1
0x40034000
MCAN1_INT0
37
MCAN1_INT1
38
PIOA
11004V
Parallel Input/Output Controller
PIO
PIO_
0x400E0E00
0
0x168
registers
PIOA
10
PER
PIO Enable Register
0x0000
32
write-only
P0
PIO Enable
0
1
P1
PIO Enable
1
1
P2
PIO Enable
2
1
P3
PIO Enable
3
1
P4
PIO Enable
4
1
P5
PIO Enable
5
1
P6
PIO Enable
6
1
P7
PIO Enable
7
1
P8
PIO Enable
8
1
P9
PIO Enable
9
1
P10
PIO Enable
10
1
P11
PIO Enable
11
1
P12
PIO Enable
12
1
P13
PIO Enable
13
1
P14
PIO Enable
14
1
P15
PIO Enable
15
1
P16
PIO Enable
16
1
P17
PIO Enable
17
1
P18
PIO Enable
18
1
P19
PIO Enable
19
1
P20
PIO Enable
20
1
P21
PIO Enable
21
1
P22
PIO Enable
22
1
P23
PIO Enable
23
1
P24
PIO Enable
24
1
P25
PIO Enable
25
1
P26
PIO Enable
26
1
P27
PIO Enable
27
1
P28
PIO Enable
28
1
P29
PIO Enable
29
1
P30
PIO Enable
30
1
P31
PIO Enable
31
1
PDR
PIO Disable Register
0x0004
32
write-only
P0
PIO Disable
0
1
P1
PIO Disable
1
1
P2
PIO Disable
2
1
P3
PIO Disable
3
1
P4
PIO Disable
4
1
P5
PIO Disable
5
1
P6
PIO Disable
6
1
P7
PIO Disable
7
1
P8
PIO Disable
8
1
P9
PIO Disable
9
1
P10
PIO Disable
10
1
P11
PIO Disable
11
1
P12
PIO Disable
12
1
P13
PIO Disable
13
1
P14
PIO Disable
14
1
P15
PIO Disable
15
1
P16
PIO Disable
16
1
P17
PIO Disable
17
1
P18
PIO Disable
18
1
P19
PIO Disable
19
1
P20
PIO Disable
20
1
P21
PIO Disable
21
1
P22
PIO Disable
22
1
P23
PIO Disable
23
1
P24
PIO Disable
24
1
P25
PIO Disable
25
1
P26
PIO Disable
26
1
P27
PIO Disable
27
1
P28
PIO Disable
28
1
P29
PIO Disable
29
1
P30
PIO Disable
30
1
P31
PIO Disable
31
1
PSR
PIO Status Register
0x0008
32
read-only
P0
PIO Status
0
1
P1
PIO Status
1
1
P2
PIO Status
2
1
P3
PIO Status
3
1
P4
PIO Status
4
1
P5
PIO Status
5
1
P6
PIO Status
6
1
P7
PIO Status
7
1
P8
PIO Status
8
1
P9
PIO Status
9
1
P10
PIO Status
10
1
P11
PIO Status
11
1
P12
PIO Status
12
1
P13
PIO Status
13
1
P14
PIO Status
14
1
P15
PIO Status
15
1
P16
PIO Status
16
1
P17
PIO Status
17
1
P18
PIO Status
18
1
P19
PIO Status
19
1
P20
PIO Status
20
1
P21
PIO Status
21
1
P22
PIO Status
22
1
P23
PIO Status
23
1
P24
PIO Status
24
1
P25
PIO Status
25
1
P26
PIO Status
26
1
P27
PIO Status
27
1
P28
PIO Status
28
1
P29
PIO Status
29
1
P30
PIO Status
30
1
P31
PIO Status
31
1
OER
Output Enable Register
0x0010
32
write-only
P0
Output Enable
0
1
P1
Output Enable
1
1
P2
Output Enable
2
1
P3
Output Enable
3
1
P4
Output Enable
4
1
P5
Output Enable
5
1
P6
Output Enable
6
1
P7
Output Enable
7
1
P8
Output Enable
8
1
P9
Output Enable
9
1
P10
Output Enable
10
1
P11
Output Enable
11
1
P12
Output Enable
12
1
P13
Output Enable
13
1
P14
Output Enable
14
1
P15
Output Enable
15
1
P16
Output Enable
16
1
P17
Output Enable
17
1
P18
Output Enable
18
1
P19
Output Enable
19
1
P20
Output Enable
20
1
P21
Output Enable
21
1
P22
Output Enable
22
1
P23
Output Enable
23
1
P24
Output Enable
24
1
P25
Output Enable
25
1
P26
Output Enable
26
1
P27
Output Enable
27
1
P28
Output Enable
28
1
P29
Output Enable
29
1
P30
Output Enable
30
1
P31
Output Enable
31
1
ODR
Output Disable Register
0x0014
32
write-only
P0
Output Disable
0
1
P1
Output Disable
1
1
P2
Output Disable
2
1
P3
Output Disable
3
1
P4
Output Disable
4
1
P5
Output Disable
5
1
P6
Output Disable
6
1
P7
Output Disable
7
1
P8
Output Disable
8
1
P9
Output Disable
9
1
P10
Output Disable
10
1
P11
Output Disable
11
1
P12
Output Disable
12
1
P13
Output Disable
13
1
P14
Output Disable
14
1
P15
Output Disable
15
1
P16
Output Disable
16
1
P17
Output Disable
17
1
P18
Output Disable
18
1
P19
Output Disable
19
1
P20
Output Disable
20
1
P21
Output Disable
21
1
P22
Output Disable
22
1
P23
Output Disable
23
1
P24
Output Disable
24
1
P25
Output Disable
25
1
P26
Output Disable
26
1
P27
Output Disable
27
1
P28
Output Disable
28
1
P29
Output Disable
29
1
P30
Output Disable
30
1
P31
Output Disable
31
1
OSR
Output Status Register
0x0018
32
read-only
P0
Output Status
0
1
P1
Output Status
1
1
P2
Output Status
2
1
P3
Output Status
3
1
P4
Output Status
4
1
P5
Output Status
5
1
P6
Output Status
6
1
P7
Output Status
7
1
P8
Output Status
8
1
P9
Output Status
9
1
P10
Output Status
10
1
P11
Output Status
11
1
P12
Output Status
12
1
P13
Output Status
13
1
P14
Output Status
14
1
P15
Output Status
15
1
P16
Output Status
16
1
P17
Output Status
17
1
P18
Output Status
18
1
P19
Output Status
19
1
P20
Output Status
20
1
P21
Output Status
21
1
P22
Output Status
22
1
P23
Output Status
23
1
P24
Output Status
24
1
P25
Output Status
25
1
P26
Output Status
26
1
P27
Output Status
27
1
P28
Output Status
28
1
P29
Output Status
29
1
P30
Output Status
30
1
P31
Output Status
31
1
IFER
Glitch Input Filter Enable Register
0x0020
32
write-only
P0
Input Filter Enable
0
1
P1
Input Filter Enable
1
1
P2
Input Filter Enable
2
1
P3
Input Filter Enable
3
1
P4
Input Filter Enable
4
1
P5
Input Filter Enable
5
1
P6
Input Filter Enable
6
1
P7
Input Filter Enable
7
1
P8
Input Filter Enable
8
1
P9
Input Filter Enable
9
1
P10
Input Filter Enable
10
1
P11
Input Filter Enable
11
1
P12
Input Filter Enable
12
1
P13
Input Filter Enable
13
1
P14
Input Filter Enable
14
1
P15
Input Filter Enable
15
1
P16
Input Filter Enable
16
1
P17
Input Filter Enable
17
1
P18
Input Filter Enable
18
1
P19
Input Filter Enable
19
1
P20
Input Filter Enable
20
1
P21
Input Filter Enable
21
1
P22
Input Filter Enable
22
1
P23
Input Filter Enable
23
1
P24
Input Filter Enable
24
1
P25
Input Filter Enable
25
1
P26
Input Filter Enable
26
1
P27
Input Filter Enable
27
1
P28
Input Filter Enable
28
1
P29
Input Filter Enable
29
1
P30
Input Filter Enable
30
1
P31
Input Filter Enable
31
1
IFDR
Glitch Input Filter Disable Register
0x0024
32
write-only
P0
Input Filter Disable
0
1
P1
Input Filter Disable
1
1
P2
Input Filter Disable
2
1
P3
Input Filter Disable
3
1
P4
Input Filter Disable
4
1
P5
Input Filter Disable
5
1
P6
Input Filter Disable
6
1
P7
Input Filter Disable
7
1
P8
Input Filter Disable
8
1
P9
Input Filter Disable
9
1
P10
Input Filter Disable
10
1
P11
Input Filter Disable
11
1
P12
Input Filter Disable
12
1
P13
Input Filter Disable
13
1
P14
Input Filter Disable
14
1
P15
Input Filter Disable
15
1
P16
Input Filter Disable
16
1
P17
Input Filter Disable
17
1
P18
Input Filter Disable
18
1
P19
Input Filter Disable
19
1
P20
Input Filter Disable
20
1
P21
Input Filter Disable
21
1
P22
Input Filter Disable
22
1
P23
Input Filter Disable
23
1
P24
Input Filter Disable
24
1
P25
Input Filter Disable
25
1
P26
Input Filter Disable
26
1
P27
Input Filter Disable
27
1
P28
Input Filter Disable
28
1
P29
Input Filter Disable
29
1
P30
Input Filter Disable
30
1
P31
Input Filter Disable
31
1
IFSR
Glitch Input Filter Status Register
0x0028
32
read-only
P0
Input Filter Status
0
1
P1
Input Filter Status
1
1
P2
Input Filter Status
2
1
P3
Input Filter Status
3
1
P4
Input Filter Status
4
1
P5
Input Filter Status
5
1
P6
Input Filter Status
6
1
P7
Input Filter Status
7
1
P8
Input Filter Status
8
1
P9
Input Filter Status
9
1
P10
Input Filter Status
10
1
P11
Input Filter Status
11
1
P12
Input Filter Status
12
1
P13
Input Filter Status
13
1
P14
Input Filter Status
14
1
P15
Input Filter Status
15
1
P16
Input Filter Status
16
1
P17
Input Filter Status
17
1
P18
Input Filter Status
18
1
P19
Input Filter Status
19
1
P20
Input Filter Status
20
1
P21
Input Filter Status
21
1
P22
Input Filter Status
22
1
P23
Input Filter Status
23
1
P24
Input Filter Status
24
1
P25
Input Filter Status
25
1
P26
Input Filter Status
26
1
P27
Input Filter Status
27
1
P28
Input Filter Status
28
1
P29
Input Filter Status
29
1
P30
Input Filter Status
30
1
P31
Input Filter Status
31
1
SODR
Set Output Data Register
0x0030
32
write-only
P0
Set Output Data
0
1
P1
Set Output Data
1
1
P2
Set Output Data
2
1
P3
Set Output Data
3
1
P4
Set Output Data
4
1
P5
Set Output Data
5
1
P6
Set Output Data
6
1
P7
Set Output Data
7
1
P8
Set Output Data
8
1
P9
Set Output Data
9
1
P10
Set Output Data
10
1
P11
Set Output Data
11
1
P12
Set Output Data
12
1
P13
Set Output Data
13
1
P14
Set Output Data
14
1
P15
Set Output Data
15
1
P16
Set Output Data
16
1
P17
Set Output Data
17
1
P18
Set Output Data
18
1
P19
Set Output Data
19
1
P20
Set Output Data
20
1
P21
Set Output Data
21
1
P22
Set Output Data
22
1
P23
Set Output Data
23
1
P24
Set Output Data
24
1
P25
Set Output Data
25
1
P26
Set Output Data
26
1
P27
Set Output Data
27
1
P28
Set Output Data
28
1
P29
Set Output Data
29
1
P30
Set Output Data
30
1
P31
Set Output Data
31
1
CODR
Clear Output Data Register
0x0034
32
write-only
P0
Clear Output Data
0
1
P1
Clear Output Data
1
1
P2
Clear Output Data
2
1
P3
Clear Output Data
3
1
P4
Clear Output Data
4
1
P5
Clear Output Data
5
1
P6
Clear Output Data
6
1
P7
Clear Output Data
7
1
P8
Clear Output Data
8
1
P9
Clear Output Data
9
1
P10
Clear Output Data
10
1
P11
Clear Output Data
11
1
P12
Clear Output Data
12
1
P13
Clear Output Data
13
1
P14
Clear Output Data
14
1
P15
Clear Output Data
15
1
P16
Clear Output Data
16
1
P17
Clear Output Data
17
1
P18
Clear Output Data
18
1
P19
Clear Output Data
19
1
P20
Clear Output Data
20
1
P21
Clear Output Data
21
1
P22
Clear Output Data
22
1
P23
Clear Output Data
23
1
P24
Clear Output Data
24
1
P25
Clear Output Data
25
1
P26
Clear Output Data
26
1
P27
Clear Output Data
27
1
P28
Clear Output Data
28
1
P29
Clear Output Data
29
1
P30
Clear Output Data
30
1
P31
Clear Output Data
31
1
ODSR
Output Data Status Register
0x0038
32
P0
Output Data Status
0
1
P1
Output Data Status
1
1
P2
Output Data Status
2
1
P3
Output Data Status
3
1
P4
Output Data Status
4
1
P5
Output Data Status
5
1
P6
Output Data Status
6
1
P7
Output Data Status
7
1
P8
Output Data Status
8
1
P9
Output Data Status
9
1
P10
Output Data Status
10
1
P11
Output Data Status
11
1
P12
Output Data Status
12
1
P13
Output Data Status
13
1
P14
Output Data Status
14
1
P15
Output Data Status
15
1
P16
Output Data Status
16
1
P17
Output Data Status
17
1
P18
Output Data Status
18
1
P19
Output Data Status
19
1
P20
Output Data Status
20
1
P21
Output Data Status
21
1
P22
Output Data Status
22
1
P23
Output Data Status
23
1
P24
Output Data Status
24
1
P25
Output Data Status
25
1
P26
Output Data Status
26
1
P27
Output Data Status
27
1
P28
Output Data Status
28
1
P29
Output Data Status
29
1
P30
Output Data Status
30
1
P31
Output Data Status
31
1
PDSR
Pin Data Status Register
0x003C
32
read-only
P0
Output Data Status
0
1
P1
Output Data Status
1
1
P2
Output Data Status
2
1
P3
Output Data Status
3
1
P4
Output Data Status
4
1
P5
Output Data Status
5
1
P6
Output Data Status
6
1
P7
Output Data Status
7
1
P8
Output Data Status
8
1
P9
Output Data Status
9
1
P10
Output Data Status
10
1
P11
Output Data Status
11
1
P12
Output Data Status
12
1
P13
Output Data Status
13
1
P14
Output Data Status
14
1
P15
Output Data Status
15
1
P16
Output Data Status
16
1
P17
Output Data Status
17
1
P18
Output Data Status
18
1
P19
Output Data Status
19
1
P20
Output Data Status
20
1
P21
Output Data Status
21
1
P22
Output Data Status
22
1
P23
Output Data Status
23
1
P24
Output Data Status
24
1
P25
Output Data Status
25
1
P26
Output Data Status
26
1
P27
Output Data Status
27
1
P28
Output Data Status
28
1
P29
Output Data Status
29
1
P30
Output Data Status
30
1
P31
Output Data Status
31
1
IER
Interrupt Enable Register
0x0040
32
write-only
P0
Input Change Interrupt Enable
0
1
P1
Input Change Interrupt Enable
1
1
P2
Input Change Interrupt Enable
2
1
P3
Input Change Interrupt Enable
3
1
P4
Input Change Interrupt Enable
4
1
P5
Input Change Interrupt Enable
5
1
P6
Input Change Interrupt Enable
6
1
P7
Input Change Interrupt Enable
7
1
P8
Input Change Interrupt Enable
8
1
P9
Input Change Interrupt Enable
9
1
P10
Input Change Interrupt Enable
10
1
P11
Input Change Interrupt Enable
11
1
P12
Input Change Interrupt Enable
12
1
P13
Input Change Interrupt Enable
13
1
P14
Input Change Interrupt Enable
14
1
P15
Input Change Interrupt Enable
15
1
P16
Input Change Interrupt Enable
16
1
P17
Input Change Interrupt Enable
17
1
P18
Input Change Interrupt Enable
18
1
P19
Input Change Interrupt Enable
19
1
P20
Input Change Interrupt Enable
20
1
P21
Input Change Interrupt Enable
21
1
P22
Input Change Interrupt Enable
22
1
P23
Input Change Interrupt Enable
23
1
P24
Input Change Interrupt Enable
24
1
P25
Input Change Interrupt Enable
25
1
P26
Input Change Interrupt Enable
26
1
P27
Input Change Interrupt Enable
27
1
P28
Input Change Interrupt Enable
28
1
P29
Input Change Interrupt Enable
29
1
P30
Input Change Interrupt Enable
30
1
P31
Input Change Interrupt Enable
31
1
IDR
Interrupt Disable Register
0x0044
32
write-only
P0
Input Change Interrupt Disable
0
1
P1
Input Change Interrupt Disable
1
1
P2
Input Change Interrupt Disable
2
1
P3
Input Change Interrupt Disable
3
1
P4
Input Change Interrupt Disable
4
1
P5
Input Change Interrupt Disable
5
1
P6
Input Change Interrupt Disable
6
1
P7
Input Change Interrupt Disable
7
1
P8
Input Change Interrupt Disable
8
1
P9
Input Change Interrupt Disable
9
1
P10
Input Change Interrupt Disable
10
1
P11
Input Change Interrupt Disable
11
1
P12
Input Change Interrupt Disable
12
1
P13
Input Change Interrupt Disable
13
1
P14
Input Change Interrupt Disable
14
1
P15
Input Change Interrupt Disable
15
1
P16
Input Change Interrupt Disable
16
1
P17
Input Change Interrupt Disable
17
1
P18
Input Change Interrupt Disable
18
1
P19
Input Change Interrupt Disable
19
1
P20
Input Change Interrupt Disable
20
1
P21
Input Change Interrupt Disable
21
1
P22
Input Change Interrupt Disable
22
1
P23
Input Change Interrupt Disable
23
1
P24
Input Change Interrupt Disable
24
1
P25
Input Change Interrupt Disable
25
1
P26
Input Change Interrupt Disable
26
1
P27
Input Change Interrupt Disable
27
1
P28
Input Change Interrupt Disable
28
1
P29
Input Change Interrupt Disable
29
1
P30
Input Change Interrupt Disable
30
1
P31
Input Change Interrupt Disable
31
1
IMR
Interrupt Mask Register
0x0048
32
read-only
P0
Input Change Interrupt Mask
0
1
P1
Input Change Interrupt Mask
1
1
P2
Input Change Interrupt Mask
2
1
P3
Input Change Interrupt Mask
3
1
P4
Input Change Interrupt Mask
4
1
P5
Input Change Interrupt Mask
5
1
P6
Input Change Interrupt Mask
6
1
P7
Input Change Interrupt Mask
7
1
P8
Input Change Interrupt Mask
8
1
P9
Input Change Interrupt Mask
9
1
P10
Input Change Interrupt Mask
10
1
P11
Input Change Interrupt Mask
11
1
P12
Input Change Interrupt Mask
12
1
P13
Input Change Interrupt Mask
13
1
P14
Input Change Interrupt Mask
14
1
P15
Input Change Interrupt Mask
15
1
P16
Input Change Interrupt Mask
16
1
P17
Input Change Interrupt Mask
17
1
P18
Input Change Interrupt Mask
18
1
P19
Input Change Interrupt Mask
19
1
P20
Input Change Interrupt Mask
20
1
P21
Input Change Interrupt Mask
21
1
P22
Input Change Interrupt Mask
22
1
P23
Input Change Interrupt Mask
23
1
P24
Input Change Interrupt Mask
24
1
P25
Input Change Interrupt Mask
25
1
P26
Input Change Interrupt Mask
26
1
P27
Input Change Interrupt Mask
27
1
P28
Input Change Interrupt Mask
28
1
P29
Input Change Interrupt Mask
29
1
P30
Input Change Interrupt Mask
30
1
P31
Input Change Interrupt Mask
31
1
ISR
Interrupt Status Register
0x004C
32
read-only
P0
Input Change Interrupt Status
0
1
P1
Input Change Interrupt Status
1
1
P2
Input Change Interrupt Status
2
1
P3
Input Change Interrupt Status
3
1
P4
Input Change Interrupt Status
4
1
P5
Input Change Interrupt Status
5
1
P6
Input Change Interrupt Status
6
1
P7
Input Change Interrupt Status
7
1
P8
Input Change Interrupt Status
8
1
P9
Input Change Interrupt Status
9
1
P10
Input Change Interrupt Status
10
1
P11
Input Change Interrupt Status
11
1
P12
Input Change Interrupt Status
12
1
P13
Input Change Interrupt Status
13
1
P14
Input Change Interrupt Status
14
1
P15
Input Change Interrupt Status
15
1
P16
Input Change Interrupt Status
16
1
P17
Input Change Interrupt Status
17
1
P18
Input Change Interrupt Status
18
1
P19
Input Change Interrupt Status
19
1
P20
Input Change Interrupt Status
20
1
P21
Input Change Interrupt Status
21
1
P22
Input Change Interrupt Status
22
1
P23
Input Change Interrupt Status
23
1
P24
Input Change Interrupt Status
24
1
P25
Input Change Interrupt Status
25
1
P26
Input Change Interrupt Status
26
1
P27
Input Change Interrupt Status
27
1
P28
Input Change Interrupt Status
28
1
P29
Input Change Interrupt Status
29
1
P30
Input Change Interrupt Status
30
1
P31
Input Change Interrupt Status
31
1
MDER
Multi-driver Enable Register
0x0050
32
write-only
P0
Multi-drive Enable
0
1
P1
Multi-drive Enable
1
1
P2
Multi-drive Enable
2
1
P3
Multi-drive Enable
3
1
P4
Multi-drive Enable
4
1
P5
Multi-drive Enable
5
1
P6
Multi-drive Enable
6
1
P7
Multi-drive Enable
7
1
P8
Multi-drive Enable
8
1
P9
Multi-drive Enable
9
1
P10
Multi-drive Enable
10
1
P11
Multi-drive Enable
11
1
P12
Multi-drive Enable
12
1
P13
Multi-drive Enable
13
1
P14
Multi-drive Enable
14
1
P15
Multi-drive Enable
15
1
P16
Multi-drive Enable
16
1
P17
Multi-drive Enable
17
1
P18
Multi-drive Enable
18
1
P19
Multi-drive Enable
19
1
P20
Multi-drive Enable
20
1
P21
Multi-drive Enable
21
1
P22
Multi-drive Enable
22
1
P23
Multi-drive Enable
23
1
P24
Multi-drive Enable
24
1
P25
Multi-drive Enable
25
1
P26
Multi-drive Enable
26
1
P27
Multi-drive Enable
27
1
P28
Multi-drive Enable
28
1
P29
Multi-drive Enable
29
1
P30
Multi-drive Enable
30
1
P31
Multi-drive Enable
31
1
MDDR
Multi-driver Disable Register
0x0054
32
write-only
P0
Multi-drive Disable
0
1
P1
Multi-drive Disable
1
1
P2
Multi-drive Disable
2
1
P3
Multi-drive Disable
3
1
P4
Multi-drive Disable
4
1
P5
Multi-drive Disable
5
1
P6
Multi-drive Disable
6
1
P7
Multi-drive Disable
7
1
P8
Multi-drive Disable
8
1
P9
Multi-drive Disable
9
1
P10
Multi-drive Disable
10
1
P11
Multi-drive Disable
11
1
P12
Multi-drive Disable
12
1
P13
Multi-drive Disable
13
1
P14
Multi-drive Disable
14
1
P15
Multi-drive Disable
15
1
P16
Multi-drive Disable
16
1
P17
Multi-drive Disable
17
1
P18
Multi-drive Disable
18
1
P19
Multi-drive Disable
19
1
P20
Multi-drive Disable
20
1
P21
Multi-drive Disable
21
1
P22
Multi-drive Disable
22
1
P23
Multi-drive Disable
23
1
P24
Multi-drive Disable
24
1
P25
Multi-drive Disable
25
1
P26
Multi-drive Disable
26
1
P27
Multi-drive Disable
27
1
P28
Multi-drive Disable
28
1
P29
Multi-drive Disable
29
1
P30
Multi-drive Disable
30
1
P31
Multi-drive Disable
31
1
MDSR
Multi-driver Status Register
0x0058
32
read-only
P0
Multi-drive Status
0
1
P1
Multi-drive Status
1
1
P2
Multi-drive Status
2
1
P3
Multi-drive Status
3
1
P4
Multi-drive Status
4
1
P5
Multi-drive Status
5
1
P6
Multi-drive Status
6
1
P7
Multi-drive Status
7
1
P8
Multi-drive Status
8
1
P9
Multi-drive Status
9
1
P10
Multi-drive Status
10
1
P11
Multi-drive Status
11
1
P12
Multi-drive Status
12
1
P13
Multi-drive Status
13
1
P14
Multi-drive Status
14
1
P15
Multi-drive Status
15
1
P16
Multi-drive Status
16
1
P17
Multi-drive Status
17
1
P18
Multi-drive Status
18
1
P19
Multi-drive Status
19
1
P20
Multi-drive Status
20
1
P21
Multi-drive Status
21
1
P22
Multi-drive Status
22
1
P23
Multi-drive Status
23
1
P24
Multi-drive Status
24
1
P25
Multi-drive Status
25
1
P26
Multi-drive Status
26
1
P27
Multi-drive Status
27
1
P28
Multi-drive Status
28
1
P29
Multi-drive Status
29
1
P30
Multi-drive Status
30
1
P31
Multi-drive Status
31
1
PUDR
Pull-up Disable Register
0x0060
32
write-only
P0
Pull-Up Disable
0
1
P1
Pull-Up Disable
1
1
P2
Pull-Up Disable
2
1
P3
Pull-Up Disable
3
1
P4
Pull-Up Disable
4
1
P5
Pull-Up Disable
5
1
P6
Pull-Up Disable
6
1
P7
Pull-Up Disable
7
1
P8
Pull-Up Disable
8
1
P9
Pull-Up Disable
9
1
P10
Pull-Up Disable
10
1
P11
Pull-Up Disable
11
1
P12
Pull-Up Disable
12
1
P13
Pull-Up Disable
13
1
P14
Pull-Up Disable
14
1
P15
Pull-Up Disable
15
1
P16
Pull-Up Disable
16
1
P17
Pull-Up Disable
17
1
P18
Pull-Up Disable
18
1
P19
Pull-Up Disable
19
1
P20
Pull-Up Disable
20
1
P21
Pull-Up Disable
21
1
P22
Pull-Up Disable
22
1
P23
Pull-Up Disable
23
1
P24
Pull-Up Disable
24
1
P25
Pull-Up Disable
25
1
P26
Pull-Up Disable
26
1
P27
Pull-Up Disable
27
1
P28
Pull-Up Disable
28
1
P29
Pull-Up Disable
29
1
P30
Pull-Up Disable
30
1
P31
Pull-Up Disable
31
1
PUER
Pull-up Enable Register
0x0064
32
write-only
P0
Pull-Up Enable
0
1
P1
Pull-Up Enable
1
1
P2
Pull-Up Enable
2
1
P3
Pull-Up Enable
3
1
P4
Pull-Up Enable
4
1
P5
Pull-Up Enable
5
1
P6
Pull-Up Enable
6
1
P7
Pull-Up Enable
7
1
P8
Pull-Up Enable
8
1
P9
Pull-Up Enable
9
1
P10
Pull-Up Enable
10
1
P11
Pull-Up Enable
11
1
P12
Pull-Up Enable
12
1
P13
Pull-Up Enable
13
1
P14
Pull-Up Enable
14
1
P15
Pull-Up Enable
15
1
P16
Pull-Up Enable
16
1
P17
Pull-Up Enable
17
1
P18
Pull-Up Enable
18
1
P19
Pull-Up Enable
19
1
P20
Pull-Up Enable
20
1
P21
Pull-Up Enable
21
1
P22
Pull-Up Enable
22
1
P23
Pull-Up Enable
23
1
P24
Pull-Up Enable
24
1
P25
Pull-Up Enable
25
1
P26
Pull-Up Enable
26
1
P27
Pull-Up Enable
27
1
P28
Pull-Up Enable
28
1
P29
Pull-Up Enable
29
1
P30
Pull-Up Enable
30
1
P31
Pull-Up Enable
31
1
PUSR
Pad Pull-up Status Register
0x0068
32
read-only
P0
Pull-Up Status
0
1
P1
Pull-Up Status
1
1
P2
Pull-Up Status
2
1
P3
Pull-Up Status
3
1
P4
Pull-Up Status
4
1
P5
Pull-Up Status
5
1
P6
Pull-Up Status
6
1
P7
Pull-Up Status
7
1
P8
Pull-Up Status
8
1
P9
Pull-Up Status
9
1
P10
Pull-Up Status
10
1
P11
Pull-Up Status
11
1
P12
Pull-Up Status
12
1
P13
Pull-Up Status
13
1
P14
Pull-Up Status
14
1
P15
Pull-Up Status
15
1
P16
Pull-Up Status
16
1
P17
Pull-Up Status
17
1
P18
Pull-Up Status
18
1
P19
Pull-Up Status
19
1
P20
Pull-Up Status
20
1
P21
Pull-Up Status
21
1
P22
Pull-Up Status
22
1
P23
Pull-Up Status
23
1
P24
Pull-Up Status
24
1
P25
Pull-Up Status
25
1
P26
Pull-Up Status
26
1
P27
Pull-Up Status
27
1
P28
Pull-Up Status
28
1
P29
Pull-Up Status
29
1
P30
Pull-Up Status
30
1
P31
Pull-Up Status
31
1
2
4
ABCDSR[%s]
Peripheral ABCD Select Register 0
0x70
32
P0
Peripheral Select
0
1
P1
Peripheral Select
1
1
P2
Peripheral Select
2
1
P3
Peripheral Select
3
1
P4
Peripheral Select
4
1
P5
Peripheral Select
5
1
P6
Peripheral Select
6
1
P7
Peripheral Select
7
1
P8
Peripheral Select
8
1
P9
Peripheral Select
9
1
P10
Peripheral Select
10
1
P11
Peripheral Select
11
1
P12
Peripheral Select
12
1
P13
Peripheral Select
13
1
P14
Peripheral Select
14
1
P15
Peripheral Select
15
1
P16
Peripheral Select
16
1
P17
Peripheral Select
17
1
P18
Peripheral Select
18
1
P19
Peripheral Select
19
1
P20
Peripheral Select
20
1
P21
Peripheral Select
21
1
P22
Peripheral Select
22
1
P23
Peripheral Select
23
1
P24
Peripheral Select
24
1
P25
Peripheral Select
25
1
P26
Peripheral Select
26
1
P27
Peripheral Select
27
1
P28
Peripheral Select
28
1
P29
Peripheral Select
29
1
P30
Peripheral Select
30
1
P31
Peripheral Select
31
1
IFSCDR
Input Filter Slow Clock Disable Register
0x0080
32
write-only
P0
Peripheral Clock Glitch Filtering Select
0
1
P1
Peripheral Clock Glitch Filtering Select
1
1
P2
Peripheral Clock Glitch Filtering Select
2
1
P3
Peripheral Clock Glitch Filtering Select
3
1
P4
Peripheral Clock Glitch Filtering Select
4
1
P5
Peripheral Clock Glitch Filtering Select
5
1
P6
Peripheral Clock Glitch Filtering Select
6
1
P7
Peripheral Clock Glitch Filtering Select
7
1
P8
Peripheral Clock Glitch Filtering Select
8
1
P9
Peripheral Clock Glitch Filtering Select
9
1
P10
Peripheral Clock Glitch Filtering Select
10
1
P11
Peripheral Clock Glitch Filtering Select
11
1
P12
Peripheral Clock Glitch Filtering Select
12
1
P13
Peripheral Clock Glitch Filtering Select
13
1
P14
Peripheral Clock Glitch Filtering Select
14
1
P15
Peripheral Clock Glitch Filtering Select
15
1
P16
Peripheral Clock Glitch Filtering Select
16
1
P17
Peripheral Clock Glitch Filtering Select
17
1
P18
Peripheral Clock Glitch Filtering Select
18
1
P19
Peripheral Clock Glitch Filtering Select
19
1
P20
Peripheral Clock Glitch Filtering Select
20
1
P21
Peripheral Clock Glitch Filtering Select
21
1
P22
Peripheral Clock Glitch Filtering Select
22
1
P23
Peripheral Clock Glitch Filtering Select
23
1
P24
Peripheral Clock Glitch Filtering Select
24
1
P25
Peripheral Clock Glitch Filtering Select
25
1
P26
Peripheral Clock Glitch Filtering Select
26
1
P27
Peripheral Clock Glitch Filtering Select
27
1
P28
Peripheral Clock Glitch Filtering Select
28
1
P29
Peripheral Clock Glitch Filtering Select
29
1
P30
Peripheral Clock Glitch Filtering Select
30
1
P31
Peripheral Clock Glitch Filtering Select
31
1
IFSCER
Input Filter Slow Clock Enable Register
0x0084
32
write-only
P0
Slow Clock Debouncing Filtering Select
0
1
P1
Slow Clock Debouncing Filtering Select
1
1
P2
Slow Clock Debouncing Filtering Select
2
1
P3
Slow Clock Debouncing Filtering Select
3
1
P4
Slow Clock Debouncing Filtering Select
4
1
P5
Slow Clock Debouncing Filtering Select
5
1
P6
Slow Clock Debouncing Filtering Select
6
1
P7
Slow Clock Debouncing Filtering Select
7
1
P8
Slow Clock Debouncing Filtering Select
8
1
P9
Slow Clock Debouncing Filtering Select
9
1
P10
Slow Clock Debouncing Filtering Select
10
1
P11
Slow Clock Debouncing Filtering Select
11
1
P12
Slow Clock Debouncing Filtering Select
12
1
P13
Slow Clock Debouncing Filtering Select
13
1
P14
Slow Clock Debouncing Filtering Select
14
1
P15
Slow Clock Debouncing Filtering Select
15
1
P16
Slow Clock Debouncing Filtering Select
16
1
P17
Slow Clock Debouncing Filtering Select
17
1
P18
Slow Clock Debouncing Filtering Select
18
1
P19
Slow Clock Debouncing Filtering Select
19
1
P20
Slow Clock Debouncing Filtering Select
20
1
P21
Slow Clock Debouncing Filtering Select
21
1
P22
Slow Clock Debouncing Filtering Select
22
1
P23
Slow Clock Debouncing Filtering Select
23
1
P24
Slow Clock Debouncing Filtering Select
24
1
P25
Slow Clock Debouncing Filtering Select
25
1
P26
Slow Clock Debouncing Filtering Select
26
1
P27
Slow Clock Debouncing Filtering Select
27
1
P28
Slow Clock Debouncing Filtering Select
28
1
P29
Slow Clock Debouncing Filtering Select
29
1
P30
Slow Clock Debouncing Filtering Select
30
1
P31
Slow Clock Debouncing Filtering Select
31
1
IFSCSR
Input Filter Slow Clock Status Register
0x0088
32
read-only
P0
Glitch or Debouncing Filter Selection Status
0
1
P1
Glitch or Debouncing Filter Selection Status
1
1
P2
Glitch or Debouncing Filter Selection Status
2
1
P3
Glitch or Debouncing Filter Selection Status
3
1
P4
Glitch or Debouncing Filter Selection Status
4
1
P5
Glitch or Debouncing Filter Selection Status
5
1
P6
Glitch or Debouncing Filter Selection Status
6
1
P7
Glitch or Debouncing Filter Selection Status
7
1
P8
Glitch or Debouncing Filter Selection Status
8
1
P9
Glitch or Debouncing Filter Selection Status
9
1
P10
Glitch or Debouncing Filter Selection Status
10
1
P11
Glitch or Debouncing Filter Selection Status
11
1
P12
Glitch or Debouncing Filter Selection Status
12
1
P13
Glitch or Debouncing Filter Selection Status
13
1
P14
Glitch or Debouncing Filter Selection Status
14
1
P15
Glitch or Debouncing Filter Selection Status
15
1
P16
Glitch or Debouncing Filter Selection Status
16
1
P17
Glitch or Debouncing Filter Selection Status
17
1
P18
Glitch or Debouncing Filter Selection Status
18
1
P19
Glitch or Debouncing Filter Selection Status
19
1
P20
Glitch or Debouncing Filter Selection Status
20
1
P21
Glitch or Debouncing Filter Selection Status
21
1
P22
Glitch or Debouncing Filter Selection Status
22
1
P23
Glitch or Debouncing Filter Selection Status
23
1
P24
Glitch or Debouncing Filter Selection Status
24
1
P25
Glitch or Debouncing Filter Selection Status
25
1
P26
Glitch or Debouncing Filter Selection Status
26
1
P27
Glitch or Debouncing Filter Selection Status
27
1
P28
Glitch or Debouncing Filter Selection Status
28
1
P29
Glitch or Debouncing Filter Selection Status
29
1
P30
Glitch or Debouncing Filter Selection Status
30
1
P31
Glitch or Debouncing Filter Selection Status
31
1
SCDR
Slow Clock Divider Debouncing Register
0x008C
32
DIV
Slow Clock Divider Selection for Debouncing
0
14
PPDDR
Pad Pull-down Disable Register
0x0090
32
write-only
P0
Pull-Down Disable
0
1
P1
Pull-Down Disable
1
1
P2
Pull-Down Disable
2
1
P3
Pull-Down Disable
3
1
P4
Pull-Down Disable
4
1
P5
Pull-Down Disable
5
1
P6
Pull-Down Disable
6
1
P7
Pull-Down Disable
7
1
P8
Pull-Down Disable
8
1
P9
Pull-Down Disable
9
1
P10
Pull-Down Disable
10
1
P11
Pull-Down Disable
11
1
P12
Pull-Down Disable
12
1
P13
Pull-Down Disable
13
1
P14
Pull-Down Disable
14
1
P15
Pull-Down Disable
15
1
P16
Pull-Down Disable
16
1
P17
Pull-Down Disable
17
1
P18
Pull-Down Disable
18
1
P19
Pull-Down Disable
19
1
P20
Pull-Down Disable
20
1
P21
Pull-Down Disable
21
1
P22
Pull-Down Disable
22
1
P23
Pull-Down Disable
23
1
P24
Pull-Down Disable
24
1
P25
Pull-Down Disable
25
1
P26
Pull-Down Disable
26
1
P27
Pull-Down Disable
27
1
P28
Pull-Down Disable
28
1
P29
Pull-Down Disable
29
1
P30
Pull-Down Disable
30
1
P31
Pull-Down Disable
31
1
PPDER
Pad Pull-down Enable Register
0x0094
32
write-only
P0
Pull-Down Enable
0
1
P1
Pull-Down Enable
1
1
P2
Pull-Down Enable
2
1
P3
Pull-Down Enable
3
1
P4
Pull-Down Enable
4
1
P5
Pull-Down Enable
5
1
P6
Pull-Down Enable
6
1
P7
Pull-Down Enable
7
1
P8
Pull-Down Enable
8
1
P9
Pull-Down Enable
9
1
P10
Pull-Down Enable
10
1
P11
Pull-Down Enable
11
1
P12
Pull-Down Enable
12
1
P13
Pull-Down Enable
13
1
P14
Pull-Down Enable
14
1
P15
Pull-Down Enable
15
1
P16
Pull-Down Enable
16
1
P17
Pull-Down Enable
17
1
P18
Pull-Down Enable
18
1
P19
Pull-Down Enable
19
1
P20
Pull-Down Enable
20
1
P21
Pull-Down Enable
21
1
P22
Pull-Down Enable
22
1
P23
Pull-Down Enable
23
1
P24
Pull-Down Enable
24
1
P25
Pull-Down Enable
25
1
P26
Pull-Down Enable
26
1
P27
Pull-Down Enable
27
1
P28
Pull-Down Enable
28
1
P29
Pull-Down Enable
29
1
P30
Pull-Down Enable
30
1
P31
Pull-Down Enable
31
1
PPDSR
Pad Pull-down Status Register
0x0098
32
read-only
P0
Pull-Down Status
0
1
P1
Pull-Down Status
1
1
P2
Pull-Down Status
2
1
P3
Pull-Down Status
3
1
P4
Pull-Down Status
4
1
P5
Pull-Down Status
5
1
P6
Pull-Down Status
6
1
P7
Pull-Down Status
7
1
P8
Pull-Down Status
8
1
P9
Pull-Down Status
9
1
P10
Pull-Down Status
10
1
P11
Pull-Down Status
11
1
P12
Pull-Down Status
12
1
P13
Pull-Down Status
13
1
P14
Pull-Down Status
14
1
P15
Pull-Down Status
15
1
P16
Pull-Down Status
16
1
P17
Pull-Down Status
17
1
P18
Pull-Down Status
18
1
P19
Pull-Down Status
19
1
P20
Pull-Down Status
20
1
P21
Pull-Down Status
21
1
P22
Pull-Down Status
22
1
P23
Pull-Down Status
23
1
P24
Pull-Down Status
24
1
P25
Pull-Down Status
25
1
P26
Pull-Down Status
26
1
P27
Pull-Down Status
27
1
P28
Pull-Down Status
28
1
P29
Pull-Down Status
29
1
P30
Pull-Down Status
30
1
P31
Pull-Down Status
31
1
OWER
Output Write Enable
0x00A0
32
write-only
P0
Output Write Enable
0
1
P1
Output Write Enable
1
1
P2
Output Write Enable
2
1
P3
Output Write Enable
3
1
P4
Output Write Enable
4
1
P5
Output Write Enable
5
1
P6
Output Write Enable
6
1
P7
Output Write Enable
7
1
P8
Output Write Enable
8
1
P9
Output Write Enable
9
1
P10
Output Write Enable
10
1
P11
Output Write Enable
11
1
P12
Output Write Enable
12
1
P13
Output Write Enable
13
1
P14
Output Write Enable
14
1
P15
Output Write Enable
15
1
P16
Output Write Enable
16
1
P17
Output Write Enable
17
1
P18
Output Write Enable
18
1
P19
Output Write Enable
19
1
P20
Output Write Enable
20
1
P21
Output Write Enable
21
1
P22
Output Write Enable
22
1
P23
Output Write Enable
23
1
P24
Output Write Enable
24
1
P25
Output Write Enable
25
1
P26
Output Write Enable
26
1
P27
Output Write Enable
27
1
P28
Output Write Enable
28
1
P29
Output Write Enable
29
1
P30
Output Write Enable
30
1
P31
Output Write Enable
31
1
OWDR
Output Write Disable
0x00A4
32
write-only
P0
Output Write Disable
0
1
P1
Output Write Disable
1
1
P2
Output Write Disable
2
1
P3
Output Write Disable
3
1
P4
Output Write Disable
4
1
P5
Output Write Disable
5
1
P6
Output Write Disable
6
1
P7
Output Write Disable
7
1
P8
Output Write Disable
8
1
P9
Output Write Disable
9
1
P10
Output Write Disable
10
1
P11
Output Write Disable
11
1
P12
Output Write Disable
12
1
P13
Output Write Disable
13
1
P14
Output Write Disable
14
1
P15
Output Write Disable
15
1
P16
Output Write Disable
16
1
P17
Output Write Disable
17
1
P18
Output Write Disable
18
1
P19
Output Write Disable
19
1
P20
Output Write Disable
20
1
P21
Output Write Disable
21
1
P22
Output Write Disable
22
1
P23
Output Write Disable
23
1
P24
Output Write Disable
24
1
P25
Output Write Disable
25
1
P26
Output Write Disable
26
1
P27
Output Write Disable
27
1
P28
Output Write Disable
28
1
P29
Output Write Disable
29
1
P30
Output Write Disable
30
1
P31
Output Write Disable
31
1
OWSR
Output Write Status Register
0x00A8
32
read-only
P0
Output Write Status
0
1
P1
Output Write Status
1
1
P2
Output Write Status
2
1
P3
Output Write Status
3
1
P4
Output Write Status
4
1
P5
Output Write Status
5
1
P6
Output Write Status
6
1
P7
Output Write Status
7
1
P8
Output Write Status
8
1
P9
Output Write Status
9
1
P10
Output Write Status
10
1
P11
Output Write Status
11
1
P12
Output Write Status
12
1
P13
Output Write Status
13
1
P14
Output Write Status
14
1
P15
Output Write Status
15
1
P16
Output Write Status
16
1
P17
Output Write Status
17
1
P18
Output Write Status
18
1
P19
Output Write Status
19
1
P20
Output Write Status
20
1
P21
Output Write Status
21
1
P22
Output Write Status
22
1
P23
Output Write Status
23
1
P24
Output Write Status
24
1
P25
Output Write Status
25
1
P26
Output Write Status
26
1
P27
Output Write Status
27
1
P28
Output Write Status
28
1
P29
Output Write Status
29
1
P30
Output Write Status
30
1
P31
Output Write Status
31
1
AIMER
Additional Interrupt Modes Enable Register
0x00B0
32
write-only
P0
Additional Interrupt Modes Enable
0
1
P1
Additional Interrupt Modes Enable
1
1
P2
Additional Interrupt Modes Enable
2
1
P3
Additional Interrupt Modes Enable
3
1
P4
Additional Interrupt Modes Enable
4
1
P5
Additional Interrupt Modes Enable
5
1
P6
Additional Interrupt Modes Enable
6
1
P7
Additional Interrupt Modes Enable
7
1
P8
Additional Interrupt Modes Enable
8
1
P9
Additional Interrupt Modes Enable
9
1
P10
Additional Interrupt Modes Enable
10
1
P11
Additional Interrupt Modes Enable
11
1
P12
Additional Interrupt Modes Enable
12
1
P13
Additional Interrupt Modes Enable
13
1
P14
Additional Interrupt Modes Enable
14
1
P15
Additional Interrupt Modes Enable
15
1
P16
Additional Interrupt Modes Enable
16
1
P17
Additional Interrupt Modes Enable
17
1
P18
Additional Interrupt Modes Enable
18
1
P19
Additional Interrupt Modes Enable
19
1
P20
Additional Interrupt Modes Enable
20
1
P21
Additional Interrupt Modes Enable
21
1
P22
Additional Interrupt Modes Enable
22
1
P23
Additional Interrupt Modes Enable
23
1
P24
Additional Interrupt Modes Enable
24
1
P25
Additional Interrupt Modes Enable
25
1
P26
Additional Interrupt Modes Enable
26
1
P27
Additional Interrupt Modes Enable
27
1
P28
Additional Interrupt Modes Enable
28
1
P29
Additional Interrupt Modes Enable
29
1
P30
Additional Interrupt Modes Enable
30
1
P31
Additional Interrupt Modes Enable
31
1
AIMDR
Additional Interrupt Modes Disable Register
0x00B4
32
write-only
P0
Additional Interrupt Modes Disable
0
1
P1
Additional Interrupt Modes Disable
1
1
P2
Additional Interrupt Modes Disable
2
1
P3
Additional Interrupt Modes Disable
3
1
P4
Additional Interrupt Modes Disable
4
1
P5
Additional Interrupt Modes Disable
5
1
P6
Additional Interrupt Modes Disable
6
1
P7
Additional Interrupt Modes Disable
7
1
P8
Additional Interrupt Modes Disable
8
1
P9
Additional Interrupt Modes Disable
9
1
P10
Additional Interrupt Modes Disable
10
1
P11
Additional Interrupt Modes Disable
11
1
P12
Additional Interrupt Modes Disable
12
1
P13
Additional Interrupt Modes Disable
13
1
P14
Additional Interrupt Modes Disable
14
1
P15
Additional Interrupt Modes Disable
15
1
P16
Additional Interrupt Modes Disable
16
1
P17
Additional Interrupt Modes Disable
17
1
P18
Additional Interrupt Modes Disable
18
1
P19
Additional Interrupt Modes Disable
19
1
P20
Additional Interrupt Modes Disable
20
1
P21
Additional Interrupt Modes Disable
21
1
P22
Additional Interrupt Modes Disable
22
1
P23
Additional Interrupt Modes Disable
23
1
P24
Additional Interrupt Modes Disable
24
1
P25
Additional Interrupt Modes Disable
25
1
P26
Additional Interrupt Modes Disable
26
1
P27
Additional Interrupt Modes Disable
27
1
P28
Additional Interrupt Modes Disable
28
1
P29
Additional Interrupt Modes Disable
29
1
P30
Additional Interrupt Modes Disable
30
1
P31
Additional Interrupt Modes Disable
31
1
AIMMR
Additional Interrupt Modes Mask Register
0x00B8
32
read-only
P0
IO Line Index
0
1
P1
IO Line Index
1
1
P2
IO Line Index
2
1
P3
IO Line Index
3
1
P4
IO Line Index
4
1
P5
IO Line Index
5
1
P6
IO Line Index
6
1
P7
IO Line Index
7
1
P8
IO Line Index
8
1
P9
IO Line Index
9
1
P10
IO Line Index
10
1
P11
IO Line Index
11
1
P12
IO Line Index
12
1
P13
IO Line Index
13
1
P14
IO Line Index
14
1
P15
IO Line Index
15
1
P16
IO Line Index
16
1
P17
IO Line Index
17
1
P18
IO Line Index
18
1
P19
IO Line Index
19
1
P20
IO Line Index
20
1
P21
IO Line Index
21
1
P22
IO Line Index
22
1
P23
IO Line Index
23
1
P24
IO Line Index
24
1
P25
IO Line Index
25
1
P26
IO Line Index
26
1
P27
IO Line Index
27
1
P28
IO Line Index
28
1
P29
IO Line Index
29
1
P30
IO Line Index
30
1
P31
IO Line Index
31
1
ESR
Edge Select Register
0x00C0
32
write-only
P0
Edge Interrupt Selection
0
1
P1
Edge Interrupt Selection
1
1
P2
Edge Interrupt Selection
2
1
P3
Edge Interrupt Selection
3
1
P4
Edge Interrupt Selection
4
1
P5
Edge Interrupt Selection
5
1
P6
Edge Interrupt Selection
6
1
P7
Edge Interrupt Selection
7
1
P8
Edge Interrupt Selection
8
1
P9
Edge Interrupt Selection
9
1
P10
Edge Interrupt Selection
10
1
P11
Edge Interrupt Selection
11
1
P12
Edge Interrupt Selection
12
1
P13
Edge Interrupt Selection
13
1
P14
Edge Interrupt Selection
14
1
P15
Edge Interrupt Selection
15
1
P16
Edge Interrupt Selection
16
1
P17
Edge Interrupt Selection
17
1
P18
Edge Interrupt Selection
18
1
P19
Edge Interrupt Selection
19
1
P20
Edge Interrupt Selection
20
1
P21
Edge Interrupt Selection
21
1
P22
Edge Interrupt Selection
22
1
P23
Edge Interrupt Selection
23
1
P24
Edge Interrupt Selection
24
1
P25
Edge Interrupt Selection
25
1
P26
Edge Interrupt Selection
26
1
P27
Edge Interrupt Selection
27
1
P28
Edge Interrupt Selection
28
1
P29
Edge Interrupt Selection
29
1
P30
Edge Interrupt Selection
30
1
P31
Edge Interrupt Selection
31
1
LSR
Level Select Register
0x00C4
32
write-only
P0
Level Interrupt Selection
0
1
P1
Level Interrupt Selection
1
1
P2
Level Interrupt Selection
2
1
P3
Level Interrupt Selection
3
1
P4
Level Interrupt Selection
4
1
P5
Level Interrupt Selection
5
1
P6
Level Interrupt Selection
6
1
P7
Level Interrupt Selection
7
1
P8
Level Interrupt Selection
8
1
P9
Level Interrupt Selection
9
1
P10
Level Interrupt Selection
10
1
P11
Level Interrupt Selection
11
1
P12
Level Interrupt Selection
12
1
P13
Level Interrupt Selection
13
1
P14
Level Interrupt Selection
14
1
P15
Level Interrupt Selection
15
1
P16
Level Interrupt Selection
16
1
P17
Level Interrupt Selection
17
1
P18
Level Interrupt Selection
18
1
P19
Level Interrupt Selection
19
1
P20
Level Interrupt Selection
20
1
P21
Level Interrupt Selection
21
1
P22
Level Interrupt Selection
22
1
P23
Level Interrupt Selection
23
1
P24
Level Interrupt Selection
24
1
P25
Level Interrupt Selection
25
1
P26
Level Interrupt Selection
26
1
P27
Level Interrupt Selection
27
1
P28
Level Interrupt Selection
28
1
P29
Level Interrupt Selection
29
1
P30
Level Interrupt Selection
30
1
P31
Level Interrupt Selection
31
1
ELSR
Edge/Level Status Register
0x00C8
32
read-only
P0
Edge/Level Interrupt Source Selection
0
1
P1
Edge/Level Interrupt Source Selection
1
1
P2
Edge/Level Interrupt Source Selection
2
1
P3
Edge/Level Interrupt Source Selection
3
1
P4
Edge/Level Interrupt Source Selection
4
1
P5
Edge/Level Interrupt Source Selection
5
1
P6
Edge/Level Interrupt Source Selection
6
1
P7
Edge/Level Interrupt Source Selection
7
1
P8
Edge/Level Interrupt Source Selection
8
1
P9
Edge/Level Interrupt Source Selection
9
1
P10
Edge/Level Interrupt Source Selection
10
1
P11
Edge/Level Interrupt Source Selection
11
1
P12
Edge/Level Interrupt Source Selection
12
1
P13
Edge/Level Interrupt Source Selection
13
1
P14
Edge/Level Interrupt Source Selection
14
1
P15
Edge/Level Interrupt Source Selection
15
1
P16
Edge/Level Interrupt Source Selection
16
1
P17
Edge/Level Interrupt Source Selection
17
1
P18
Edge/Level Interrupt Source Selection
18
1
P19
Edge/Level Interrupt Source Selection
19
1
P20
Edge/Level Interrupt Source Selection
20
1
P21
Edge/Level Interrupt Source Selection
21
1
P22
Edge/Level Interrupt Source Selection
22
1
P23
Edge/Level Interrupt Source Selection
23
1
P24
Edge/Level Interrupt Source Selection
24
1
P25
Edge/Level Interrupt Source Selection
25
1
P26
Edge/Level Interrupt Source Selection
26
1
P27
Edge/Level Interrupt Source Selection
27
1
P28
Edge/Level Interrupt Source Selection
28
1
P29
Edge/Level Interrupt Source Selection
29
1
P30
Edge/Level Interrupt Source Selection
30
1
P31
Edge/Level Interrupt Source Selection
31
1
FELLSR
Falling Edge/Low-Level Select Register
0x00D0
32
write-only
P0
Falling Edge/Low-Level Interrupt Selection
0
1
P1
Falling Edge/Low-Level Interrupt Selection
1
1
P2
Falling Edge/Low-Level Interrupt Selection
2
1
P3
Falling Edge/Low-Level Interrupt Selection
3
1
P4
Falling Edge/Low-Level Interrupt Selection
4
1
P5
Falling Edge/Low-Level Interrupt Selection
5
1
P6
Falling Edge/Low-Level Interrupt Selection
6
1
P7
Falling Edge/Low-Level Interrupt Selection
7
1
P8
Falling Edge/Low-Level Interrupt Selection
8
1
P9
Falling Edge/Low-Level Interrupt Selection
9
1
P10
Falling Edge/Low-Level Interrupt Selection
10
1
P11
Falling Edge/Low-Level Interrupt Selection
11
1
P12
Falling Edge/Low-Level Interrupt Selection
12
1
P13
Falling Edge/Low-Level Interrupt Selection
13
1
P14
Falling Edge/Low-Level Interrupt Selection
14
1
P15
Falling Edge/Low-Level Interrupt Selection
15
1
P16
Falling Edge/Low-Level Interrupt Selection
16
1
P17
Falling Edge/Low-Level Interrupt Selection
17
1
P18
Falling Edge/Low-Level Interrupt Selection
18
1
P19
Falling Edge/Low-Level Interrupt Selection
19
1
P20
Falling Edge/Low-Level Interrupt Selection
20
1
P21
Falling Edge/Low-Level Interrupt Selection
21
1
P22
Falling Edge/Low-Level Interrupt Selection
22
1
P23
Falling Edge/Low-Level Interrupt Selection
23
1
P24
Falling Edge/Low-Level Interrupt Selection
24
1
P25
Falling Edge/Low-Level Interrupt Selection
25
1
P26
Falling Edge/Low-Level Interrupt Selection
26
1
P27
Falling Edge/Low-Level Interrupt Selection
27
1
P28
Falling Edge/Low-Level Interrupt Selection
28
1
P29
Falling Edge/Low-Level Interrupt Selection
29
1
P30
Falling Edge/Low-Level Interrupt Selection
30
1
P31
Falling Edge/Low-Level Interrupt Selection
31
1
REHLSR
Rising Edge/High-Level Select Register
0x00D4
32
write-only
P0
Rising Edge/High-Level Interrupt Selection
0
1
P1
Rising Edge/High-Level Interrupt Selection
1
1
P2
Rising Edge/High-Level Interrupt Selection
2
1
P3
Rising Edge/High-Level Interrupt Selection
3
1
P4
Rising Edge/High-Level Interrupt Selection
4
1
P5
Rising Edge/High-Level Interrupt Selection
5
1
P6
Rising Edge/High-Level Interrupt Selection
6
1
P7
Rising Edge/High-Level Interrupt Selection
7
1
P8
Rising Edge/High-Level Interrupt Selection
8
1
P9
Rising Edge/High-Level Interrupt Selection
9
1
P10
Rising Edge/High-Level Interrupt Selection
10
1
P11
Rising Edge/High-Level Interrupt Selection
11
1
P12
Rising Edge/High-Level Interrupt Selection
12
1
P13
Rising Edge/High-Level Interrupt Selection
13
1
P14
Rising Edge/High-Level Interrupt Selection
14
1
P15
Rising Edge/High-Level Interrupt Selection
15
1
P16
Rising Edge/High-Level Interrupt Selection
16
1
P17
Rising Edge/High-Level Interrupt Selection
17
1
P18
Rising Edge/High-Level Interrupt Selection
18
1
P19
Rising Edge/High-Level Interrupt Selection
19
1
P20
Rising Edge/High-Level Interrupt Selection
20
1
P21
Rising Edge/High-Level Interrupt Selection
21
1
P22
Rising Edge/High-Level Interrupt Selection
22
1
P23
Rising Edge/High-Level Interrupt Selection
23
1
P24
Rising Edge/High-Level Interrupt Selection
24
1
P25
Rising Edge/High-Level Interrupt Selection
25
1
P26
Rising Edge/High-Level Interrupt Selection
26
1
P27
Rising Edge/High-Level Interrupt Selection
27
1
P28
Rising Edge/High-Level Interrupt Selection
28
1
P29
Rising Edge/High-Level Interrupt Selection
29
1
P30
Rising Edge/High-Level Interrupt Selection
30
1
P31
Rising Edge/High-Level Interrupt Selection
31
1
FRLHSR
Fall/Rise - Low/High Status Register
0x00D8
32
read-only
P0
Edge/Level Interrupt Source Selection
0
1
P1
Edge/Level Interrupt Source Selection
1
1
P2
Edge/Level Interrupt Source Selection
2
1
P3
Edge/Level Interrupt Source Selection
3
1
P4
Edge/Level Interrupt Source Selection
4
1
P5
Edge/Level Interrupt Source Selection
5
1
P6
Edge/Level Interrupt Source Selection
6
1
P7
Edge/Level Interrupt Source Selection
7
1
P8
Edge/Level Interrupt Source Selection
8
1
P9
Edge/Level Interrupt Source Selection
9
1
P10
Edge/Level Interrupt Source Selection
10
1
P11
Edge/Level Interrupt Source Selection
11
1
P12
Edge/Level Interrupt Source Selection
12
1
P13
Edge/Level Interrupt Source Selection
13
1
P14
Edge/Level Interrupt Source Selection
14
1
P15
Edge/Level Interrupt Source Selection
15
1
P16
Edge/Level Interrupt Source Selection
16
1
P17
Edge/Level Interrupt Source Selection
17
1
P18
Edge/Level Interrupt Source Selection
18
1
P19
Edge/Level Interrupt Source Selection
19
1
P20
Edge/Level Interrupt Source Selection
20
1
P21
Edge/Level Interrupt Source Selection
21
1
P22
Edge/Level Interrupt Source Selection
22
1
P23
Edge/Level Interrupt Source Selection
23
1
P24
Edge/Level Interrupt Source Selection
24
1
P25
Edge/Level Interrupt Source Selection
25
1
P26
Edge/Level Interrupt Source Selection
26
1
P27
Edge/Level Interrupt Source Selection
27
1
P28
Edge/Level Interrupt Source Selection
28
1
P29
Edge/Level Interrupt Source Selection
29
1
P30
Edge/Level Interrupt Source Selection
30
1
P31
Edge/Level Interrupt Source Selection
31
1
LOCKSR
Lock Status
0x00E0
32
read-only
P0
Lock Status
0
1
P1
Lock Status
1
1
P2
Lock Status
2
1
P3
Lock Status
3
1
P4
Lock Status
4
1
P5
Lock Status
5
1
P6
Lock Status
6
1
P7
Lock Status
7
1
P8
Lock Status
8
1
P9
Lock Status
9
1
P10
Lock Status
10
1
P11
Lock Status
11
1
P12
Lock Status
12
1
P13
Lock Status
13
1
P14
Lock Status
14
1
P15
Lock Status
15
1
P16
Lock Status
16
1
P17
Lock Status
17
1
P18
Lock Status
18
1
P19
Lock Status
19
1
P20
Lock Status
20
1
P21
Lock Status
21
1
P22
Lock Status
22
1
P23
Lock Status
23
1
P24
Lock Status
24
1
P25
Lock Status
25
1
P26
Lock Status
26
1
P27
Lock Status
27
1
P28
Lock Status
28
1
P29
Lock Status
29
1
P30
Lock Status
30
1
P31
Lock Status
31
1
WPMR
Write Protection Mode Register
0x00E4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x50494F
WPSR
Write Protection Status Register
0x00E8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
16
SCHMITT
Schmitt Trigger Register
0x0100
32
SCHMITT0
Schmitt Trigger Control
0
1
SCHMITT1
Schmitt Trigger Control
1
1
SCHMITT2
Schmitt Trigger Control
2
1
SCHMITT3
Schmitt Trigger Control
3
1
SCHMITT4
Schmitt Trigger Control
4
1
SCHMITT5
Schmitt Trigger Control
5
1
SCHMITT6
Schmitt Trigger Control
6
1
SCHMITT7
Schmitt Trigger Control
7
1
SCHMITT8
Schmitt Trigger Control
8
1
SCHMITT9
Schmitt Trigger Control
9
1
SCHMITT10
Schmitt Trigger Control
10
1
SCHMITT11
Schmitt Trigger Control
11
1
SCHMITT12
Schmitt Trigger Control
12
1
SCHMITT13
Schmitt Trigger Control
13
1
SCHMITT14
Schmitt Trigger Control
14
1
SCHMITT15
Schmitt Trigger Control
15
1
SCHMITT16
Schmitt Trigger Control
16
1
SCHMITT17
Schmitt Trigger Control
17
1
SCHMITT18
Schmitt Trigger Control
18
1
SCHMITT19
Schmitt Trigger Control
19
1
SCHMITT20
Schmitt Trigger Control
20
1
SCHMITT21
Schmitt Trigger Control
21
1
SCHMITT22
Schmitt Trigger Control
22
1
SCHMITT23
Schmitt Trigger Control
23
1
SCHMITT24
Schmitt Trigger Control
24
1
SCHMITT25
Schmitt Trigger Control
25
1
SCHMITT26
Schmitt Trigger Control
26
1
SCHMITT27
Schmitt Trigger Control
27
1
SCHMITT28
Schmitt Trigger Control
28
1
SCHMITT29
Schmitt Trigger Control
29
1
SCHMITT30
Schmitt Trigger Control
30
1
SCHMITT31
Schmitt Trigger Control
31
1
DRIVER
I/O Drive Register
0x0118
32
LINE0
Drive of PIO Line 0
0
1
LINE0Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE1
Drive of PIO Line 1
1
1
LINE1Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE2
Drive of PIO Line 2
2
1
LINE2Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE3
Drive of PIO Line 3
3
1
LINE3Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE4
Drive of PIO Line 4
4
1
LINE4Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE5
Drive of PIO Line 5
5
1
LINE5Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE6
Drive of PIO Line 6
6
1
LINE6Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE7
Drive of PIO Line 7
7
1
LINE7Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE8
Drive of PIO Line 8
8
1
LINE8Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE9
Drive of PIO Line 9
9
1
LINE9Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE10
Drive of PIO Line 10
10
1
LINE10Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE11
Drive of PIO Line 11
11
1
LINE11Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE12
Drive of PIO Line 12
12
1
LINE12Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE13
Drive of PIO Line 13
13
1
LINE13Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE14
Drive of PIO Line 14
14
1
LINE14Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE15
Drive of PIO Line 15
15
1
LINE15Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE16
Drive of PIO Line 16
16
1
LINE16Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE17
Drive of PIO Line 17
17
1
LINE17Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE18
Drive of PIO Line 18
18
1
LINE18Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE19
Drive of PIO Line 19
19
1
LINE19Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE20
Drive of PIO Line 20
20
1
LINE20Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE21
Drive of PIO Line 21
21
1
LINE21Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE22
Drive of PIO Line 22
22
1
LINE22Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE23
Drive of PIO Line 23
23
1
LINE23Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE24
Drive of PIO Line 24
24
1
LINE24Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE25
Drive of PIO Line 25
25
1
LINE25Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE26
Drive of PIO Line 26
26
1
LINE26Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE27
Drive of PIO Line 27
27
1
LINE27Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE28
Drive of PIO Line 28
28
1
LINE28Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE29
Drive of PIO Line 29
29
1
LINE29Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE30
Drive of PIO Line 30
30
1
LINE30Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE31
Drive of PIO Line 31
31
1
LINE31Select
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
PCMR
Parallel Capture Mode Register
0x0150
32
PCEN
Parallel Capture Mode Enable
0
1
DSIZE
Parallel Capture Mode Data Size
4
2
DSIZESelect
BYTE
The reception data in the PIO_PCRHR is a byte (8-bit)
0x0
HALFWORD
The reception data in the PIO_PCRHR is a half-word (16-bit)
0x1
WORD
The reception data in the PIO_PCRHR is a word (32-bit)
0x2
ALWYS
Parallel Capture Mode Always Sampling
9
1
HALFS
Parallel Capture Mode Half Sampling
10
1
FRSTS
Parallel Capture Mode First Sample
11
1
PCIER
Parallel Capture Interrupt Enable Register
0x0154
32
write-only
DRDY
Parallel Capture Mode Data Ready Interrupt Enable
0
1
OVRE
Parallel Capture Mode Overrun Error Interrupt Enable
1
1
ENDRX
End of Reception Transfer Interrupt Enable
2
1
RXBUFF
Reception Buffer Full Interrupt Enable
3
1
PCIDR
Parallel Capture Interrupt Disable Register
0x0158
32
write-only
DRDY
Parallel Capture Mode Data Ready Interrupt Disable
0
1
OVRE
Parallel Capture Mode Overrun Error Interrupt Disable
1
1
ENDRX
End of Reception Transfer Interrupt Disable
2
1
RXBUFF
Reception Buffer Full Interrupt Disable
3
1
PCIMR
Parallel Capture Interrupt Mask Register
0x015C
32
read-only
DRDY
Parallel Capture Mode Data Ready Interrupt Mask
0
1
OVRE
Parallel Capture Mode Overrun Error Interrupt Mask
1
1
ENDRX
End of Reception Transfer Interrupt Mask
2
1
RXBUFF
Reception Buffer Full Interrupt Mask
3
1
PCISR
Parallel Capture Interrupt Status Register
0x0160
32
read-only
DRDY
Parallel Capture Mode Data Ready
0
1
OVRE
Parallel Capture Mode Overrun Error
1
1
PCRHR
Parallel Capture Reception Holding Register
0x0164
32
read-only
RDATA
Parallel Capture Mode Reception Data
0
32
PIOB
0x400E1000
PIOB
11
PIOD
0x400E1400
PIOD
16
PMC
44006P
Power Management Controller
0x400E0600
0
0x148
registers
PMC
5
SCER
System Clock Enable Register
0x0000
32
write-only
USBCLK
Enable USB FS Clock
5
1
PCK0
Programmable Clock 0 Output Enable
8
1
PCK1
Programmable Clock 1 Output Enable
9
1
PCK2
Programmable Clock 2 Output Enable
10
1
PCK3
Programmable Clock 3 Output Enable
11
1
PCK4
Programmable Clock 4 Output Enable
12
1
PCK5
Programmable Clock 5 Output Enable
13
1
PCK6
Programmable Clock 6 Output Enable
14
1
PCK7
Programmable Clock 7 Output Enable
15
1
SCDR
System Clock Disable Register
0x0004
32
write-only
USBCLK
Disable USB FS Clock
5
1
PCK0
Programmable Clock 0 Output Disable
8
1
PCK1
Programmable Clock 1 Output Disable
9
1
PCK2
Programmable Clock 2 Output Disable
10
1
PCK3
Programmable Clock 3 Output Disable
11
1
PCK4
Programmable Clock 4 Output Disable
12
1
PCK5
Programmable Clock 5 Output Disable
13
1
PCK6
Programmable Clock 6 Output Disable
14
1
PCK7
Programmable Clock 7 Output Disable
15
1
SCSR
System Clock Status Register
0x0008
32
read-only
HCLKS
HCLK Status
0
1
USBCLK
USB FS Clock Status
5
1
PCK0
Programmable Clock 0 Output Status
8
1
PCK1
Programmable Clock 1 Output Status
9
1
PCK2
Programmable Clock 2 Output Status
10
1
PCK3
Programmable Clock 3 Output Status
11
1
PCK4
Programmable Clock 4 Output Status
12
1
PCK5
Programmable Clock 5 Output Status
13
1
PCK6
Programmable Clock 6 Output Status
14
1
PCK7
Programmable Clock 7 Output Status
15
1
PCER0
Peripheral Clock Enable Register 0
0x0010
32
write-only
PID7
Peripheral Clock 7 Enable
7
1
PID8
Peripheral Clock 8 Enable
8
1
PID10
Peripheral Clock 10 Enable
10
1
PID11
Peripheral Clock 11 Enable
11
1
PID13
Peripheral Clock 13 Enable
13
1
PID14
Peripheral Clock 14 Enable
14
1
PID15
Peripheral Clock 15 Enable
15
1
PID16
Peripheral Clock 16 Enable
16
1
PID18
Peripheral Clock 18 Enable
18
1
PID19
Peripheral Clock 19 Enable
19
1
PID20
Peripheral Clock 20 Enable
20
1
PID21
Peripheral Clock 21 Enable
21
1
PID22
Peripheral Clock 22 Enable
22
1
PID23
Peripheral Clock 23 Enable
23
1
PID24
Peripheral Clock 24 Enable
24
1
PID25
Peripheral Clock 25 Enable
25
1
PID26
Peripheral Clock 26 Enable
26
1
PID27
Peripheral Clock 27 Enable
27
1
PID28
Peripheral Clock 28 Enable
28
1
PID29
Peripheral Clock 29 Enable
29
1
PID30
Peripheral Clock 30 Enable
30
1
PID31
Peripheral Clock 31 Enable
31
1
PCDR0
Peripheral Clock Disable Register 0
0x0014
32
write-only
PID7
Peripheral Clock 7 Disable
7
1
PID8
Peripheral Clock 8 Disable
8
1
PID10
Peripheral Clock 10 Disable
10
1
PID11
Peripheral Clock 11 Disable
11
1
PID13
Peripheral Clock 13 Disable
13
1
PID14
Peripheral Clock 14 Disable
14
1
PID15
Peripheral Clock 15 Disable
15
1
PID16
Peripheral Clock 16 Disable
16
1
PID18
Peripheral Clock 18 Disable
18
1
PID19
Peripheral Clock 19 Disable
19
1
PID20
Peripheral Clock 20 Disable
20
1
PID21
Peripheral Clock 21 Disable
21
1
PID22
Peripheral Clock 22 Disable
22
1
PID23
Peripheral Clock 23 Disable
23
1
PID24
Peripheral Clock 24 Disable
24
1
PID25
Peripheral Clock 25 Disable
25
1
PID26
Peripheral Clock 26 Disable
26
1
PID27
Peripheral Clock 27 Disable
27
1
PID28
Peripheral Clock 28 Disable
28
1
PID29
Peripheral Clock 29 Disable
29
1
PID30
Peripheral Clock 30 Disable
30
1
PID31
Peripheral Clock 31 Disable
31
1
PCSR0
Peripheral Clock Status Register 0
0x0018
32
read-only
PID7
Peripheral Clock 7 Status
7
1
PID8
Peripheral Clock 8 Status
8
1
PID10
Peripheral Clock 10 Status
10
1
PID11
Peripheral Clock 11 Status
11
1
PID13
Peripheral Clock 13 Status
13
1
PID14
Peripheral Clock 14 Status
14
1
PID15
Peripheral Clock 15 Status
15
1
PID16
Peripheral Clock 16 Status
16
1
PID18
Peripheral Clock 18 Status
18
1
PID19
Peripheral Clock 19 Status
19
1
PID20
Peripheral Clock 20 Status
20
1
PID21
Peripheral Clock 21 Status
21
1
PID22
Peripheral Clock 22 Status
22
1
PID23
Peripheral Clock 23 Status
23
1
PID24
Peripheral Clock 24 Status
24
1
PID25
Peripheral Clock 25 Status
25
1
PID26
Peripheral Clock 26 Status
26
1
PID27
Peripheral Clock 27 Status
27
1
PID28
Peripheral Clock 28 Status
28
1
PID29
Peripheral Clock 29 Status
29
1
PID30
Peripheral Clock 30 Status
30
1
PID31
Peripheral Clock 31 Status
31
1
CKGR_UCKR
UTMI Clock Register
0x001C
32
UPLLEN
UTMI PLL Enable
16
1
UPLLCOUNT
UTMI PLL Start-up Time
20
4
CKGR_MOR
Main Oscillator Register
0x0020
32
MOSCXTEN
Main Crystal Oscillator Enable
0
1
MOSCXTBY
Main Crystal Oscillator Bypass
1
1
WAITMODE
Wait Mode Command (Write-only)
2
1
MOSCRCEN
Main RC Oscillator Enable
3
1
MOSCRCF
Main RC Oscillator Frequency Selection
4
3
MOSCRCFSelect
_4_MHz
The RC oscillator frequency is at 4 MHz
0x0
_8_MHz
The RC oscillator frequency is at 8 MHz
0x1
_12_MHz
The RC oscillator frequency is at 12 MHz
0x2
MOSCXTST
Main Crystal Oscillator Startup Time
8
8
KEY
Write Access Password
16
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
0x37
MOSCSEL
Main Clock Oscillator Selection
24
1
CFDEN
Clock Failure Detector Enable
25
1
XT32KFME
32.768 kHz Crystal Oscillator Frequency Monitoring Enable
26
1
CKGR_MCFR
Main Clock Frequency Register
0x0024
32
MAINF
Main Clock Frequency
0
16
MAINFRDY
Main Clock Frequency Measure Ready
16
1
RCMEAS
RC Oscillator Frequency Measure (write-only)
20
1
CCSS
Counter Clock Source Selection
24
1
CKGR_PLLAR
PLLA Register
0x0028
32
DIVA
PLLA Front End Divider
0
8
DIVASelect
_0
Divider output is 0 and PLLA is disabled.
0
BYPASS
Divider is bypassed (divide by 1) and PLLA is enabled.
1
PLLACOUNT
PLLA Counter
8
6
MULA
PLLA Multiplier
16
11
ONE
Must Be Set to 1
29
1
MCKR
Master Clock Register
0x0030
32
CSS
Master Clock Source Selection
0
2
CSSSelect
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
UPLL_CLK
Divided UPLL Clock is selected
0x3
PRES
Processor Clock Prescaler
4
3
PRESSelect
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
CLK_3
Selected clock divided by 3
0x7
MDIV
Master Clock Division
8
2
MDIVSelect
EQ_PCK
Master Clock is Prescaler Output Clock divided by 1.
0x0
PCK_DIV2
Master Clock is Prescaler Output Clock divided by 2.
0x1
PCK_DIV4
Master Clock is Prescaler Output Clock divided by 4.
0x2
PCK_DIV3
Master Clock is Prescaler Output Clock divided by 3.
0x3
UPLLDIV2
UPLL Divider by 2
13
1
USB
USB Clock Register
0x0038
32
USBS
USB Input Clock Selection
0
1
USBDIV
Divider for USB_48M
8
4
8
4
PCK[%s]
Programmable Clock Register
0x40
32
CSS
Programmable Clock Source Selection
0
3
CSSSelect
SLOW_CLK
SLCK is selected
0x0
MAIN_CLK
MAINCK is selected
0x1
PLLA_CLK
PLLACK is selected
0x2
UPLL_CLK
UPLLCKDIV is selected
0x3
MCK
MCK is selected
0x4
PRES
Programmable Clock Prescaler
4
8
IER
Interrupt Enable Register
0x0060
32
write-only
MOSCXTS
Main Crystal Oscillator Status Interrupt Enable
0
1
LOCKA
PLLA Lock Interrupt Enable
1
1
MCKRDY
Master Clock Ready Interrupt Enable
3
1
LOCKU
UTMI PLL Lock Interrupt Enable
6
1
PCKRDY0
Programmable Clock Ready 0 Interrupt Enable
8
1
PCKRDY1
Programmable Clock Ready 1 Interrupt Enable
9
1
PCKRDY2
Programmable Clock Ready 2 Interrupt Enable
10
1
PCKRDY3
Programmable Clock Ready 3 Interrupt Enable
11
1
PCKRDY4
Programmable Clock Ready 4 Interrupt Enable
12
1
PCKRDY5
Programmable Clock Ready 5 Interrupt Enable
13
1
PCKRDY6
Programmable Clock Ready 6 Interrupt Enable
14
1
PCKRDY7
Programmable Clock Ready 7 Interrupt Enable
15
1
MOSCSELS
Main Clock Source Oscillator Selection Status Interrupt Enable
16
1
MOSCRCS
Main RC Oscillator Status Interrupt Enable
17
1
CFDEV
Clock Failure Detector Event Interrupt Enable
18
1
XT32KERR
32.768 kHz Crystal Oscillator Error Interrupt Enable
21
1
IDR
Interrupt Disable Register
0x0064
32
write-only
MOSCXTS
Main Crystal Oscillator Status Interrupt Disable
0
1
LOCKA
PLLA Lock Interrupt Disable
1
1
MCKRDY
Master Clock Ready Interrupt Disable
3
1
LOCKU
UTMI PLL Lock Interrupt Disable
6
1
PCKRDY0
Programmable Clock Ready 0 Interrupt Disable
8
1
PCKRDY1
Programmable Clock Ready 1 Interrupt Disable
9
1
PCKRDY2
Programmable Clock Ready 2 Interrupt Disable
10
1
PCKRDY3
Programmable Clock Ready 3 Interrupt Disable
11
1
PCKRDY4
Programmable Clock Ready 4 Interrupt Disable
12
1
PCKRDY5
Programmable Clock Ready 5 Interrupt Disable
13
1
PCKRDY6
Programmable Clock Ready 6 Interrupt Disable
14
1
PCKRDY7
Programmable Clock Ready 7 Interrupt Disable
15
1
MOSCSELS
Main Clock Source Oscillator Selection Status Interrupt Disable
16
1
MOSCRCS
Main RC Status Interrupt Disable
17
1
CFDEV
Clock Failure Detector Event Interrupt Disable
18
1
XT32KERR
32.768 kHz Crystal Oscillator Error Interrupt Disable
21
1
SR
Status Register
0x0068
32
read-only
MOSCXTS
Main Crystal Oscillator Status
0
1
LOCKA
PLLA Lock Status
1
1
MCKRDY
Master Clock Status
3
1
LOCKU
UTMI PLL Lock Status
6
1
OSCSELS
Slow Clock Source Oscillator Selection
7
1
PCKRDY0
Programmable Clock Ready 0 Status
8
1
PCKRDY1
Programmable Clock Ready 1 Status
9
1
PCKRDY2
Programmable Clock Ready 2 Status
10
1
PCKRDY3
Programmable Clock Ready 3 Status
11
1
PCKRDY4
Programmable Clock Ready 4 Status
12
1
PCKRDY5
Programmable Clock Ready 5 Status
13
1
PCKRDY6
Programmable Clock Ready 6 Status
14
1
PCKRDY7
Programmable Clock Ready 7 Status
15
1
MOSCSELS
Main Clock Source Oscillator Selection Status
16
1
MOSCRCS
Main RC Oscillator Status
17
1
CFDEV
Clock Failure Detector Event
18
1
CFDS
Clock Failure Detector Status
19
1
FOS
Clock Failure Detector Fault Output Status
20
1
XT32KERR
Slow Crystal Oscillator Error
21
1
IMR
Interrupt Mask Register
0x006C
32
read-only
MOSCXTS
Main Crystal Oscillator Status Interrupt Mask
0
1
LOCKA
PLLA Lock Interrupt Mask
1
1
MCKRDY
Master Clock Ready Interrupt Mask
3
1
LOCKU
UTMI PLL Lock Interrupt Mask
6
1
PCKRDY0
Programmable Clock Ready 0 Interrupt Mask
8
1
PCKRDY1
Programmable Clock Ready 1 Interrupt Mask
9
1
PCKRDY2
Programmable Clock Ready 2 Interrupt Mask
10
1
PCKRDY3
Programmable Clock Ready 3 Interrupt Mask
11
1
PCKRDY4
Programmable Clock Ready 4 Interrupt Mask
12
1
PCKRDY5
Programmable Clock Ready 5 Interrupt Mask
13
1
PCKRDY6
Programmable Clock Ready 6 Interrupt Mask
14
1
PCKRDY7
Programmable Clock Ready 7 Interrupt Mask
15
1
MOSCSELS
Main Clock Source Oscillator Selection Status Interrupt Mask
16
1
MOSCRCS
Main RC Status Interrupt Mask
17
1
CFDEV
Clock Failure Detector Event Interrupt Mask
18
1
XT32KERR
32.768 kHz Crystal Oscillator Error Interrupt Mask
21
1
FSMR
Fast Startup Mode Register
0x0070
32
FSTT0
Fast Startup Input Enable 0
0
1
FSTT1
Fast Startup Input Enable 1
1
1
FSTT2
Fast Startup Input Enable 2
2
1
FSTT3
Fast Startup Input Enable 3
3
1
FSTT4
Fast Startup Input Enable 4
4
1
FSTT5
Fast Startup Input Enable 5
5
1
FSTT6
Fast Startup Input Enable 6
6
1
FSTT7
Fast Startup Input Enable 7
7
1
FSTT8
Fast Startup Input Enable 8
8
1
FSTT9
Fast Startup Input Enable 9
9
1
FSTT10
Fast Startup Input Enable 10
10
1
FSTT11
Fast Startup Input Enable 11
11
1
FSTT12
Fast Startup Input Enable 12
12
1
FSTT13
Fast Startup Input Enable 13
13
1
FSTT14
Fast Startup Input Enable 14
14
1
FSTT15
Fast Startup Input Enable 15
15
1
RTTAL
RTT Alarm Enable
16
1
RTCAL
RTC Alarm Enable
17
1
USBAL
USB Alarm Enable
18
1
LPM
Low-power Mode
20
1
FLPM
Flash Low-power Mode
21
2
FLPMSelect
FLASH_STANDBY
Flash is in Standby Mode when system enters Wait Mode
0x0
FLASH_DEEP_POWERDOWN
Flash is in Deep-power-down mode when system enters Wait Mode
0x1
FLASH_IDLE
Idle mode
0x2
FFLPM
Force Flash Low-power Mode
23
1
FSPR
Fast Startup Polarity Register
0x0074
32
FSTP0
Fast Startup Input Polarity 0
0
1
FSTP1
Fast Startup Input Polarity 1
1
1
FSTP2
Fast Startup Input Polarity 2
2
1
FSTP3
Fast Startup Input Polarity 3
3
1
FSTP4
Fast Startup Input Polarity 4
4
1
FSTP5
Fast Startup Input Polarity 5
5
1
FSTP6
Fast Startup Input Polarity 6
6
1
FSTP7
Fast Startup Input Polarity 7
7
1
FSTP8
Fast Startup Input Polarity 8
8
1
FSTP9
Fast Startup Input Polarity 9
9
1
FSTP10
Fast Startup Input Polarity 10
10
1
FSTP11
Fast Startup Input Polarity 11
11
1
FSTP12
Fast Startup Input Polarity 12
12
1
FSTP13
Fast Startup Input Polarity 13
13
1
FSTP14
Fast Startup Input Polarity 14
14
1
FSTP15
Fast Startup Input Polarity 15
15
1
FOCR
Fault Output Clear Register
0x0078
32
write-only
FOCLR
Fault Output Clear
0
1
WPMR
Write Protection Mode Register
0x00E4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x504D43
WPSR
Write Protection Status Register
0x00E8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
16
PCER1
Peripheral Clock Enable Register 1
0x0100
32
write-only
PID32
Peripheral Clock 32 Enable
0
1
PID33
Peripheral Clock 33 Enable
1
1
PID34
Peripheral Clock 34 Enable
2
1
PID35
Peripheral Clock 35 Enable
3
1
PID37
Peripheral Clock 37 Enable
5
1
PID39
Peripheral Clock 39 Enable
7
1
PID40
Peripheral Clock 40 Enable
8
1
PID41
Peripheral Clock 41 Enable
9
1
PID43
Peripheral Clock 43 Enable
11
1
PID44
Peripheral Clock 44 Enable
12
1
PID45
Peripheral Clock 45 Enable
13
1
PID46
Peripheral Clock 46 Enable
14
1
PID47
Peripheral Clock 47 Enable
15
1
PID48
Peripheral Clock 48 Enable
16
1
PID49
Peripheral Clock 49 Enable
17
1
PID50
Peripheral Clock 50 Enable
18
1
PID51
Peripheral Clock 51 Enable
19
1
PID52
Peripheral Clock 52 Enable
20
1
PID56
Peripheral Clock 56 Enable
24
1
PID57
Peripheral Clock 57 Enable
25
1
PID58
Peripheral Clock 58 Enable
26
1
PID59
Peripheral Clock 59 Enable
27
1
PID60
Peripheral Clock 60 Enable
28
1
PCDR1
Peripheral Clock Disable Register 1
0x0104
32
write-only
PID32
Peripheral Clock 32 Disable
0
1
PID33
Peripheral Clock 33 Disable
1
1
PID34
Peripheral Clock 34 Disable
2
1
PID35
Peripheral Clock 35 Disable
3
1
PID37
Peripheral Clock 37 Disable
5
1
PID39
Peripheral Clock 39 Disable
7
1
PID40
Peripheral Clock 40 Disable
8
1
PID41
Peripheral Clock 41 Disable
9
1
PID43
Peripheral Clock 43 Disable
11
1
PID44
Peripheral Clock 44 Disable
12
1
PID45
Peripheral Clock 45 Disable
13
1
PID46
Peripheral Clock 46 Disable
14
1
PID47
Peripheral Clock 47 Disable
15
1
PID48
Peripheral Clock 48 Disable
16
1
PID49
Peripheral Clock 49 Disable
17
1
PID50
Peripheral Clock 50 Disable
18
1
PID51
Peripheral Clock 51 Disable
19
1
PID52
Peripheral Clock 52 Disable
20
1
PID56
Peripheral Clock 56 Disable
24
1
PID57
Peripheral Clock 57 Disable
25
1
PID58
Peripheral Clock 58 Disable
26
1
PID59
Peripheral Clock 59 Disable
27
1
PID60
Peripheral Clock 60 Disable
28
1
PCSR1
Peripheral Clock Status Register 1
0x0108
32
read-only
PID32
Peripheral Clock 32 Status
0
1
PID33
Peripheral Clock 33 Status
1
1
PID34
Peripheral Clock 34 Status
2
1
PID35
Peripheral Clock 35 Status
3
1
PID37
Peripheral Clock 37 Status
5
1
PID39
Peripheral Clock 39 Status
7
1
PID40
Peripheral Clock 40 Status
8
1
PID41
Peripheral Clock 41 Status
9
1
PID43
Peripheral Clock 43 Status
11
1
PID44
Peripheral Clock 44 Status
12
1
PID45
Peripheral Clock 45 Status
13
1
PID46
Peripheral Clock 46 Status
14
1
PID47
Peripheral Clock 47 Status
15
1
PID48
Peripheral Clock 48 Status
16
1
PID49
Peripheral Clock 49 Status
17
1
PID50
Peripheral Clock 50 Status
18
1
PID51
Peripheral Clock 51 Status
19
1
PID52
Peripheral Clock 52 Status
20
1
PID56
Peripheral Clock 56 Status
24
1
PID57
Peripheral Clock 57 Status
25
1
PID58
Peripheral Clock 58 Status
26
1
PID59
Peripheral Clock 59 Status
27
1
PID60
Peripheral Clock 60 Status
28
1
PCR
Peripheral Control Register
0x010C
32
PID
Peripheral ID
0
7
GCLKCSS
Generic Clock Source Selection
8
3
GCLKCSSSelect
SLOW_CLK
Slow clock is selected
0x0
MAIN_CLK
Main clock is selected
0x1
PLLA_CLK
PLLACK is selected
0x2
UPLL_CLK
UPLL Clock is selected
0x3
MCK_CLK
Master Clock is selected
0x4
CMD
Command
12
1
GCLKDIV
Generic Clock Division Ratio
20
8
EN
Enable
28
1
GCLKEN
Generic Clock Enable
29
1
OCR
Oscillator Calibration Register
0x0110
32
CAL4
Main RC Oscillator Calibration Bits for 4 MHz
0
7
SEL4
Selection of Main RC Oscillator Calibration Bits for 4 MHz
7
1
CAL8
Main RC Oscillator Calibration Bits for 8 MHz
8
7
SEL8
Selection of Main RC Oscillator Calibration Bits for 8 MHz
15
1
CAL12
Main RC Oscillator Calibration Bits for 12 MHz
16
7
SEL12
Selection of Main RC Oscillator Calibration Bits for 12 MHz
23
1
SLPWK_ER0
SleepWalking Enable Register 0
0x0114
32
write-only
PID7
Peripheral 7 SleepWalking Enable
7
1
PID8
Peripheral 8 SleepWalking Enable
8
1
PID10
Peripheral 10 SleepWalking Enable
10
1
PID11
Peripheral 11 SleepWalking Enable
11
1
PID13
Peripheral 13 SleepWalking Enable
13
1
PID14
Peripheral 14 SleepWalking Enable
14
1
PID15
Peripheral 15 SleepWalking Enable
15
1
PID16
Peripheral 16 SleepWalking Enable
16
1
PID18
Peripheral 18 SleepWalking Enable
18
1
PID19
Peripheral 19 SleepWalking Enable
19
1
PID20
Peripheral 20 SleepWalking Enable
20
1
PID21
Peripheral 21 SleepWalking Enable
21
1
PID22
Peripheral 22 SleepWalking Enable
22
1
PID23
Peripheral 23 SleepWalking Enable
23
1
PID24
Peripheral 24 SleepWalking Enable
24
1
PID25
Peripheral 25 SleepWalking Enable
25
1
PID26
Peripheral 26 SleepWalking Enable
26
1
PID27
Peripheral 27 SleepWalking Enable
27
1
PID28
Peripheral 28 SleepWalking Enable
28
1
PID29
Peripheral 29 SleepWalking Enable
29
1
PID30
Peripheral 30 SleepWalking Enable
30
1
PID31
Peripheral 31 SleepWalking Enable
31
1
SLPWK_DR0
SleepWalking Disable Register 0
0x0118
32
write-only
PID7
Peripheral 7 SleepWalking Disable
7
1
PID8
Peripheral 8 SleepWalking Disable
8
1
PID10
Peripheral 10 SleepWalking Disable
10
1
PID11
Peripheral 11 SleepWalking Disable
11
1
PID13
Peripheral 13 SleepWalking Disable
13
1
PID14
Peripheral 14 SleepWalking Disable
14
1
PID15
Peripheral 15 SleepWalking Disable
15
1
PID16
Peripheral 16 SleepWalking Disable
16
1
PID18
Peripheral 18 SleepWalking Disable
18
1
PID19
Peripheral 19 SleepWalking Disable
19
1
PID20
Peripheral 20 SleepWalking Disable
20
1
PID21
Peripheral 21 SleepWalking Disable
21
1
PID22
Peripheral 22 SleepWalking Disable
22
1
PID23
Peripheral 23 SleepWalking Disable
23
1
PID24
Peripheral 24 SleepWalking Disable
24
1
PID25
Peripheral 25 SleepWalking Disable
25
1
PID26
Peripheral 26 SleepWalking Disable
26
1
PID27
Peripheral 27 SleepWalking Disable
27
1
PID28
Peripheral 28 SleepWalking Disable
28
1
PID29
Peripheral 29 SleepWalking Disable
29
1
PID30
Peripheral 30 SleepWalking Disable
30
1
PID31
Peripheral 31 SleepWalking Disable
31
1
SLPWK_SR0
SleepWalking Status Register 0
0x011C
32
read-only
PID7
Peripheral 7 SleepWalking Status
7
1
PID8
Peripheral 8 SleepWalking Status
8
1
PID10
Peripheral 10 SleepWalking Status
10
1
PID11
Peripheral 11 SleepWalking Status
11
1
PID13
Peripheral 13 SleepWalking Status
13
1
PID14
Peripheral 14 SleepWalking Status
14
1
PID15
Peripheral 15 SleepWalking Status
15
1
PID16
Peripheral 16 SleepWalking Status
16
1
PID18
Peripheral 18 SleepWalking Status
18
1
PID19
Peripheral 19 SleepWalking Status
19
1
PID20
Peripheral 20 SleepWalking Status
20
1
PID21
Peripheral 21 SleepWalking Status
21
1
PID22
Peripheral 22 SleepWalking Status
22
1
PID23
Peripheral 23 SleepWalking Status
23
1
PID24
Peripheral 24 SleepWalking Status
24
1
PID25
Peripheral 25 SleepWalking Status
25
1
PID26
Peripheral 26 SleepWalking Status
26
1
PID27
Peripheral 27 SleepWalking Status
27
1
PID28
Peripheral 28 SleepWalking Status
28
1
PID29
Peripheral 29 SleepWalking Status
29
1
PID30
Peripheral 30 SleepWalking Status
30
1
PID31
Peripheral 31 SleepWalking Status
31
1
SLPWK_ASR0
SleepWalking Activity Status Register 0
0x0120
32
read-only
PID7
Peripheral 7 Activity Status
7
1
PID8
Peripheral 8 Activity Status
8
1
PID10
Peripheral 10 Activity Status
10
1
PID11
Peripheral 11 Activity Status
11
1
PID13
Peripheral 13 Activity Status
13
1
PID14
Peripheral 14 Activity Status
14
1
PID15
Peripheral 15 Activity Status
15
1
PID16
Peripheral 16 Activity Status
16
1
PID18
Peripheral 18 Activity Status
18
1
PID19
Peripheral 19 Activity Status
19
1
PID20
Peripheral 20 Activity Status
20
1
PID21
Peripheral 21 Activity Status
21
1
PID22
Peripheral 22 Activity Status
22
1
PID23
Peripheral 23 Activity Status
23
1
PID24
Peripheral 24 Activity Status
24
1
PID25
Peripheral 25 Activity Status
25
1
PID26
Peripheral 26 Activity Status
26
1
PID27
Peripheral 27 Activity Status
27
1
PID28
Peripheral 28 Activity Status
28
1
PID29
Peripheral 29 Activity Status
29
1
PID30
Peripheral 30 Activity Status
30
1
PID31
Peripheral 31 Activity Status
31
1
PMMR
PLL Maximum Multiplier Value Register
0x0130
32
PLLA_MMAX
PLLA Maximum Allowed Multiplier Value
0
11
SLPWK_ER1
SleepWalking Enable Register 1
0x0134
32
write-only
PID32
Peripheral 32 SleepWalking Enable
0
1
PID33
Peripheral 33 SleepWalking Enable
1
1
PID34
Peripheral 34 SleepWalking Enable
2
1
PID35
Peripheral 35 SleepWalking Enable
3
1
PID37
Peripheral 37 SleepWalking Enable
5
1
PID39
Peripheral 39 SleepWalking Enable
7
1
PID40
Peripheral 40 SleepWalking Enable
8
1
PID41
Peripheral 41 SleepWalking Enable
9
1
PID43
Peripheral 43 SleepWalking Enable
11
1
PID44
Peripheral 44 SleepWalking Enable
12
1
PID45
Peripheral 45 SleepWalking Enable
13
1
PID46
Peripheral 46 SleepWalking Enable
14
1
PID47
Peripheral 47 SleepWalking Enable
15
1
PID48
Peripheral 48 SleepWalking Enable
16
1
PID49
Peripheral 49 SleepWalking Enable
17
1
PID50
Peripheral 50 SleepWalking Enable
18
1
PID51
Peripheral 51 SleepWalking Enable
19
1
PID52
Peripheral 52 SleepWalking Enable
20
1
PID56
Peripheral 56 SleepWalking Enable
24
1
PID57
Peripheral 57 SleepWalking Enable
25
1
PID58
Peripheral 58 SleepWalking Enable
26
1
PID59
Peripheral 59 SleepWalking Enable
27
1
PID60
Peripheral 60 SleepWalking Enable
28
1
SLPWK_DR1
SleepWalking Disable Register 1
0x0138
32
write-only
PID32
Peripheral 32 SleepWalking Disable
0
1
PID33
Peripheral 33 SleepWalking Disable
1
1
PID34
Peripheral 34 SleepWalking Disable
2
1
PID35
Peripheral 35 SleepWalking Disable
3
1
PID37
Peripheral 37 SleepWalking Disable
5
1
PID39
Peripheral 39 SleepWalking Disable
7
1
PID40
Peripheral 40 SleepWalking Disable
8
1
PID41
Peripheral 41 SleepWalking Disable
9
1
PID43
Peripheral 43 SleepWalking Disable
11
1
PID44
Peripheral 44 SleepWalking Disable
12
1
PID45
Peripheral 45 SleepWalking Disable
13
1
PID46
Peripheral 46 SleepWalking Disable
14
1
PID47
Peripheral 47 SleepWalking Disable
15
1
PID48
Peripheral 48 SleepWalking Disable
16
1
PID49
Peripheral 49 SleepWalking Disable
17
1
PID50
Peripheral 50 SleepWalking Disable
18
1
PID51
Peripheral 51 SleepWalking Disable
19
1
PID52
Peripheral 52 SleepWalking Disable
20
1
PID56
Peripheral 56 SleepWalking Disable
24
1
PID57
Peripheral 57 SleepWalking Disable
25
1
PID58
Peripheral 58 SleepWalking Disable
26
1
PID59
Peripheral 59 SleepWalking Disable
27
1
PID60
Peripheral 60 SleepWalking Disable
28
1
SLPWK_SR1
SleepWalking Status Register 1
0x013C
32
read-only
PID32
Peripheral 32 SleepWalking Status
0
1
PID33
Peripheral 33 SleepWalking Status
1
1
PID34
Peripheral 34 SleepWalking Status
2
1
PID35
Peripheral 35 SleepWalking Status
3
1
PID37
Peripheral 37 SleepWalking Status
5
1
PID39
Peripheral 39 SleepWalking Status
7
1
PID40
Peripheral 40 SleepWalking Status
8
1
PID41
Peripheral 41 SleepWalking Status
9
1
PID43
Peripheral 43 SleepWalking Status
11
1
PID44
Peripheral 44 SleepWalking Status
12
1
PID45
Peripheral 45 SleepWalking Status
13
1
PID46
Peripheral 46 SleepWalking Status
14
1
PID47
Peripheral 47 SleepWalking Status
15
1
PID48
Peripheral 48 SleepWalking Status
16
1
PID49
Peripheral 49 SleepWalking Status
17
1
PID50
Peripheral 50 SleepWalking Status
18
1
PID51
Peripheral 51 SleepWalking Status
19
1
PID52
Peripheral 52 SleepWalking Status
20
1
PID56
Peripheral 56 SleepWalking Status
24
1
PID57
Peripheral 57 SleepWalking Status
25
1
PID58
Peripheral 58 SleepWalking Status
26
1
PID59
Peripheral 59 SleepWalking Status
27
1
PID60
Peripheral 60 SleepWalking Status
28
1
SLPWK_ASR1
SleepWalking Activity Status Register 1
0x0140
32
read-only
PID32
Peripheral 32 Activity Status
0
1
PID33
Peripheral 33 Activity Status
1
1
PID34
Peripheral 34 Activity Status
2
1
PID35
Peripheral 35 Activity Status
3
1
PID37
Peripheral 37 Activity Status
5
1
PID39
Peripheral 39 Activity Status
7
1
PID40
Peripheral 40 Activity Status
8
1
PID41
Peripheral 41 Activity Status
9
1
PID43
Peripheral 43 Activity Status
11
1
PID44
Peripheral 44 Activity Status
12
1
PID45
Peripheral 45 Activity Status
13
1
PID46
Peripheral 46 Activity Status
14
1
PID47
Peripheral 47 Activity Status
15
1
PID48
Peripheral 48 Activity Status
16
1
PID49
Peripheral 49 Activity Status
17
1
PID50
Peripheral 50 Activity Status
18
1
PID51
Peripheral 51 Activity Status
19
1
PID52
Peripheral 52 Activity Status
20
1
PID56
Peripheral 56 Activity Status
24
1
PID57
Peripheral 57 Activity Status
25
1
PID58
Peripheral 58 Activity Status
26
1
PID59
Peripheral 59 Activity Status
27
1
PID60
Peripheral 60 Activity Status
28
1
SLPWK_AIPR
SleepWalking Activity In Progress Register
0x0144
32
read-only
AIP
Activity In Progress
0
1
PWM0
6343Y
Pulse Width Modulation Controller
PWM
PWM_
0x40020000
0
0x464
registers
PWM0
31
CLK
PWM Clock Register
0x00
32
DIVA
CLKA Divide Factor
0
8
DIVASelect
CLKA_POFF
CLKA clock is turned off
0
PREA
CLKA clock is clock selected by PREA
1
PREA
CLKA Source Clock Selection
8
4
PREASelect
CLK
Peripheral clock
0x0
CLK_DIV2
Peripheral clock/2
0x1
CLK_DIV4
Peripheral clock/4
0x2
CLK_DIV8
Peripheral clock/8
0x3
CLK_DIV16
Peripheral clock/16
0x4
CLK_DIV32
Peripheral clock/32
0x5
CLK_DIV64
Peripheral clock/64
0x6
CLK_DIV128
Peripheral clock/128
0x7
CLK_DIV256
Peripheral clock/256
0x8
CLK_DIV512
Peripheral clock/512
0x9
CLK_DIV1024
Peripheral clock/1024
0xA
DIVB
CLKB Divide Factor
16
8
DIVBSelect
CLKB_POFF
CLKB clock is turned off
0
PREB
CLKB clock is clock selected by PREB
1
PREB
CLKB Source Clock Selection
24
4
PREBSelect
CLK
Peripheral clock
0x0
CLK_DIV2
Peripheral clock/2
0x1
CLK_DIV4
Peripheral clock/4
0x2
CLK_DIV8
Peripheral clock/8
0x3
CLK_DIV16
Peripheral clock/16
0x4
CLK_DIV32
Peripheral clock/32
0x5
CLK_DIV64
Peripheral clock/64
0x6
CLK_DIV128
Peripheral clock/128
0x7
CLK_DIV256
Peripheral clock/256
0x8
CLK_DIV512
Peripheral clock/512
0x9
CLK_DIV1024
Peripheral clock/1024
0xA
ENA
PWM Enable Register
0x04
32
write-only
CHID0
Channel ID
0
1
CHID1
Channel ID
1
1
CHID2
Channel ID
2
1
CHID3
Channel ID
3
1
DIS
PWM Disable Register
0x08
32
write-only
CHID0
Channel ID
0
1
CHID1
Channel ID
1
1
CHID2
Channel ID
2
1
CHID3
Channel ID
3
1
SR
PWM Status Register
0x0C
32
read-only
CHID0
Channel ID
0
1
CHID1
Channel ID
1
1
CHID2
Channel ID
2
1
CHID3
Channel ID
3
1
IER1
PWM Interrupt Enable Register 1
0x10
32
write-only
CHID0
Counter Event on Channel 0 Interrupt Enable
0
1
CHID1
Counter Event on Channel 1 Interrupt Enable
1
1
CHID2
Counter Event on Channel 2 Interrupt Enable
2
1
CHID3
Counter Event on Channel 3 Interrupt Enable
3
1
FCHID0
Fault Protection Trigger on Channel 0 Interrupt Enable
16
1
FCHID1
Fault Protection Trigger on Channel 1 Interrupt Enable
17
1
FCHID2
Fault Protection Trigger on Channel 2 Interrupt Enable
18
1
FCHID3
Fault Protection Trigger on Channel 3 Interrupt Enable
19
1
IDR1
PWM Interrupt Disable Register 1
0x14
32
write-only
CHID0
Counter Event on Channel 0 Interrupt Disable
0
1
CHID1
Counter Event on Channel 1 Interrupt Disable
1
1
CHID2
Counter Event on Channel 2 Interrupt Disable
2
1
CHID3
Counter Event on Channel 3 Interrupt Disable
3
1
FCHID0
Fault Protection Trigger on Channel 0 Interrupt Disable
16
1
FCHID1
Fault Protection Trigger on Channel 1 Interrupt Disable
17
1
FCHID2
Fault Protection Trigger on Channel 2 Interrupt Disable
18
1
FCHID3
Fault Protection Trigger on Channel 3 Interrupt Disable
19
1
IMR1
PWM Interrupt Mask Register 1
0x18
32
read-only
CHID0
Counter Event on Channel 0 Interrupt Mask
0
1
CHID1
Counter Event on Channel 1 Interrupt Mask
1
1
CHID2
Counter Event on Channel 2 Interrupt Mask
2
1
CHID3
Counter Event on Channel 3 Interrupt Mask
3
1
FCHID0
Fault Protection Trigger on Channel 0 Interrupt Mask
16
1
FCHID1
Fault Protection Trigger on Channel 1 Interrupt Mask
17
1
FCHID2
Fault Protection Trigger on Channel 2 Interrupt Mask
18
1
FCHID3
Fault Protection Trigger on Channel 3 Interrupt Mask
19
1
ISR1
PWM Interrupt Status Register 1
0x1C
32
read-only
CHID0
Counter Event on Channel 0
0
1
CHID1
Counter Event on Channel 1
1
1
CHID2
Counter Event on Channel 2
2
1
CHID3
Counter Event on Channel 3
3
1
FCHID0
Fault Protection Trigger on Channel 0
16
1
FCHID1
Fault Protection Trigger on Channel 1
17
1
FCHID2
Fault Protection Trigger on Channel 2
18
1
FCHID3
Fault Protection Trigger on Channel 3
19
1
SCM
PWM Sync Channels Mode Register
0x20
32
SYNC0
Synchronous Channel 0
0
1
SYNC1
Synchronous Channel 1
1
1
SYNC2
Synchronous Channel 2
2
1
SYNC3
Synchronous Channel 3
3
1
UPDM
Synchronous Channels Update Mode
16
2
UPDMSelect
MODE0
Manual write of double buffer registers and manual update of synchronous channels
0x0
MODE1
Manual write of double buffer registers and automatic update of synchronous channels
0x1
MODE2
Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels
0x2
PTRM
DMA Controller Transfer Request Mode
20
1
PTRCS
DMA Controller Transfer Request Comparison Selection
21
3
DMAR
PWM DMA Register
0x24
32
write-only
DMADUTY
Duty-Cycle Holding Register for DMA Access
0
24
SCUC
PWM Sync Channels Update Control Register
0x28
32
UPDULOCK
Synchronous Channels Update Unlock
0
1
SCUP
PWM Sync Channels Update Period Register
0x2C
32
UPR
Update Period
0
4
UPRCNT
Update Period Counter
4
4
SCUPUPD
PWM Sync Channels Update Period Update Register
0x30
32
write-only
UPRUPD
Update Period Update
0
4
IER2
PWM Interrupt Enable Register 2
0x34
32
write-only
WRDY
Write Ready for Synchronous Channels Update Interrupt Enable
0
1
UNRE
Synchronous Channels Update Underrun Error Interrupt Enable
3
1
CMPM0
Comparison 0 Match Interrupt Enable
8
1
CMPM1
Comparison 1 Match Interrupt Enable
9
1
CMPM2
Comparison 2 Match Interrupt Enable
10
1
CMPM3
Comparison 3 Match Interrupt Enable
11
1
CMPM4
Comparison 4 Match Interrupt Enable
12
1
CMPM5
Comparison 5 Match Interrupt Enable
13
1
CMPM6
Comparison 6 Match Interrupt Enable
14
1
CMPM7
Comparison 7 Match Interrupt Enable
15
1
CMPU0
Comparison 0 Update Interrupt Enable
16
1
CMPU1
Comparison 1 Update Interrupt Enable
17
1
CMPU2
Comparison 2 Update Interrupt Enable
18
1
CMPU3
Comparison 3 Update Interrupt Enable
19
1
CMPU4
Comparison 4 Update Interrupt Enable
20
1
CMPU5
Comparison 5 Update Interrupt Enable
21
1
CMPU6
Comparison 6 Update Interrupt Enable
22
1
CMPU7
Comparison 7 Update Interrupt Enable
23
1
IDR2
PWM Interrupt Disable Register 2
0x38
32
write-only
WRDY
Write Ready for Synchronous Channels Update Interrupt Disable
0
1
UNRE
Synchronous Channels Update Underrun Error Interrupt Disable
3
1
CMPM0
Comparison 0 Match Interrupt Disable
8
1
CMPM1
Comparison 1 Match Interrupt Disable
9
1
CMPM2
Comparison 2 Match Interrupt Disable
10
1
CMPM3
Comparison 3 Match Interrupt Disable
11
1
CMPM4
Comparison 4 Match Interrupt Disable
12
1
CMPM5
Comparison 5 Match Interrupt Disable
13
1
CMPM6
Comparison 6 Match Interrupt Disable
14
1
CMPM7
Comparison 7 Match Interrupt Disable
15
1
CMPU0
Comparison 0 Update Interrupt Disable
16
1
CMPU1
Comparison 1 Update Interrupt Disable
17
1
CMPU2
Comparison 2 Update Interrupt Disable
18
1
CMPU3
Comparison 3 Update Interrupt Disable
19
1
CMPU4
Comparison 4 Update Interrupt Disable
20
1
CMPU5
Comparison 5 Update Interrupt Disable
21
1
CMPU6
Comparison 6 Update Interrupt Disable
22
1
CMPU7
Comparison 7 Update Interrupt Disable
23
1
IMR2
PWM Interrupt Mask Register 2
0x3C
32
read-only
WRDY
Write Ready for Synchronous Channels Update Interrupt Mask
0
1
UNRE
Synchronous Channels Update Underrun Error Interrupt Mask
3
1
CMPM0
Comparison 0 Match Interrupt Mask
8
1
CMPM1
Comparison 1 Match Interrupt Mask
9
1
CMPM2
Comparison 2 Match Interrupt Mask
10
1
CMPM3
Comparison 3 Match Interrupt Mask
11
1
CMPM4
Comparison 4 Match Interrupt Mask
12
1
CMPM5
Comparison 5 Match Interrupt Mask
13
1
CMPM6
Comparison 6 Match Interrupt Mask
14
1
CMPM7
Comparison 7 Match Interrupt Mask
15
1
CMPU0
Comparison 0 Update Interrupt Mask
16
1
CMPU1
Comparison 1 Update Interrupt Mask
17
1
CMPU2
Comparison 2 Update Interrupt Mask
18
1
CMPU3
Comparison 3 Update Interrupt Mask
19
1
CMPU4
Comparison 4 Update Interrupt Mask
20
1
CMPU5
Comparison 5 Update Interrupt Mask
21
1
CMPU6
Comparison 6 Update Interrupt Mask
22
1
CMPU7
Comparison 7 Update Interrupt Mask
23
1
ISR2
PWM Interrupt Status Register 2
0x40
32
read-only
WRDY
Write Ready for Synchronous Channels Update
0
1
UNRE
Synchronous Channels Update Underrun Error
3
1
CMPM0
Comparison 0 Match
8
1
CMPM1
Comparison 1 Match
9
1
CMPM2
Comparison 2 Match
10
1
CMPM3
Comparison 3 Match
11
1
CMPM4
Comparison 4 Match
12
1
CMPM5
Comparison 5 Match
13
1
CMPM6
Comparison 6 Match
14
1
CMPM7
Comparison 7 Match
15
1
CMPU0
Comparison 0 Update
16
1
CMPU1
Comparison 1 Update
17
1
CMPU2
Comparison 2 Update
18
1
CMPU3
Comparison 3 Update
19
1
CMPU4
Comparison 4 Update
20
1
CMPU5
Comparison 5 Update
21
1
CMPU6
Comparison 6 Update
22
1
CMPU7
Comparison 7 Update
23
1
OOV
PWM Output Override Value Register
0x44
32
OOVH0
Output Override Value for PWMH output of the channel 0
0
1
OOVH1
Output Override Value for PWMH output of the channel 1
1
1
OOVH2
Output Override Value for PWMH output of the channel 2
2
1
OOVH3
Output Override Value for PWMH output of the channel 3
3
1
OOVL0
Output Override Value for PWML output of the channel 0
16
1
OOVL1
Output Override Value for PWML output of the channel 1
17
1
OOVL2
Output Override Value for PWML output of the channel 2
18
1
OOVL3
Output Override Value for PWML output of the channel 3
19
1
OS
PWM Output Selection Register
0x48
32
OSH0
Output Selection for PWMH output of the channel 0
0
1
OSH1
Output Selection for PWMH output of the channel 1
1
1
OSH2
Output Selection for PWMH output of the channel 2
2
1
OSH3
Output Selection for PWMH output of the channel 3
3
1
OSL0
Output Selection for PWML output of the channel 0
16
1
OSL1
Output Selection for PWML output of the channel 1
17
1
OSL2
Output Selection for PWML output of the channel 2
18
1
OSL3
Output Selection for PWML output of the channel 3
19
1
OSS
PWM Output Selection Set Register
0x4C
32
write-only
OSSH0
Output Selection Set for PWMH output of the channel 0
0
1
OSSH1
Output Selection Set for PWMH output of the channel 1
1
1
OSSH2
Output Selection Set for PWMH output of the channel 2
2
1
OSSH3
Output Selection Set for PWMH output of the channel 3
3
1
OSSL0
Output Selection Set for PWML output of the channel 0
16
1
OSSL1
Output Selection Set for PWML output of the channel 1
17
1
OSSL2
Output Selection Set for PWML output of the channel 2
18
1
OSSL3
Output Selection Set for PWML output of the channel 3
19
1
OSC
PWM Output Selection Clear Register
0x50
32
write-only
OSCH0
Output Selection Clear for PWMH output of the channel 0
0
1
OSCH1
Output Selection Clear for PWMH output of the channel 1
1
1
OSCH2
Output Selection Clear for PWMH output of the channel 2
2
1
OSCH3
Output Selection Clear for PWMH output of the channel 3
3
1
OSCL0
Output Selection Clear for PWML output of the channel 0
16
1
OSCL1
Output Selection Clear for PWML output of the channel 1
17
1
OSCL2
Output Selection Clear for PWML output of the channel 2
18
1
OSCL3
Output Selection Clear for PWML output of the channel 3
19
1
OSSUPD
PWM Output Selection Set Update Register
0x54
32
write-only
OSSUPH0
Output Selection Set for PWMH output of the channel 0
0
1
OSSUPH1
Output Selection Set for PWMH output of the channel 1
1
1
OSSUPH2
Output Selection Set for PWMH output of the channel 2
2
1
OSSUPH3
Output Selection Set for PWMH output of the channel 3
3
1
OSSUPL0
Output Selection Set for PWML output of the channel 0
16
1
OSSUPL1
Output Selection Set for PWML output of the channel 1
17
1
OSSUPL2
Output Selection Set for PWML output of the channel 2
18
1
OSSUPL3
Output Selection Set for PWML output of the channel 3
19
1
OSCUPD
PWM Output Selection Clear Update Register
0x58
32
write-only
OSCUPH0
Output Selection Clear for PWMH output of the channel 0
0
1
OSCUPH1
Output Selection Clear for PWMH output of the channel 1
1
1
OSCUPH2
Output Selection Clear for PWMH output of the channel 2
2
1
OSCUPH3
Output Selection Clear for PWMH output of the channel 3
3
1
OSCUPL0
Output Selection Clear for PWML output of the channel 0
16
1
OSCUPL1
Output Selection Clear for PWML output of the channel 1
17
1
OSCUPL2
Output Selection Clear for PWML output of the channel 2
18
1
OSCUPL3
Output Selection Clear for PWML output of the channel 3
19
1
FMR
PWM Fault Mode Register
0x5C
32
FPOL
Fault Polarity
0
8
FMOD
Fault Activation Mode
8
8
FFIL
Fault Filtering
16
8
FSR
PWM Fault Status Register
0x60
32
read-only
FIV
Fault Input Value
0
8
FS
Fault Status
8
8
FCR
PWM Fault Clear Register
0x64
32
write-only
FCLR
Fault Clear
0
8
FPV1
PWM Fault Protection Value Register 1
0x68
32
FPVH0
Fault Protection Value for PWMH output on channel 0
0
1
FPVH1
Fault Protection Value for PWMH output on channel 1
1
1
FPVH2
Fault Protection Value for PWMH output on channel 2
2
1
FPVH3
Fault Protection Value for PWMH output on channel 3
3
1
FPVL0
Fault Protection Value for PWML output on channel 0
16
1
FPVL1
Fault Protection Value for PWML output on channel 1
17
1
FPVL2
Fault Protection Value for PWML output on channel 2
18
1
FPVL3
Fault Protection Value for PWML output on channel 3
19
1
FPE
PWM Fault Protection Enable Register
0x6C
32
FPE0
Fault Protection Enable for channel 0
0
8
FPE1
Fault Protection Enable for channel 1
8
8
FPE2
Fault Protection Enable for channel 2
16
8
FPE3
Fault Protection Enable for channel 3
24
8
2
4
ELMR[%s]
PWM Event Line 0 Mode Register 0
0x7C
32
CSEL0
Comparison 0 Selection
0
1
CSEL1
Comparison 1 Selection
1
1
CSEL2
Comparison 2 Selection
2
1
CSEL3
Comparison 3 Selection
3
1
CSEL4
Comparison 4 Selection
4
1
CSEL5
Comparison 5 Selection
5
1
CSEL6
Comparison 6 Selection
6
1
CSEL7
Comparison 7 Selection
7
1
SSPR
PWM Spread Spectrum Register
0xA0
32
SPRD
Spread Spectrum Limit Value
0
24
SPRDM
Spread Spectrum Counter Mode
24
1
SSPUP
PWM Spread Spectrum Update Register
0xA4
32
write-only
SPRDUP
Spread Spectrum Limit Value Update
0
24
SMMR
PWM Stepper Motor Mode Register
0xB0
32
GCEN0
Gray Count ENable
0
1
GCEN1
Gray Count ENable
1
1
DOWN0
DOWN Count
16
1
DOWN1
DOWN Count
17
1
FPV2
PWM Fault Protection Value 2 Register
0xC0
32
FPZH0
Fault Protection to Hi-Z for PWMH output on channel 0
0
1
FPZH1
Fault Protection to Hi-Z for PWMH output on channel 1
1
1
FPZH2
Fault Protection to Hi-Z for PWMH output on channel 2
2
1
FPZH3
Fault Protection to Hi-Z for PWMH output on channel 3
3
1
FPZL0
Fault Protection to Hi-Z for PWML output on channel 0
16
1
FPZL1
Fault Protection to Hi-Z for PWML output on channel 1
17
1
FPZL2
Fault Protection to Hi-Z for PWML output on channel 2
18
1
FPZL3
Fault Protection to Hi-Z for PWML output on channel 3
19
1
WPCR
PWM Write Protection Control Register
0xE4
32
write-only
WPCMD
Write Protection Command
0
2
WPCMDSelect
DISABLE_SW_PROT
Disables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x0
ENABLE_SW_PROT
Enables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x1
ENABLE_HW_PROT
Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.
0x2
WPRG0
Write Protection Register Group 0
2
1
WPRG1
Write Protection Register Group 1
3
1
WPRG2
Write Protection Register Group 2
4
1
WPRG3
Write Protection Register Group 3
5
1
WPRG4
Write Protection Register Group 4
6
1
WPRG5
Write Protection Register Group 5
7
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0
0x50574D
WPSR
PWM Write Protection Status Register
0xE8
32
read-only
WPSWS0
Write Protect SW Status
0
1
WPSWS1
Write Protect SW Status
1
1
WPSWS2
Write Protect SW Status
2
1
WPSWS3
Write Protect SW Status
3
1
WPSWS4
Write Protect SW Status
4
1
WPSWS5
Write Protect SW Status
5
1
WPVS
Write Protect Violation Status
7
1
WPHWS0
Write Protect HW Status
8
1
WPHWS1
Write Protect HW Status
9
1
WPHWS2
Write Protect HW Status
10
1
WPHWS3
Write Protect HW Status
11
1
WPHWS4
Write Protect HW Status
12
1
WPHWS5
Write Protect HW Status
13
1
WPVSRC
Write Protect Violation Source
16
16
8
16
PWM_CMP[%s]
PWM Comparison 0 Value Register
0x130
CMPV
PWM Comparison 0 Value Register
0x00
32
CV
Comparison x Value
0
24
CVM
Comparison x Value Mode
24
1
CVMSelect
COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x0
COMPARE_AT_DECREMENT
Compare when counter is decrementing
0x1
CMPVUPD
PWM Comparison 0 Value Update Register
0x04
32
write-only
CVUPD
Comparison x Value Update
0
24
CVMUPD
Comparison x Value Mode Update
24
1
CMPM
PWM Comparison 0 Mode Register
0x08
32
CEN
Comparison x Enable
0
1
CTR
Comparison x Trigger
4
4
CPR
Comparison x Period
8
4
CPRCNT
Comparison x Period Counter
12
4
CUPR
Comparison x Update Period
16
4
CUPRCNT
Comparison x Update Period Counter
20
4
CMPMUPD
PWM Comparison 0 Mode Update Register
0x0C
32
write-only
CENUPD
Comparison x Enable Update
0
1
CTRUPD
Comparison x Trigger Update
4
4
CPRUPD
Comparison x Period Update
8
4
CUPRUPD
Comparison x Update Period Update
16
4
4
32
PWM_CH_NUM[%s]
PWM Channel Mode Register
0x200
CMR
PWM Channel Mode Register
0x00
32
CPRE
Channel Pre-scaler
0
4
CPRESelect
MCK
Peripheral clock
0x0
MCK_DIV_2
Peripheral clock/2
0x1
MCK_DIV_4
Peripheral clock/4
0x2
MCK_DIV_8
Peripheral clock/8
0x3
MCK_DIV_16
Peripheral clock/16
0x4
MCK_DIV_32
Peripheral clock/32
0x5
MCK_DIV_64
Peripheral clock/64
0x6
MCK_DIV_128
Peripheral clock/128
0x7
MCK_DIV_256
Peripheral clock/256
0x8
MCK_DIV_512
Peripheral clock/512
0x9
MCK_DIV_1024
Peripheral clock/1024
0xA
CLKA
Clock A
0xB
CLKB
Clock B
0xC
CALG
Channel Alignment
8
1
CALGSelect
LEFT_ALIGNED
Left aligned
0x0
CENTER_ALIGNED
Center aligned
0x1
CPOL
Channel Polarity
9
1
CPOLSelect
LOW_POLARITY
Waveform starts at low level
0x0
HIGH_POLARITY
Waveform starts at high level
0x1
CES
Counter Event Selection
10
1
CESSelect
SINGLE_EVENT
At the end of PWM period
0x0
DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
0x1
UPDS
Update Selection
11
1
UPDSSelect
UPDATE_AT_PERIOD
At the next end of PWM period
0x0
UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
0x1
DPOLI
Disabled Polarity Inverted
12
1
TCTS
Timer Counter Trigger Selection
13
1
DTE
Dead-Time Generator Enable
16
1
DTHI
Dead-Time PWMHx Output Inverted
17
1
DTLI
Dead-Time PWMLx Output Inverted
18
1
PPM
Push-Pull Mode
19
1
CDTY
PWM Channel Duty Cycle Register
0x04
32
CDTY
Channel Duty-Cycle
0
24
CDTYUPD
PWM Channel Duty Cycle Update Register
0x08
32
write-only
CDTYUPD
Channel Duty-Cycle Update
0
24
CPRD
PWM Channel Period Register
0x0C
32
CPRD
Channel Period
0
24
CPRDUPD
PWM Channel Period Update Register
0x10
32
write-only
CPRDUPD
Channel Period Update
0
24
CCNT
PWM Channel Counter Register
0x14
32
read-only
CNT
Channel Counter Register
0
24
DT
PWM Channel Dead Time Register
0x18
32
DTH
Dead-Time Value for PWMHx Output
0
16
DTL
Dead-Time Value for PWMLx Output
16
16
DTUPD
PWM Channel Dead Time Update Register
0x1C
32
write-only
DTHUPD
Dead-Time Value Update for PWMHx Output
0
16
DTLUPD
Dead-Time Value Update for PWMLx Output
16
16
CMUPD0
PWM Channel Mode Update Register (ch_num = 0)
0x400
32
write-only
CPOLUP
Channel Polarity Update
9
1
CPOLINVUP
Channel Polarity Inversion Update
13
1
CMUPD1
PWM Channel Mode Update Register (ch_num = 1)
0x420
32
write-only
CPOLUP
Channel Polarity Update
9
1
CPOLINVUP
Channel Polarity Inversion Update
13
1
ETRG1
PWM External Trigger Register (trg_num = 1)
0x42C
32
MAXCNT
Maximum Counter value
0
24
TRGMODE
External Trigger Mode
24
2
TRGMODESelect
OFF
External trigger is not enabled.
0x0
MODE1
External PWM Reset Mode
0x1
MODE2
External PWM Start Mode
0x2
MODE3
Cycle-by-cycle Duty Mode
0x3
TRGEDGE
Edge Selection
28
1
TRGEDGESelect
FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
0
RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
1
TRGFILT
Filtered input
29
1
TRGSRC
Trigger Source
30
1
RFEN
Recoverable Fault Enable
31
1
LEBR1
PWM Leading-Edge Blanking Register (trg_num = 1)
0x430
32
LEBDELAY
Leading-Edge Blanking Delay for TRGINx
0
7
PWMLFEN
PWML Falling Edge Enable
16
1
PWMLREN
PWML Rising Edge Enable
17
1
PWMHFEN
PWMH Falling Edge Enable
18
1
PWMHREN
PWMH Rising Edge Enable
19
1
CMUPD2
PWM Channel Mode Update Register (ch_num = 2)
0x440
32
write-only
CPOLUP
Channel Polarity Update
9
1
CPOLINVUP
Channel Polarity Inversion Update
13
1
ETRG2
PWM External Trigger Register (trg_num = 2)
0x44C
32
MAXCNT
Maximum Counter value
0
24
TRGMODE
External Trigger Mode
24
2
TRGMODESelect
OFF
External trigger is not enabled.
0x0
MODE1
External PWM Reset Mode
0x1
MODE2
External PWM Start Mode
0x2
MODE3
Cycle-by-cycle Duty Mode
0x3
TRGEDGE
Edge Selection
28
1
TRGEDGESelect
FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
0
RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
1
TRGFILT
Filtered input
29
1
TRGSRC
Trigger Source
30
1
RFEN
Recoverable Fault Enable
31
1
LEBR2
PWM Leading-Edge Blanking Register (trg_num = 2)
0x450
32
LEBDELAY
Leading-Edge Blanking Delay for TRGINx
0
7
PWMLFEN
PWML Falling Edge Enable
16
1
PWMLREN
PWML Rising Edge Enable
17
1
PWMHFEN
PWMH Falling Edge Enable
18
1
PWMHREN
PWMH Rising Edge Enable
19
1
CMUPD3
PWM Channel Mode Update Register (ch_num = 3)
0x460
32
write-only
CPOLUP
Channel Polarity Update
9
1
CPOLINVUP
Channel Polarity Inversion Update
13
1
PWM1
0x4005C000
PWM1
60
QSPI
11171J
Quad Serial Peripheral Interface
0x4007C000
0
0xEC
registers
QSPI
43
CR
Control Register
0x00
32
write-only
QSPIEN
QSPI Enable
0
1
QSPIDIS
QSPI Disable
1
1
SWRST
QSPI Software Reset
7
1
LASTXFER
Last Transfer
24
1
MR
Mode Register
0x04
32
SMM
Serial Memory Mode
0
1
SMMSelect
SPI
The QSPI is in SPI mode.
0
MEMORY
The QSPI is in Serial Memory mode.
1
LLB
Local Loopback Enable
1
1
LLBSelect
DISABLED
Local loopback path disabled.
0
ENABLED
Local loopback path enabled.
1
WDRBT
Wait Data Read Before Transfer
2
1
WDRBTSelect
DISABLED
No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.
0
ENABLED
In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.
1
CSMODE
Chip Select Mode
4
2
CSMODESelect
NOT_RELOADED
The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.
0x0
LASTXFER
The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred.
0x1
SYSTEMATICALLY
The chip select is deasserted systematically after each transfer.
0x2
NBBITS
Number Of Bits Per Transfer
8
4
NBBITSSelect
_8_BIT
8 bits for transfer
0x0
_16_BIT
16 bits for transfer
0x8
DLYBCT
Delay Between Consecutive Transfers
16
8
DLYCS
Minimum Inactive QCS Delay
24
8
RDR
Receive Data Register
0x08
32
read-only
RD
Receive Data
0
16
TDR
Transmit Data Register
0x0C
32
write-only
TD
Transmit Data
0
16
SR
Status Register
0x10
32
read-only
RDRF
Receive Data Register Full (cleared by reading SPI_RDR)
0
1
TDRE
Transmit Data Register Empty (cleared by writing SPI_TDR)
1
1
TXEMPTY
Transmission Registers Empty (cleared by writing SPI_TDR)
2
1
OVRES
Overrun Error Status (cleared on read)
3
1
CSR
Chip Select Rise (cleared on read)
8
1
CSS
Chip Select Status
9
1
INSTRE
Instruction End Status (cleared on read)
10
1
QSPIENS
QSPI Enable Status
24
1
IER
Interrupt Enable Register
0x14
32
write-only
RDRF
Receive Data Register Full Interrupt Enable
0
1
TDRE
Transmit Data Register Empty Interrupt Enable
1
1
TXEMPTY
Transmission Registers Empty Enable
2
1
OVRES
Overrun Error Interrupt Enable
3
1
CSR
Chip Select Rise Interrupt Enable
8
1
CSS
Chip Select Status Interrupt Enable
9
1
INSTRE
Instruction End Interrupt Enable
10
1
IDR
Interrupt Disable Register
0x18
32
write-only
RDRF
Receive Data Register Full Interrupt Disable
0
1
TDRE
Transmit Data Register Empty Interrupt Disable
1
1
TXEMPTY
Transmission Registers Empty Disable
2
1
OVRES
Overrun Error Interrupt Disable
3
1
CSR
Chip Select Rise Interrupt Disable
8
1
CSS
Chip Select Status Interrupt Disable
9
1
INSTRE
Instruction End Interrupt Disable
10
1
IMR
Interrupt Mask Register
0x1C
32
read-only
RDRF
Receive Data Register Full Interrupt Mask
0
1
TDRE
Transmit Data Register Empty Interrupt Mask
1
1
TXEMPTY
Transmission Registers Empty Mask
2
1
OVRES
Overrun Error Interrupt Mask
3
1
CSR
Chip Select Rise Interrupt Mask
8
1
CSS
Chip Select Status Interrupt Mask
9
1
INSTRE
Instruction End Interrupt Mask
10
1
SCR
Serial Clock Register
0x20
32
CPOL
Clock Polarity
0
1
CPHA
Clock Phase
1
1
SCBR
Serial Clock Baud Rate
8
8
DLYBS
Delay Before QSCK
16
8
IAR
Instruction Address Register
0x30
32
ADDR
Address
0
32
ICR
Instruction Code Register
0x34
32
INST
Instruction Code
0
8
OPT
Option Code
16
8
IFR
Instruction Frame Register
0x38
32
WIDTH
Width of Instruction Code, Address, Option Code and Data
0
3
WIDTHSelect
SINGLE_BIT_SPI
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
0x0
DUAL_OUTPUT
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
0x1
QUAD_OUTPUT
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
0x2
DUAL_IO
Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
0x3
QUAD_IO
Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
0x4
DUAL_CMD
Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
0x5
QUAD_CMD
Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
0x6
INSTEN
Instruction Enable
4
1
ADDREN
Address Enable
5
1
OPTEN
Option Enable
6
1
DATAEN
Data Enable
7
1
OPTL
Option Code Length
8
2
OPTLSelect
OPTION_1BIT
The option code is 1 bit long.
0x0
OPTION_2BIT
The option code is 2 bits long.
0x1
OPTION_4BIT
The option code is 4 bits long.
0x2
OPTION_8BIT
The option code is 8 bits long.
0x3
ADDRL
Address Length
10
1
ADDRLSelect
_24_BIT
The address is 24 bits long.
0
_32_BIT
The address is 32 bits long.
1
TFRTYP
Data Transfer Type
12
2
TFRTYPSelect
TRSFR_READ
Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible.
0x0
TRSFR_READ_MEMORY
Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible.
0x1
TRSFR_WRITE
Write transfer into the serial memory.Scrambling is not performed.
0x2
TRSFR_WRITE_MEMORY
Write data transfer into the serial memory.If enabled, scrambling is performed.
0x3
CRM
Continuous Read Mode
14
1
CRMSelect
DISABLED
The Continuous Read mode is disabled.
0
ENABLED
The Continuous Read mode is enabled.
1
NBDUM
Number Of Dummy Cycles
16
5
SMR
Scrambling Mode Register
0x40
32
SCREN
Scrambling/Unscrambling Enable
0
1
SCRENSelect
DISABLED
The scrambling/unscrambling is disabled.
0
ENABLED
The scrambling/unscrambling is enabled.
1
RVDIS
Scrambling/Unscrambling Random Value Disable
1
1
SKR
Scrambling Key Register
0x44
32
write-only
USRK
User Scrambling Key
0
32
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x515350
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
8
RSTC
11009N
Reset Controller
0x400E1800
0
0xC
registers
RSTC
1
CR
Control Register
0x00
32
write-only
PROCRST
Processor Reset
0
1
EXTRST
External Reset
3
1
KEY
System Reset Key
24
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
SR
Status Register
0x04
32
read-only
URSTS
User Reset Status
0
1
RSTTYP
Reset Type
8
3
RSTTYPSelect
GENERAL_RST
First power-up reset
0x0
BACKUP_RST
Return from Backup Mode
0x1
WDT_RST
Watchdog fault occurred
0x2
SOFT_RST
Processor reset required by the software
0x3
USER_RST
NRST pin detected low
0x4
NRSTL
NRST Pin Level
16
1
SRCMP
Software Reset Command in Progress
17
1
MR
Mode Register
0x08
32
URSTEN
User Reset Enable
0
1
URSTIEN
User Reset Interrupt Enable
4
1
ERSTL
External Reset Length
8
4
KEY
Write Access Password
24
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
0xA5
RSWDT
11110G
Reinforced Safety Watchdog Timer
0x400E1900
0
0xC
registers
RSWDT
63
CR
Control Register
0x00
32
write-only
WDRSTT
Watchdog Restart
0
1
KEY
Password
24
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.
0xC4
MR
Mode Register
0x04
32
WDV
Watchdog Counter Value
0
12
WDFIEN
Watchdog Fault Interrupt Enable
12
1
WDRSTEN
Watchdog Reset Enable
13
1
WDDIS
Watchdog Disable
15
1
ALLONES
Must Always Be Written with 0xFFF
16
12
WDDBGHLT
Watchdog Debug Halt
28
1
WDIDLEHLT
Watchdog Idle Halt
29
1
SR
Status Register
0x08
32
read-only
WDUNF
Watchdog Underflow
0
1
RTC
6056ZB
Real-time Clock
0x400E1860
0
0x30
registers
RTC
2
CR
Control Register
0x00
32
UPDTIM
Update Request Time Register
0
1
UPDCAL
Update Request Calendar Register
1
1
TIMEVSEL
Time Event Selection
8
2
TIMEVSELSelect
MINUTE
Minute change
0x0
HOUR
Hour change
0x1
MIDNIGHT
Every day at midnight
0x2
NOON
Every day at noon
0x3
CALEVSEL
Calendar Event Selection
16
2
CALEVSELSelect
WEEK
Week change (every Monday at time 00:00:00)
0x0
MONTH
Month change (every 01 of each month at time 00:00:00)
0x1
YEAR
Year change (every January 1 at time 00:00:00)
0x2
MR
Mode Register
0x04
32
HRMOD
12-/24-hour Mode
0
1
PERSIAN
PERSIAN Calendar
1
1
NEGPPM
NEGative PPM Correction
4
1
CORRECTION
Slow Clock Correction
8
7
HIGHPPM
HIGH PPM Correction
15
1
OUT0
RTCOUT0 OutputSource Selection
16
3
OUT0Select
NO_WAVE
No waveform, stuck at '0'
0x0
FREQ1HZ
1 Hz square wave
0x1
FREQ32HZ
32 Hz square wave
0x2
FREQ64HZ
64 Hz square wave
0x3
FREQ512HZ
512 Hz square wave
0x4
ALARM_TOGGLE
Output toggles when alarm flag rises
0x5
ALARM_FLAG
Output is a copy of the alarm flag
0x6
PROG_PULSE
Duty cycle programmable pulse
0x7
OUT1
RTCOUT1 Output Source Selection
20
3
OUT1Select
NO_WAVE
No waveform, stuck at '0'
0x0
FREQ1HZ
1 Hz square wave
0x1
FREQ32HZ
32 Hz square wave
0x2
FREQ64HZ
64 Hz square wave
0x3
FREQ512HZ
512 Hz square wave
0x4
ALARM_TOGGLE
Output toggles when alarm flag rises
0x5
ALARM_FLAG
Output is a copy of the alarm flag
0x6
PROG_PULSE
Duty cycle programmable pulse
0x7
THIGH
High Duration of the Output Pulse
24
3
THIGHSelect
H_31MS
31.2 ms
0x0
H_16MS
15.6 ms
0x1
H_4MS
3.91 ms
0x2
H_976US
976 us
0x3
H_488US
488 us
0x4
H_122US
122 us
0x5
H_30US
30.5 us
0x6
H_15US
15.2 us
0x7
TPERIOD
Period of the Output Pulse
28
2
TPERIODSelect
P_1S
1 second
0x0
P_500MS
500 ms
0x1
P_250MS
250 ms
0x2
P_125MS
125 ms
0x3
TIMR
Time Register
0x08
32
SEC
Current Second
0
7
MIN
Current Minute
8
7
HOUR
Current Hour
16
6
AMPM
Ante Meridiem Post Meridiem Indicator
22
1
CALR
Calendar Register
0x0C
32
CENT
Current Century
0
7
YEAR
Current Year
8
8
MONTH
Current Month
16
5
DAY
Current Day in Current Week
21
3
DATE
Current Day in Current Month
24
6
TIMALR
Time Alarm Register
0x10
32
SEC
Second Alarm
0
7
SECEN
Second Alarm Enable
7
1
MIN
Minute Alarm
8
7
MINEN
Minute Alarm Enable
15
1
HOUR
Hour Alarm
16
6
AMPM
AM/PM Indicator
22
1
HOUREN
Hour Alarm Enable
23
1
CALALR
Calendar Alarm Register
0x14
32
MONTH
Month Alarm
16
5
MTHEN
Month Alarm Enable
23
1
DATE
Date Alarm
24
6
DATEEN
Date Alarm Enable
31
1
SR
Status Register
0x18
32
read-only
ACKUPD
Acknowledge for Update
0
1
ACKUPDSelect
FREERUN
Time and calendar registers cannot be updated.
0
UPDATE
Time and calendar registers can be updated.
1
ALARM
Alarm Flag
1
1
ALARMSelect
NO_ALARMEVENT
No alarm matching condition occurred.
0
ALARMEVENT
An alarm matching condition has occurred.
1
SEC
Second Event
2
1
SECSelect
NO_SECEVENT
No second event has occurred since the last clear.
0
SECEVENT
At least one second event has occurred since the last clear.
1
TIMEV
Time Event
3
1
TIMEVSelect
NO_TIMEVENT
No time event has occurred since the last clear.
0
TIMEVENT
At least one time event has occurred since the last clear.
1
CALEV
Calendar Event
4
1
CALEVSelect
NO_CALEVENT
No calendar event has occurred since the last clear.
0
CALEVENT
At least one calendar event has occurred since the last clear.
1
TDERR
Time and/or Date Free Running Error
5
1
TDERRSelect
CORRECT
The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR).
0
ERR_TIMEDATE
The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid.
1
SCCR
Status Clear Command Register
0x1C
32
write-only
ACKCLR
Acknowledge Clear
0
1
ALRCLR
Alarm Clear
1
1
SECCLR
Second Clear
2
1
TIMCLR
Time Clear
3
1
CALCLR
Calendar Clear
4
1
TDERRCLR
Time and/or Date Free Running Error Clear
5
1
IER
Interrupt Enable Register
0x20
32
write-only
ACKEN
Acknowledge Update Interrupt Enable
0
1
ALREN
Alarm Interrupt Enable
1
1
SECEN
Second Event Interrupt Enable
2
1
TIMEN
Time Event Interrupt Enable
3
1
CALEN
Calendar Event Interrupt Enable
4
1
TDERREN
Time and/or Date Error Interrupt Enable
5
1
IDR
Interrupt Disable Register
0x24
32
write-only
ACKDIS
Acknowledge Update Interrupt Disable
0
1
ALRDIS
Alarm Interrupt Disable
1
1
SECDIS
Second Event Interrupt Disable
2
1
TIMDIS
Time Event Interrupt Disable
3
1
CALDIS
Calendar Event Interrupt Disable
4
1
TDERRDIS
Time and/or Date Error Interrupt Disable
5
1
IMR
Interrupt Mask Register
0x28
32
read-only
ACK
Acknowledge Update Interrupt Mask
0
1
ALR
Alarm Interrupt Mask
1
1
SEC
Second Event Interrupt Mask
2
1
TIM
Time Event Interrupt Mask
3
1
CAL
Calendar Event Interrupt Mask
4
1
TDERR
Time and/or Date Error Mask
5
1
VER
Valid Entry Register
0x2C
32
read-only
NVTIM
Non-valid Time
0
1
NVCAL
Non-valid Calendar
1
1
NVTIMALR
Non-valid Time Alarm
2
1
NVCALALR
Non-valid Calendar Alarm
3
1
RTT
6081M
Real-time Timer
0x400E1830
0
0x10
registers
RTT
3
MR
Mode Register
0x00
32
RTPRES
Real-time Timer Prescaler Value
0
16
ALMIEN
Alarm Interrupt Enable
16
1
RTTINCIEN
Real-time Timer Increment Interrupt Enable
17
1
RTTRST
Real-time Timer Restart
18
1
RTTDIS
Real-time Timer Disable
20
1
RTC1HZ
Real-Time Clock 1Hz Clock Selection
24
1
AR
Alarm Register
0x04
32
ALMV
Alarm Value
0
32
VR
Value Register
0x08
32
read-only
CRTV
Current Real-time Value
0
32
SR
Status Register
0x0C
32
read-only
ALMS
Real-time Alarm Status (cleared on read)
0
1
RTTINC
Prescaler Roll-over Status (cleared on read)
1
1
SPI0
6088ZM
Serial Peripheral Interface
SPI
SPI_
0x40008000
0
0xEC
registers
SPI0
21
CR
Control Register
0x00
32
write-only
SPIEN
SPI Enable
0
1
SPIDIS
SPI Disable
1
1
SWRST
SPI Software Reset
7
1
REQCLR
Request to Clear the Comparison Trigger
12
1
LASTXFER
Last Transfer
24
1
MR
Mode Register
0x04
32
MSTR
Master/Slave Mode
0
1
MSTRSelect
MASTER
Master
0x1
SLAVE
Slave
0x0
PS
Peripheral Select
1
1
PCSDEC
Chip Select Decode
2
1
MODFDIS
Mode Fault Detection
4
1
WDRBT
Wait Data Read Before Transfer
5
1
LLB
Local Loopback Enable
7
1
PCS
Peripheral Chip Select
16
4
PCSSelect
NPCS0
NPCS0 as Chip Select
0xE
NPCS1
NPCS1 as Chip Select
0xD
NPCS2
NPCS2 as Chip Select
0xB
NPCS3
NPCS3 as Chip Select
0x7
DLYBCS
Delay Between Chip Selects
24
8
RDR
Receive Data Register
0x08
32
read-only
RD
Receive Data
0
16
PCS
Peripheral Chip Select
16
4
TDR
Transmit Data Register
0x0C
32
write-only
TD
Transmit Data
0
16
PCS
Peripheral Chip Select
16
4
PCSSelect
NPCS0
NPCS0 as Chip Select
0xE
NPCS1
NPCS1 as Chip Select
0xD
NPCS2
NPCS2 as Chip Select
0xB
NPCS3
NPCS3 as Chip Select
0x7
LASTXFER
Last Transfer
24
1
SR
Status Register
0x10
32
read-only
RDRF
Receive Data Register Full (cleared by reading SPI_RDR)
0
1
TDRE
Transmit Data Register Empty (cleared by writing SPI_TDR)
1
1
MODF
Mode Fault Error (cleared on read)
2
1
OVRES
Overrun Error Status (cleared on read)
3
1
NSSR
NSS Rising (cleared on read)
8
1
TXEMPTY
Transmission Registers Empty (cleared by writing SPI_TDR)
9
1
UNDES
Underrun Error Status (Slave mode only) (cleared on read)
10
1
SPIENS
SPI Enable Status
16
1
IER
Interrupt Enable Register
0x14
32
write-only
RDRF
Receive Data Register Full Interrupt Enable
0
1
TDRE
SPI Transmit Data Register Empty Interrupt Enable
1
1
MODF
Mode Fault Error Interrupt Enable
2
1
OVRES
Overrun Error Interrupt Enable
3
1
NSSR
NSS Rising Interrupt Enable
8
1
TXEMPTY
Transmission Registers Empty Enable
9
1
UNDES
Underrun Error Interrupt Enable
10
1
IDR
Interrupt Disable Register
0x18
32
write-only
RDRF
Receive Data Register Full Interrupt Disable
0
1
TDRE
SPI Transmit Data Register Empty Interrupt Disable
1
1
MODF
Mode Fault Error Interrupt Disable
2
1
OVRES
Overrun Error Interrupt Disable
3
1
NSSR
NSS Rising Interrupt Disable
8
1
TXEMPTY
Transmission Registers Empty Disable
9
1
UNDES
Underrun Error Interrupt Disable
10
1
IMR
Interrupt Mask Register
0x1C
32
read-only
RDRF
Receive Data Register Full Interrupt Mask
0
1
TDRE
SPI Transmit Data Register Empty Interrupt Mask
1
1
MODF
Mode Fault Error Interrupt Mask
2
1
OVRES
Overrun Error Interrupt Mask
3
1
NSSR
NSS Rising Interrupt Mask
8
1
TXEMPTY
Transmission Registers Empty Mask
9
1
UNDES
Underrun Error Interrupt Mask
10
1
4
4
CSR[%s]
Chip Select Register
0x30
32
CPOL
Clock Polarity
0
1
CPOLSelect
IDLE_LOW
Clock is low when inactive (CPOL=0)
0x0
IDLE_HIGH
Clock is high when inactive (CPOL=1)
0x1
NCPHA
Clock Phase
1
1
NCPHASelect
VALID_LEADING_EDGE
Data is valid on clock leading edge (NCPHA=1)
0x1
VALID_TRAILING_EDGE
Data is valid on clock trailing edge (NCPHA=0)
0x0
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
CSAAT
Chip Select Active After Transfer
3
1
BITS
Bits Per Transfer
4
4
BITSSelect
_8_BIT
8 bits for transfer
0x0
_9_BIT
9 bits for transfer
0x1
_10_BIT
10 bits for transfer
0x2
_11_BIT
11 bits for transfer
0x3
_12_BIT
12 bits for transfer
0x4
_13_BIT
13 bits for transfer
0x5
_14_BIT
14 bits for transfer
0x6
_15_BIT
15 bits for transfer
0x7
_16_BIT
16 bits for transfer
0x8
SCBR
Serial Clock Bit Rate
8
8
DLYBS
Delay Before SPCK
16
8
DLYBCT
Delay Between Consecutive Transfers
24
8
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x535049
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
8
SSC
6078Q
Synchronous Serial Controller
0x40004000
0
0xEC
registers
SSC
22
CR
Control Register
0x0
32
write-only
RXEN
Receive Enable
0
1
RXDIS
Receive Disable
1
1
TXEN
Transmit Enable
8
1
TXDIS
Transmit Disable
9
1
SWRST
Software Reset
15
1
CMR
Clock Mode Register
0x4
32
DIV
Clock Divider
0
12
RCMR
Receive Clock Mode Register
0x10
32
CKS
Receive Clock Selection
0
2
CKSSelect
MCK
Divided Clock
0x0
TK
TK Clock signal
0x1
RK
RK pin
0x2
CKO
Receive Clock Output Mode Selection
2
3
CKOSelect
NONE
None, RK pin is an input
0x0
CONTINUOUS
Continuous Receive Clock, RK pin is an output
0x1
TRANSFER
Receive Clock only during data transfers, RK pin is an output
0x2
CKI
Receive Clock Inversion
5
1
CKG
Receive Clock Gating Selection
6
2
CKGSelect
CONTINUOUS
None
0x0
EN_RF_LOW
Receive Clock enabled only if RF Low
0x1
EN_RF_HIGH
Receive Clock enabled only if RF High
0x2
START
Receive Start Selection
8
4
STARTSelect
CONTINUOUS
Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
0x0
TRANSMIT
Transmit start
0x1
RF_LOW
Detection of a low level on RF signal
0x2
RF_HIGH
Detection of a high level on RF signal
0x3
RF_FALLING
Detection of a falling edge on RF signal
0x4
RF_RISING
Detection of a rising edge on RF signal
0x5
RF_LEVEL
Detection of any level change on RF signal
0x6
RF_EDGE
Detection of any edge on RF signal
0x7
CMP_0
Compare 0
0x8
STOP
Receive Stop Selection
12
1
STTDLY
Receive Start Delay
16
8
PERIOD
Receive Period Divider Selection
24
8
RFMR
Receive Frame Mode Register
0x14
32
DATLEN
Data Length
0
5
LOOP
Loop Mode
5
1
MSBF
Most Significant Bit First
7
1
DATNB
Data Number per Frame
8
4
FSLEN
Receive Frame Sync Length
16
4
FSOS
Receive Frame Sync Output Selection
20
3
FSOSSelect
NONE
None, RF pin is an input
0x0
NEGATIVE
Negative Pulse, RF pin is an output
0x1
POSITIVE
Positive Pulse, RF pin is an output
0x2
LOW
Driven Low during data transfer, RF pin is an output
0x3
HIGH
Driven High during data transfer, RF pin is an output
0x4
TOGGLING
Toggling at each start of data transfer, RF pin is an output
0x5
FSEDGE
Frame Sync Edge Detection
24
1
FSEDGESelect
POSITIVE
Positive Edge Detection
0
NEGATIVE
Negative Edge Detection
1
FSLEN_EXT
FSLEN Field Extension
28
4
TCMR
Transmit Clock Mode Register
0x18
32
CKS
Transmit Clock Selection
0
2
CKSSelect
MCK
Divided Clock
0x0
RK
RK Clock signal
0x1
TK
TK pin
0x2
CKO
Transmit Clock Output Mode Selection
2
3
CKOSelect
NONE
None, TK pin is an input
0x0
CONTINUOUS
Continuous Transmit Clock, TK pin is an output
0x1
TRANSFER
Transmit Clock only during data transfers, TK pin is an output
0x2
CKI
Transmit Clock Inversion
5
1
CKG
Transmit Clock Gating Selection
6
2
CKGSelect
CONTINUOUS
None
0x0
EN_TF_LOW
Transmit Clock enabled only if TF Low
0x1
EN_TF_HIGH
Transmit Clock enabled only if TF High
0x2
START
Transmit Start Selection
8
4
STARTSelect
CONTINUOUS
Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data
0x0
RECEIVE
Receive start
0x1
TF_LOW
Detection of a low level on TF signal
0x2
TF_HIGH
Detection of a high level on TF signal
0x3
TF_FALLING
Detection of a falling edge on TF signal
0x4
TF_RISING
Detection of a rising edge on TF signal
0x5
TF_LEVEL
Detection of any level change on TF signal
0x6
TF_EDGE
Detection of any edge on TF signal
0x7
STTDLY
Transmit Start Delay
16
8
PERIOD
Transmit Period Divider Selection
24
8
TFMR
Transmit Frame Mode Register
0x1C
32
DATLEN
Data Length
0
5
DATDEF
Data Default Value
5
1
MSBF
Most Significant Bit First
7
1
DATNB
Data Number per Frame
8
4
FSLEN
Transmit Frame Sync Length
16
4
FSOS
Transmit Frame Sync Output Selection
20
3
FSOSSelect
NONE
None, TF pin is an input
0x0
NEGATIVE
Negative Pulse, TF pin is an output
0x1
POSITIVE
Positive Pulse, TF pin is an output
0x2
LOW
Driven Low during data transfer
0x3
HIGH
Driven High during data transfer
0x4
TOGGLING
Toggling at each start of data transfer
0x5
FSDEN
Frame Sync Data Enable
23
1
FSEDGE
Frame Sync Edge Detection
24
1
FSEDGESelect
POSITIVE
Positive Edge Detection
0
NEGATIVE
Negative Edge Detection
1
FSLEN_EXT
FSLEN Field Extension
28
4
RHR
Receive Holding Register
0x20
32
read-only
RDAT
Receive Data
0
32
THR
Transmit Holding Register
0x24
32
write-only
TDAT
Transmit Data
0
32
RSHR
Receive Sync. Holding Register
0x30
32
read-only
RSDAT
Receive Synchronization Data
0
16
TSHR
Transmit Sync. Holding Register
0x34
32
TSDAT
Transmit Synchronization Data
0
16
RC0R
Receive Compare 0 Register
0x38
32
CP0
Receive Compare Data 0
0
16
RC1R
Receive Compare 1 Register
0x3C
32
CP1
Receive Compare Data 1
0
16
SR
Status Register
0x40
32
read-only
TXRDY
Transmit Ready
0
1
TXEMPTY
Transmit Empty
1
1
RXRDY
Receive Ready
4
1
OVRUN
Receive Overrun
5
1
CP0
Compare 0
8
1
CP1
Compare 1
9
1
TXSYN
Transmit Sync
10
1
RXSYN
Receive Sync
11
1
TXEN
Transmit Enable
16
1
RXEN
Receive Enable
17
1
IER
Interrupt Enable Register
0x44
32
write-only
TXRDY
Transmit Ready Interrupt Enable
0
1
TXEMPTY
Transmit Empty Interrupt Enable
1
1
RXRDY
Receive Ready Interrupt Enable
4
1
OVRUN
Receive Overrun Interrupt Enable
5
1
CP0
Compare 0 Interrupt Enable
8
1
CP1
Compare 1 Interrupt Enable
9
1
TXSYN
Tx Sync Interrupt Enable
10
1
RXSYN
Rx Sync Interrupt Enable
11
1
IDR
Interrupt Disable Register
0x48
32
write-only
TXRDY
Transmit Ready Interrupt Disable
0
1
TXEMPTY
Transmit Empty Interrupt Disable
1
1
RXRDY
Receive Ready Interrupt Disable
4
1
OVRUN
Receive Overrun Interrupt Disable
5
1
CP0
Compare 0 Interrupt Disable
8
1
CP1
Compare 1 Interrupt Disable
9
1
TXSYN
Tx Sync Interrupt Enable
10
1
RXSYN
Rx Sync Interrupt Enable
11
1
IMR
Interrupt Mask Register
0x4C
32
read-only
TXRDY
Transmit Ready Interrupt Mask
0
1
TXEMPTY
Transmit Empty Interrupt Mask
1
1
RXRDY
Receive Ready Interrupt Mask
4
1
OVRUN
Receive Overrun Interrupt Mask
5
1
CP0
Compare 0 Interrupt Mask
8
1
CP1
Compare 1 Interrupt Mask
9
1
TXSYN
Tx Sync Interrupt Mask
10
1
RXSYN
Rx Sync Interrupt Mask
11
1
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x535343
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protect Violation Source
8
16
SUPC
6452ZE
Supply Controller
0x400E1810
0
0xD8
registers
SUPC
0
CR
Supply Controller Control Register
0x00
32
write-only
VROFF
Voltage Regulator Off
2
1
VROFFSelect
NO_EFFECT
No effect.
0
STOP_VREG
If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.
1
XTALSEL
Crystal Oscillator Select
3
1
XTALSELSelect
NO_EFFECT
No effect.
0
CRYSTAL_SEL
If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output.
1
KEY
Password
24
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
SMMR
Supply Controller Supply Monitor Mode Register
0x04
32
SMTH
Supply Monitor Threshold
0
4
SMSMPL
Supply Monitor Sampling Period
8
3
SMSMPLSelect
SMD
Supply Monitor disabled
0x0
CSM
Continuous Supply Monitor
0x1
_32SLCK
Supply Monitor enabled one SLCK period every 32 SLCK periods
0x2
_256SLCK
Supply Monitor enabled one SLCK period every 256 SLCK periods
0x3
_2048SLCK
Supply Monitor enabled one SLCK period every 2,048 SLCK periods
0x4
SMRSTEN
Supply Monitor Reset Enable
12
1
SMRSTENSelect
NOT_ENABLE
The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs.
0
ENABLE
The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
1
SMIEN
Supply Monitor Interrupt Enable
13
1
SMIENSelect
NOT_ENABLE
The SUPC interrupt signal is not affected when a supply monitor detection occurs.
0
ENABLE
The SUPC interrupt signal is asserted when a supply monitor detection occurs.
1
MR
Supply Controller Mode Register
0x08
32
BODRSTEN
Brownout Detector Reset Enable
12
1
BODRSTENSelect
NOT_ENABLE
The core reset signal vddcore_nreset is not affected when a brownout detection occurs.
0
ENABLE
The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
1
BODDIS
Brownout Detector Disable
13
1
BODDISSelect
ENABLE
The core brownout detector is enabled.
0
DISABLE
The core brownout detector is disabled.
1
ONREG
Voltage Regulator Enable
14
1
ONREGSelect
ONREG_UNUSED
Internal voltage regulator is not used (external power supply is used).
0
ONREG_USED
Internal voltage regulator is used.
1
BKUPRETON
SRAM On In Backup Mode
17
1
OSCBYPASS
Oscillator Bypass
20
1
OSCBYPASSSelect
NO_EFFECT
No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).
0
BYPASS
The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL.
1
KEY
Password Key
24
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
WUMR
Supply Controller Wake-up Mode Register
0x0C
32
SMEN
Supply Monitor Wake-up Enable
1
1
SMENSelect
NOT_ENABLE
The supply monitor detection has no wake-up effect.
0
ENABLE
The supply monitor detection forces the wake-up of the core power supply.
1
RTTEN
Real-time Timer Wake-up Enable
2
1
RTTENSelect
NOT_ENABLE
The RTT alarm signal has no wake-up effect.
0
ENABLE
The RTT alarm signal forces the wake-up of the core power supply.
1
RTCEN
Real-time Clock Wake-up Enable
3
1
RTCENSelect
NOT_ENABLE
The RTC alarm signal has no wake-up effect.
0
ENABLE
The RTC alarm signal forces the wake-up of the core power supply.
1
LPDBCEN0
Low-power Debouncer Enable WKUP0
5
1
LPDBCEN0Select
NOT_ENABLE
The WKUP0 input pin is not connected to the low-power debouncer.
0
ENABLE
The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.
1
LPDBCEN1
Low-power Debouncer Enable WKUP1
6
1
LPDBCEN1Select
NOT_ENABLE
The WKUP1 input pin is not connected to the low-power debouncer.
0
ENABLE
The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.
1
LPDBCCLR
Low-power Debouncer Clear
7
1
LPDBCCLRSelect
NOT_ENABLE
A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
0
ENABLE
A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers.
1
WKUPDBC
Wake-up Inputs Debouncer Period
12
3
WKUPDBCSelect
IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x0
_3_SLCK
WKUPx shall be in its active state for at least 3 SLCK periods
0x1
_32_SLCK
WKUPx shall be in its active state for at least 32 SLCK periods
0x2
_512_SLCK
WKUPx shall be in its active state for at least 512 SLCK periods
0x3
_4096_SLCK
WKUPx shall be in its active state for at least 4,096 SLCK periods
0x4
_32768_SLCK
WKUPx shall be in its active state for at least 32,768 SLCK periods
0x5
LPDBC
Low-power Debouncer Period
16
3
LPDBCSelect
DISABLE
Disable the low-power debouncers.
0x0
_2_RTCOUT
WKUP0/1 in active state for at least 2 RTCOUTx clock periods
0x1
_3_RTCOUT
WKUP0/1 in active state for at least 3 RTCOUTx clock periods
0x2
_4_RTCOUT
WKUP0/1 in active state for at least 4 RTCOUTx clock periods
0x3
_5_RTCOUT
WKUP0/1 in active state for at least 5 RTCOUTx clock periods
0x4
_6_RTCOUT
WKUP0/1 in active state for at least 6 RTCOUTx clock periods
0x5
_7_RTCOUT
WKUP0/1 in active state for at least 7 RTCOUTx clock periods
0x6
_8_RTCOUT
WKUP0/1 in active state for at least 8 RTCOUTx clock periods
0x7
WUIR
Supply Controller Wake-up Inputs Register
0x10
32
WKUPEN0
Wake-up Input Enable 0 to 0
0
1
WKUPEN0Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN1
Wake-up Input Enable 0 to 1
1
1
WKUPEN1Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN2
Wake-up Input Enable 0 to 2
2
1
WKUPEN2Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN3
Wake-up Input Enable 0 to 3
3
1
WKUPEN3Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN4
Wake-up Input Enable 0 to 4
4
1
WKUPEN4Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN5
Wake-up Input Enable 0 to 5
5
1
WKUPEN5Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN6
Wake-up Input Enable 0 to 6
6
1
WKUPEN6Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN7
Wake-up Input Enable 0 to 7
7
1
WKUPEN7Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN8
Wake-up Input Enable 0 to 8
8
1
WKUPEN8Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN9
Wake-up Input Enable 0 to 9
9
1
WKUPEN9Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN10
Wake-up Input Enable 0 to 10
10
1
WKUPEN10Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN11
Wake-up Input Enable 0 to 11
11
1
WKUPEN11Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN12
Wake-up Input Enable 0 to 12
12
1
WKUPEN12Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPEN13
Wake-up Input Enable 0 to 13
13
1
WKUPEN13Select
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
1
WKUPT0
Wake-up Input Type 0 to 0
16
1
WKUPT0Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT1
Wake-up Input Type 0 to 1
17
1
WKUPT1Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT2
Wake-up Input Type 0 to 2
18
1
WKUPT2Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT3
Wake-up Input Type 0 to 3
19
1
WKUPT3Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT4
Wake-up Input Type 0 to 4
20
1
WKUPT4Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT5
Wake-up Input Type 0 to 5
21
1
WKUPT5Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT6
Wake-up Input Type 0 to 6
22
1
WKUPT6Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT7
Wake-up Input Type 0 to 7
23
1
WKUPT7Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT8
Wake-up Input Type 0 to 8
24
1
WKUPT8Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT9
Wake-up Input Type 0 to 9
25
1
WKUPT9Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT10
Wake-up Input Type 0 to 10
26
1
WKUPT10Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT11
Wake-up Input Type 0 to 11
27
1
WKUPT11Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT12
Wake-up Input Type 0 to 12
28
1
WKUPT12Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
WKUPT13
Wake-up Input Type 0 to 13
29
1
WKUPT13Select
LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
0
HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
1
SR
Supply Controller Status Register
0x14
32
read-only
WKUPS
WKUP Wake-up Status (cleared on read)
1
1
WKUPSSelect
NO
No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1
SMWS
Supply Monitor Detection Wake-up Status (cleared on read)
2
1
SMWSSelect
NO
No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1
BODRSTS
Brownout Detector Reset Status (cleared on read)
3
1
BODRSTSSelect
NO
No core brownout rising edge event has been detected since the last read of the SUPC_SR.
0
PRESENT
At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
1
SMRSTS
Supply Monitor Reset Status (cleared on read)
4
1
SMRSTSSelect
NO
No supply monitor detection has generated a core reset since the last read of the SUPC_SR.
0
PRESENT
At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1
SMS
Supply Monitor Status (cleared on read)
5
1
SMSSelect
NO
No supply monitor detection since the last read of SUPC_SR.
0
PRESENT
At least one supply monitor detection since the last read of SUPC_SR.
1
SMOS
Supply Monitor Output Status
6
1
SMOSSelect
HIGH
The supply monitor detected VDDIO higher than its threshold at its last measurement.
0
LOW
The supply monitor detected VDDIO lower than its threshold at its last measurement.
1
OSCSEL
32-kHz Oscillator Selection Status
7
1
OSCSELSelect
RC
The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.
0
CRYST
The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
1
LPDBCS0
Low-power Debouncer Wake-up Status on WKUP0 (cleared on read)
13
1
LPDBCS0Select
NO
No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
1
LPDBCS1
Low-power Debouncer Wake-up Status on WKUP1 (cleared on read)
14
1
LPDBCS1Select
NO
No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
1
WKUPIS0
WKUPx Input Status (cleared on read)
16
1
WKUPIS0Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS1
WKUPx Input Status (cleared on read)
17
1
WKUPIS1Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS2
WKUPx Input Status (cleared on read)
18
1
WKUPIS2Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS3
WKUPx Input Status (cleared on read)
19
1
WKUPIS3Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS4
WKUPx Input Status (cleared on read)
20
1
WKUPIS4Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS5
WKUPx Input Status (cleared on read)
21
1
WKUPIS5Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS6
WKUPx Input Status (cleared on read)
22
1
WKUPIS6Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS7
WKUPx Input Status (cleared on read)
23
1
WKUPIS7Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS8
WKUPx Input Status (cleared on read)
24
1
WKUPIS8Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS9
WKUPx Input Status (cleared on read)
25
1
WKUPIS9Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS10
WKUPx Input Status (cleared on read)
26
1
WKUPIS10Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS11
WKUPx Input Status (cleared on read)
27
1
WKUPIS11Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS12
WKUPx Input Status (cleared on read)
28
1
WKUPIS12Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS13
WKUPx Input Status (cleared on read)
29
1
WKUPIS13Select
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
SYSC_WPMR
Write Protection Mode Register
0xD4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x525443
TC0
6082ZL
Timer Counter
TC
TC_
0x4000C000
0
0xE8
registers
TC0
23
TC1
24
TC2
25
3
64
TC_CHANNEL[%s]
Channel Control Register (channel = 0)
0x0
CCR
Channel Control Register (channel = 0)
0x00
32
write-only
CLKEN
Counter Clock Enable Command
0
1
CLKDIS
Counter Clock Disable Command
1
1
SWTRG
Software Trigger Command
2
1
CMR_CAPTURE_MODE
Channel Mode Register (channel = 0)
0x04
32
TCCLKS
Clock Selection
0
3
TCCLKSSelect
TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
CLKI
Clock Invert
3
1
BURST
Burst Signal Selection
4
2
BURSTSelect
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
LDBDIS
Counter Clock Disable with RB Loading
7
1
ETRGEDG
External Trigger Edge Selection
8
2
ETRGEDGSelect
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ABETRG
TIOAx or TIOBx External Trigger Selection
10
1
CPCTRG
RC Compare Trigger Enable
14
1
WAVE
Waveform Mode
15
1
LDRA
RA Loading Edge Selection
16
2
LDRASelect
NONE
None
0x0
RISING
Rising edge of TIOAx
0x1
FALLING
Falling edge of TIOAx
0x2
EDGE
Each edge of TIOAx
0x3
LDRB
RB Loading Edge Selection
18
2
LDRBSelect
NONE
None
0x0
RISING
Rising edge of TIOAx
0x1
FALLING
Falling edge of TIOAx
0x2
EDGE
Each edge of TIOAx
0x3
SBSMPLR
Loading Edge Subsampling Ratio
20
3
SBSMPLRSelect
ONE
Load a Capture Register each selected edge
0x0
HALF
Load a Capture Register every 2 selected edges
0x1
FOURTH
Load a Capture Register every 4 selected edges
0x2
EIGHTH
Load a Capture Register every 8 selected edges
0x3
SIXTEENTH
Load a Capture Register every 16 selected edges
0x4
CMR_WAVEFORM_MODE
Channel Mode Register (channel = 0)
CMR_CAPTURE_MODE
0x04
32
TCCLKS
Clock Selection
0
3
TCCLKSSelect
TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
CLKI
Clock Invert
3
1
BURST
Burst Signal Selection
4
2
BURSTSelect
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
CPCDIS
Counter Clock Disable with RC Loading
7
1
EEVTEDG
External Event Edge Selection
8
2
EEVTEDGSelect
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edges
0x3
EEVT
External Event Selection
10
2
EEVTSelect
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
ENETRG
External Event Trigger Enable
12
1
WAVSEL
Waveform Selection
13
2
WAVSELSelect
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
WAVE
Waveform Mode
15
1
ACPA
RA Compare Effect on TIOAx
16
2
ACPASelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
ACPC
RC Compare Effect on TIOAx
18
2
ACPCSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
AEEVT
External Event Effect on TIOAx
20
2
AEEVTSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
ASWTRG
Software Trigger Effect on TIOAx
22
2
ASWTRGSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
BCPB
RB Compare Effect on TIOBx
24
2
BCPBSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
BCPC
RC Compare Effect on TIOBx
26
2
BCPCSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
BEEVT
External Event Effect on TIOBx
28
2
BEEVTSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
BSWTRG
Software Trigger Effect on TIOBx
30
2
BSWTRGSelect
NONE
NONE
0x0
SET
SET
0x1
CLEAR
CLEAR
0x2
TOGGLE
TOGGLE
0x3
SMMR
Stepper Motor Mode Register (channel = 0)
0x08
32
GCEN
Gray Count Enable
0
1
DOWN
Down Count
1
1
RAB
Register AB (channel = 0)
0x0C
32
read-only
RAB
Register A or Register B
0
32
CV
Counter Value (channel = 0)
0x10
32
read-only
CV
Counter Value
0
32
RA
Register A (channel = 0)
0x14
32
RA
Register A
0
32
RB
Register B (channel = 0)
0x18
32
RB
Register B
0
32
RC
Register C (channel = 0)
0x1C
32
RC
Register C
0
32
SR
Status Register (channel = 0)
0x20
32
read-only
COVFS
Counter Overflow Status (cleared on read)
0
1
LOVRS
Load Overrun Status (cleared on read)
1
1
CPAS
RA Compare Status (cleared on read)
2
1
CPBS
RB Compare Status (cleared on read)
3
1
CPCS
RC Compare Status (cleared on read)
4
1
LDRAS
RA Loading Status (cleared on read)
5
1
LDRBS
RB Loading Status (cleared on read)
6
1
ETRGS
External Trigger Status (cleared on read)
7
1
CLKSTA
Clock Enabling Status
16
1
MTIOA
TIOAx Mirror
17
1
MTIOB
TIOBx Mirror
18
1
IER
Interrupt Enable Register (channel = 0)
0x24
32
write-only
COVFS
Counter Overflow
0
1
LOVRS
Load Overrun
1
1
CPAS
RA Compare
2
1
CPBS
RB Compare
3
1
CPCS
RC Compare
4
1
LDRAS
RA Loading
5
1
LDRBS
RB Loading
6
1
ETRGS
External Trigger
7
1
IDR
Interrupt Disable Register (channel = 0)
0x28
32
write-only
COVFS
Counter Overflow
0
1
LOVRS
Load Overrun
1
1
CPAS
RA Compare
2
1
CPBS
RB Compare
3
1
CPCS
RC Compare
4
1
LDRAS
RA Loading
5
1
LDRBS
RB Loading
6
1
ETRGS
External Trigger
7
1
IMR
Interrupt Mask Register (channel = 0)
0x2C
32
read-only
COVFS
Counter Overflow
0
1
LOVRS
Load Overrun
1
1
CPAS
RA Compare
2
1
CPBS
RB Compare
3
1
CPCS
RC Compare
4
1
LDRAS
RA Loading
5
1
LDRBS
RB Loading
6
1
ETRGS
External Trigger
7
1
EMR
Extended Mode Register (channel = 0)
0x30
32
TRIGSRCA
Trigger Source for Input A
0
2
TRIGSRCASelect
EXTERNAL_TIOAx
The trigger/capture input A is driven by external pin TIOAx
0
PWMx
The trigger/capture input A is driven internally by PWMx
1
TRIGSRCB
Trigger Source for Input B
4
2
TRIGSRCBSelect
EXTERNAL_TIOBx
The trigger/capture input B is driven by external pin TIOBx
0
PWMx
For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).
1
NODIVCLK
No Divided Clock
8
1
BCR
Block Control Register
0xC0
32
write-only
SYNC
Synchro Command
0
1
BMR
Block Mode Register
0xC4
32
TC0XC0S
External Clock Signal 0 Selection
0
2
TC0XC0SSelect
TCLK0
Signal connected to XC0: TCLK0
0x0
TIOA1
Signal connected to XC0: TIOA1
0x2
TIOA2
Signal connected to XC0: TIOA2
0x3
TC1XC1S
External Clock Signal 1 Selection
2
2
TC1XC1SSelect
TCLK1
Signal connected to XC1: TCLK1
0x0
TIOA0
Signal connected to XC1: TIOA0
0x2
TIOA2
Signal connected to XC1: TIOA2
0x3
TC2XC2S
External Clock Signal 2 Selection
4
2
TC2XC2SSelect
TCLK2
Signal connected to XC2: TCLK2
0x0
TIOA0
Signal connected to XC2: TIOA0
0x2
TIOA1
Signal connected to XC2: TIOA1
0x3
QDEN
Quadrature Decoder Enabled
8
1
POSEN
Position Enabled
9
1
SPEEDEN
Speed Enabled
10
1
QDTRANS
Quadrature Decoding Transparent
11
1
EDGPHA
Edge on PHA Count Mode
12
1
INVA
Inverted PHA
13
1
INVB
Inverted PHB
14
1
INVIDX
Inverted Index
15
1
SWAP
Swap PHA and PHB
16
1
IDXPHB
Index Pin is PHB Pin
17
1
AUTOC
AutoCorrection of missing pulses
18
1
MAXFILT
Maximum Filter
20
6
MAXCMP
Maximum Consecutive Missing Pulses
26
4
QIER
QDEC Interrupt Enable Register
0xC8
32
write-only
IDX
Index
0
1
DIRCHG
Direction Change
1
1
QERR
Quadrature Error
2
1
MPE
Consecutive Missing Pulse Error
3
1
QIDR
QDEC Interrupt Disable Register
0xCC
32
write-only
IDX
Index
0
1
DIRCHG
Direction Change
1
1
QERR
Quadrature Error
2
1
MPE
Consecutive Missing Pulse Error
3
1
QIMR
QDEC Interrupt Mask Register
0xD0
32
read-only
IDX
Index
0
1
DIRCHG
Direction Change
1
1
QERR
Quadrature Error
2
1
MPE
Consecutive Missing Pulse Error
3
1
QISR
QDEC Interrupt Status Register
0xD4
32
read-only
IDX
Index
0
1
DIRCHG
Direction Change
1
1
QERR
Quadrature Error
2
1
MPE
Consecutive Missing Pulse Error
3
1
DIR
Direction
8
1
FMR
Fault Mode Register
0xD8
32
ENCF0
Enable Compare Fault Channel 0
0
1
ENCF1
Enable Compare Fault Channel 1
1
1
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x54494D
TC1
0x40010000
TC3
26
TC4
27
TC5
28
TC2
0x40014000
TC6
47
TC7
48
TC8
49
TC3
0x40054000
TC9
50
TC10
51
TC11
52
TRNG
6334G
True Random Number Generator
0x40070000
0
0x54
registers
TRNG
57
CR
Control Register
0x00
32
write-only
ENABLE
Enables the TRNG to Provide Random Values
0
1
KEY
Security Key
8
24
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.
0x524E47
IER
Interrupt Enable Register
0x10
32
write-only
DATRDY
Data Ready Interrupt Enable
0
1
IDR
Interrupt Disable Register
0x14
32
write-only
DATRDY
Data Ready Interrupt Disable
0
1
IMR
Interrupt Mask Register
0x18
32
read-only
DATRDY
Data Ready Interrupt Mask
0
1
ISR
Interrupt Status Register
0x1C
32
read-only
DATRDY
Data Ready
0
1
ODATA
Output Data Register
0x50
32
read-only
ODATA
Output Data
0
32
TWIHS0
11210Z
Two-wire Interface High Speed
TWIHS
TWIHS_
0x40018000
0
0xEC
registers
TWIHS0
19
CR
Control Register
0x00
32
write-only
START
Send a START Condition
0
1
STOP
Send a STOP Condition
1
1
MSEN
TWIHS Master Mode Enabled
2
1
MSDIS
TWIHS Master Mode Disabled
3
1
SVEN
TWIHS Slave Mode Enabled
4
1
SVDIS
TWIHS Slave Mode Disabled
5
1
QUICK
SMBus Quick Command
6
1
SWRST
Software Reset
7
1
HSEN
TWIHS High-Speed Mode Enabled
8
1
HSDIS
TWIHS High-Speed Mode Disabled
9
1
SMBEN
SMBus Mode Enabled
10
1
SMBDIS
SMBus Mode Disabled
11
1
PECEN
Packet Error Checking Enable
12
1
PECDIS
Packet Error Checking Disable
13
1
PECRQ
PEC Request
14
1
CLEAR
Bus CLEAR Command
15
1
ACMEN
Alternative Command Mode Enable
16
1
ACMDIS
Alternative Command Mode Disable
17
1
THRCLR
Transmit Holding Register Clear
24
1
LOCKCLR
Lock Clear
26
1
FIFOEN
FIFO Enable
28
1
FIFODIS
FIFO Disable
29
1
MMR
Master Mode Register
0x04
32
IADRSZ
Internal Device Address Size
8
2
IADRSZSelect
NONE
No internal device address
0x0
_1_BYTE
One-byte internal device address
0x1
_2_BYTE
Two-byte internal device address
0x2
_3_BYTE
Three-byte internal device address
0x3
MREAD
Master Read Direction
12
1
DADR
Device Address
16
7
SMR
Slave Mode Register
0x08
32
NACKEN
Slave Receiver Data Phase NACK enable
0
1
SMDA
SMBus Default Address
2
1
SMHH
SMBus Host Header
3
1
SCLWSDIS
Clock Wait State Disable
6
1
MASK
Slave Address Mask
8
7
SADR
Slave Address
16
7
SADR1EN
Slave Address 1 Enable
28
1
SADR2EN
Slave Address 2 Enable
29
1
SADR3EN
Slave Address 3 Enable
30
1
DATAMEN
Data Matching Enable
31
1
IADR
Internal Address Register
0x0C
32
IADR
Internal Address
0
24
CWGR
Clock Waveform Generator Register
0x10
32
CLDIV
Clock Low Divider
0
8
CHDIV
Clock High Divider
8
8
CKDIV
Clock Divider
16
3
HOLD
TWD Hold Time Versus TWCK Falling
24
6
SR
Status Register
0x20
32
read-only
TXCOMP
Transmission Completed (cleared by writing TWIHS_THR)
0
1
RXRDY
Receive Holding Register Ready (cleared by reading TWIHS_RHR)
1
1
TXRDY
Transmit Holding Register Ready (cleared by writing TWIHS_THR)
2
1
SVREAD
Slave Read
3
1
SVACC
Slave Access
4
1
GACC
General Call Access (cleared on read)
5
1
OVRE
Overrun Error (cleared on read)
6
1
UNRE
Underrun Error (cleared on read)
7
1
NACK
Not Acknowledged (cleared on read)
8
1
ARBLST
Arbitration Lost (cleared on read)
9
1
SCLWS
Clock Wait State
10
1
EOSACC
End Of Slave Access (cleared on read)
11
1
MCACK
Master Code Acknowledge (cleared on read)
16
1
TOUT
Timeout Error (cleared on read)
18
1
PECERR
PEC Error (cleared on read)
19
1
SMBDAM
SMBus Default Address Match (cleared on read)
20
1
SMBHHM
SMBus Host Header Address Match (cleared on read)
21
1
SCL
SCL Line Value
24
1
SDA
SDA Line Value
25
1
IER
Interrupt Enable Register
0x24
32
write-only
TXCOMP
Transmission Completed Interrupt Enable
0
1
RXRDY
Receive Holding Register Ready Interrupt Enable
1
1
TXRDY
Transmit Holding Register Ready Interrupt Enable
2
1
SVACC
Slave Access Interrupt Enable
4
1
GACC
General Call Access Interrupt Enable
5
1
OVRE
Overrun Error Interrupt Enable
6
1
UNRE
Underrun Error Interrupt Enable
7
1
NACK
Not Acknowledge Interrupt Enable
8
1
ARBLST
Arbitration Lost Interrupt Enable
9
1
SCL_WS
Clock Wait State Interrupt Enable
10
1
EOSACC
End Of Slave Access Interrupt Enable
11
1
MCACK
Master Code Acknowledge Interrupt Enable
16
1
TOUT
Timeout Error Interrupt Enable
18
1
PECERR
PEC Error Interrupt Enable
19
1
SMBDAM
SMBus Default Address Match Interrupt Enable
20
1
SMBHHM
SMBus Host Header Address Match Interrupt Enable
21
1
IDR
Interrupt Disable Register
0x28
32
write-only
TXCOMP
Transmission Completed Interrupt Disable
0
1
RXRDY
Receive Holding Register Ready Interrupt Disable
1
1
TXRDY
Transmit Holding Register Ready Interrupt Disable
2
1
SVACC
Slave Access Interrupt Disable
4
1
GACC
General Call Access Interrupt Disable
5
1
OVRE
Overrun Error Interrupt Disable
6
1
UNRE
Underrun Error Interrupt Disable
7
1
NACK
Not Acknowledge Interrupt Disable
8
1
ARBLST
Arbitration Lost Interrupt Disable
9
1
SCL_WS
Clock Wait State Interrupt Disable
10
1
EOSACC
End Of Slave Access Interrupt Disable
11
1
MCACK
Master Code Acknowledge Interrupt Disable
16
1
TOUT
Timeout Error Interrupt Disable
18
1
PECERR
PEC Error Interrupt Disable
19
1
SMBDAM
SMBus Default Address Match Interrupt Disable
20
1
SMBHHM
SMBus Host Header Address Match Interrupt Disable
21
1
IMR
Interrupt Mask Register
0x2C
32
read-only
TXCOMP
Transmission Completed Interrupt Mask
0
1
RXRDY
Receive Holding Register Ready Interrupt Mask
1
1
TXRDY
Transmit Holding Register Ready Interrupt Mask
2
1
SVACC
Slave Access Interrupt Mask
4
1
GACC
General Call Access Interrupt Mask
5
1
OVRE
Overrun Error Interrupt Mask
6
1
UNRE
Underrun Error Interrupt Mask
7
1
NACK
Not Acknowledge Interrupt Mask
8
1
ARBLST
Arbitration Lost Interrupt Mask
9
1
SCL_WS
Clock Wait State Interrupt Mask
10
1
EOSACC
End Of Slave Access Interrupt Mask
11
1
MCACK
Master Code Acknowledge Interrupt Mask
16
1
TOUT
Timeout Error Interrupt Mask
18
1
PECERR
PEC Error Interrupt Mask
19
1
SMBDAM
SMBus Default Address Match Interrupt Mask
20
1
SMBHHM
SMBus Host Header Address Match Interrupt Mask
21
1
RHR
Receive Holding Register
0x30
32
read-only
RXDATA
Master or Slave Receive Holding Data
0
8
THR
Transmit Holding Register
0x34
32
write-only
TXDATA
Master or Slave Transmit Holding Data
0
8
SMBTR
SMBus Timing Register
0x38
32
PRESC
SMBus Clock Prescaler
0
4
TLOWS
Slave Clock Stretch Maximum Cycles
8
8
TLOWM
Master Clock Stretch Maximum Cycles
16
8
THMAX
Clock High Maximum Cycles
24
8
FILTR
Filter Register
0x44
32
FILT
RX Digital Filter
0
1
PADFEN
PAD Filter Enable
1
1
PADFCFG
PAD Filter Config
2
1
THRES
Digital Filter Threshold
8
3
SWMR
SleepWalking Matching Register
0x4C
32
SADR1
Slave Address 1
0
7
SADR2
Slave Address 2
8
7
SADR3
Slave Address 3
16
7
DATAM
Data Match
24
8
WPMR
Write Protection Mode Register
0xE4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
0x545749
WPSR
Write Protection Status Register
0xE8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
24
TWIHS1
0x4001C000
TWIHS1
20
TWIHS2
0x40060000
TWIHS2
41
UART0
6418R
Universal Asynchronous Receiver Transmitter
UART
UART_
0x400E0800
0
0xE8
registers
UART0
7
CR
Control Register
0x0000
32
write-only
RSTRX
Reset Receiver
2
1
RSTTX
Reset Transmitter
3
1
RXEN
Receiver Enable
4
1
RXDIS
Receiver Disable
5
1
TXEN
Transmitter Enable
6
1
TXDIS
Transmitter Disable
7
1
RSTSTA
Reset Status
8
1
REQCLR
Request Clear
12
1
MR
Mode Register
0x0004
32
FILTER
Receiver Digital Filter
4
1
FILTERSelect
DISABLED
UART does not filter the receive line.
0
ENABLED
UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
1
PAR
Parity Type
9
3
PARSelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
SPACE
Space: parity forced to 0
0x2
MARK
Mark: parity forced to 1
0x3
NO
No parity
0x4
BRSRCCK
Baud Rate Source Clock
12
1
BRSRCCKSelect
PERIPH_CLK
The baud rate is driven by the peripheral clock
0
PMC_PCK
The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)).
1
CHMODE
Channel Mode
14
2
CHMODESelect
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic echo
0x1
LOCAL_LOOPBACK
Local loopback
0x2
REMOTE_LOOPBACK
Remote loopback
0x3
IER
Interrupt Enable Register
0x0008
32
write-only
RXRDY
Enable RXRDY Interrupt
0
1
TXRDY
Enable TXRDY Interrupt
1
1
OVRE
Enable Overrun Error Interrupt
5
1
FRAME
Enable Framing Error Interrupt
6
1
PARE
Enable Parity Error Interrupt
7
1
TXEMPTY
Enable TXEMPTY Interrupt
9
1
CMP
Enable Comparison Interrupt
15
1
IDR
Interrupt Disable Register
0x000C
32
write-only
RXRDY
Disable RXRDY Interrupt
0
1
TXRDY
Disable TXRDY Interrupt
1
1
OVRE
Disable Overrun Error Interrupt
5
1
FRAME
Disable Framing Error Interrupt
6
1
PARE
Disable Parity Error Interrupt
7
1
TXEMPTY
Disable TXEMPTY Interrupt
9
1
CMP
Disable Comparison Interrupt
15
1
IMR
Interrupt Mask Register
0x0010
32
read-only
RXRDY
Mask RXRDY Interrupt
0
1
TXRDY
Disable TXRDY Interrupt
1
1
OVRE
Mask Overrun Error Interrupt
5
1
FRAME
Mask Framing Error Interrupt
6
1
PARE
Mask Parity Error Interrupt
7
1
TXEMPTY
Mask TXEMPTY Interrupt
9
1
CMP
Mask Comparison Interrupt
15
1
SR
Status Register
0x0014
32
read-only
RXRDY
Receiver Ready
0
1
TXRDY
Transmitter Ready
1
1
OVRE
Overrun Error
5
1
FRAME
Framing Error
6
1
PARE
Parity Error
7
1
TXEMPTY
Transmitter Empty
9
1
CMP
Comparison Match
15
1
RHR
Receive Holding Register
0x0018
32
read-only
RXCHR
Received Character
0
8
THR
Transmit Holding Register
0x001C
32
write-only
TXCHR
Character to be Transmitted
0
8
BRGR
Baud Rate Generator Register
0x0020
32
CD
Clock Divisor
0
16
CMPR
Comparison Register
0x0024
32
VAL1
First Comparison Value for Received Character
0
8
CMPMODE
Comparison Mode
12
1
CMPMODESelect
FLAG_ONLY
Any character is received and comparison function drives CMP flag.
0
START_CONDITION
Comparison condition must be met to start reception.
1
CMPPAR
Compare Parity
14
1
VAL2
Second Comparison Value for Received Character
16
8
WPMR
Write Protection Mode Register
0x00E4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
0x554152
UART1
0x400E0A00
UART1
8
UART2
0x400E1A00
UART2
44
UART3
0x400E1C00
UART3
45
UART4
0x400E1E00
UART4
46
USART0
6089ZW
Universal Synchronous Asynchronous Receiver Transmitter
USART
USART_
0x40024000
0
0xEC
registers
USART0
13
US_CR_USART_MODE
Control Register
0x0000
32
write-only
RSTRX
Reset Receiver
2
1
RSTTX
Reset Transmitter
3
1
RXEN
Receiver Enable
4
1
RXDIS
Receiver Disable
5
1
TXEN
Transmitter Enable
6
1
TXDIS
Transmitter Disable
7
1
RSTSTA
Reset Status Bits
8
1
STTBRK
Start Break
9
1
STPBRK
Stop Break
10
1
STTTO
Clear TIMEOUT Flag and Start Timeout After Next Character Received
11
1
SENDA
Send Address
12
1
RSTIT
Reset Iterations
13
1
RSTNACK
Reset Non Acknowledge
14
1
RETTO
Start Timeout Immediately
15
1
DTREN
Data Terminal Ready Enable
16
1
DTRDIS
Data Terminal Ready Disable
17
1
RTSEN
Request to Send Enable
18
1
RTSDIS
Request to Send Disable
19
1
US_CR_SPI_MODE
Control Register
US_CR_USART_MODE
0x0000
32
write-only
RSTRX
Reset Receiver
2
1
RSTTX
Reset Transmitter
3
1
RXEN
Receiver Enable
4
1
RXDIS
Receiver Disable
5
1
TXEN
Transmitter Enable
6
1
TXDIS
Transmitter Disable
7
1
RSTSTA
Reset Status Bits
8
1
FCS
Force SPI Chip Select
18
1
RCS
Release SPI Chip Select
19
1
US_CR_LIN_MODE
Control Register
US_CR_USART_MODE
0x0000
32
write-only
RSTRX
Reset Receiver
2
1
RSTTX
Reset Transmitter
3
1
RXEN
Receiver Enable
4
1
RXDIS
Receiver Disable
5
1
TXEN
Transmitter Enable
6
1
TXDIS
Transmitter Disable
7
1
RSTSTA
Reset Status Bits
8
1
LINABT
Abort LIN Transmission
20
1
LINWKUP
Send LIN Wakeup Signal
21
1
US_MR_USART_MODE
Mode Register
0x0004
32
USART_MODE
USART Mode of Operation
0
4
USART_MODESelect
NORMAL
Normal mode
0x0
RS485
RS485
0x1
HW_HANDSHAKING
Hardware handshaking
0x2
MODEM
Modem
0x3
IS07816_T_0
IS07816 Protocol: T = 0
0x4
IS07816_T_1
IS07816 Protocol: T = 1
0x6
IRDA
IrDA
0x8
LON
LON
0x9
LIN_MASTER
LIN Master mode
0xA
LIN_SLAVE
LIN Slave mode
0xB
SPI_MASTER
SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)
0xE
SPI_SLAVE
SPI Slave mode
0xF
USCLKS
Clock Selection
4
2
USCLKSSelect
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV = 8) is selected
0x1
PCK
PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.
0x2
SCK
Serial clock (SCK) is selected
0x3
CHRL
Character Length
6
2
CHRLSelect
_5_BIT
Character length is 5 bits
0x0
_6_BIT
Character length is 6 bits
0x1
_7_BIT
Character length is 7 bits
0x2
_8_BIT
Character length is 8 bits
0x3
SYNC
Synchronous Mode Select
8
1
PAR
Parity Type
9
3
PARSelect
EVEN
Even parity
0x0
ODD
Odd parity
0x1
SPACE
Parity forced to 0 (Space)
0x2
MARK
Parity forced to 1 (Mark)
0x3
NO
No parity
0x4
MULTIDROP
Multidrop mode
0x6
NBSTOP
Number of Stop Bits
12
2
NBSTOPSelect
_1_BIT
1 stop bit
0x0
_1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x1
_2_BIT
2 stop bits
0x2
CHMODE
Channel Mode
14
2
CHMODESelect
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x1
LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x2
REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
0x3
MSBF
Bit Order
16
1
MODE9
9-bit Character Length
17
1
CLKO
Clock Output Select
18
1
OVER
Oversampling Mode
19
1
INACK
Inhibit Non Acknowledge
20
1
DSNACK
Disable Successive NACK
21
1
VAR_SYNC
Variable Synchronization of Command/Data Sync Start Frame Delimiter
22
1
INVDATA
Inverted Data
23
1
MAX_ITERATION
Maximum Number of Automatic Iteration
24
3
FILTER
Receive Line Filter
28
1
MAN
Manchester Encoder/Decoder Enable
29
1
MODSYNC
Manchester Synchronization Mode
30
1
ONEBIT
Start Frame Delimiter Selector
31
1
US_MR_SPI_MODE
Mode Register
US_MR_USART_MODE
0x0004
32
USART_MODE
USART Mode of Operation
0
4
USART_MODESelect
NORMAL
Normal mode
0x0
RS485
RS485
0x1
HW_HANDSHAKING
Hardware handshaking
0x2
MODEM
Modem
0x3
IS07816_T_0
IS07816 Protocol: T = 0
0x4
IS07816_T_1
IS07816 Protocol: T = 1
0x6
IRDA
IrDA
0x8
LON
LON
0x9
LIN_MASTER
LIN Master mode
0xA
LIN_SLAVE
LIN Slave mode
0xB
SPI_MASTER
SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)
0xE
SPI_SLAVE
SPI Slave mode
0xF
USCLKS
Clock Selection
4
2
USCLKSSelect
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV = 8) is selected
0x1
PCK
PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.
0x2
SCK
Serial clock (SCK) is selected
0x3
CHRL
Character Length
6
2
CHRLSelect
_5_BIT
Character length is 5 bits
0x0
_6_BIT
Character length is 6 bits
0x1
_7_BIT
Character length is 7 bits
0x2
_8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
CPHA
SPI Clock Phase
8
1
CPOL
SPI Clock Polarity
16
1
WRDBT
Wait Read Data Before Transfer
20
1
US_IER_USART_MODE
Interrupt Enable Register
0x0008
32
write-only
RXRDY
RXRDY Interrupt Enable
0
1
TXRDY
TXRDY Interrupt Enable
1
1
RXBRK
Receiver Break Interrupt Enable
2
1
OVRE
Overrun Error Interrupt Enable
5
1
FRAME
Framing Error Interrupt Enable
6
1
PARE
Parity Error Interrupt Enable
7
1
TIMEOUT
Timeout Interrupt Enable
8
1
TXEMPTY
TXEMPTY Interrupt Enable
9
1
ITER
Max number of Repetitions Reached Interrupt Enable
10
1
NACK
Non Acknowledge Interrupt Enable
13
1
RIIC
Ring Indicator Input Change Enable
16
1
DSRIC
Data Set Ready Input Change Enable
17
1
DCDIC
Data Carrier Detect Input Change Interrupt Enable
18
1
CTSIC
Clear to Send Input Change Interrupt Enable
19
1
MANE
Manchester Error Interrupt Enable
24
1
US_IER_SPI_MODE
Interrupt Enable Register
US_IER_USART_MODE
0x0008
32
write-only
RXRDY
RXRDY Interrupt Enable
0
1
TXRDY
TXRDY Interrupt Enable
1
1
OVRE
Overrun Error Interrupt Enable
5
1
TXEMPTY
TXEMPTY Interrupt Enable
9
1
UNRE
Underrun Error Interrupt Enable
10
1
NSSE
NSS Line (Driving CTS Pin) Rising or Falling Edge Event
19
1
US_IER_LIN_MODE
Interrupt Enable Register
US_IER_USART_MODE
0x0008
32
write-only
RXRDY
RXRDY Interrupt Enable
0
1
TXRDY
TXRDY Interrupt Enable
1
1
OVRE
Overrun Error Interrupt Enable
5
1
FRAME
Framing Error Interrupt Enable
6
1
PARE
Parity Error Interrupt Enable
7
1
TIMEOUT
Timeout Interrupt Enable
8
1
TXEMPTY
TXEMPTY Interrupt Enable
9
1
LINBK
LIN Break Sent or LIN Break Received Interrupt Enable
13
1
LINID
LIN Identifier Sent or LIN Identifier Received Interrupt Enable
14
1
LINTC
LIN Transfer Completed Interrupt Enable
15
1
LINBE
LIN Bus Error Interrupt Enable
25
1
LINISFE
LIN Inconsistent Synch Field Error Interrupt Enable
26
1
LINIPE
LIN Identifier Parity Interrupt Enable
27
1
LINCE
LIN Checksum Error Interrupt Enable
28
1
LINSNRE
LIN Slave Not Responding Error Interrupt Enable
29
1
LINSTE
LIN Synch Tolerance Error Interrupt Enable
30
1
LINHTE
LIN Header Timeout Error Interrupt Enable
31
1
US_IER_LON_MODE
Interrupt Enable Register
US_IER_USART_MODE
0x0008
32
write-only
RXRDY
RXRDY Interrupt Enable
0
1
TXRDY
TXRDY Interrupt Enable
1
1
OVRE
Overrun Error Interrupt Enable
5
1
LSFE
LON Short Frame Error Interrupt Enable
6
1
LCRCE
LON CRC Error Interrupt Enable
7
1
TXEMPTY
TXEMPTY Interrupt Enable
9
1
UNRE
Underrun Error Interrupt Enable
10
1
LTXD
LON Transmission Done Interrupt Enable
24
1
LCOL
LON Collision Interrupt Enable
25
1
LFET
LON Frame Early Termination Interrupt Enable
26
1
LRXD
LON Reception Done Interrupt Enable
27
1
LBLOVFE
LON Backlog Overflow Error Interrupt Enable
28
1
US_IDR_USART_MODE
Interrupt Disable Register
0x000C
32
write-only
RXRDY
RXRDY Interrupt Disable
0
1
TXRDY
TXRDY Interrupt Disable
1
1
RXBRK
Receiver Break Interrupt Disable
2
1
OVRE
Overrun Error Interrupt Enable
5
1
FRAME
Framing Error Interrupt Disable
6
1
PARE
Parity Error Interrupt Disable
7
1
TIMEOUT
Timeout Interrupt Disable
8
1
TXEMPTY
TXEMPTY Interrupt Disable
9
1
ITER
Max Number of Repetitions Reached Interrupt Disable
10
1
NACK
Non Acknowledge Interrupt Disable
13
1
RIIC
Ring Indicator Input Change Disable
16
1
DSRIC
Data Set Ready Input Change Disable
17
1
DCDIC
Data Carrier Detect Input Change Interrupt Disable
18
1
CTSIC
Clear to Send Input Change Interrupt Disable
19
1
MANE
Manchester Error Interrupt Disable
24
1
US_IDR_SPI_MODE
Interrupt Disable Register
US_IDR_USART_MODE
0x000C
32
write-only
RXRDY
RXRDY Interrupt Disable
0
1
TXRDY
TXRDY Interrupt Disable
1
1
OVRE
Overrun Error Interrupt Enable
5
1
TXEMPTY
TXEMPTY Interrupt Disable
9
1
UNRE
SPI Underrun Error Interrupt Disable
10
1
NSSE
NSS Line (Driving CTS Pin) Rising or Falling Edge Event
19
1
US_IDR_LIN_MODE
Interrupt Disable Register
US_IDR_USART_MODE
0x000C
32
write-only
RXRDY
RXRDY Interrupt Disable
0
1
TXRDY
TXRDY Interrupt Disable
1
1
OVRE
Overrun Error Interrupt Enable
5
1
FRAME
Framing Error Interrupt Disable
6
1
PARE
Parity Error Interrupt Disable
7
1
TIMEOUT
Timeout Interrupt Disable
8
1
TXEMPTY
TXEMPTY Interrupt Disable
9
1
LINBK
LIN Break Sent or LIN Break Received Interrupt Disable
13
1
LINID
LIN Identifier Sent or LIN Identifier Received Interrupt Disable
14
1
LINTC
LIN Transfer Completed Interrupt Disable
15
1
LINBE
LIN Bus Error Interrupt Disable
25
1
LINISFE
LIN Inconsistent Synch Field Error Interrupt Disable
26
1
LINIPE
LIN Identifier Parity Interrupt Disable
27
1
LINCE
LIN Checksum Error Interrupt Disable
28
1
LINSNRE
LIN Slave Not Responding Error Interrupt Disable
29
1
LINSTE
LIN Synch Tolerance Error Interrupt Disable
30
1
LINHTE
LIN Header Timeout Error Interrupt Disable
31
1
US_IDR_LON_MODE
Interrupt Disable Register
US_IDR_USART_MODE
0x000C
32
write-only
RXRDY
RXRDY Interrupt Disable
0
1
TXRDY
TXRDY Interrupt Disable
1
1
OVRE
Overrun Error Interrupt Enable
5
1
LSFE
LON Short Frame Error Interrupt Disable
6
1
LCRCE
LON CRC Error Interrupt Disable
7
1
TXEMPTY
TXEMPTY Interrupt Disable
9
1
UNRE
SPI Underrun Error Interrupt Disable
10
1
LTXD
LON Transmission Done Interrupt Disable
24
1
LCOL
LON Collision Interrupt Disable
25
1
LFET
LON Frame Early Termination Interrupt Disable
26
1
LRXD
LON Reception Done Interrupt Disable
27
1
LBLOVFE
LON Backlog Overflow Error Interrupt Disable
28
1
US_IMR_USART_MODE
Interrupt Mask Register
0x0010
32
read-only
RXRDY
RXRDY Interrupt Mask
0
1
TXRDY
TXRDY Interrupt Mask
1
1
RXBRK
Receiver Break Interrupt Mask
2
1
OVRE
Overrun Error Interrupt Mask
5
1
FRAME
Framing Error Interrupt Mask
6
1
PARE
Parity Error Interrupt Mask
7
1
TIMEOUT
Timeout Interrupt Mask
8
1
TXEMPTY
TXEMPTY Interrupt Mask
9
1
ITER
Max Number of Repetitions Reached Interrupt Mask
10
1
NACK
Non Acknowledge Interrupt Mask
13
1
RIIC
Ring Indicator Input Change Mask
16
1
DSRIC
Data Set Ready Input Change Mask
17
1
DCDIC
Data Carrier Detect Input Change Interrupt Mask
18
1
CTSIC
Clear to Send Input Change Interrupt Mask
19
1
MANE
Manchester Error Interrupt Mask
24
1
US_IMR_SPI_MODE
Interrupt Mask Register
US_IMR_USART_MODE
0x0010
32
read-only
RXRDY
RXRDY Interrupt Mask
0
1
TXRDY
TXRDY Interrupt Mask
1
1
OVRE
Overrun Error Interrupt Mask
5
1
UNRE
SPI Underrun Error Interrupt Mask
10
1
TXEMPTY
TXEMPTY Interrupt Mask
9
1
NSSE
NSS Line (Driving CTS Pin) Rising or Falling Edge Event
19
1
US_IMR_LIN_MODE
Interrupt Mask Register
US_IMR_USART_MODE
0x0010
32
read-only
RXRDY
RXRDY Interrupt Mask
0
1
TXRDY
TXRDY Interrupt Mask
1
1
OVRE
Overrun Error Interrupt Mask
5
1
FRAME
Framing Error Interrupt Mask
6
1
PARE
Parity Error Interrupt Mask
7
1
TIMEOUT
Timeout Interrupt Mask
8
1
TXEMPTY
TXEMPTY Interrupt Mask
9
1
LINBK
LIN Break Sent or LIN Break Received Interrupt Mask
13
1
LINID
LIN Identifier Sent or LIN Identifier Received Interrupt Mask
14
1
LINTC
LIN Transfer Completed Interrupt Mask
15
1
LINBE
LIN Bus Error Interrupt Mask
25
1
LINISFE
LIN Inconsistent Synch Field Error Interrupt Mask
26
1
LINIPE
LIN Identifier Parity Interrupt Mask
27
1
LINCE
LIN Checksum Error Interrupt Mask
28
1
LINSNRE
LIN Slave Not Responding Error Interrupt Mask
29
1
LINSTE
LIN Synch Tolerance Error Interrupt Mask
30
1
LINHTE
LIN Header Timeout Error Interrupt Mask
31
1
US_IMR_LON_MODE
Interrupt Mask Register
US_IMR_USART_MODE
0x0010
32
read-only
RXRDY
RXRDY Interrupt Mask
0
1
TXRDY
TXRDY Interrupt Mask
1
1
OVRE
Overrun Error Interrupt Mask
5
1
LSFE
LON Short Frame Error Interrupt Mask
6
1
LCRCE
LON CRC Error Interrupt Mask
7
1
TXEMPTY
TXEMPTY Interrupt Mask
9
1
UNRE
SPI Underrun Error Interrupt Mask
10
1
LTXD
LON Transmission Done Interrupt Mask
24
1
LCOL
LON Collision Interrupt Mask
25
1
LFET
LON Frame Early Termination Interrupt Mask
26
1
LRXD
LON Reception Done Interrupt Mask
27
1
LBLOVFE
LON Backlog Overflow Error Interrupt Mask
28
1
US_CSR_USART_MODE
Channel Status Register
0x0014
32
read-only
RXRDY
Receiver Ready (cleared by reading US_RHR)
0
1
TXRDY
Transmitter Ready (cleared by writing US_THR)
1
1
RXBRK
Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)
2
1
OVRE
Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
5
1
FRAME
Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
6
1
PARE
Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
7
1
TIMEOUT
Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)
8
1
TXEMPTY
Transmitter Empty (cleared by writing US_THR)
9
1
ITER
Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)
10
1
NACK
Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)
13
1
RIIC
Ring Indicator Input Change Flag (cleared on read)
16
1
DSRIC
Data Set Ready Input Change Flag (cleared on read)
17
1
DCDIC
Data Carrier Detect Input Change Flag (cleared on read)
18
1
CTSIC
Clear to Send Input Change Flag (cleared on read)
19
1
RI
Image of RI Input
20
1
DSR
Image of DSR Input
21
1
DCD
Image of DCD Input
22
1
CTS
Image of CTS Input
23
1
MANERR
Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)
24
1
US_CSR_SPI_MODE
Channel Status Register
US_CSR_USART_MODE
0x0014
32
read-only
RXRDY
Receiver Ready (cleared by reading US_RHR)
0
1
TXRDY
Transmitter Ready (cleared by writing US_THR)
1
1
OVRE
Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
5
1
TXEMPTY
Transmitter Empty (cleared by writing US_THR)
9
1
UNRE
SPI Underrun Error
10
1
NSSE
NSS Line (Driving CTS Pin) Rising or Falling Edge Event
19
1
NSS
Image of NSS Line
23
1
US_CSR_LIN_MODE
Channel Status Register
US_CSR_USART_MODE
0x0014
32
read-only
RXRDY
Receiver Ready (cleared by reading US_RHR)
0
1
TXRDY
Transmitter Ready (cleared by writing US_THR)
1
1
OVRE
Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
5
1
FRAME
Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
6
1
PARE
Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
7
1
TIMEOUT
Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)
8
1
TXEMPTY
Transmitter Empty (cleared by writing US_THR)
9
1
LINBK
LIN Break Sent or LIN Break Received
13
1
LINID
LIN Identifier Sent or LIN Identifier Received
14
1
LINTC
LIN Transfer Completed
15
1
LINBLS
LIN Bus Line Status
23
1
LINBE
LIN Bus Error
25
1
LINISFE
LIN Inconsistent Synch Field Error
26
1
LINIPE
LIN Identifier Parity Error
27
1
LINCE
LIN Checksum Error
28
1
LINSNRE
LIN Slave Not Responding Error Interrupt Mask
29
1
LINSTE
LIN Synch Tolerance Error
30
1
LINHTE
LIN Header Timeout Error
31
1
US_CSR_LON_MODE
Channel Status Register
US_CSR_USART_MODE
0x0014
32
read-only
RXRDY
Receiver Ready (cleared by reading US_RHR)
0
1
TXRDY
Transmitter Ready (cleared by writing US_THR)
1
1
OVRE
Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
5
1
LSFE
LON Short Frame Error
6
1
LCRCE
LON CRC Error
7
1
TXEMPTY
Transmitter Empty (cleared by writing US_THR)
9
1
UNRE
Underrun Error
10
1
LTXD
LON Transmission End Flag
24
1
LCOL
LON Collision Detected Flag
25
1
LFET
LON Frame Early Termination
26
1
LRXD
LON Reception End Flag
27
1
LBLOVFE
LON Backlog Overflow Error
28
1
US_RHR
Receive Holding Register
0x0018
32
read-only
RXCHR
Received Character
0
9
RXSYNH
Received Sync
15
1
US_THR
Transmit Holding Register
0x001C
32
write-only
TXCHR
Character to be Transmitted
0
9
TXSYNH
Sync Field to be Transmitted
15
1
US_BRGR
Baud Rate Generator Register
0x0020
32
CD
Clock Divider
0
16
FP
Fractional Part
16
3
US_RTOR
Receiver Timeout Register
0x0024
32
TO
Timeout Value
0
17
US_TTGR_USART_MODE
Transmitter Timeguard Register
0x0028
32
TG
Timeguard Value
0
8
US_TTGR_LON_MODE
Transmitter Timeguard Register
US_TTGR_USART_MODE
0x0028
32
PCYCLE
LON PCYCLE Length
0
24
US_FIDI_USART_MODE
FI DI Ratio Register
0x0040
32
FI_DI_RATIO
FI Over DI Ratio Value
0
16
US_FIDI_LON_MODE
FI DI Ratio Register
US_FIDI_USART_MODE
0x0040
32
BETA2
LON BETA2 Length
0
24
US_NER
Number of Errors Register
0x0044
32
read-only
NB_ERRORS
Number of Errors
0
8
US_IF
IrDA Filter Register
0x004C
32
IRDA_FILTER
IrDA Filter
0
8
US_MAN
Manchester Configuration Register
0x0050
32
TX_PL
Transmitter Preamble Length
0
4
TX_PP
Transmitter Preamble Pattern
8
2
TX_PPSelect
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
TX_MPOL
Transmitter Manchester Polarity
12
1
RX_PL
Receiver Preamble Length
16
4
RX_PP
Receiver Preamble Pattern detected
24
2
RX_PPSelect
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
RX_MPOL
Receiver Manchester Polarity
28
1
ONE
Must Be Set to 1
29
1
DRIFT
Drift Compensation
30
1
RXIDLEV
Receiver Idle Value
31
1
US_LINMR
LIN Mode Register
0x0054
32
NACT
LIN Node Action
0
2
NACTSelect
PUBLISH
The USART transmits the response.
0x0
SUBSCRIBE
The USART receives the response.
0x1
IGNORE
The USART does not transmit and does not receive the response.
0x2
PARDIS
Parity Disable
2
1
CHKDIS
Checksum Disable
3
1
CHKTYP
Checksum Type
4
1
DLM
Data Length Mode
5
1
FSDIS
Frame Slot Mode Disable
6
1
WKUPTYP
Wakeup Signal Type
7
1
DLC
Data Length Control
8
8
PDCM
DMAC Mode
16
1
SYNCDIS
Synchronization Disable
17
1
US_LINIR
LIN Identifier Register
0x0058
32
IDCHR
Identifier Character
0
8
US_LINBRR
LIN Baud Rate Register
0x005C
32
read-only
LINCD
Clock Divider after Synchronization
0
16
LINFP
Fractional Part after Synchronization
16
3
US_LONMR
LON Mode Register
0x0060
32
COMMT
LON comm_type Parameter Value
0
1
COLDET
LON Collision Detection Feature
1
1
TCOL
Terminate Frame upon Collision Notification
2
1
CDTAIL
LON Collision Detection on Frame Tail
3
1
DMAM
LON DMA Mode
4
1
LCDS
LON Collision Detection Source
5
1
EOFS
End of Frame Condition Size
16
8
US_LONPR
LON Preamble Register
0x0064
32
LONPL
LON Preamble Length
0
14
US_LONDL
LON Data Length Register
0x0068
32
LONDL
LON Data Length
0
8
US_LONL2HDR
LON L2HDR Register
0x006C
32
BLI
LON Backlog Increment
0
6
ALTP
LON Alternate Path Bit
6
1
PB
LON Priority Bit
7
1
US_LONBL
LON Backlog Register
0x0070
32
read-only
LONBL
LON Node Backlog Value
0
6
US_LONB1TX
LON Beta1 Tx Register
0x0074
32
BETA1TX
LON Beta1 Length after Transmission
0
24
US_LONB1RX
LON Beta1 Rx Register
0x0078
32
BETA1RX
LON Beta1 Length after Reception
0
24
US_LONPRIO
LON Priority Register
0x007C
32
PSNB
LON Priority Slot Number
0
7
NPS
LON Node Priority Slot
8
7
US_IDTTX
LON IDT Tx Register
0x0080
32
IDTTX
LON Indeterminate Time after Transmission (comm_type = 1 mode only)
0
24
US_IDTRX
LON IDT Rx Register
0x0084
32
IDTRX
LON Indeterminate Time after Reception (comm_type = 1 mode only)
0
24
US_ICDIFF
IC DIFF Register
0x0088
32
ICDIFF
IC Differentiator Number
0
4
US_WPMR
Write Protection Mode Register
0x00E4
32
WPEN
Write Protection Enable
0
1
WPKEY
Write Protection Key
8
24
WPKEYSelect
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x555341
US_WPSR
Write Protection Status Register
0x00E8
32
read-only
WPVS
Write Protection Violation Status
0
1
WPVSRC
Write Protection Violation Source
8
16
USART1
0x40028000
USART1
14
USART2
0x4002C000
USART2
15
USBHS
11292G
USB High-Speed Interface
0x40038000
0
0x810
registers
USBHS
34
DEVCTRL
Device General Control Register
0x0000
32
UADD
USB Address
0
7
ADDEN
Address Enable
7
1
DETACH
Detach
8
1
RMWKUP
Remote Wake-Up
9
1
SPDCONF
Mode Configuration
10
2
SPDCONFSelect
NORMAL
The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.
0x0
LOW_POWER
For a better consumption, if high speed is not needed.
0x1
HIGH_SPEED
Forced high speed.
0x2
FORCED_FS
The peripheral remains in Full-speed mode whatever the host speed capability.
0x3
LS
Low-Speed Mode Force
12
1
TSTJ
Test mode J
13
1
TSTK
Test mode K
14
1
TSTPCKT
Test packet mode
15
1
OPMODE2
Specific Operational mode
16
1
DEVISR
Device Global Interrupt Status Register
0x0004
32
read-only
SUSP
Suspend Interrupt
0
1
MSOF
Micro Start of Frame Interrupt
1
1
SOF
Start of Frame Interrupt
2
1
EORST
End of Reset Interrupt
3
1
WAKEUP
Wake-Up Interrupt
4
1
EORSM
End of Resume Interrupt
5
1
UPRSM
Upstream Resume Interrupt
6
1
PEP_0
Endpoint 0 Interrupt
12
1
PEP_1
Endpoint 1 Interrupt
13
1
PEP_2
Endpoint 2 Interrupt
14
1
PEP_3
Endpoint 3 Interrupt
15
1
PEP_4
Endpoint 4 Interrupt
16
1
PEP_5
Endpoint 5 Interrupt
17
1
PEP_6
Endpoint 6 Interrupt
18
1
PEP_7
Endpoint 7 Interrupt
19
1
PEP_8
Endpoint 8 Interrupt
20
1
PEP_9
Endpoint 9 Interrupt
21
1
DMA_1
DMA Channel 1 Interrupt
25
1
DMA_2
DMA Channel 2 Interrupt
26
1
DMA_3
DMA Channel 3 Interrupt
27
1
DMA_4
DMA Channel 4 Interrupt
28
1
DMA_5
DMA Channel 5 Interrupt
29
1
DMA_6
DMA Channel 6 Interrupt
30
1
DMA_7
DMA Channel 7 Interrupt
31
1
DEVICR
Device Global Interrupt Clear Register
0x0008
32
write-only
SUSPC
Suspend Interrupt Clear
0
1
MSOFC
Micro Start of Frame Interrupt Clear
1
1
SOFC
Start of Frame Interrupt Clear
2
1
EORSTC
End of Reset Interrupt Clear
3
1
WAKEUPC
Wake-Up Interrupt Clear
4
1
EORSMC
End of Resume Interrupt Clear
5
1
UPRSMC
Upstream Resume Interrupt Clear
6
1
DEVIFR
Device Global Interrupt Set Register
0x000C
32
write-only
SUSPS
Suspend Interrupt Set
0
1
MSOFS
Micro Start of Frame Interrupt Set
1
1
SOFS
Start of Frame Interrupt Set
2
1
EORSTS
End of Reset Interrupt Set
3
1
WAKEUPS
Wake-Up Interrupt Set
4
1
EORSMS
End of Resume Interrupt Set
5
1
UPRSMS
Upstream Resume Interrupt Set
6
1
DMA_1
DMA Channel 1 Interrupt Set
25
1
DMA_2
DMA Channel 2 Interrupt Set
26
1
DMA_3
DMA Channel 3 Interrupt Set
27
1
DMA_4
DMA Channel 4 Interrupt Set
28
1
DMA_5
DMA Channel 5 Interrupt Set
29
1
DMA_6
DMA Channel 6 Interrupt Set
30
1
DMA_7
DMA Channel 7 Interrupt Set
31
1
DEVIMR
Device Global Interrupt Mask Register
0x0010
32
read-only
SUSPE
Suspend Interrupt Mask
0
1
MSOFE
Micro Start of Frame Interrupt Mask
1
1
SOFE
Start of Frame Interrupt Mask
2
1
EORSTE
End of Reset Interrupt Mask
3
1
WAKEUPE
Wake-Up Interrupt Mask
4
1
EORSME
End of Resume Interrupt Mask
5
1
UPRSME
Upstream Resume Interrupt Mask
6
1
PEP_0
Endpoint 0 Interrupt Mask
12
1
PEP_1
Endpoint 1 Interrupt Mask
13
1
PEP_2
Endpoint 2 Interrupt Mask
14
1
PEP_3
Endpoint 3 Interrupt Mask
15
1
PEP_4
Endpoint 4 Interrupt Mask
16
1
PEP_5
Endpoint 5 Interrupt Mask
17
1
PEP_6
Endpoint 6 Interrupt Mask
18
1
PEP_7
Endpoint 7 Interrupt Mask
19
1
PEP_8
Endpoint 8 Interrupt Mask
20
1
PEP_9
Endpoint 9 Interrupt Mask
21
1
DMA_1
DMA Channel 1 Interrupt Mask
25
1
DMA_2
DMA Channel 2 Interrupt Mask
26
1
DMA_3
DMA Channel 3 Interrupt Mask
27
1
DMA_4
DMA Channel 4 Interrupt Mask
28
1
DMA_5
DMA Channel 5 Interrupt Mask
29
1
DMA_6
DMA Channel 6 Interrupt Mask
30
1
DMA_7
DMA Channel 7 Interrupt Mask
31
1
DEVIDR
Device Global Interrupt Disable Register
0x0014
32
write-only
SUSPEC
Suspend Interrupt Disable
0
1
MSOFEC
Micro Start of Frame Interrupt Disable
1
1
SOFEC
Start of Frame Interrupt Disable
2
1
EORSTEC
End of Reset Interrupt Disable
3
1
WAKEUPEC
Wake-Up Interrupt Disable
4
1
EORSMEC
End of Resume Interrupt Disable
5
1
UPRSMEC
Upstream Resume Interrupt Disable
6
1
PEP_0
Endpoint 0 Interrupt Disable
12
1
PEP_1
Endpoint 1 Interrupt Disable
13
1
PEP_2
Endpoint 2 Interrupt Disable
14
1
PEP_3
Endpoint 3 Interrupt Disable
15
1
PEP_4
Endpoint 4 Interrupt Disable
16
1
PEP_5
Endpoint 5 Interrupt Disable
17
1
PEP_6
Endpoint 6 Interrupt Disable
18
1
PEP_7
Endpoint 7 Interrupt Disable
19
1
PEP_8
Endpoint 8 Interrupt Disable
20
1
PEP_9
Endpoint 9 Interrupt Disable
21
1
DMA_1
DMA Channel 1 Interrupt Disable
25
1
DMA_2
DMA Channel 2 Interrupt Disable
26
1
DMA_3
DMA Channel 3 Interrupt Disable
27
1
DMA_4
DMA Channel 4 Interrupt Disable
28
1
DMA_5
DMA Channel 5 Interrupt Disable
29
1
DMA_6
DMA Channel 6 Interrupt Disable
30
1
DMA_7
DMA Channel 7 Interrupt Disable
31
1
DEVIER
Device Global Interrupt Enable Register
0x0018
32
write-only
SUSPES
Suspend Interrupt Enable
0
1
MSOFES
Micro Start of Frame Interrupt Enable
1
1
SOFES
Start of Frame Interrupt Enable
2
1
EORSTES
End of Reset Interrupt Enable
3
1
WAKEUPES
Wake-Up Interrupt Enable
4
1
EORSMES
End of Resume Interrupt Enable
5
1
UPRSMES
Upstream Resume Interrupt Enable
6
1
PEP_0
Endpoint 0 Interrupt Enable
12
1
PEP_1
Endpoint 1 Interrupt Enable
13
1
PEP_2
Endpoint 2 Interrupt Enable
14
1
PEP_3
Endpoint 3 Interrupt Enable
15
1
PEP_4
Endpoint 4 Interrupt Enable
16
1
PEP_5
Endpoint 5 Interrupt Enable
17
1
PEP_6
Endpoint 6 Interrupt Enable
18
1
PEP_7
Endpoint 7 Interrupt Enable
19
1
PEP_8
Endpoint 8 Interrupt Enable
20
1
PEP_9
Endpoint 9 Interrupt Enable
21
1
DMA_1
DMA Channel 1 Interrupt Enable
25
1
DMA_2
DMA Channel 2 Interrupt Enable
26
1
DMA_3
DMA Channel 3 Interrupt Enable
27
1
DMA_4
DMA Channel 4 Interrupt Enable
28
1
DMA_5
DMA Channel 5 Interrupt Enable
29
1
DMA_6
DMA Channel 6 Interrupt Enable
30
1
DMA_7
DMA Channel 7 Interrupt Enable
31
1
DEVEPT
Device Endpoint Register
0x001C
32
EPEN0
Endpoint 0 Enable
0
1
EPEN1
Endpoint 1 Enable
1
1
EPEN2
Endpoint 2 Enable
2
1
EPEN3
Endpoint 3 Enable
3
1
EPEN4
Endpoint 4 Enable
4
1
EPEN5
Endpoint 5 Enable
5
1
EPEN6
Endpoint 6 Enable
6
1
EPEN7
Endpoint 7 Enable
7
1
EPEN8
Endpoint 8 Enable
8
1
EPEN9
Endpoint 9 Enable
9
1
EPRST0
Endpoint 0 Reset
16
1
EPRST1
Endpoint 1 Reset
17
1
EPRST2
Endpoint 2 Reset
18
1
EPRST3
Endpoint 3 Reset
19
1
EPRST4
Endpoint 4 Reset
20
1
EPRST5
Endpoint 5 Reset
21
1
EPRST6
Endpoint 6 Reset
22
1
EPRST7
Endpoint 7 Reset
23
1
EPRST8
Endpoint 8 Reset
24
1
EPRST9
Endpoint 9 Reset
25
1
DEVFNUM
Device Frame Number Register
0x0020
32
read-only
MFNUM
Micro Frame Number
0
3
FNUM
Frame Number
3
11
FNCERR
Frame Number CRC Error
15
1
10
4
DEVEPTCFG[%s]
Device Endpoint Configuration Register
0x100
32
ALLOC
Endpoint Memory Allocate
1
1
EPBK
Endpoint Banks
2
2
EPBKSelect
1_BANK
Single-bank endpoint
0x0
2_BANK
Double-bank endpoint
0x1
3_BANK
Triple-bank endpoint
0x2
EPSIZE
Endpoint Size
4
3
EPSIZESelect
8_BYTE
8 bytes
0x0
16_BYTE
16 bytes
0x1
32_BYTE
32 bytes
0x2
64_BYTE
64 bytes
0x3
128_BYTE
128 bytes
0x4
256_BYTE
256 bytes
0x5
512_BYTE
512 bytes
0x6
1024_BYTE
1024 bytes
0x7
EPDIR
Endpoint Direction
8
1
EPDIRSelect
OUT
The endpoint direction is OUT.
0
IN
The endpoint direction is IN (nor for control endpoints).
1
AUTOSW
Automatic Switch
9
1
EPTYPE
Endpoint Type
11
2
EPTYPESelect
CTRL
Control
0x0
ISO
Isochronous
0x1
BLK
Bulk
0x2
INTRPT
Interrupt
0x3
NBTRANS
Number of transactions per microframe for isochronous endpoint
13
2
NBTRANSSelect
_0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x0
_1_TRANS
Default value: one transaction per microframe.
0x1
_2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x2
_3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
0x3
10
4
DEVEPTISR_CTRL_MODE[%s]
Device Endpoint Interrupt Status Register
0x130
32
read-only
TXINI
Transmitted IN Data Interrupt
0
1
RXOUTI
Received OUT Data Interrupt
1
1
RXSTPI
Received SETUP Interrupt
2
1
NAKOUTI
NAKed OUT Interrupt
3
1
NAKINI
NAKed IN Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
STALLEDI
STALLed Interrupt
6
1
SHORTPACKET
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0x0
DATA1
Data1 toggle sequence
0x1
DATA2
Reserved for high-bandwidth isochronous endpoint
0x2
MDATA
Reserved for high-bandwidth isochronous endpoint
0x3
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CTRLDIR
Control Direction
17
1
CFGOK
Configuration OK Status
18
1
BYCT
Byte Count
20
11
10
4
DEVEPTISR_ISO_MODE[%s]
Device Endpoint Interrupt Status Register
DEVEPTISR_CTRL_MODE[%s]
0x130
32
read-only
TXINI
Transmitted IN Data Interrupt
0
1
RXOUTI
Received OUT Data Interrupt
1
1
UNDERFI
Underflow Interrupt
2
1
HBISOINERRI
High Bandwidth Isochronous IN Underflow Error Interrupt
3
1
HBISOFLUSHI
High Bandwidth Isochronous IN Flush Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
CRCERRI
CRC Error Interrupt
6
1
SHORTPACKET
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0x0
DATA1
Data1 toggle sequence
0x1
DATA2
Reserved for high-bandwidth isochronous endpoint
0x2
MDATA
Reserved for high-bandwidth isochronous endpoint
0x3
ERRORTRANS
High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt
10
1
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CFGOK
Configuration OK Status
18
1
BYCT
Byte Count
20
11
10
4
DEVEPTISR_BLK_MODE[%s]
Device Endpoint Interrupt Status Register
DEVEPTISR_CTRL_MODE[%s]
0x130
32
read-only
TXINI
Transmitted IN Data Interrupt
0
1
RXOUTI
Received OUT Data Interrupt
1
1
RXSTPI
Received SETUP Interrupt
2
1
NAKOUTI
NAKed OUT Interrupt
3
1
NAKINI
NAKed IN Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
STALLEDI
STALLed Interrupt
6
1
SHORTPACKET
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0x0
DATA1
Data1 toggle sequence
0x1
DATA2
Reserved for high-bandwidth isochronous endpoint
0x2
MDATA
Reserved for high-bandwidth isochronous endpoint
0x3
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CTRLDIR
Control Direction
17
1
CFGOK
Configuration OK Status
18
1
BYCT
Byte Count
20
11
10
4
DEVEPTISR_INTRPT_MODE[%s]
Device Endpoint Interrupt Status Register
DEVEPTISR_CTRL_MODE[%s]
0x130
32
read-only
TXINI
Transmitted IN Data Interrupt
0
1
RXOUTI
Received OUT Data Interrupt
1
1
RXSTPI
Received SETUP Interrupt
2
1
NAKOUTI
NAKed OUT Interrupt
3
1
NAKINI
NAKed IN Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
STALLEDI
STALLed Interrupt
6
1
SHORTPACKET
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0x0
DATA1
Data1 toggle sequence
0x1
DATA2
Reserved for high-bandwidth isochronous endpoint
0x2
MDATA
Reserved for high-bandwidth isochronous endpoint
0x3
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CTRLDIR
Control Direction
17
1
CFGOK
Configuration OK Status
18
1
BYCT
Byte Count
20
11
10
4
DEVEPTICR_CTRL_MODE[%s]
Device Endpoint Interrupt Clear Register
0x160
32
write-only
TXINIC
Transmitted IN Data Interrupt Clear
0
1
RXOUTIC
Received OUT Data Interrupt Clear
1
1
RXSTPIC
Received SETUP Interrupt Clear
2
1
NAKOUTIC
NAKed OUT Interrupt Clear
3
1
NAKINIC
NAKed IN Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
STALLEDIC
STALLed Interrupt Clear
6
1
SHORTPACKETC
Short Packet Interrupt Clear
7
1
10
4
DEVEPTICR_ISO_MODE[%s]
Device Endpoint Interrupt Clear Register
DEVEPTICR_CTRL_MODE[%s]
0x160
32
write-only
TXINIC
Transmitted IN Data Interrupt Clear
0
1
RXOUTIC
Received OUT Data Interrupt Clear
1
1
UNDERFIC
Underflow Interrupt Clear
2
1
HBISOINERRIC
High Bandwidth Isochronous IN Underflow Error Interrupt Clear
3
1
HBISOFLUSHIC
High Bandwidth Isochronous IN Flush Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
CRCERRIC
CRC Error Interrupt Clear
6
1
SHORTPACKETC
Short Packet Interrupt Clear
7
1
10
4
DEVEPTICR_BLK_MODE[%s]
Device Endpoint Interrupt Clear Register
DEVEPTICR_CTRL_MODE[%s]
0x160
32
write-only
TXINIC
Transmitted IN Data Interrupt Clear
0
1
RXOUTIC
Received OUT Data Interrupt Clear
1
1
RXSTPIC
Received SETUP Interrupt Clear
2
1
NAKOUTIC
NAKed OUT Interrupt Clear
3
1
NAKINIC
NAKed IN Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
STALLEDIC
STALLed Interrupt Clear
6
1
SHORTPACKETC
Short Packet Interrupt Clear
7
1
10
4
DEVEPTICR_INTRPT_MODE[%s]
Device Endpoint Interrupt Clear Register
DEVEPTICR_CTRL_MODE[%s]
0x160
32
write-only
TXINIC
Transmitted IN Data Interrupt Clear
0
1
RXOUTIC
Received OUT Data Interrupt Clear
1
1
RXSTPIC
Received SETUP Interrupt Clear
2
1
NAKOUTIC
NAKed OUT Interrupt Clear
3
1
NAKINIC
NAKed IN Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
STALLEDIC
STALLed Interrupt Clear
6
1
SHORTPACKETC
Short Packet Interrupt Clear
7
1
10
4
DEVEPTIFR_CTRL_MODE[%s]
Device Endpoint Interrupt Set Register
0x190
32
write-only
TXINIS
Transmitted IN Data Interrupt Set
0
1
RXOUTIS
Received OUT Data Interrupt Set
1
1
RXSTPIS
Received SETUP Interrupt Set
2
1
NAKOUTIS
NAKed OUT Interrupt Set
3
1
NAKINIS
NAKed IN Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
STALLEDIS
STALLed Interrupt Set
6
1
SHORTPACKETS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Interrupt Set
12
1
10
4
DEVEPTIFR_ISO_MODE[%s]
Device Endpoint Interrupt Set Register
DEVEPTIFR_CTRL_MODE[%s]
0x190
32
write-only
TXINIS
Transmitted IN Data Interrupt Set
0
1
RXOUTIS
Received OUT Data Interrupt Set
1
1
UNDERFIS
Underflow Interrupt Set
2
1
HBISOINERRIS
High Bandwidth Isochronous IN Underflow Error Interrupt Set
3
1
HBISOFLUSHIS
High Bandwidth Isochronous IN Flush Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
CRCERRIS
CRC Error Interrupt Set
6
1
SHORTPACKETS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Interrupt Set
12
1
10
4
DEVEPTIFR_BLK_MODE[%s]
Device Endpoint Interrupt Set Register
DEVEPTIFR_CTRL_MODE[%s]
0x190
32
write-only
TXINIS
Transmitted IN Data Interrupt Set
0
1
RXOUTIS
Received OUT Data Interrupt Set
1
1
RXSTPIS
Received SETUP Interrupt Set
2
1
NAKOUTIS
NAKed OUT Interrupt Set
3
1
NAKINIS
NAKed IN Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
STALLEDIS
STALLed Interrupt Set
6
1
SHORTPACKETS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Interrupt Set
12
1
10
4
DEVEPTIFR_INTRPT_MODE[%s]
Device Endpoint Interrupt Set Register
DEVEPTIFR_CTRL_MODE[%s]
0x190
32
write-only
TXINIS
Transmitted IN Data Interrupt Set
0
1
RXOUTIS
Received OUT Data Interrupt Set
1
1
RXSTPIS
Received SETUP Interrupt Set
2
1
NAKOUTIS
NAKed OUT Interrupt Set
3
1
NAKINIS
NAKed IN Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
STALLEDIS
STALLed Interrupt Set
6
1
SHORTPACKETS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Interrupt Set
12
1
10
4
DEVEPTIMR_CTRL_MODE[%s]
Device Endpoint Interrupt Mask Register
0x1C0
32
read-only
TXINE
Transmitted IN Data Interrupt
0
1
RXOUTE
Received OUT Data Interrupt
1
1
RXSTPE
Received SETUP Interrupt
2
1
NAKOUTE
NAKed OUT Interrupt
3
1
NAKINE
NAKed IN Interrupt
4
1
OVERFE
Overflow Interrupt
5
1
STALLEDE
STALLed Interrupt
6
1
SHORTPACKETE
Short Packet Interrupt
7
1
NBUSYBKE
Number of Busy Banks Interrupt
12
1
KILLBK
Kill IN Bank
13
1
FIFOCON
FIFO Control
14
1
EPDISHDMA
Endpoint Interrupts Disable HDMA Request
16
1
NYETDIS
NYET Token Disable
17
1
RSTDT
Reset Data Toggle
18
1
STALLRQ
STALL Request
19
1
10
4
DEVEPTIMR_ISO_MODE[%s]
Device Endpoint Interrupt Mask Register
DEVEPTIMR_CTRL_MODE[%s]
0x1C0
32
read-only
TXINE
Transmitted IN Data Interrupt
0
1
RXOUTE
Received OUT Data Interrupt
1
1
UNDERFE
Underflow Interrupt
2
1
HBISOINERRE
High Bandwidth Isochronous IN Underflow Error Interrupt
3
1
HBISOFLUSHE
High Bandwidth Isochronous IN Flush Interrupt
4
1
OVERFE
Overflow Interrupt
5
1
CRCERRE
CRC Error Interrupt
6
1
SHORTPACKETE
Short Packet Interrupt
7
1
MDATAE
MData Interrupt
8
1
DATAXE
DataX Interrupt
9
1
ERRORTRANSE
Transaction Error Interrupt
10
1
NBUSYBKE
Number of Busy Banks Interrupt
12
1
KILLBK
Kill IN Bank
13
1
FIFOCON
FIFO Control
14
1
EPDISHDMA
Endpoint Interrupts Disable HDMA Request
16
1
RSTDT
Reset Data Toggle
18
1
10
4
DEVEPTIMR_BLK_MODE[%s]
Device Endpoint Interrupt Mask Register
DEVEPTIMR_CTRL_MODE[%s]
0x1C0
32
read-only
TXINE
Transmitted IN Data Interrupt
0
1
RXOUTE
Received OUT Data Interrupt
1
1
RXSTPE
Received SETUP Interrupt
2
1
NAKOUTE
NAKed OUT Interrupt
3
1
NAKINE
NAKed IN Interrupt
4
1
OVERFE
Overflow Interrupt
5
1
STALLEDE
STALLed Interrupt
6
1
SHORTPACKETE
Short Packet Interrupt
7
1
NBUSYBKE
Number of Busy Banks Interrupt
12
1
KILLBK
Kill IN Bank
13
1
FIFOCON
FIFO Control
14
1
EPDISHDMA
Endpoint Interrupts Disable HDMA Request
16
1
NYETDIS
NYET Token Disable
17
1
RSTDT
Reset Data Toggle
18
1
STALLRQ
STALL Request
19
1
10
4
DEVEPTIMR_INTRPT_MODE[%s]
Device Endpoint Interrupt Mask Register
DEVEPTIMR_CTRL_MODE[%s]
0x1C0
32
read-only
TXINE
Transmitted IN Data Interrupt
0
1
RXOUTE
Received OUT Data Interrupt
1
1
RXSTPE
Received SETUP Interrupt
2
1
NAKOUTE
NAKed OUT Interrupt
3
1
NAKINE
NAKed IN Interrupt
4
1
OVERFE
Overflow Interrupt
5
1
STALLEDE
STALLed Interrupt
6
1
SHORTPACKETE
Short Packet Interrupt
7
1
NBUSYBKE
Number of Busy Banks Interrupt
12
1
KILLBK
Kill IN Bank
13
1
FIFOCON
FIFO Control
14
1
EPDISHDMA
Endpoint Interrupts Disable HDMA Request
16
1
NYETDIS
NYET Token Disable
17
1
RSTDT
Reset Data Toggle
18
1
STALLRQ
STALL Request
19
1
10
4
DEVEPTIER_CTRL_MODE[%s]
Device Endpoint Interrupt Enable Register
0x1F0
32
write-only
TXINES
Transmitted IN Data Interrupt Enable
0
1
RXOUTES
Received OUT Data Interrupt Enable
1
1
RXSTPES
Received SETUP Interrupt Enable
2
1
NAKOUTES
NAKed OUT Interrupt Enable
3
1
NAKINES
NAKed IN Interrupt Enable
4
1
OVERFES
Overflow Interrupt Enable
5
1
STALLEDES
STALLed Interrupt Enable
6
1
SHORTPACKETES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Interrupt Enable
12
1
KILLBKS
Kill IN Bank
13
1
FIFOCONS
FIFO Control
14
1
EPDISHDMAS
Endpoint Interrupts Disable HDMA Request Enable
16
1
NYETDISS
NYET Token Disable Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
STALLRQS
STALL Request Enable
19
1
10
4
DEVEPTIER_ISO_MODE[%s]
Device Endpoint Interrupt Enable Register
DEVEPTIER_CTRL_MODE[%s]
0x1F0
32
write-only
TXINES
Transmitted IN Data Interrupt Enable
0
1
RXOUTES
Received OUT Data Interrupt Enable
1
1
UNDERFES
Underflow Interrupt Enable
2
1
HBISOINERRES
High Bandwidth Isochronous IN Underflow Error Interrupt Enable
3
1
HBISOFLUSHES
High Bandwidth Isochronous IN Flush Interrupt Enable
4
1
OVERFES
Overflow Interrupt Enable
5
1
CRCERRES
CRC Error Interrupt Enable
6
1
SHORTPACKETES
Short Packet Interrupt Enable
7
1
MDATAES
MData Interrupt Enable
8
1
DATAXES
DataX Interrupt Enable
9
1
ERRORTRANSES
Transaction Error Interrupt Enable
10
1
NBUSYBKES
Number of Busy Banks Interrupt Enable
12
1
KILLBKS
Kill IN Bank
13
1
FIFOCONS
FIFO Control
14
1
EPDISHDMAS
Endpoint Interrupts Disable HDMA Request Enable
16
1
RSTDTS
Reset Data Toggle Enable
18
1
10
4
DEVEPTIER_BLK_MODE[%s]
Device Endpoint Interrupt Enable Register
DEVEPTIER_CTRL_MODE[%s]
0x1F0
32
write-only
TXINES
Transmitted IN Data Interrupt Enable
0
1
RXOUTES
Received OUT Data Interrupt Enable
1
1
RXSTPES
Received SETUP Interrupt Enable
2
1
NAKOUTES
NAKed OUT Interrupt Enable
3
1
NAKINES
NAKed IN Interrupt Enable
4
1
OVERFES
Overflow Interrupt Enable
5
1
STALLEDES
STALLed Interrupt Enable
6
1
SHORTPACKETES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Interrupt Enable
12
1
KILLBKS
Kill IN Bank
13
1
FIFOCONS
FIFO Control
14
1
EPDISHDMAS
Endpoint Interrupts Disable HDMA Request Enable
16
1
NYETDISS
NYET Token Disable Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
STALLRQS
STALL Request Enable
19
1
10
4
DEVEPTIER_INTRPT_MODE[%s]
Device Endpoint Interrupt Enable Register
DEVEPTIER_CTRL_MODE[%s]
0x1F0
32
write-only
TXINES
Transmitted IN Data Interrupt Enable
0
1
RXOUTES
Received OUT Data Interrupt Enable
1
1
RXSTPES
Received SETUP Interrupt Enable
2
1
NAKOUTES
NAKed OUT Interrupt Enable
3
1
NAKINES
NAKed IN Interrupt Enable
4
1
OVERFES
Overflow Interrupt Enable
5
1
STALLEDES
STALLed Interrupt Enable
6
1
SHORTPACKETES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Interrupt Enable
12
1
KILLBKS
Kill IN Bank
13
1
FIFOCONS
FIFO Control
14
1
EPDISHDMAS
Endpoint Interrupts Disable HDMA Request Enable
16
1
NYETDISS
NYET Token Disable Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
STALLRQS
STALL Request Enable
19
1
10
4
DEVEPTIDR_CTRL_MODE[%s]
Device Endpoint Interrupt Disable Register
0x220
32
write-only
TXINEC
Transmitted IN Interrupt Clear
0
1
RXOUTEC
Received OUT Data Interrupt Clear
1
1
RXSTPEC
Received SETUP Interrupt Clear
2
1
NAKOUTEC
NAKed OUT Interrupt Clear
3
1
NAKINEC
NAKed IN Interrupt Clear
4
1
OVERFEC
Overflow Interrupt Clear
5
1
STALLEDEC
STALLed Interrupt Clear
6
1
SHORTPACKETEC
Shortpacket Interrupt Clear
7
1
NBUSYBKEC
Number of Busy Banks Interrupt Clear
12
1
FIFOCONC
FIFO Control Clear
14
1
EPDISHDMAC
Endpoint Interrupts Disable HDMA Request Clear
16
1
NYETDISC
NYET Token Disable Clear
17
1
STALLRQC
STALL Request Clear
19
1
10
4
DEVEPTIDR_ISO_MODE[%s]
Device Endpoint Interrupt Disable Register
DEVEPTIDR_CTRL_MODE[%s]
0x220
32
write-only
TXINEC
Transmitted IN Interrupt Clear
0
1
RXOUTEC
Received OUT Data Interrupt Clear
1
1
UNDERFEC
Underflow Interrupt Clear
2
1
HBISOINERREC
High Bandwidth Isochronous IN Underflow Error Interrupt Clear
3
1
HBISOFLUSHEC
High Bandwidth Isochronous IN Flush Interrupt Clear
4
1
OVERFEC
Overflow Interrupt Clear
5
1
SHORTPACKETEC
Shortpacket Interrupt Clear
7
1
MDATAEC
MData Interrupt Clear
8
1
DATAXEC
DataX Interrupt Clear
9
1
ERRORTRANSEC
Transaction Error Interrupt Clear
10
1
NBUSYBKEC
Number of Busy Banks Interrupt Clear
12
1
FIFOCONC
FIFO Control Clear
14
1
EPDISHDMAC
Endpoint Interrupts Disable HDMA Request Clear
16
1
10
4
DEVEPTIDR_BLK_MODE[%s]
Device Endpoint Interrupt Disable Register
DEVEPTIDR_CTRL_MODE[%s]
0x220
32
write-only
TXINEC
Transmitted IN Interrupt Clear
0
1
RXOUTEC
Received OUT Data Interrupt Clear
1
1
RXSTPEC
Received SETUP Interrupt Clear
2
1
NAKOUTEC
NAKed OUT Interrupt Clear
3
1
NAKINEC
NAKed IN Interrupt Clear
4
1
OVERFEC
Overflow Interrupt Clear
5
1
STALLEDEC
STALLed Interrupt Clear
6
1
SHORTPACKETEC
Shortpacket Interrupt Clear
7
1
NBUSYBKEC
Number of Busy Banks Interrupt Clear
12
1
FIFOCONC
FIFO Control Clear
14
1
EPDISHDMAC
Endpoint Interrupts Disable HDMA Request Clear
16
1
NYETDISC
NYET Token Disable Clear
17
1
STALLRQC
STALL Request Clear
19
1
10
4
DEVEPTIDR_INTRPT_MODE[%s]
Device Endpoint Interrupt Disable Register
DEVEPTIDR_CTRL_MODE[%s]
0x220
32
write-only
TXINEC
Transmitted IN Interrupt Clear
0
1
RXOUTEC
Received OUT Data Interrupt Clear
1
1
RXSTPEC
Received SETUP Interrupt Clear
2
1
NAKOUTEC
NAKed OUT Interrupt Clear
3
1
NAKINEC
NAKed IN Interrupt Clear
4
1
OVERFEC
Overflow Interrupt Clear
5
1
STALLEDEC
STALLed Interrupt Clear
6
1
SHORTPACKETEC
Shortpacket Interrupt Clear
7
1
NBUSYBKEC
Number of Busy Banks Interrupt Clear
12
1
FIFOCONC
FIFO Control Clear
14
1
EPDISHDMAC
Endpoint Interrupts Disable HDMA Request Clear
16
1
NYETDISC
NYET Token Disable Clear
17
1
STALLRQC
STALL Request Clear
19
1
7
16
USBHS_DEVDMA[%s]
Device DMA Channel Next Descriptor Address Register
0x310
DEVDMANXTDSC
Device DMA Channel Next Descriptor Address Register
0x00
32
NXT_DSC_ADD
Next Descriptor Address
0
32
DEVDMAADDRESS
Device DMA Channel Address Register
0x04
32
BUFF_ADD
Buffer Address
0
32
DEVDMACONTROL
Device DMA Channel Control Register
0x08
32
CHANN_ENB
Channel Enable Command
0
1
LDNXT_DSC
Load Next Channel Transfer Descriptor Enable Command
1
1
END_TR_EN
End of Transfer Enable Control (OUT transfers only)
2
1
END_B_EN
End of Buffer Enable Control
3
1
END_TR_IT
End of Transfer Interrupt Enable
4
1
END_BUFFIT
End of Buffer Interrupt Enable
5
1
DESC_LD_IT
Descriptor Loaded Interrupt Enable
6
1
BURST_LCK
Burst Lock Enable
7
1
BUFF_LENGTH
Buffer Byte Length (Write-only)
16
16
DEVDMASTATUS
Device DMA Channel Status Register
0x0C
32
CHANN_ENB
Channel Enable Status
0
1
CHANN_ACT
Channel Active Status
1
1
END_TR_ST
End of Channel Transfer Status
4
1
END_BF_ST
End of Channel Buffer Status
5
1
DESC_LDST
Descriptor Loaded Status
6
1
BUFF_COUNT
Buffer Byte Count
16
16
HSTCTRL
Host General Control Register
0x0400
32
SOFE
Start of Frame Generation Enable
8
1
RESET
Send USB Reset
9
1
RESUME
Send USB Resume
10
1
SPDCONF
Mode Configuration
12
2
SPDCONFSelect
NORMAL
The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.
0x0
LOW_POWER
For a better consumption, if high speed is not needed.
0x1
HIGH_SPEED
Forced high speed.
0x2
FORCED_FS
The host remains in Full-speed mode whatever the peripheral speed capability.
0x3
HSTISR
Host Global Interrupt Status Register
0x0404
32
read-only
DCONNI
Device Connection Interrupt
0
1
DDISCI
Device Disconnection Interrupt
1
1
RSTI
USB Reset Sent Interrupt
2
1
RSMEDI
Downstream Resume Sent Interrupt
3
1
RXRSMI
Upstream Resume Received Interrupt
4
1
HSOFI
Host Start of Frame Interrupt
5
1
HWUPI
Host Wake-Up Interrupt
6
1
PEP_0
Pipe 0 Interrupt
8
1
PEP_1
Pipe 1 Interrupt
9
1
PEP_2
Pipe 2 Interrupt
10
1
PEP_3
Pipe 3 Interrupt
11
1
PEP_4
Pipe 4 Interrupt
12
1
PEP_5
Pipe 5 Interrupt
13
1
PEP_6
Pipe 6 Interrupt
14
1
PEP_7
Pipe 7 Interrupt
15
1
PEP_8
Pipe 8 Interrupt
16
1
PEP_9
Pipe 9 Interrupt
17
1
DMA_1
DMA Channel 0 Interrupt
25
1
DMA_2
DMA Channel 1 Interrupt
26
1
DMA_3
DMA Channel 2 Interrupt
27
1
DMA_4
DMA Channel 3 Interrupt
28
1
DMA_5
DMA Channel 4 Interrupt
29
1
DMA_6
DMA Channel 5 Interrupt
30
1
DMA_7
DMA Channel 6 Interrupt
31
1
HSTICR
Host Global Interrupt Clear Register
0x0408
32
write-only
DCONNIC
Device Connection Interrupt Clear
0
1
DDISCIC
Device Disconnection Interrupt Clear
1
1
RSTIC
USB Reset Sent Interrupt Clear
2
1
RSMEDIC
Downstream Resume Sent Interrupt Clear
3
1
RXRSMIC
Upstream Resume Received Interrupt Clear
4
1
HSOFIC
Host Start of Frame Interrupt Clear
5
1
HWUPIC
Host Wake-Up Interrupt Clear
6
1
HSTIFR
Host Global Interrupt Set Register
0x040C
32
write-only
DCONNIS
Device Connection Interrupt Set
0
1
DDISCIS
Device Disconnection Interrupt Set
1
1
RSTIS
USB Reset Sent Interrupt Set
2
1
RSMEDIS
Downstream Resume Sent Interrupt Set
3
1
RXRSMIS
Upstream Resume Received Interrupt Set
4
1
HSOFIS
Host Start of Frame Interrupt Set
5
1
HWUPIS
Host Wake-Up Interrupt Set
6
1
DMA_1
DMA Channel 0 Interrupt Set
25
1
DMA_2
DMA Channel 1 Interrupt Set
26
1
DMA_3
DMA Channel 2 Interrupt Set
27
1
DMA_4
DMA Channel 3 Interrupt Set
28
1
DMA_5
DMA Channel 4 Interrupt Set
29
1
DMA_6
DMA Channel 5 Interrupt Set
30
1
DMA_7
DMA Channel 6 Interrupt Set
31
1
HSTIMR
Host Global Interrupt Mask Register
0x0410
32
read-only
DCONNIE
Device Connection Interrupt Enable
0
1
DDISCIE
Device Disconnection Interrupt Enable
1
1
RSTIE
USB Reset Sent Interrupt Enable
2
1
RSMEDIE
Downstream Resume Sent Interrupt Enable
3
1
RXRSMIE
Upstream Resume Received Interrupt Enable
4
1
HSOFIE
Host Start of Frame Interrupt Enable
5
1
HWUPIE
Host Wake-Up Interrupt Enable
6
1
PEP_0
Pipe 0 Interrupt Enable
8
1
PEP_1
Pipe 1 Interrupt Enable
9
1
PEP_2
Pipe 2 Interrupt Enable
10
1
PEP_3
Pipe 3 Interrupt Enable
11
1
PEP_4
Pipe 4 Interrupt Enable
12
1
PEP_5
Pipe 5 Interrupt Enable
13
1
PEP_6
Pipe 6 Interrupt Enable
14
1
PEP_7
Pipe 7 Interrupt Enable
15
1
PEP_8
Pipe 8 Interrupt Enable
16
1
PEP_9
Pipe 9 Interrupt Enable
17
1
DMA_1
DMA Channel 0 Interrupt Enable
25
1
DMA_2
DMA Channel 1 Interrupt Enable
26
1
DMA_3
DMA Channel 2 Interrupt Enable
27
1
DMA_4
DMA Channel 3 Interrupt Enable
28
1
DMA_5
DMA Channel 4 Interrupt Enable
29
1
DMA_6
DMA Channel 5 Interrupt Enable
30
1
DMA_7
DMA Channel 6 Interrupt Enable
31
1
HSTIDR
Host Global Interrupt Disable Register
0x0414
32
write-only
DCONNIEC
Device Connection Interrupt Disable
0
1
DDISCIEC
Device Disconnection Interrupt Disable
1
1
RSTIEC
USB Reset Sent Interrupt Disable
2
1
RSMEDIEC
Downstream Resume Sent Interrupt Disable
3
1
RXRSMIEC
Upstream Resume Received Interrupt Disable
4
1
HSOFIEC
Host Start of Frame Interrupt Disable
5
1
HWUPIEC
Host Wake-Up Interrupt Disable
6
1
PEP_0
Pipe 0 Interrupt Disable
8
1
PEP_1
Pipe 1 Interrupt Disable
9
1
PEP_2
Pipe 2 Interrupt Disable
10
1
PEP_3
Pipe 3 Interrupt Disable
11
1
PEP_4
Pipe 4 Interrupt Disable
12
1
PEP_5
Pipe 5 Interrupt Disable
13
1
PEP_6
Pipe 6 Interrupt Disable
14
1
PEP_7
Pipe 7 Interrupt Disable
15
1
PEP_8
Pipe 8 Interrupt Disable
16
1
PEP_9
Pipe 9 Interrupt Disable
17
1
DMA_1
DMA Channel 0 Interrupt Disable
25
1
DMA_2
DMA Channel 1 Interrupt Disable
26
1
DMA_3
DMA Channel 2 Interrupt Disable
27
1
DMA_4
DMA Channel 3 Interrupt Disable
28
1
DMA_5
DMA Channel 4 Interrupt Disable
29
1
DMA_6
DMA Channel 5 Interrupt Disable
30
1
DMA_7
DMA Channel 6 Interrupt Disable
31
1
HSTIER
Host Global Interrupt Enable Register
0x0418
32
write-only
DCONNIES
Device Connection Interrupt Enable
0
1
DDISCIES
Device Disconnection Interrupt Enable
1
1
RSTIES
USB Reset Sent Interrupt Enable
2
1
RSMEDIES
Downstream Resume Sent Interrupt Enable
3
1
RXRSMIES
Upstream Resume Received Interrupt Enable
4
1
HSOFIES
Host Start of Frame Interrupt Enable
5
1
HWUPIES
Host Wake-Up Interrupt Enable
6
1
PEP_0
Pipe 0 Interrupt Enable
8
1
PEP_1
Pipe 1 Interrupt Enable
9
1
PEP_2
Pipe 2 Interrupt Enable
10
1
PEP_3
Pipe 3 Interrupt Enable
11
1
PEP_4
Pipe 4 Interrupt Enable
12
1
PEP_5
Pipe 5 Interrupt Enable
13
1
PEP_6
Pipe 6 Interrupt Enable
14
1
PEP_7
Pipe 7 Interrupt Enable
15
1
PEP_8
Pipe 8 Interrupt Enable
16
1
PEP_9
Pipe 9 Interrupt Enable
17
1
DMA_1
DMA Channel 0 Interrupt Enable
25
1
DMA_2
DMA Channel 1 Interrupt Enable
26
1
DMA_3
DMA Channel 2 Interrupt Enable
27
1
DMA_4
DMA Channel 3 Interrupt Enable
28
1
DMA_5
DMA Channel 4 Interrupt Enable
29
1
DMA_6
DMA Channel 5 Interrupt Enable
30
1
DMA_7
DMA Channel 6 Interrupt Enable
31
1
HSTPIP
Host Pipe Register
0x0041C
32
PEN0
Pipe 0 Enable
0
1
PEN1
Pipe 1 Enable
1
1
PEN2
Pipe 2 Enable
2
1
PEN3
Pipe 3 Enable
3
1
PEN4
Pipe 4 Enable
4
1
PEN5
Pipe 5 Enable
5
1
PEN6
Pipe 6 Enable
6
1
PEN7
Pipe 7 Enable
7
1
PEN8
Pipe 8 Enable
8
1
PRST0
Pipe 0 Reset
16
1
PRST1
Pipe 1 Reset
17
1
PRST2
Pipe 2 Reset
18
1
PRST3
Pipe 3 Reset
19
1
PRST4
Pipe 4 Reset
20
1
PRST5
Pipe 5 Reset
21
1
PRST6
Pipe 6 Reset
22
1
PRST7
Pipe 7 Reset
23
1
PRST8
Pipe 8 Reset
24
1
HSTFNUM
Host Frame Number Register
0x0420
32
MFNUM
Micro Frame Number
0
3
FNUM
Frame Number
3
11
FLENHIGH
Frame Length
16
8
HSTADDR1
Host Address 1 Register
0x0424
32
HSTADDRP0
USB Host Address
0
7
HSTADDRP1
USB Host Address
8
7
HSTADDRP2
USB Host Address
16
7
HSTADDRP3
USB Host Address
24
7
HSTADDR2
Host Address 2 Register
0x0428
32
HSTADDRP4
USB Host Address
0
7
HSTADDRP5
USB Host Address
8
7
HSTADDRP6
USB Host Address
16
7
HSTADDRP7
USB Host Address
24
7
HSTADDR3
Host Address 3 Register
0x042C
32
HSTADDRP8
USB Host Address
0
7
HSTADDRP9
USB Host Address
8
7
10
4
HSTPIPCFG[%s]
Host Pipe Configuration Register
0x500
32
ALLOC
Pipe Memory Allocate
1
1
PBK
Pipe Banks
2
2
PBKSelect
_1_BANK
Single-bank pipe
0x0
_2_BANK
Double-bank pipe
0x1
_3_BANK
Triple-bank pipe
0x2
PSIZE
Pipe Size
4
3
PSIZESelect
_8_BYTE
8 bytes
0x0
_16_BYTE
16 bytes
0x1
_32_BYTE
32 bytes
0x2
_64_BYTE
64 bytes
0x3
_128_BYTE
128 bytes
0x4
_256_BYTE
256 bytes
0x5
_512_BYTE
512 bytes
0x6
_1024_BYTE
1024 bytes
0x7
PTOKEN
Pipe Token
8
2
PTOKENSelect
SETUP
SETUP
0x0
IN
IN
0x1
OUT
OUT
0x2
AUTOSW
Automatic Switch
10
1
PTYPE
Pipe Type
12
2
PTYPESelect
CTRL
Control
0x0
ISO
Isochronous
0x1
BLK
Bulk
0x2
INTRPT
Interrupt
0x3
PEPNUM
Pipe Endpoint Number
16
4
INTFRQ
Pipe Interrupt Request Frequency
24
8
10
4
HSTPIPCFG_CTRL_BULK_MODE[%s]
Host Pipe Configuration Register
HSTPIPCFG[%s]
0x500
32
ALLOC
Pipe Memory Allocate
1
1
PBK
Pipe Banks
2
2
PBKSelect
_1_BANK
Single-bank pipe
0x0
_2_BANK
Double-bank pipe
0x1
_3_BANK
Triple-bank pipe
0x2
PSIZE
Pipe Size
4
3
PSIZESelect
_8_BYTE
8 bytes
0x0
_16_BYTE
16 bytes
0x1
_32_BYTE
32 bytes
0x2
_64_BYTE
64 bytes
0x3
_128_BYTE
128 bytes
0x4
_256_BYTE
256 bytes
0x5
_512_BYTE
512 bytes
0x6
_1024_BYTE
1024 bytes
0x7
PTOKEN
Pipe Token
8
2
PTOKENSelect
SETUP
SETUP
0x0
IN
IN
0x1
OUT
OUT
0x2
AUTOSW
Automatic Switch
10
1
PTYPE
Pipe Type
12
2
PTYPESelect
CTRL
Control
0x0
ISO
Isochronous
0x1
BLK
Bulk
0x2
INTRPT
Interrupt
0x3
PEPNUM
Pipe Endpoint Number
16
4
PINGEN
Ping Enable
20
1
BINTERVAL
bInterval Parameter for the Bulk-Out/Ping Transaction
24
8
10
4
HSTPIPISR_CTRL_MODE[%s]
Host Pipe Status Register
0x530
32
read-only
RXINI
Received IN Data Interrupt
0
1
TXOUTI
Transmitted OUT Data Interrupt
1
1
TXSTPI
Transmitted SETUP Interrupt
2
1
PERRI
Pipe Error Interrupt
3
1
NAKEDI
NAKed Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
RXSTALLDI
Received STALLed Interrupt
6
1
SHORTPACKETI
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0
DATA1
Data1 toggle sequence
1
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CFGOK
Configuration OK Status
18
1
PBYCT
Pipe Byte Count
20
11
10
4
HSTPIPISR_ISO_MODE[%s]
Host Pipe Status Register
HSTPIPISR_CTRL_MODE[%s]
0x530
32
read-only
RXINI
Received IN Data Interrupt
0
1
TXOUTI
Transmitted OUT Data Interrupt
1
1
UNDERFI
Underflow Interrupt
2
1
PERRI
Pipe Error Interrupt
3
1
NAKEDI
NAKed Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
CRCERRI
CRC Error Interrupt
6
1
SHORTPACKETI
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0
DATA1
Data1 toggle sequence
1
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CFGOK
Configuration OK Status
18
1
PBYCT
Pipe Byte Count
20
11
10
4
HSTPIPISR_BLK_MODE[%s]
Host Pipe Status Register
HSTPIPISR_CTRL_MODE[%s]
0x530
32
read-only
RXINI
Received IN Data Interrupt
0
1
TXOUTI
Transmitted OUT Data Interrupt
1
1
TXSTPI
Transmitted SETUP Interrupt
2
1
PERRI
Pipe Error Interrupt
3
1
NAKEDI
NAKed Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
RXSTALLDI
Received STALLed Interrupt
6
1
SHORTPACKETI
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0
DATA1
Data1 toggle sequence
1
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CFGOK
Configuration OK Status
18
1
PBYCT
Pipe Byte Count
20
11
10
4
HSTPIPISR_INTRPT_MODE[%s]
Host Pipe Status Register
HSTPIPISR_CTRL_MODE[%s]
0x530
32
read-only
RXINI
Received IN Data Interrupt
0
1
TXOUTI
Transmitted OUT Data Interrupt
1
1
UNDERFI
Underflow Interrupt
2
1
PERRI
Pipe Error Interrupt
3
1
NAKEDI
NAKed Interrupt
4
1
OVERFI
Overflow Interrupt
5
1
RXSTALLDI
Received STALLed Interrupt
6
1
SHORTPACKETI
Short Packet Interrupt
7
1
DTSEQ
Data Toggle Sequence
8
2
DTSEQSelect
DATA0
Data0 toggle sequence
0
DATA1
Data1 toggle sequence
1
NBUSYBK
Number of Busy Banks
12
2
NBUSYBKSelect
_0_BUSY
0 busy bank (all banks free)
0x0
_1_BUSY
1 busy bank
0x1
_2_BUSY
2 busy banks
0x2
_3_BUSY
3 busy banks
0x3
CURRBK
Current Bank
14
2
CURRBKSelect
BANK0
Current bank is bank0
0x0
BANK1
Current bank is bank1
0x1
BANK2
Current bank is bank2
0x2
RWALL
Read/Write Allowed
16
1
CFGOK
Configuration OK Status
18
1
PBYCT
Pipe Byte Count
20
11
10
4
HSTPIPICR_CTRL_MODE[%s]
Host Pipe Clear Register
0x560
32
write-only
RXINIC
Received IN Data Interrupt Clear
0
1
TXOUTIC
Transmitted OUT Data Interrupt Clear
1
1
TXSTPIC
Transmitted SETUP Interrupt Clear
2
1
NAKEDIC
NAKed Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
RXSTALLDIC
Received STALLed Interrupt Clear
6
1
SHORTPACKETIC
Short Packet Interrupt Clear
7
1
10
4
HSTPIPICR_ISO_MODE[%s]
Host Pipe Clear Register
HSTPIPICR_CTRL_MODE[%s]
0x560
32
write-only
RXINIC
Received IN Data Interrupt Clear
0
1
TXOUTIC
Transmitted OUT Data Interrupt Clear
1
1
UNDERFIC
Underflow Interrupt Clear
2
1
NAKEDIC
NAKed Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
CRCERRIC
CRC Error Interrupt Clear
6
1
SHORTPACKETIC
Short Packet Interrupt Clear
7
1
10
4
HSTPIPICR_BLK_MODE[%s]
Host Pipe Clear Register
HSTPIPICR_CTRL_MODE[%s]
0x560
32
write-only
RXINIC
Received IN Data Interrupt Clear
0
1
TXOUTIC
Transmitted OUT Data Interrupt Clear
1
1
TXSTPIC
Transmitted SETUP Interrupt Clear
2
1
NAKEDIC
NAKed Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
RXSTALLDIC
Received STALLed Interrupt Clear
6
1
SHORTPACKETIC
Short Packet Interrupt Clear
7
1
10
4
HSTPIPICR_INTRPT_MODE[%s]
Host Pipe Clear Register
HSTPIPICR_CTRL_MODE[%s]
0x560
32
write-only
RXINIC
Received IN Data Interrupt Clear
0
1
TXOUTIC
Transmitted OUT Data Interrupt Clear
1
1
UNDERFIC
Underflow Interrupt Clear
2
1
NAKEDIC
NAKed Interrupt Clear
4
1
OVERFIC
Overflow Interrupt Clear
5
1
RXSTALLDIC
Received STALLed Interrupt Clear
6
1
SHORTPACKETIC
Short Packet Interrupt Clear
7
1
10
4
HSTPIPIFR_CTRL_MODE[%s]
Host Pipe Set Register
0x590
32
write-only
RXINIS
Received IN Data Interrupt Set
0
1
TXOUTIS
Transmitted OUT Data Interrupt Set
1
1
TXSTPIS
Transmitted SETUP Interrupt Set
2
1
PERRIS
Pipe Error Interrupt Set
3
1
NAKEDIS
NAKed Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
RXSTALLDIS
Received STALLed Interrupt Set
6
1
SHORTPACKETIS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Set
12
1
10
4
HSTPIPIFR_ISO_MODE[%s]
Host Pipe Set Register
HSTPIPIFR_CTRL_MODE[%s]
0x590
32
write-only
RXINIS
Received IN Data Interrupt Set
0
1
TXOUTIS
Transmitted OUT Data Interrupt Set
1
1
UNDERFIS
Underflow Interrupt Set
2
1
PERRIS
Pipe Error Interrupt Set
3
1
NAKEDIS
NAKed Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
CRCERRIS
CRC Error Interrupt Set
6
1
SHORTPACKETIS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Set
12
1
10
4
HSTPIPIFR_BLK_MODE[%s]
Host Pipe Set Register
HSTPIPIFR_CTRL_MODE[%s]
0x590
32
write-only
RXINIS
Received IN Data Interrupt Set
0
1
TXOUTIS
Transmitted OUT Data Interrupt Set
1
1
TXSTPIS
Transmitted SETUP Interrupt Set
2
1
PERRIS
Pipe Error Interrupt Set
3
1
NAKEDIS
NAKed Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
RXSTALLDIS
Received STALLed Interrupt Set
6
1
SHORTPACKETIS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Set
12
1
10
4
HSTPIPIFR_INTRPT_MODE[%s]
Host Pipe Set Register
HSTPIPIFR_CTRL_MODE[%s]
0x590
32
write-only
RXINIS
Received IN Data Interrupt Set
0
1
TXOUTIS
Transmitted OUT Data Interrupt Set
1
1
UNDERFIS
Underflow Interrupt Set
2
1
PERRIS
Pipe Error Interrupt Set
3
1
NAKEDIS
NAKed Interrupt Set
4
1
OVERFIS
Overflow Interrupt Set
5
1
RXSTALLDIS
Received STALLed Interrupt Set
6
1
SHORTPACKETIS
Short Packet Interrupt Set
7
1
NBUSYBKS
Number of Busy Banks Set
12
1
10
4
HSTPIPIMR_CTRL_MODE[%s]
Host Pipe Mask Register
0x5C0
32
read-only
RXINE
Received IN Data Interrupt Enable
0
1
TXOUTE
Transmitted OUT Data Interrupt Enable
1
1
TXSTPE
Transmitted SETUP Interrupt Enable
2
1
PERRE
Pipe Error Interrupt Enable
3
1
NAKEDE
NAKed Interrupt Enable
4
1
OVERFIE
Overflow Interrupt Enable
5
1
RXSTALLDE
Received STALLed Interrupt Enable
6
1
SHORTPACKETIE
Short Packet Interrupt Enable
7
1
NBUSYBKE
Number of Busy Banks Interrupt Enable
12
1
FIFOCON
FIFO Control
14
1
PDISHDMA
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZE
Pipe Freeze
17
1
RSTDT
Reset Data Toggle
18
1
10
4
HSTPIPIMR_ISO_MODE[%s]
Host Pipe Mask Register
HSTPIPIMR_CTRL_MODE[%s]
0x5C0
32
read-only
RXINE
Received IN Data Interrupt Enable
0
1
TXOUTE
Transmitted OUT Data Interrupt Enable
1
1
UNDERFIE
Underflow Interrupt Enable
2
1
PERRE
Pipe Error Interrupt Enable
3
1
NAKEDE
NAKed Interrupt Enable
4
1
OVERFIE
Overflow Interrupt Enable
5
1
CRCERRE
CRC Error Interrupt Enable
6
1
SHORTPACKETIE
Short Packet Interrupt Enable
7
1
NBUSYBKE
Number of Busy Banks Interrupt Enable
12
1
FIFOCON
FIFO Control
14
1
PDISHDMA
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZE
Pipe Freeze
17
1
RSTDT
Reset Data Toggle
18
1
10
4
HSTPIPIMR_BLK_MODE[%s]
Host Pipe Mask Register
HSTPIPIMR_CTRL_MODE[%s]
0x5C0
32
read-only
RXINE
Received IN Data Interrupt Enable
0
1
TXOUTE
Transmitted OUT Data Interrupt Enable
1
1
TXSTPE
Transmitted SETUP Interrupt Enable
2
1
PERRE
Pipe Error Interrupt Enable
3
1
NAKEDE
NAKed Interrupt Enable
4
1
OVERFIE
Overflow Interrupt Enable
5
1
RXSTALLDE
Received STALLed Interrupt Enable
6
1
SHORTPACKETIE
Short Packet Interrupt Enable
7
1
NBUSYBKE
Number of Busy Banks Interrupt Enable
12
1
FIFOCON
FIFO Control
14
1
PDISHDMA
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZE
Pipe Freeze
17
1
RSTDT
Reset Data Toggle
18
1
10
4
HSTPIPIMR_INTRPT_MODE[%s]
Host Pipe Mask Register
HSTPIPIMR_CTRL_MODE[%s]
0x5C0
32
read-only
RXINE
Received IN Data Interrupt Enable
0
1
TXOUTE
Transmitted OUT Data Interrupt Enable
1
1
UNDERFIE
Underflow Interrupt Enable
2
1
PERRE
Pipe Error Interrupt Enable
3
1
NAKEDE
NAKed Interrupt Enable
4
1
OVERFIE
Overflow Interrupt Enable
5
1
RXSTALLDE
Received STALLed Interrupt Enable
6
1
SHORTPACKETIE
Short Packet Interrupt Enable
7
1
NBUSYBKE
Number of Busy Banks Interrupt Enable
12
1
FIFOCON
FIFO Control
14
1
PDISHDMA
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZE
Pipe Freeze
17
1
RSTDT
Reset Data Toggle
18
1
10
4
HSTPIPIER_CTRL_MODE[%s]
Host Pipe Enable Register
0x5F0
32
write-only
RXINES
Received IN Data Interrupt Enable
0
1
TXOUTES
Transmitted OUT Data Interrupt Enable
1
1
TXSTPES
Transmitted SETUP Interrupt Enable
2
1
PERRES
Pipe Error Interrupt Enable
3
1
NAKEDES
NAKed Interrupt Enable
4
1
OVERFIES
Overflow Interrupt Enable
5
1
RXSTALLDES
Received STALLed Interrupt Enable
6
1
SHORTPACKETIES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Enable
12
1
PDISHDMAS
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZES
Pipe Freeze Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
10
4
HSTPIPIER_ISO_MODE[%s]
Host Pipe Enable Register
HSTPIPIER_CTRL_MODE[%s]
0x5F0
32
write-only
RXINES
Received IN Data Interrupt Enable
0
1
TXOUTES
Transmitted OUT Data Interrupt Enable
1
1
UNDERFIES
Underflow Interrupt Enable
2
1
PERRES
Pipe Error Interrupt Enable
3
1
NAKEDES
NAKed Interrupt Enable
4
1
OVERFIES
Overflow Interrupt Enable
5
1
CRCERRES
CRC Error Interrupt Enable
6
1
SHORTPACKETIES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Enable
12
1
PDISHDMAS
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZES
Pipe Freeze Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
10
4
HSTPIPIER_BLK_MODE[%s]
Host Pipe Enable Register
HSTPIPIER_CTRL_MODE[%s]
0x5F0
32
write-only
RXINES
Received IN Data Interrupt Enable
0
1
TXOUTES
Transmitted OUT Data Interrupt Enable
1
1
TXSTPES
Transmitted SETUP Interrupt Enable
2
1
PERRES
Pipe Error Interrupt Enable
3
1
NAKEDES
NAKed Interrupt Enable
4
1
OVERFIES
Overflow Interrupt Enable
5
1
RXSTALLDES
Received STALLed Interrupt Enable
6
1
SHORTPACKETIES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Enable
12
1
PDISHDMAS
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZES
Pipe Freeze Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
10
4
HSTPIPIER_INTRPT_MODE[%s]
Host Pipe Enable Register
HSTPIPIER_CTRL_MODE[%s]
0x5F0
32
write-only
RXINES
Received IN Data Interrupt Enable
0
1
TXOUTES
Transmitted OUT Data Interrupt Enable
1
1
UNDERFIES
Underflow Interrupt Enable
2
1
PERRES
Pipe Error Interrupt Enable
3
1
NAKEDES
NAKed Interrupt Enable
4
1
OVERFIES
Overflow Interrupt Enable
5
1
RXSTALLDES
Received STALLed Interrupt Enable
6
1
SHORTPACKETIES
Short Packet Interrupt Enable
7
1
NBUSYBKES
Number of Busy Banks Enable
12
1
PDISHDMAS
Pipe Interrupts Disable HDMA Request Enable
16
1
PFREEZES
Pipe Freeze Enable
17
1
RSTDTS
Reset Data Toggle Enable
18
1
10
4
HSTPIPIDR_CTRL_MODE[%s]
Host Pipe Disable Register
0x620
32
write-only
RXINEC
Received IN Data Interrupt Disable
0
1
TXOUTEC
Transmitted OUT Data Interrupt Disable
1
1
TXSTPEC
Transmitted SETUP Interrupt Disable
2
1
PERREC
Pipe Error Interrupt Disable
3
1
NAKEDEC
NAKed Interrupt Disable
4
1
OVERFIEC
Overflow Interrupt Disable
5
1
RXSTALLDEC
Received STALLed Interrupt Disable
6
1
SHORTPACKETIEC
Short Packet Interrupt Disable
7
1
NBUSYBKEC
Number of Busy Banks Disable
12
1
FIFOCONC
FIFO Control Disable
14
1
PDISHDMAC
Pipe Interrupts Disable HDMA Request Disable
16
1
PFREEZEC
Pipe Freeze Disable
17
1
10
4
HSTPIPIDR_ISO_MODE[%s]
Host Pipe Disable Register
HSTPIPIDR_CTRL_MODE[%s]
0x620
32
write-only
RXINEC
Received IN Data Interrupt Disable
0
1
TXOUTEC
Transmitted OUT Data Interrupt Disable
1
1
UNDERFIEC
Underflow Interrupt Disable
2
1
PERREC
Pipe Error Interrupt Disable
3
1
NAKEDEC
NAKed Interrupt Disable
4
1
OVERFIEC
Overflow Interrupt Disable
5
1
CRCERREC
CRC Error Interrupt Disable
6
1
SHORTPACKETIEC
Short Packet Interrupt Disable
7
1
NBUSYBKEC
Number of Busy Banks Disable
12
1
FIFOCONC
FIFO Control Disable
14
1
PDISHDMAC
Pipe Interrupts Disable HDMA Request Disable
16
1
PFREEZEC
Pipe Freeze Disable
17
1
10
4
HSTPIPIDR_BLK_MODE[%s]
Host Pipe Disable Register
HSTPIPIDR_CTRL_MODE[%s]
0x620
32
write-only
RXINEC
Received IN Data Interrupt Disable
0
1
TXOUTEC
Transmitted OUT Data Interrupt Disable
1
1
TXSTPEC
Transmitted SETUP Interrupt Disable
2
1
PERREC
Pipe Error Interrupt Disable
3
1
NAKEDEC
NAKed Interrupt Disable
4
1
OVERFIEC
Overflow Interrupt Disable
5
1
RXSTALLDEC
Received STALLed Interrupt Disable
6
1
SHORTPACKETIEC
Short Packet Interrupt Disable
7
1
NBUSYBKEC
Number of Busy Banks Disable
12
1
FIFOCONC
FIFO Control Disable
14
1
PDISHDMAC
Pipe Interrupts Disable HDMA Request Disable
16
1
PFREEZEC
Pipe Freeze Disable
17
1
10
4
HSTPIPIDR_INTRPT_MODE[%s]
Host Pipe Disable Register
HSTPIPIDR_CTRL_MODE[%s]
0x620
32
write-only
RXINEC
Received IN Data Interrupt Disable
0
1
TXOUTEC
Transmitted OUT Data Interrupt Disable
1
1
UNDERFIEC
Underflow Interrupt Disable
2
1
PERREC
Pipe Error Interrupt Disable
3
1
NAKEDEC
NAKed Interrupt Disable
4
1
OVERFIEC
Overflow Interrupt Disable
5
1
RXSTALLDEC
Received STALLed Interrupt Disable
6
1
SHORTPACKETIEC
Short Packet Interrupt Disable
7
1
NBUSYBKEC
Number of Busy Banks Disable
12
1
FIFOCONC
FIFO Control Disable
14
1
PDISHDMAC
Pipe Interrupts Disable HDMA Request Disable
16
1
PFREEZEC
Pipe Freeze Disable
17
1
10
4
HSTPIPINRQ[%s]
Host Pipe IN Request Register
0x650
32
INRQ
IN Request Number before Freeze
0
8
INMODE
IN Request Mode
8
1
10
4
HSTPIPERR[%s]
Host Pipe Error Register
0x680
32
DATATGL
Data Toggle Error
0
1
DATAPID
Data PID Error
1
1
PID
Data PID Error
2
1
TIMEOUT
Time-Out Error
3
1
CRC16
CRC16 Error
4
1
COUNTER
Error Counter
5
2
7
16
USBHS_HSTDMA[%s]
Host DMA Channel Next Descriptor Address Register
0x710
HSTDMANXTDSC
Host DMA Channel Next Descriptor Address Register
0x00
32
NXT_DSC_ADD
Next Descriptor Address
0
32
HSTDMAADDRESS
Host DMA Channel Address Register
0x04
32
BUFF_ADD
Buffer Address
0
32
HSTDMACONTROL
Host DMA Channel Control Register
0x08
32
CHANN_ENB
Channel Enable Command
0
1
LDNXT_DSC
Load Next Channel Transfer Descriptor Enable Command
1
1
END_TR_EN
End of Transfer Enable Control (OUT transfers only)
2
1
END_B_EN
End of Buffer Enable Control
3
1
END_TR_IT
End of Transfer Interrupt Enable
4
1
END_BUFFIT
End of Buffer Interrupt Enable
5
1
DESC_LD_IT
Descriptor Loaded Interrupt Enable
6
1
BURST_LCK
Burst Lock Enable
7
1
BUFF_LENGTH
Buffer Byte Length (Write-only)
16
16
HSTDMASTATUS
Host DMA Channel Status Register
0x0C
32
CHANN_ENB
Channel Enable Status
0
1
CHANN_ACT
Channel Active Status
1
1
END_TR_ST
End of Channel Transfer Status
4
1
END_BF_ST
End of Channel Buffer Status
5
1
DESC_LDST
Descriptor Loaded Status
6
1
BUFF_COUNT
Buffer Byte Count
16
16
CTRL
General Control Register
0x0800
32
RDERRE
Remote Device Connection Error Interrupt Enable
4
1
VBUSHWC
VBUS Hardware Control
8
1
FRZCLK
Freeze USB Clock
14
1
USBE
USBHS Enable
15
1
UID
UID Pin Enable
24
1
UIMOD
USBHS Mode
25
1
UIMODSelect
HOST
The module is in USB Host mode.
0
DEVICE
The module is in USB Device mode.
1
SR
General Status Register
0x0804
32
read-only
RDERRI
Remote Device Connection Error Interrupt (Host mode only)
4
1
SPEED
Speed Status (Device mode only)
12
2
SPEEDSelect
FULL_SPEED
Full-Speed mode
0x0
HIGH_SPEED
High-Speed mode
0x1
LOW_SPEED
Low-Speed mode
0x2
CLKUSABLE
UTMI Clock Usable
14
1
SCR
General Status Clear Register
0x0808
32
write-only
RDERRIC
Remote Device Connection Error Interrupt Clear
4
1
SFR
General Status Set Register
0x080C
32
write-only
RDERRIS
Remote Device Connection Error Interrupt Set
4
1
VBUSRQS
VBUS Request Set
9
1
UTMI
11300A
USB Transmitter Interface Macrocell
0x400E0400
0
0x34
registers
OHCIICR
OHCI Interrupt Configuration Register
0x10
32
RES0
USB PORTx Reset
0
1
ARIE
OHCI Asynchronous Resume Interrupt Enable
4
1
APPSTART
5
1
UDPPUDIS
USB Device Pull-up Disable
23
1
CKTRIM
UTMI Clock Trimming Register
0x30
32
FREQ
UTMI Reference Clock Frequency
0
2
FREQSelect
XTAL12
12 MHz reference clock
0
XTAL16
16 MHz reference clock
1
WDT
6080N
Watchdog Timer
0x400E1850
0
0xC
registers
WDT
4
CR
Control Register
0x00
32
write-only
WDRSTT
Watchdog Restart
0
1
KEY
Password
24
8
KEYSelect
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
MR
Mode Register
0x04
32
WDV
Watchdog Counter Value
0
12
WDFIEN
Watchdog Fault Interrupt Enable
12
1
WDRSTEN
Watchdog Reset Enable
13
1
WDDIS
Watchdog Disable
15
1
WDD
Watchdog Delta Value
16
12
WDDBGHLT
Watchdog Debug Halt
28
1
WDIDLEHLT
Watchdog Idle Halt
29
1
SR
Status Register
0x08
32
read-only
WDUNF
Watchdog Underflow (cleared on read)
0
1
WDERR
Watchdog Error (cleared on read)
1
1
XDMAC
11161K
Extensible DMA Controller
0x40078000
0
0xE60
registers
XDMAC
58
GTYPE
Global Type Register
0x00
32
read-only
NB_CH
Number of Channels Minus One
0
5
FIFO_SZ
Number of Bytes
5
11
NB_REQ
Number of Peripheral Requests Minus One
16
7
GCFG
Global Configuration Register
0x04
32
CGDISREG
Configuration Registers Clock Gating Disable
0
1
CGDISPIPE
Pipeline Clock Gating Disable
1
1
CGDISFIFO
FIFO Clock Gating Disable
2
1
CGDISIF
Bus Interface Clock Gating Disable
3
1
BXKBEN
Boundary X Kilobyte Enable
8
1
GWAC
Global Weighted Arbiter Configuration Register
0x08
32
PW0
Pool Weight 0
0
4
PW1
Pool Weight 1
4
4
PW2
Pool Weight 2
8
4
PW3
Pool Weight 3
12
4
GIE
Global Interrupt Enable Register
0x0C
32
write-only
IE0
XDMAC Channel 0 Interrupt Enable Bit
0
1
IE1
XDMAC Channel 1 Interrupt Enable Bit
1
1
IE2
XDMAC Channel 2 Interrupt Enable Bit
2
1
IE3
XDMAC Channel 3 Interrupt Enable Bit
3
1
IE4
XDMAC Channel 4 Interrupt Enable Bit
4
1
IE5
XDMAC Channel 5 Interrupt Enable Bit
5
1
IE6
XDMAC Channel 6 Interrupt Enable Bit
6
1
IE7
XDMAC Channel 7 Interrupt Enable Bit
7
1
IE8
XDMAC Channel 8 Interrupt Enable Bit
8
1
IE9
XDMAC Channel 9 Interrupt Enable Bit
9
1
IE10
XDMAC Channel 10 Interrupt Enable Bit
10
1
IE11
XDMAC Channel 11 Interrupt Enable Bit
11
1
IE12
XDMAC Channel 12 Interrupt Enable Bit
12
1
IE13
XDMAC Channel 13 Interrupt Enable Bit
13
1
IE14
XDMAC Channel 14 Interrupt Enable Bit
14
1
IE15
XDMAC Channel 15 Interrupt Enable Bit
15
1
IE16
XDMAC Channel 16 Interrupt Enable Bit
16
1
IE17
XDMAC Channel 17 Interrupt Enable Bit
17
1
IE18
XDMAC Channel 18 Interrupt Enable Bit
18
1
IE19
XDMAC Channel 19 Interrupt Enable Bit
19
1
IE20
XDMAC Channel 20 Interrupt Enable Bit
20
1
IE21
XDMAC Channel 21 Interrupt Enable Bit
21
1
IE22
XDMAC Channel 22 Interrupt Enable Bit
22
1
IE23
XDMAC Channel 23 Interrupt Enable Bit
23
1
GID
Global Interrupt Disable Register
0x10
32
write-only
ID0
XDMAC Channel 0 Interrupt Disable Bit
0
1
ID1
XDMAC Channel 1 Interrupt Disable Bit
1
1
ID2
XDMAC Channel 2 Interrupt Disable Bit
2
1
ID3
XDMAC Channel 3 Interrupt Disable Bit
3
1
ID4
XDMAC Channel 4 Interrupt Disable Bit
4
1
ID5
XDMAC Channel 5 Interrupt Disable Bit
5
1
ID6
XDMAC Channel 6 Interrupt Disable Bit
6
1
ID7
XDMAC Channel 7 Interrupt Disable Bit
7
1
ID8
XDMAC Channel 8 Interrupt Disable Bit
8
1
ID9
XDMAC Channel 9 Interrupt Disable Bit
9
1
ID10
XDMAC Channel 10 Interrupt Disable Bit
10
1
ID11
XDMAC Channel 11 Interrupt Disable Bit
11
1
ID12
XDMAC Channel 12 Interrupt Disable Bit
12
1
ID13
XDMAC Channel 13 Interrupt Disable Bit
13
1
ID14
XDMAC Channel 14 Interrupt Disable Bit
14
1
ID15
XDMAC Channel 15 Interrupt Disable Bit
15
1
ID16
XDMAC Channel 16 Interrupt Disable Bit
16
1
ID17
XDMAC Channel 17 Interrupt Disable Bit
17
1
ID18
XDMAC Channel 18 Interrupt Disable Bit
18
1
ID19
XDMAC Channel 19 Interrupt Disable Bit
19
1
ID20
XDMAC Channel 20 Interrupt Disable Bit
20
1
ID21
XDMAC Channel 21 Interrupt Disable Bit
21
1
ID22
XDMAC Channel 22 Interrupt Disable Bit
22
1
ID23
XDMAC Channel 23 Interrupt Disable Bit
23
1
GIM
Global Interrupt Mask Register
0x14
32
read-only
IM0
XDMAC Channel 0 Interrupt Mask Bit
0
1
IM1
XDMAC Channel 1 Interrupt Mask Bit
1
1
IM2
XDMAC Channel 2 Interrupt Mask Bit
2
1
IM3
XDMAC Channel 3 Interrupt Mask Bit
3
1
IM4
XDMAC Channel 4 Interrupt Mask Bit
4
1
IM5
XDMAC Channel 5 Interrupt Mask Bit
5
1
IM6
XDMAC Channel 6 Interrupt Mask Bit
6
1
IM7
XDMAC Channel 7 Interrupt Mask Bit
7
1
IM8
XDMAC Channel 8 Interrupt Mask Bit
8
1
IM9
XDMAC Channel 9 Interrupt Mask Bit
9
1
IM10
XDMAC Channel 10 Interrupt Mask Bit
10
1
IM11
XDMAC Channel 11 Interrupt Mask Bit
11
1
IM12
XDMAC Channel 12 Interrupt Mask Bit
12
1
IM13
XDMAC Channel 13 Interrupt Mask Bit
13
1
IM14
XDMAC Channel 14 Interrupt Mask Bit
14
1
IM15
XDMAC Channel 15 Interrupt Mask Bit
15
1
IM16
XDMAC Channel 16 Interrupt Mask Bit
16
1
IM17
XDMAC Channel 17 Interrupt Mask Bit
17
1
IM18
XDMAC Channel 18 Interrupt Mask Bit
18
1
IM19
XDMAC Channel 19 Interrupt Mask Bit
19
1
IM20
XDMAC Channel 20 Interrupt Mask Bit
20
1
IM21
XDMAC Channel 21 Interrupt Mask Bit
21
1
IM22
XDMAC Channel 22 Interrupt Mask Bit
22
1
IM23
XDMAC Channel 23 Interrupt Mask Bit
23
1
GIS
Global Interrupt Status Register
0x18
32
read-only
IS0
XDMAC Channel 0 Interrupt Status Bit
0
1
IS1
XDMAC Channel 1 Interrupt Status Bit
1
1
IS2
XDMAC Channel 2 Interrupt Status Bit
2
1
IS3
XDMAC Channel 3 Interrupt Status Bit
3
1
IS4
XDMAC Channel 4 Interrupt Status Bit
4
1
IS5
XDMAC Channel 5 Interrupt Status Bit
5
1
IS6
XDMAC Channel 6 Interrupt Status Bit
6
1
IS7
XDMAC Channel 7 Interrupt Status Bit
7
1
IS8
XDMAC Channel 8 Interrupt Status Bit
8
1
IS9
XDMAC Channel 9 Interrupt Status Bit
9
1
IS10
XDMAC Channel 10 Interrupt Status Bit
10
1
IS11
XDMAC Channel 11 Interrupt Status Bit
11
1
IS12
XDMAC Channel 12 Interrupt Status Bit
12
1
IS13
XDMAC Channel 13 Interrupt Status Bit
13
1
IS14
XDMAC Channel 14 Interrupt Status Bit
14
1
IS15
XDMAC Channel 15 Interrupt Status Bit
15
1
IS16
XDMAC Channel 16 Interrupt Status Bit
16
1
IS17
XDMAC Channel 17 Interrupt Status Bit
17
1
IS18
XDMAC Channel 18 Interrupt Status Bit
18
1
IS19
XDMAC Channel 19 Interrupt Status Bit
19
1
IS20
XDMAC Channel 20 Interrupt Status Bit
20
1
IS21
XDMAC Channel 21 Interrupt Status Bit
21
1
IS22
XDMAC Channel 22 Interrupt Status Bit
22
1
IS23
XDMAC Channel 23 Interrupt Status Bit
23
1
GE
Global Channel Enable Register
0x1C
32
write-only
EN0
XDMAC Channel 0 Enable Bit
0
1
EN1
XDMAC Channel 1 Enable Bit
1
1
EN2
XDMAC Channel 2 Enable Bit
2
1
EN3
XDMAC Channel 3 Enable Bit
3
1
EN4
XDMAC Channel 4 Enable Bit
4
1
EN5
XDMAC Channel 5 Enable Bit
5
1
EN6
XDMAC Channel 6 Enable Bit
6
1
EN7
XDMAC Channel 7 Enable Bit
7
1
EN8
XDMAC Channel 8 Enable Bit
8
1
EN9
XDMAC Channel 9 Enable Bit
9
1
EN10
XDMAC Channel 10 Enable Bit
10
1
EN11
XDMAC Channel 11 Enable Bit
11
1
EN12
XDMAC Channel 12 Enable Bit
12
1
EN13
XDMAC Channel 13 Enable Bit
13
1
EN14
XDMAC Channel 14 Enable Bit
14
1
EN15
XDMAC Channel 15 Enable Bit
15
1
EN16
XDMAC Channel 16 Enable Bit
16
1
EN17
XDMAC Channel 17 Enable Bit
17
1
EN18
XDMAC Channel 18 Enable Bit
18
1
EN19
XDMAC Channel 19 Enable Bit
19
1
EN20
XDMAC Channel 20 Enable Bit
20
1
EN21
XDMAC Channel 21 Enable Bit
21
1
EN22
XDMAC Channel 22 Enable Bit
22
1
EN23
XDMAC Channel 23 Enable Bit
23
1
GD
Global Channel Disable Register
0x20
32
write-only
DI0
XDMAC Channel 0 Disable Bit
0
1
DI1
XDMAC Channel 1 Disable Bit
1
1
DI2
XDMAC Channel 2 Disable Bit
2
1
DI3
XDMAC Channel 3 Disable Bit
3
1
DI4
XDMAC Channel 4 Disable Bit
4
1
DI5
XDMAC Channel 5 Disable Bit
5
1
DI6
XDMAC Channel 6 Disable Bit
6
1
DI7
XDMAC Channel 7 Disable Bit
7
1
DI8
XDMAC Channel 8 Disable Bit
8
1
DI9
XDMAC Channel 9 Disable Bit
9
1
DI10
XDMAC Channel 10 Disable Bit
10
1
DI11
XDMAC Channel 11 Disable Bit
11
1
DI12
XDMAC Channel 12 Disable Bit
12
1
DI13
XDMAC Channel 13 Disable Bit
13
1
DI14
XDMAC Channel 14 Disable Bit
14
1
DI15
XDMAC Channel 15 Disable Bit
15
1
DI16
XDMAC Channel 16 Disable Bit
16
1
DI17
XDMAC Channel 17 Disable Bit
17
1
DI18
XDMAC Channel 18 Disable Bit
18
1
DI19
XDMAC Channel 19 Disable Bit
19
1
DI20
XDMAC Channel 20 Disable Bit
20
1
DI21
XDMAC Channel 21 Disable Bit
21
1
DI22
XDMAC Channel 22 Disable Bit
22
1
DI23
XDMAC Channel 23 Disable Bit
23
1
GS
Global Channel Status Register
0x24
32
read-only
ST0
XDMAC Channel 0 Status Bit
0
1
ST1
XDMAC Channel 1 Status Bit
1
1
ST2
XDMAC Channel 2 Status Bit
2
1
ST3
XDMAC Channel 3 Status Bit
3
1
ST4
XDMAC Channel 4 Status Bit
4
1
ST5
XDMAC Channel 5 Status Bit
5
1
ST6
XDMAC Channel 6 Status Bit
6
1
ST7
XDMAC Channel 7 Status Bit
7
1
ST8
XDMAC Channel 8 Status Bit
8
1
ST9
XDMAC Channel 9 Status Bit
9
1
ST10
XDMAC Channel 10 Status Bit
10
1
ST11
XDMAC Channel 11 Status Bit
11
1
ST12
XDMAC Channel 12 Status Bit
12
1
ST13
XDMAC Channel 13 Status Bit
13
1
ST14
XDMAC Channel 14 Status Bit
14
1
ST15
XDMAC Channel 15 Status Bit
15
1
ST16
XDMAC Channel 16 Status Bit
16
1
ST17
XDMAC Channel 17 Status Bit
17
1
ST18
XDMAC Channel 18 Status Bit
18
1
ST19
XDMAC Channel 19 Status Bit
19
1
ST20
XDMAC Channel 20 Status Bit
20
1
ST21
XDMAC Channel 21 Status Bit
21
1
ST22
XDMAC Channel 22 Status Bit
22
1
ST23
XDMAC Channel 23 Status Bit
23
1
GRS
Global Channel Read Suspend Register
0x28
32
RS0
XDMAC Channel 0 Read Suspend Bit
0
1
RS1
XDMAC Channel 1 Read Suspend Bit
1
1
RS2
XDMAC Channel 2 Read Suspend Bit
2
1
RS3
XDMAC Channel 3 Read Suspend Bit
3
1
RS4
XDMAC Channel 4 Read Suspend Bit
4
1
RS5
XDMAC Channel 5 Read Suspend Bit
5
1
RS6
XDMAC Channel 6 Read Suspend Bit
6
1
RS7
XDMAC Channel 7 Read Suspend Bit
7
1
RS8
XDMAC Channel 8 Read Suspend Bit
8
1
RS9
XDMAC Channel 9 Read Suspend Bit
9
1
RS10
XDMAC Channel 10 Read Suspend Bit
10
1
RS11
XDMAC Channel 11 Read Suspend Bit
11
1
RS12
XDMAC Channel 12 Read Suspend Bit
12
1
RS13
XDMAC Channel 13 Read Suspend Bit
13
1
RS14
XDMAC Channel 14 Read Suspend Bit
14
1
RS15
XDMAC Channel 15 Read Suspend Bit
15
1
RS16
XDMAC Channel 16 Read Suspend Bit
16
1
RS17
XDMAC Channel 17 Read Suspend Bit
17
1
RS18
XDMAC Channel 18 Read Suspend Bit
18
1
RS19
XDMAC Channel 19 Read Suspend Bit
19
1
RS20
XDMAC Channel 20 Read Suspend Bit
20
1
RS21
XDMAC Channel 21 Read Suspend Bit
21
1
RS22
XDMAC Channel 22 Read Suspend Bit
22
1
RS23
XDMAC Channel 23 Read Suspend Bit
23
1
GWS
Global Channel Write Suspend Register
0x2C
32
WS0
XDMAC Channel 0 Write Suspend Bit
0
1
WS1
XDMAC Channel 1 Write Suspend Bit
1
1
WS2
XDMAC Channel 2 Write Suspend Bit
2
1
WS3
XDMAC Channel 3 Write Suspend Bit
3
1
WS4
XDMAC Channel 4 Write Suspend Bit
4
1
WS5
XDMAC Channel 5 Write Suspend Bit
5
1
WS6
XDMAC Channel 6 Write Suspend Bit
6
1
WS7
XDMAC Channel 7 Write Suspend Bit
7
1
WS8
XDMAC Channel 8 Write Suspend Bit
8
1
WS9
XDMAC Channel 9 Write Suspend Bit
9
1
WS10
XDMAC Channel 10 Write Suspend Bit
10
1
WS11
XDMAC Channel 11 Write Suspend Bit
11
1
WS12
XDMAC Channel 12 Write Suspend Bit
12
1
WS13
XDMAC Channel 13 Write Suspend Bit
13
1
WS14
XDMAC Channel 14 Write Suspend Bit
14
1
WS15
XDMAC Channel 15 Write Suspend Bit
15
1
WS16
XDMAC Channel 16 Write Suspend Bit
16
1
WS17
XDMAC Channel 17 Write Suspend Bit
17
1
WS18
XDMAC Channel 18 Write Suspend Bit
18
1
WS19
XDMAC Channel 19 Write Suspend Bit
19
1
WS20
XDMAC Channel 20 Write Suspend Bit
20
1
WS21
XDMAC Channel 21 Write Suspend Bit
21
1
WS22
XDMAC Channel 22 Write Suspend Bit
22
1
WS23
XDMAC Channel 23 Write Suspend Bit
23
1
GRWS
Global Channel Read Write Suspend Register
0x30
32
write-only
RWS0
XDMAC Channel 0 Read Write Suspend Bit
0
1
RWS1
XDMAC Channel 1 Read Write Suspend Bit
1
1
RWS2
XDMAC Channel 2 Read Write Suspend Bit
2
1
RWS3
XDMAC Channel 3 Read Write Suspend Bit
3
1
RWS4
XDMAC Channel 4 Read Write Suspend Bit
4
1
RWS5
XDMAC Channel 5 Read Write Suspend Bit
5
1
RWS6
XDMAC Channel 6 Read Write Suspend Bit
6
1
RWS7
XDMAC Channel 7 Read Write Suspend Bit
7
1
RWS8
XDMAC Channel 8 Read Write Suspend Bit
8
1
RWS9
XDMAC Channel 9 Read Write Suspend Bit
9
1
RWS10
XDMAC Channel 10 Read Write Suspend Bit
10
1
RWS11
XDMAC Channel 11 Read Write Suspend Bit
11
1
RWS12
XDMAC Channel 12 Read Write Suspend Bit
12
1
RWS13
XDMAC Channel 13 Read Write Suspend Bit
13
1
RWS14
XDMAC Channel 14 Read Write Suspend Bit
14
1
RWS15
XDMAC Channel 15 Read Write Suspend Bit
15
1
RWS16
XDMAC Channel 16 Read Write Suspend Bit
16
1
RWS17
XDMAC Channel 17 Read Write Suspend Bit
17
1
RWS18
XDMAC Channel 18 Read Write Suspend Bit
18
1
RWS19
XDMAC Channel 19 Read Write Suspend Bit
19
1
RWS20
XDMAC Channel 20 Read Write Suspend Bit
20
1
RWS21
XDMAC Channel 21 Read Write Suspend Bit
21
1
RWS22
XDMAC Channel 22 Read Write Suspend Bit
22
1
RWS23
XDMAC Channel 23 Read Write Suspend Bit
23
1
GRWR
Global Channel Read Write Resume Register
0x34
32
write-only
RWR0
XDMAC Channel 0 Read Write Resume Bit
0
1
RWR1
XDMAC Channel 1 Read Write Resume Bit
1
1
RWR2
XDMAC Channel 2 Read Write Resume Bit
2
1
RWR3
XDMAC Channel 3 Read Write Resume Bit
3
1
RWR4
XDMAC Channel 4 Read Write Resume Bit
4
1
RWR5
XDMAC Channel 5 Read Write Resume Bit
5
1
RWR6
XDMAC Channel 6 Read Write Resume Bit
6
1
RWR7
XDMAC Channel 7 Read Write Resume Bit
7
1
RWR8
XDMAC Channel 8 Read Write Resume Bit
8
1
RWR9
XDMAC Channel 9 Read Write Resume Bit
9
1
RWR10
XDMAC Channel 10 Read Write Resume Bit
10
1
RWR11
XDMAC Channel 11 Read Write Resume Bit
11
1
RWR12
XDMAC Channel 12 Read Write Resume Bit
12
1
RWR13
XDMAC Channel 13 Read Write Resume Bit
13
1
RWR14
XDMAC Channel 14 Read Write Resume Bit
14
1
RWR15
XDMAC Channel 15 Read Write Resume Bit
15
1
RWR16
XDMAC Channel 16 Read Write Resume Bit
16
1
RWR17
XDMAC Channel 17 Read Write Resume Bit
17
1
RWR18
XDMAC Channel 18 Read Write Resume Bit
18
1
RWR19
XDMAC Channel 19 Read Write Resume Bit
19
1
RWR20
XDMAC Channel 20 Read Write Resume Bit
20
1
RWR21
XDMAC Channel 21 Read Write Resume Bit
21
1
RWR22
XDMAC Channel 22 Read Write Resume Bit
22
1
RWR23
XDMAC Channel 23 Read Write Resume Bit
23
1
GSWR
Global Channel Software Request Register
0x38
32
write-only
SWREQ0
XDMAC Channel 0 Software Request Bit
0
1
SWREQ1
XDMAC Channel 1 Software Request Bit
1
1
SWREQ2
XDMAC Channel 2 Software Request Bit
2
1
SWREQ3
XDMAC Channel 3 Software Request Bit
3
1
SWREQ4
XDMAC Channel 4 Software Request Bit
4
1
SWREQ5
XDMAC Channel 5 Software Request Bit
5
1
SWREQ6
XDMAC Channel 6 Software Request Bit
6
1
SWREQ7
XDMAC Channel 7 Software Request Bit
7
1
SWREQ8
XDMAC Channel 8 Software Request Bit
8
1
SWREQ9
XDMAC Channel 9 Software Request Bit
9
1
SWREQ10
XDMAC Channel 10 Software Request Bit
10
1
SWREQ11
XDMAC Channel 11 Software Request Bit
11
1
SWREQ12
XDMAC Channel 12 Software Request Bit
12
1
SWREQ13
XDMAC Channel 13 Software Request Bit
13
1
SWREQ14
XDMAC Channel 14 Software Request Bit
14
1
SWREQ15
XDMAC Channel 15 Software Request Bit
15
1
SWREQ16
XDMAC Channel 16 Software Request Bit
16
1
SWREQ17
XDMAC Channel 17 Software Request Bit
17
1
SWREQ18
XDMAC Channel 18 Software Request Bit
18
1
SWREQ19
XDMAC Channel 19 Software Request Bit
19
1
SWREQ20
XDMAC Channel 20 Software Request Bit
20
1
SWREQ21
XDMAC Channel 21 Software Request Bit
21
1
SWREQ22
XDMAC Channel 22 Software Request Bit
22
1
SWREQ23
XDMAC Channel 23 Software Request Bit
23
1
GSWS
Global Channel Software Request Status Register
0x3C
32
read-only
SWRS0
XDMAC Channel 0 Software Request Status Bit
0
1
SWRS1
XDMAC Channel 1 Software Request Status Bit
1
1
SWRS2
XDMAC Channel 2 Software Request Status Bit
2
1
SWRS3
XDMAC Channel 3 Software Request Status Bit
3
1
SWRS4
XDMAC Channel 4 Software Request Status Bit
4
1
SWRS5
XDMAC Channel 5 Software Request Status Bit
5
1
SWRS6
XDMAC Channel 6 Software Request Status Bit
6
1
SWRS7
XDMAC Channel 7 Software Request Status Bit
7
1
SWRS8
XDMAC Channel 8 Software Request Status Bit
8
1
SWRS9
XDMAC Channel 9 Software Request Status Bit
9
1
SWRS10
XDMAC Channel 10 Software Request Status Bit
10
1
SWRS11
XDMAC Channel 11 Software Request Status Bit
11
1
SWRS12
XDMAC Channel 12 Software Request Status Bit
12
1
SWRS13
XDMAC Channel 13 Software Request Status Bit
13
1
SWRS14
XDMAC Channel 14 Software Request Status Bit
14
1
SWRS15
XDMAC Channel 15 Software Request Status Bit
15
1
SWRS16
XDMAC Channel 16 Software Request Status Bit
16
1
SWRS17
XDMAC Channel 17 Software Request Status Bit
17
1
SWRS18
XDMAC Channel 18 Software Request Status Bit
18
1
SWRS19
XDMAC Channel 19 Software Request Status Bit
19
1
SWRS20
XDMAC Channel 20 Software Request Status Bit
20
1
SWRS21
XDMAC Channel 21 Software Request Status Bit
21
1
SWRS22
XDMAC Channel 22 Software Request Status Bit
22
1
SWRS23
XDMAC Channel 23 Software Request Status Bit
23
1
GSWF
Global Channel Software Flush Request Register
0x40
32
write-only
SWF0
XDMAC Channel 0 Software Flush Request Bit
0
1
SWF1
XDMAC Channel 1 Software Flush Request Bit
1
1
SWF2
XDMAC Channel 2 Software Flush Request Bit
2
1
SWF3
XDMAC Channel 3 Software Flush Request Bit
3
1
SWF4
XDMAC Channel 4 Software Flush Request Bit
4
1
SWF5
XDMAC Channel 5 Software Flush Request Bit
5
1
SWF6
XDMAC Channel 6 Software Flush Request Bit
6
1
SWF7
XDMAC Channel 7 Software Flush Request Bit
7
1
SWF8
XDMAC Channel 8 Software Flush Request Bit
8
1
SWF9
XDMAC Channel 9 Software Flush Request Bit
9
1
SWF10
XDMAC Channel 10 Software Flush Request Bit
10
1
SWF11
XDMAC Channel 11 Software Flush Request Bit
11
1
SWF12
XDMAC Channel 12 Software Flush Request Bit
12
1
SWF13
XDMAC Channel 13 Software Flush Request Bit
13
1
SWF14
XDMAC Channel 14 Software Flush Request Bit
14
1
SWF15
XDMAC Channel 15 Software Flush Request Bit
15
1
SWF16
XDMAC Channel 16 Software Flush Request Bit
16
1
SWF17
XDMAC Channel 17 Software Flush Request Bit
17
1
SWF18
XDMAC Channel 18 Software Flush Request Bit
18
1
SWF19
XDMAC Channel 19 Software Flush Request Bit
19
1
SWF20
XDMAC Channel 20 Software Flush Request Bit
20
1
SWF21
XDMAC Channel 21 Software Flush Request Bit
21
1
SWF22
XDMAC Channel 22 Software Flush Request Bit
22
1
SWF23
XDMAC Channel 23 Software Flush Request Bit
23
1
24
64
XDMAC_CHID[%s]
Channel Interrupt Enable Register
0x50
CIE
Channel Interrupt Enable Register
0x00
32
write-only
BIE
End of Block Interrupt Enable Bit
0
1
LIE
End of Linked List Interrupt Enable Bit
1
1
DIE
End of Disable Interrupt Enable Bit
2
1
FIE
End of Flush Interrupt Enable Bit
3
1
RBIE
Read Bus Error Interrupt Enable Bit
4
1
WBIE
Write Bus Error Interrupt Enable Bit
5
1
ROIE
Request Overflow Error Interrupt Enable Bit
6
1
CID
Channel Interrupt Disable Register
0x04
32
write-only
BID
End of Block Interrupt Disable Bit
0
1
LID
End of Linked List Interrupt Disable Bit
1
1
DID
End of Disable Interrupt Disable Bit
2
1
FID
End of Flush Interrupt Disable Bit
3
1
RBEID
Read Bus Error Interrupt Disable Bit
4
1
WBEID
Write Bus Error Interrupt Disable Bit
5
1
ROID
Request Overflow Error Interrupt Disable Bit
6
1
CIM
Channel Interrupt Mask Register
0x08
32
read-only
BIM
End of Block Interrupt Mask Bit
0
1
LIM
End of Linked List Interrupt Mask Bit
1
1
DIM
End of Disable Interrupt Mask Bit
2
1
FIM
End of Flush Interrupt Mask Bit
3
1
RBEIM
Read Bus Error Interrupt Mask Bit
4
1
WBEIM
Write Bus Error Interrupt Mask Bit
5
1
ROIM
Request Overflow Error Interrupt Mask Bit
6
1
CIS
Channel Interrupt Status Register
0x0C
32
read-only
BIS
End of Block Interrupt Status Bit
0
1
LIS
End of Linked List Interrupt Status Bit
1
1
DIS
End of Disable Interrupt Status Bit
2
1
FIS
End of Flush Interrupt Status Bit
3
1
RBEIS
Read Bus Error Interrupt Status Bit
4
1
WBEIS
Write Bus Error Interrupt Status Bit
5
1
ROIS
Request Overflow Error Interrupt Status Bit
6
1
CSA
Channel Source Address Register
0x10
32
SA
Channel x Source Address
0
32
CDA
Channel Destination Address Register
0x14
32
DA
Channel x Destination Address
0
32
CNDA
Channel Next Descriptor Address Register
0x18
32
NDAIF
Channel x Next Descriptor Interface
0
1
NDA
Channel x Next Descriptor Address
2
30
CNDC
Channel Next Descriptor Control Register
0x1C
32
NDE
Channel x Next Descriptor Enable
0
1
NDESelect
DSCR_FETCH_DIS
Descriptor fetch is disabled.
0
DSCR_FETCH_EN
Descriptor fetch is enabled.
1
NDSUP
Channel x Next Descriptor Source Update
1
1
NDSUPSelect
SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
0
SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
1
NDDUP
Channel x Next Descriptor Destination Update
2
1
NDDUPSelect
DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
0
DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
1
NDVIEW
Channel x Next Descriptor View
3
2
NDVIEWSelect
NDV0
Next Descriptor View 0
0x0
NDV1
Next Descriptor View 1
0x1
NDV2
Next Descriptor View 2
0x2
NDV3
Next Descriptor View 3
0x3
CUBC
Channel Microblock Control Register
0x20
32
UBLEN
Channel x Microblock Length
0
24
CBC
Channel Block Control Register
0x24
32
BLEN
Channel x Block Length
0
12
CC
Channel Configuration Register
0x28
32
TYPE
Channel x Transfer Type
0
1
TYPESelect
MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
0
PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
1
MBSIZE
Channel x Memory Burst Size
1
2
MBSIZESelect
SINGLE
The memory burst size is set to one.
0x0
FOUR
The memory burst size is set to four.
0x1
EIGHT
The memory burst size is set to eight.
0x2
SIXTEEN
The memory burst size is set to sixteen.
0x3
DSYNC
Channel x Synchronization
4
1
DSYNCSelect
PER2MEM
Peripheral-to-memory transfer.
0
MEM2PER
Memory-to-peripheral transfer.
1
SWREQ
Channel x Software Request Trigger
6
1
SWREQSelect
HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
0
SWR_CONNECTED
Software request is connected to the peripheral request line.
1
MEMSET
Channel x Fill Block of memory
7
1
MEMSETSelect
NORMAL_MODE
Memset is not activated.
0
HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
1
CSIZE
Channel x Chunk Size
8
3
CSIZESelect
CHK_1
1 data transferred
0x0
CHK_2
2 data transferred
0x1
CHK_4
4 data transferred
0x2
CHK_8
8 data transferred
0x3
CHK_16
16 data transferred
0x4
DWIDTH
Channel x Data Width
11
2
DWIDTHSelect
BYTE
The data size is set to 8 bits
0x0
HALFWORD
The data size is set to 16 bits
0x1
WORD
The data size is set to 32 bits
0x2
SIF
Channel x Source Interface Identifier
13
1
SIFSelect
AHB_IF0
The data is read through the system bus interface 0.
0
AHB_IF1
The data is read through the system bus interface 1.
1
DIF
Channel x Destination Interface Identifier
14
1
DIFSelect
AHB_IF0
The data is written through the system bus interface 0.
0
AHB_IF1
The data is written though the system bus interface 1.
1
SAM
Channel x Source Addressing Mode
16
2
SAMSelect
FIXED_AM
The address remains unchanged.
0x0
INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x1
UBS_AM
The microblock stride is added at the microblock boundary.
0x2
UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
0x3
DAM
Channel x Destination Addressing Mode
18
2
DAMSelect
FIXED_AM
The address remains unchanged.
0x0
INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x1
UBS_AM
The microblock stride is added at the microblock boundary.
0x2
UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
0x3
INITD
Channel Initialization Terminated (this bit is read-only)
21
1
INITDSelect
IN_PROGRESS
Channel initialization is in progress.
0
TERMINATED
Channel initialization is completed.
1
RDIP
Read in Progress (this bit is read-only)
22
1
RDIPSelect
DONE
No active read transaction on the bus.
0
IN_PROGRESS
A read transaction is in progress.
1
WRIP
Write in Progress (this bit is read-only)
23
1
WRIPSelect
DONE
No active write transaction on the bus.
0
IN_PROGRESS
A write transaction is in progress.
1
PERID
Channel x Peripheral Hardware Request Line Identifier
24
7
PERIDSelect
HSMCI
HSMCI
0
SPI0_TX
SPI0_TX
1
SPI0_RX
SPI0_RX
2
QSPI_TX
QSPI_TX
5
QSPI_RX
QSPI_RX
6
USART0_TX
USART0_TX
7
USART0_RX
USART0_RX
8
USART1_TX
USART1_TX
9
USART1_RX
USART1_RX
10
USART2_TX
USART2_TX
11
USART2_RX
USART2_RX
12
PWM0
PWM0
13
TWIHS0_TX
TWIHS0_TX
14
TWIHS0_RX
TWIHS0_RX
15
TWIHS1_TX
TWIHS1_TX
16
TWIHS1_RX
TWIHS1_RX
17
TWIHS2_TX
TWIHS2_TX
18
TWIHS2_RX
TWIHS2_RX
19
UART0_TX
UART0_TX
20
UART0_RX
UART0_RX
21
UART1_TX
UART1_TX
22
UART1_RX
UART1_RX
23
UART2_TX
UART2_TX
24
UART2_RX
UART2_RX
25
UART3_TX
UART3_TX
26
UART3_RX
UART3_RX
27
UART4_TX
UART4_TX
28
UART4_RX
UART4_RX
29
DACC0
DACC0
30
DACC1
DACC1
31
SSC_TX
SSC_TX
32
SSC_RX
SSC_RX
33
PIOA
PIOA
34
AFEC0
AFEC0
35
AFEC1
AFEC1
36
AES_TX
AES_TX
37
AES_RX
AES_RX
38
PWM1
PWM1
39
TC0
TC0
40
TC3
TC3
41
TC6
TC6
42
TC9
TC9
43
I2SC0_TX_LEFT
I2SC0_TX_LEFT
44
I2SC0_RX_LEFT
I2SC0_RX_LEFT
45
I2SC0_TX_RIGHT
I2SC0_TX_RIGHT
48
I2SC0_RX_RIGHT
I2SC0_RX_RIGHT
49
CDS_MSP
Channel Data Stride Memory Set Pattern
0x2C
32
SDS_MSP
Channel x Source Data stride or Memory Set Pattern
0
16
DDS_MSP
Channel x Destination Data Stride or Memory Set Pattern
16
16
CSUS
Channel Source Microblock Stride
0x30
32
SUBS
Channel x Source Microblock Stride
0
24
CDUS
Channel Destination Microblock Stride
0x34
32
DUBS
Channel x Destination Microblock Stride
0
24
LOCKBIT
11
0
0
0x4
registers
WORD0
Lock Bits Word 0
0x0
32
LOCK_REGION_0
Lock Region 0
0
1
LOCK_REGION_1
Lock Region 1
1
1
LOCK_REGION_2
Lock Region 2
2
1
LOCK_REGION_3
Lock Region 3
3
1
LOCK_REGION_4
Lock Region 4
4
1
LOCK_REGION_5
Lock Region 5
5
1
LOCK_REGION_6
Lock Region 6
6
1
LOCK_REGION_7
Lock Region 7
7
1
LOCK_REGION_8
Lock Region 8
8
1
LOCK_REGION_9
Lock Region 9
9
1
LOCK_REGION_10
Lock Region 10
10
1
LOCK_REGION_11
Lock Region 11
11
1
LOCK_REGION_12
Lock Region 12
12
1
LOCK_REGION_13
Lock Region 13
13
1
LOCK_REGION_14
Lock Region 14
14
1
LOCK_REGION_15
Lock Region 15
15
1
LOCK_REGION_16
Lock Region 16
16
1
LOCK_REGION_17
Lock Region 17
17
1
LOCK_REGION_18
Lock Region 18
18
1
LOCK_REGION_19
Lock Region 19
19
1
LOCK_REGION_20
Lock Region 20
20
1
LOCK_REGION_21
Lock Region 21
21
1
LOCK_REGION_22
Lock Region 22
22
1
LOCK_REGION_23
Lock Region 23
23
1
LOCK_REGION_24
Lock Region 24
24
1
LOCK_REGION_25
Lock Region 25
25
1
LOCK_REGION_26
Lock Region 26
26
1
LOCK_REGION_27
Lock Region 27
27
1
LOCK_REGION_28
Lock Region 28
28
1
LOCK_REGION_29
Lock Region 29
29
1
LOCK_REGION_30
Lock Region 30
30
1
LOCK_REGION_31
Lock Region 31
31
1
SCnSCB
System control not in SCB
0xE000E000
0
0xC
registers
ICTR
Interrupt Controller Type Register
0x00000004
32
read-only
0
INTLINESNUM
Total number of interrupt lines supported by an implementation, defined in groups of 32
0
4
ACTLR
Auxiliary Control Register
0x00000008
32
0
DISFOLD
Disables folding of IT instructions
2
1
FPEXCODIS
Disables FPU exception outputs
10
1
DISRAMODE
Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions
11
1
DISITMATBFLUSH
Disables ITM and DWT ATB flush
12
1
DISBTACREAD
13
1
DISBTACALLOC
14
1
DISCRITAXIRUR
15
1
DISDI
16
5
DISISSCH1
21
5
DISDYNADD
Disables dynamic allocation of ADD and SUB instructions
26
1
DISCRITAXIRUW
Disable critical AXI read-under-write
27
1
DISFPUISSOPT
Disables dynamic allocation of ADD and SUB instructions
28
1
SCB
System Control Block
0xE000ED00
0
0x24C
registers
CCW
64
CCF
65
CPUID
CPUID Base Register
0x00000000
32
read-only
0x411FC271
REVISION
Indicates patch release: 0x0 = Patch 0
0
4
PARTNO
Indicates part number
4
12
ARCHITECTURE
Indicates architecture. Reads as 0xF
16
4
VARIANT
Indicates processor revision: 0x2 = Revision 2
20
4
IMPLEMENTER
Implementer code
24
8
ICSR
Interrupt Control and State Register
0x00000004
32
0
VECTACTIVE
Active exception number
0
9
RETTOBASE
Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR
11
1
RETTOBASESelect
VALUE_0
there are preempted active exceptions to execute
0
VALUE_1
there are no active exceptions, or the currently-executing exception is the only active exception
1
VECTPENDING
Exception number of the highest priority pending enabled exception
12
6
ISRPENDING
Is external interrupt, generated by the NVIC, pending
22
1
ISRPREEMPT
Indicates whether a pending exception will be serviced on exit from debug halt state
23
1
ISRPREEMPTSelect
VALUE_0
Will not service
0
VALUE_1
Will service a pending exception
1
PENDSTCLR
Removes the pending status of the SysTick exception
25
1
PENDSTCLRSelect
VALUE_0
no effect
0
VALUE_1
removes the pending state from the SysTick exception
1
PENDSTSET
Sets the SysTick exception as pending, or reads the current state of the exception
26
1
PENDSTSETSelect
VALUE_0
write: no effect; read: SysTick exception is not pending
0
VALUE_1
write: changes SysTick exception state to pending; read: SysTick exception is pending
1
PENDSVCLR
Removes the pending status of the PendSV exception
27
1
PENDSVCLRSelect
VALUE_0
no effect
0
VALUE_1
removes the pending state from the PendSV exception
1
PENDSVSET
Sets the PendSV exception as pending, or reads the current state of the exception
28
1
PENDSVSETSelect
VALUE_0
write: no effect; read: PendSV exception is not pending
0
VALUE_1
write: changes PendSV exception state to pending; read: PendSV exception is pending
1
NMIPENDSET
Makes the NMI exception active, or reads the state of the exception
31
1
NMIPENDSETSelect
VALUE_0
write: no effect; read: NMI exception is not pending
0
VALUE_1
write: changes NMI exception state to pending; read: NMI exception is pending
1
VTOR
Vector Table Offset Register
0x00000008
32
0
TBLOFF
Bits[31:7] of the vector table address
7
25
AIRCR
Application Interrupt and Reset Control Register
0x0000000c
32
0
VECTRESET
Writing 1 to this bit causes a local system reset
0
1
VECTCLRACTIVE
Clears all active state information for fixed and configurable exceptions
1
1
SYSRESETREQ
System Reset Request
2
1
SYSRESETREQSelect
VALUE_0
no system reset request
0
VALUE_1
asserts a signal to the outer system that requests a reset
1
PRIGROUP
Interrupt priority grouping field. This field determines the split of group priority from subpriority.
8
3
ENDIANNESS
Memory system endianness
15
1
ENDIANNESSSelect
VALUE_0
Little-endian
0
VALUE_1
Big-endian
1
VECTKEY
Vector key
16
16
SCR
System Control Register
0x00000010
32
0
SLEEPONEXIT
Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state
1
1
SLEEPONEXITSelect
VALUE_0
o not sleep when returning to Thread mode
0
VALUE_1
enter sleep, or deep sleep, on return from an ISR
1
SLEEPDEEP
Provides a qualifying hint indicating that waking from sleep might take longer
2
1
SLEEPDEEPSelect
VALUE_0
sleep
0
VALUE_1
deep sleep
1
SEVONPEND
Determines whether an interrupt transition from inactive state to pending state is a wakeup event
4
1
SEVONPENDSelect
VALUE_0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
0
VALUE_1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
1
CCR
Configuration and Control Register
0x00000014
32
0
NONBASETHRDENA
Controls whether the processor can enter Thread mode with exceptions active
0
1
NONBASETHRDENASelect
VALUE_0
processor can enter Thread mode only when no exception is active
0
VALUE_1
processor can enter Thread mode from any level under the control of an EXC_RETURN value
1
USERSETMPEND
Enables unprivileged software access to the STIR
1
1
USERSETMPENDSelect
VALUE_0
disable
0
VALUE_1
enable
1
UNALIGN_TRP
Enables unaligned access traps
3
1
UNALIGN_TRPSelect
VALUE_0
do not trap unaligned halfword and word accesses
0
VALUE_1
trap unaligned halfword and word accesses
1
DIV_0_TRP
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
4
1
DIV_0_TRPSelect
VALUE_0
do not trap divide by 0
0
VALUE_1
trap divide by 0
1
BFHFNMIGN
Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
8
1
BFHFNMIGNSelect
VALUE_0
data bus faults caused by load and store instructions cause a lock-up
0
VALUE_1
handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
1
STKALIGN
Indicates stack alignment on exception entry
9
1
STKALIGNSelect
VALUE_0
4-byte aligned
0
VALUE_1
8-byte aligned
1
DC
Cache enable bit
16
1
IC
Instruction cache enable bi
17
1
BP
Branch prediction enable bi
18
1
SHPR1
System Handler Priority Register 1
0x00000018
32
0
PRI_4
Priority of system handler 4, MemManage
0
8
PRI_5
Priority of system handler 5, BusFault
8
8
PRI_6
Priority of system handler 6, UsageFault
16
8
SHPR2
System Handler Priority Register 2
0x0000001c
32
0
PRI_11
Priority of system handler 11, SVCall
24
8
SHPR3
System Handler Priority Register 3
0x00000020
32
0
PRI_12
Priority of system handler 12, SysTick
0
8
PRI_14
Priority of system handler 14, PendSV
16
8
PRI_15
Priority of system handler 15, SysTick exception
24
8
SHCSR
System Handler Control and State Register
0x00000024
32
0
MEMFAULTACT
0
1
MEMFAULTACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
BUSFAULTACT
1
1
BUSFAULTACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
USGFAULTACT
3
1
USGFAULTACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
SVCALLACT
7
1
SVCALLACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
MONITORACT
8
1
MONITORACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
PENDSVACT
10
1
PENDSVACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
SYSTICKACT
11
1
SYSTICKACTSelect
VALUE_0
exception is not active
0
VALUE_1
exception is active
1
USGFAULTPENDED
12
1
USGFAULTPENDEDSelect
VALUE_0
exception is not pending
0
VALUE_1
exception is pending
1
MEMFAULTPENDED
13
1
MEMFAULTPENDEDSelect
VALUE_0
exception is not pending
0
VALUE_1
exception is pending
1
BUSFAULTPENDED
14
1
BUSFAULTPENDEDSelect
VALUE_0
exception is not pending
0
VALUE_1
exception is pending
1
SVCALLPENDED
15
1
SVCALLPENDEDSelect
VALUE_0
exception is not pending
0
VALUE_1
exception is pending
1
MEMFAULTENA
16
1
MEMFAULTENASelect
VALUE_0
disable the exception
0
VALUE_1
enable the exception
1
BUSFAULTENA
17
1
BUSFAULTENASelect
VALUE_0
disable the exception
0
VALUE_1
enable the exception
1
USGFAULTENA
18
1
USGFAULTENASelect
VALUE_0
disable the exception
0
VALUE_1
enable the exception
1
CFSR
Configurable Fault Status Registers
0x00000028
32
0
IACCVIOL
0
1
IACCVIOLSelect
VALUE_0
no instruction access violation fault
0
VALUE_1
the processor attempted an instruction fetch from a location that does not permit execution
1
DACCVIOL
1
1
DACCVIOLSelect
VALUE_0
no data access violation fault
0
VALUE_1
the processor attempted a load or store at a location that does not permit the operation
1
MUNSTKERR
3
1
MUNSTKERRSelect
VALUE_0
no unstacking fault
0
VALUE_1
unstack for an exception return has caused one or more access violations
1
MSTKERR
4
1
MSTKERRSelect
VALUE_0
no stacking fault
0
VALUE_1
stacking for an exception entry has caused one or more access violations
1
MLSPERR
5
1
MLSPERRSelect
VALUE_0
No MemManage fault occurred during floating-point lazy state preservation
0
VALUE_1
A MemManage fault occurred during floating-point lazy state preservation
1
MMARVALID
7
1
MMARVALIDSelect
VALUE_0
value in MMAR is not a valid fault address
0
VALUE_1
MMAR holds a valid fault address
1
IBUSERR
8
1
IBUSERRSelect
VALUE_0
no instruction bus error
0
VALUE_1
instruction bus error
1
PRECISERR
9
1
PRECISERRSelect
VALUE_0
no precise data bus error
0
VALUE_1
a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
1
IMPRECISERR
10
1
IMPRECISERRSelect
VALUE_0
no imprecise data bus error
0
VALUE_1
a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
1
UNSTKERR
11
1
UNSTKERRSelect
VALUE_0
no unstacking fault
0
VALUE_1
unstack for an exception return has caused one or more BusFaults
1
STKERR
12
1
STKERRSelect
VALUE_0
no stacking fault
0
VALUE_1
stacking for an exception entry has caused one or more BusFaults
1
LSPERR
13
1
LSPERRSelect
VALUE_0
No bus fault occurred during floating-point lazy state preservation
0
VALUE_1
A bus fault occurred during floating-point lazy state preservation
1
BFARVALID
15
1
BFARVALIDSelect
VALUE_0
value in BFAR is not a valid fault address
0
VALUE_1
BFAR holds a valid fault address
1
UNDEFINSTR
16
1
UNDEFINSTRSelect
VALUE_0
no undefined instruction UsageFault
0
VALUE_1
the processor has attempted to execute an undefined instruction
1
INVSTATE
17
1
INVSTATESelect
VALUE_0
no invalid state UsageFault
0
VALUE_1
the processor has attempted to execute an instruction that makes illegal use of the EPSR
1
INVPC
18
1
INVPCSelect
VALUE_0
no invalid PC load UsageFault
0
VALUE_1
the processor has attempted an illegal load of EXC_RETURN to the PC
1
NOCP
19
1
NOCPSelect
VALUE_0
no UsageFault caused by attempting to access a coprocessor
0
VALUE_1
the processor has attempted to access a coprocessor
1
UNALIGNED
24
1
UNALIGNEDSelect
VALUE_0
no unaligned access fault, or unaligned access trapping not enabled
0
VALUE_1
the processor has made an unaligned memory access
1
DIVBYZERO
25
1
DIVBYZEROSelect
VALUE_0
no divide by zero fault, or divide by zero trapping not enabled
0
VALUE_1
the processor has executed an SDIV or UDIV instruction with a divisor of 0
1
HFSR
HardFault Status register
0x0000002c
32
0
VECTTBL
Indicates when a fault has occurred because of a vector table read error on exception processing
1
1
VECTTBLSelect
VALUE_0
no BusFault on vector table read
0
VALUE_1
BusFault on vector table read
1
FORCED
Indicates that a fault with configurable priority has been escalated to a HardFault exception
30
1
FORCEDSelect
VALUE_0
no forced HardFault
0
VALUE_1
forced HardFault
1
DEBUGEVT
Indicates when a Debug event has occurred
31
1
DFSR
Debug Fault Status Register
0x00000030
32
0
HALTED
debug event generated by
0
1
HALTEDSelect
VALUE_0
No active halt request debug event
0
VALUE_1
Halt request debug event active
1
BKPT
debug event generated by BKPT instruction execution or a breakpoint match in FPB
1
1
BKPTSelect
VALUE_0
No current breakpoint debug event
0
VALUE_1
At least one current breakpoint debug event
1
DWTTRAP
debug event generated by the DWT
2
1
DWTTRAPSelect
VALUE_0
No current debug events generated by the DWT
0
VALUE_1
At least one current debug event generated by the DWT
1
VCATCH
triggering of a Vector catch
3
1
VCATCHSelect
VALUE_0
No Vector catch triggered
0
VALUE_1
Vector catch triggered
1
EXTERNAL
debug event generated because of the assertion of an external debug request
4
1
EXTERNALSelect
VALUE_0
No EDBGRQ debug event
0
VALUE_1
EDBGRQ debug event
1
MMFAR
MemManage Fault Address Register
0x00000034
32
0
ADDRESS
Data address for an MPU fault
0
32
BFAR
BusFault Address Register
0x00000038
32
0
ADDRESS
Data address for a precise bus fault
0
32
AFSR
Auxiliary Fault Status Register
0x0000003C
32
0
CLIDR
Cache Level ID Register
0x00000078
32
read-only
0x09000003
LoC
Level of Coherency
24
3
LoCSelect
LEVEL_1
if neither instruction nor data cache is implemented
0
LEVEL_2
if either cache is implemented
1
LoU
Level of Unification
27
3
LoUSelect
LEVEL_1
if neither instruction nor data cache is implemented
0
LEVEL_2
if either cache is implemented
1
CTR
Cache Type Register
0x0000007c
32
read-only
0x8303C003
IMINLINE
Smallest cache line of all the instruction caches under the control of the processor
0
4
DMINLINE
Smallest cache line of all the data and unified caches under the core control
16
4
ERG
Exclusives Reservation Granule
20
4
CWG
Cache Writeback Granule
24
4
FORMAT
Register format
29
3
CCSIDR
Cache Size ID Register
0x00000080
32
read-only
0
LineSize
number of words in each cache line
0
3
Associativity
number of ways
3
9
NumSets
number of sets
12
16
WA
Write allocation support
28
1
RA
Read allocation support
29
1
WB
Write-Back support
30
1
WT
Write-Through support
31
1
CSSELR
Cache Size Selection Register
0x00000084
32
0
IND
selection of instruction or data cache
0
1
INDSelect
DATA
Data cache
0
INSTRUCTION
Instruction cache
1
LEVEL
cache level selected
1
3
CPACR
Coprocessor Access Control Register
0x00000088
32
0
CP10
Access privileges for coprocessor 10.
20
2
CP11
Access privileges for coprocessor 11.
22
2
ICIALLU
I-cache invalidate all to PoU
0x00000150
32
write-only
ICIMVAU
I-cache invalidate by MVA to PoU
0x00000158
32
write-only
DCIMVAC
D-cache invalidate by MVA to PoC
0x0000015c
32
write-only
DCISW
D-cache invalidate by set-way
0x00000160
32
write-only
DCCMVAU
D-cache clean by MVA to PoU
0x00000164
32
write-only
DCCMVAC
D-cache clean by MVA to PoC
0x000000168
32
write-only
DCCSW
D-cache clean by set-way
0x0000016c
32
write-only
DCCIMVAC
D-cache clean and invalidate by MVA to PoC
0x00000170
32
write-only
DCCISW
D-cache clean and invalidate by set-way
0x00000174
32
write-only
BPIALL
Branch predictor invalidate all
0x00000178
32
write-only
STIR
Software Trigger Interrupt Register
0x00000200
32
write-only
0
INTID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
0
9
MVFR0
Media and VFP Feature Register 0
0x00000240
32
read-only
0x10110021
MVFR1
Media and VFP Feature Register 1
0x00000244
32
read-only
0x10110021
MVFR2
Media and VFP Feature Register 2
0x00000248
32
read-only
0x10110021
SysTick
System timer
0xE000E010
0
0x10
registers
CSR
Control and Status Register
0x00000000
32
0x4
ENABLE
Enables the counter
0
1
ENABLESelect
VALUE_0
counter disabled
0
VALUE_1
counter enabled
1
TICKINT
Enables SysTick exception request
1
1
TICKINTSelect
VALUE_0
counting down to 0 does not assert the SysTick exception request
0
VALUE_1
counting down to 0 asserts the SysTick exception request
1
CLKSOURCE
Indicates the clock source
2
1
CLKSOURCESelect
VALUE_0
external clock
0
VALUE_1
processor clock
1
COUNTFLAG
Returns 1 if timer counted to 0 since last time this was read
16
1
RVR
Reload Value Register
0x00000004
32
0
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
CVR
Current Value Register
0x00000008
32
0
CURRENT
Current value at the time the register is accessed
0
24
CALIB
Calibration Value Register
0x0000000c
32
read-only
0
TENMS
Reload value to use for 10ms timing
0
24
SKEW
Indicates whether the TENMS value is exact
30
1
SKEWSelect
VALUE_0
10ms calibration value is exact
0
VALUE_1
10ms calibration value is inexact, because of the clock frequency
1
NOREF
Indicates whether the device provides a reference clock to the processor
31
1
NOREFSelect
VALUE_0
The reference clock is provided
0
VALUE_1
The reference clock is not provided
1
NVIC
Nested Vectored Interrupt Controller
0xE000E100
0
0xE04
registers
8
4
ISER[%s]
Interrupt Set Enable Register n
0x00000000
32
0
SETENA
Interrupt set enable bits
0
32
8
4
ICER[%s]
Interrupt Clear Enable Register n
0x00000080
32
0
CLRENA
Interrupt clear-enable bits
0
32
8
4
ISPR[%s]
Interrupt Set Pending Register n
0x00000100
32
0
SETPEND
Interrupt set-pending bits
0
32
8
4
ICPR[%s]
Interrupt Clear Pending Register n
0x00000180
32
0
CLRPEND
Interrupt clear-pending bits
0
32
8
4
IABR[%s]
Interrupt Active bit Register n
0x00000200
32
0
ACTIVE
Interrupt active flags
0
32
240
1
IP[%s]
Interrupt Priority Register (8Bit wide) n
0x00000300
8
0
PRI0
Priority of interrupt 0
0
8
STIR
Software Trigger Interrupt Register
0x00000e00
32
write-only
0
INTID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
0
9
MPU
Memory Protection Unit
0xE000ED90
0
0x2C
registers
TYPE
MPU Type Register
0x00000000
32
0x00001000
SEPARATE
Indicates support for unified or separate instruction and date memory maps.
0
1
DREGION
Indicates the number of supported MPU instruction regions.
8
8
IREGION
Indicates the number of supported MPU data regions.
16
8
CTRL
MPU Control Register
0x00000004
32
0x00000000
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
1
1
PRIVDEFENA
Enables privileged software access to the default memory map.
2
1
RNR
MPU Region Number Register
0x00000008
32
REGION
Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
0
8
RBAR
MPU Region Base Address Register
0x0000000C
32
REGION
MPU region field.
0
4
VALID
MPU Region Number valid bit.
4
1
ADDR
Region base address field.
5
27
RASR
MPU Region Attribute and Size Register
0x00000010
32
ENABLE
Region enable bit.
0
1
SIZE
Specifies the size of the MPU protection region.
1
5
SRD
Subregion disable bits.
8
8
B
MPU access permission attributes.
16
1
C
MPU access permission attributes.
17
1
S
Shareable bit.
18
1
TEX
MPU access permission attributes.
19
3
AP
Access permission field.
24
3
XN
Instruction access disable bit.
28
1
RBAR_A1
MPU Alias 1 Region Base Address Register
0x00000014
32
RASR_A1
MPU Alias 1 Region Attribute and Size Register
0x00000018
32
RBAR_A2
MPU Alias 2 Region Base Address Register
0x0000001c
32
RASR_A2
MPU Alias 2 Region Attribute and Size Register
0x00000020
32
RBAR_A3
MPU Alias 3 Region Base Address Register
0x00000024
32
RASR_A3
MPU Alias 3 Region Attribute and Size Register
0x00000028
32
FPU
Floating Point Unit
0xE000EF30
0
0x1C
registers
FPU
61
IXC
68
FPCCR
Floating-point Context Control Register
0x00000004
32
0xC0000000
LSPACT
Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred.
0
1
USER
Privilege level was user when the floating-point stack frame was allocated.
1
1
THREAD
Mode was Thread Mode when the floating-point stack frame was allocated.
3
1
HFRDY
Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
4
1
MMRDY
MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
5
1
BFRDY
BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
6
1
MONRDY
DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.
8
1
LSPEN
Enable automatic lazy state preservation for floating-point context.
30
1
ASPEN
Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit.
31
1
FPCAR
Floating-point Context Address Register
0x00000008
32
ADDRESS
The location of the unpopulated floating-point register space allocated on an exception stack frame.
3
29
FPDSCR
Floating-point Default Status Control Register
0x0000000C
32
0x00000000
RMode
Default value for FPSCR.RMode.
22
2
FZ
Default value for FPSCR.FZ.
24
1
DN
Default value for FPSCR.DN.
25
1
AHP
Default value for FPSCR.AHP.
26
1
MVFR0
Media and VFP Feature Register 0
0x00000010
32
read-only
0x10110021
A_SIMD_registers
Indicates the size of the FP register bank
0
4
Single_precision
Indicates the hardware support for FP single-precision operations
4
4
Double_precision
Indicates the hardware support for FP double-precision operations
8
4
FP_excep_trapping
Indicates whether the FP hardware implementation supports exception trapping
12
4
Divide
Indicates the hardware support for FP divide operations
16
4
Square_root
Indicates the hardware support for FP square root operations
20
4
Short_vectors
Indicates the hardware support for FP short vectors
24
4
FP_rounding_modes
Indicates the rounding modes supported by the FP floating-point hardware
28
4
MVFR1
Media and VFP Feature Register 1
0x00000014
32
read-only
0x11000011
FtZ_mode
Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation
0
4
D_NaN_mode
Indicates whether the FP hardware implementation supports only the Default NaN mode
4
4
FP_HPFP
Floating Point Half-Precision and double-precision
24
4
FP_fused_MAC
Indicates whether the FP supports fused multiply accumulate operations
28
4
MVFR2
Media and VFP Feature Register 2
0x00000018
32
read-only
0x00000040
VFP_Misc
Indicates the hardware support for FP miscellaneous features
4
4
ITM
Instrumentation Trace Macrocell
0xE0000000
0
0xE84
registers
32
4
PORT_BYTE_MODE[%s]
ITM Stimulus Port Registers
0x0
32
write-only
PORT
0
8
32
4
PORT_HWORD_MODE[%s]
ITM Stimulus Port Registers
PORT_BYTE_MODE[%s]
0x0
32
write-only
PORT
0
16
32
4
PORT_WORD_MODE[%s]
ITM Stimulus Port Registers
PORT_BYTE_MODE[%s]
0x0
32
write-only
PORT
0
32
TER
ITM Trace Enable Register
0xE00
32
TPR
ITM Trace Privilege Register
0xE40
32
PRIVMASK
0
4
TCR
ITM Trace Control Register
0xE80
32
ITMENA
0
1
TSENA
1
1
SYNCENA
2
1
DWTENA
3
1
SWOENA
4
1
STALLENA
5
1
TSPrescale
8
2
GTSFREQ
10
2
TraceBusID
16
7
BUSY
23
1
DWT
Data Watchpoint and Trace Register
0xE0001000
0
0x1000
registers
CTRL
Control Register
0x0
32
CYCCNTENA
0
1
POSTPRESET
1
4
POSTINIT
5
4
CYCTAP
9
1
SYNCTAP
10
2
PCSAMPLENA
12
1
EXCTRCENA
16
1
CPIEVTENA
17
1
EXCEVTENA
18
1
SLEEPEVTENA
19
1
LSUEVTENA
20
1
FOLDEVTENA
21
1
CYCEVTENA
22
1
NOPRFCNT
24
1
NOCYCCNT
25
1
NOEXTTRIG
26
1
NOTRCPKT
27
1
NUMCOMP
28
4
CYCCNT
Cycle Count Register
0x4
32
0x00000000
CPICNT
CPI Count Register
0x8
32
CPICNT
0
8
EXCCNT
Exception Overhead Count Register
0xC
32
EXCCNT
0
8
SLEEPCNT
Sleep Count Register
0x10
32
SLEEPCNT
0
8
LSUCNT
LSU Count Register
0x14
32
LSUCNT
0
8
FOLDCNT
Folded-instruction Count Register
0x18
32
FOLDCNT
0
8
PCSR
Program Counter Sample Register
0x1C
32
read-only
COMP0
Comparator Register 0
0x20
32
MASK0
Mask Register 0
0x24
32
MASK
0
5
FUNCTION0
Function Register 0
0x28
32
0x00000000
FUNCTION
0
4
EMITRANGE
5
1
CYCMATCH
7
1
DATAVMATCH
8
1
LNK1ENA
9
1
DATAVSIZE
10
2
DATAVADDR0
12
4
DATAVADDR1
16
4
MATCHED
24
1
COMP1
Comparator Register 1
0x30
32
MASK1
Mask Register 1
0x34
32
MASK
0
5
FUNCTION1
Function Register 1
0x38
32
0x00000000
FUNCTION
0
4
EMITRANGE
5
1
CYCMATCH
7
1
DATAVMATCH
8
1
LNK1ENA
9
1
DATAVSIZE
10
2
DATAVADDR0
12
4
DATAVADDR1
16
4
MATCHED
24
1
COMP2
Comparator Register 2
0x40
32
MASK2
Mask Register 2
0x44
32
MASK
0
5
FUNCTION2
Function Register 2
0x48
32
0x00000000
FUNCTION
0
4
EMITRANGE
5
1
CYCMATCH
7
1
DATAVMATCH
8
1
LNK1ENA
9
1
DATAVSIZE
10
2
DATAVADDR0
12
4
DATAVADDR1
16
4
MATCHED
24
1
COMP3
Comparator Register 3
0x50
32
MASK3
Mask Register 3
0x54
32
MASK
0
5
FUNCTION3
Function Register 3
0x58
32
FUNCTION
0
4
EMITRANGE
5
1
CYCMATCH
7
1
DATAVMATCH
8
1
LNK1ENA
9
1
DATAVSIZE
10
2
DATAVADDR0
12
4
DATAVADDR1
16
4
MATCHED
24
1
LAR
DWT Software Lock Access Register
0xFB0
32
write-only
KEY
Lock access control
0
32
KEYSelect
UNLOCK
Unlock key value
0xC5ACCE55
LSR
DWT Software Lock Status Register
0xFB4
32
read-only
SLI
Software Lock implemented
0
1
SLK
Software Lock status
1
1
nTT
Not thirty-two bit
2
1
PID4
DWT Peripheral Identification Register 4
0xFD0
32
read-only
0x00000004
DES_2
JEP106 continuation code
0
4
SIZE
4KB count
4
4
PID5
DWT Peripheral Identification Register 5
0xFD4
32
read-only
0x00000000
PID6
DWT Peripheral Identification Register 6
0xFD8
32
read-only
0x00000000
PID7
DWT Peripheral Identification Register 7
0xFDC
32
read-only
0x00000000
PID0
DWT Peripheral Identification Register 0
0xFE0
32
read-only
0x00000002
PART_0
Part number bits[7:0]
0
8
PID1
DWT Peripheral Identification Register 1
0xFE4
32
read-only
0x000000B0
PART_1
Part number bits[11:8]
0
4
DES_0
JEP106 identification code bits [3:0]
4
4
PID2
DWT Peripheral Identification Register 2
0xFE8
32
read-only
0x0000000B
DES_1
JEP106 identification code bits[6:4]
0
3
JEDEC
JEDEC assignee value is used
3
1
REVISION
Component revision
4
4
PID3
DWT Peripheral Identification Register 3
0xFEC
32
read-only
0x00000000
CMOD
Customer Modified
0
4
REVAND
RevAnd
4
4
CID0
DWT Component Identification Register 0
0xFF0
32
read-only
0x0000000D
PRMBL_0
CoreSight component identification preamble
0
8
CID1
DWT Component Identification Register 1
0xFF4
32
read-only
0x000000E0
PRMBL_1
CoreSight component identification preamble
0
4
CLASS
CoreSight component class
4
4
CID2
DWT Component Identification Register 2
0xFF8
32
read-only
0x00000005
PRMBL_2
CoreSight component identification preamble
0
8
CID3
DWT Component Identification Register 3
0xFFC
32
read-only
0x000000B1
PRMBL_3
CoreSight component identification preamble
0
8
FPB
Flash Patch and Breakpoint
0xE0002000
0
0x1000
registers
FP_CTRL
Flash Patch Control Register
0x0
32
0x10000000
ENABLE
Flash Patch global enable
0
1
KEY
FP_CTRL write-enable key
1
1
NUM_CODE
Number of implemented code comparators bits [3:0]
4
4
NUM_LIT
Number of literal comparators
8
4
NUM_CODE_1
Number of implemented code comparators bits [6:4]
12
3
REV
Revision
28
4
FP_REMAP
Flash Patch Remap Register
0x4
32
read-only
0x00000000
REMAP
Remap address
5
24
RMPSPT
Remap supported
29
1
8
4
FP_COMP[%s]
Flash Patch Comparator Register n
0x8
32
0x00000000
BE
Breakpoint enable
0
1
FPADDR
Flash Patch address
2
27
FE
Flash Patch enable
31
1
8
4
FP_COMP_BREAKPOINT_MODE[%s]
Flash Patch Comparator Register n
FP_COMP[%s]
0x8
32
0x00000000
BE
Breakpoint enable
0
1
BPADDR
Breakpoint address
1
31
FP_LAR
FPB Software Lock Access Register
0xFB0
32
write-only
KEY
Lock access control
0
32
KEYSelect
UNLOCK
Unlock key value
0xC5ACCE55
FP_LSR
FPB Software Lock Status Register
0xFB4
32
read-only
SLI
Software Lock implemented
0
1
SLK
Software Lock status
1
1
nTT
Not thirty-two bit
2
1
FP_PID4
FP Peripheral Identification Register 4
0xFD0
32
read-only
0x00000004
DES_2
JEP106 continuation code
0
4
SIZE
4KB count
4
4
FP_PID5
FP Peripheral Identification Register 5
0xFD4
32
read-only
0x00000000
FP_PID6
FP Peripheral Identification Register 6
0xFD8
32
read-only
0x00000000
FP_PID7
FP Peripheral Identification Register 7
0xFDC
32
read-only
0x00000000
FP_PID0
FP Peripheral Identification Register 0
0xFE0
32
read-only
0x00000000
PART_0
Part number bits[7:0]
0
8
FP_PID1
FP Peripheral Identification Register 1
0xFE4
32
read-only
0x000000B0
PART_1
Part number bits[11:8]
0
4
DES_0
JEP106 identification code bits [3:0]
4
4
FP_PID2
FP Peripheral Identification Register 2
0xFE8
32
read-only
0x0000002B
DES_1
JEP106 identification code bits[6:4]
0
3
JEDEC
JEDEC assignee value is used
3
1
REVISION
Component revision
4
4
FP_PID3
FP Peripheral Identification Register 3
0xFEC
32
read-only
0x00000000
CMOD
Customer Modified
0
4
REVAND
RevAnd
4
4
FP_CID0
FP Component Identification Register 0
0xFF0
32
read-only
0x0000000D
PRMBL_0
CoreSight component identification preamble
0
8
FP_CID1
FP Component Identification Register 1
0xFF4
32
read-only
0x000000E0
PRMBL_1
CoreSight component identification preamble
0
4
CLASS
CoreSight component class
4
4
FP_CID2
FP Component Identification Register 2
0xFF8
32
read-only
0x00000005
PRMBL_2
CoreSight component identification preamble
0
8
FP_CID3
FP Component Identification Register 3
0xFFC
32
read-only
0x000000B1
PRMBL_3
CoreSight component identification preamble
0
8
CoreDebug
Core Debug Register
0xE000EDF0
0
0x100
registers
DHCSR
Debug Halting Control and Status Register
0xF0
32
0x00000000
C_DEBUGEN
0
1
C_HALT
1
1
C_STEP
2
1
C_MASKINTS
3
1
C_SNAPSTALL
5
1
S_REGRDY
16
1
S_HALT
17
1
S_SLEEP
18
1
S_LOCKUP
19
1
S_RETIRE_ST
24
1
S_RESET_ST
25
1
DCRSR
Debug Core Register Selector Register
0xF4
32
write-only
REGSEL
0
5
REGWnR
16
1
DCRDR
Debug Core Register Data Register
0xF8
32
DEMCR
Debug Exception and Monitor Control Register
0xFC
32
0x00000000
VC_CORERESET
0
1
VC_MMERR
4
1
VC_NOCPERR
5
1
VC_CHKERR
6
1
VC_STATERR
7
1
VC_BUSERR
8
1
VC_INTERR
9
1
VC_HARDERR
10
1
MON_EN
16
1
MON_PEND
17
1
MON_STEP
18
1
MON_REQ
19
1
TRCENA
24
1
ETM
Embedded Trace Macrocell
0xE0041000
0
0x1000
registers
CR
ETM Main Control Register
0x0
32
0x00000411
ETMPD
ETM Power Down
0
1
PORTSIZE
Port Size bits 2:0
4
3
STALL
Stall Processor
7
1
BROUT
Branch Output
8
1
DBGRQ
Debug Request Control
9
1
PROG
ETM Programming
10
1
PORTSEL
ETM Port Select
11
1
PORTMODE2
Port Mode bit 2
13
1
PORTMODE
Port Mode bits 1:0
16
2
PORTSIZE3
Port Size bit 3
21
1
TSEN
TimeStamp Enable
28
1
CCR
ETM Configuration Code Register
0x4
32
read-only
0x8C802000
TRIGGER
ETM Trigger Event Register
0x8
32
SR
ETM Status Register
0x10
32
SCR
ETM System Configuration Register
0x14
32
read-only
0x00020D09
TEEVR
ETM TraceEnable Event Register
0x20
32
TECR1
ETM TraceEnable Control 1 Register
0x24
32
FFLR
ETM FIFO Full Level Register
0x28
32
CNTRLDVR1
ETM Free-running Counter Reload Value
0x140
32
SYNCFR
ETM Synchronization Frequency Register
0x1E0
32
read-only
0x00000400
IDR
ETM ID Register
0x1E4
32
read-only
0x4114F250
CCER
ETM Configuration Code Extension Register
0x1E8
32
read-only
0x18541800
TESSEICR
ETM TraceEnable Start/Stop EmbeddedICE Control Register
0x1F0
32
TSEVT
ETM TimeStamp Event Register
0x1F8
32
TRACEIDR
ETM CoreSight Trace ID Register
0x200
32
0x00000000
IDR2
ETM ID Register 2
0x208
32
read-only
0x00000000
PDSR
ETM Device Power-Down Status Register
0x314
32
read-only
0x00000001
ITMISCIN
ETM Integration Test Miscellaneous Inputs
0xEE0
32
read-only
ITTRIGOUT
ETM Integration Test Trigger Out
0xEE8
32
write-only
ITATBCTR2
ETM Integration Test ATB Control 2
0xEF0
32
read-only
ITATBCTR0
ETM Integration Test ATB Control 0
0xEF8
32
write-only
ITCTRL
ETM Integration Mode Control Register
0xF00
32
0x00000000
INTEGRATION
0
1
CLAIMSET
ETM Claim Tag Set Register
0xFA0
32
CLAIMCLR
ETM Claim Tag Clear Register
0xFA4
32
LAR
ETM Lock Access Register
0xFB0
32
write-only
LSR
ETM Lock Status Register
0xFB4
32
read-only
Present
0
1
Access
1
1
ByteAcc
2
1
AUTHSTATUS
ETM Authentication Status Register
0xFB8
32
read-only
DEVTYPE
ETM CoreSight Device Type Register
0xFCC
32
read-only
0x00000013
PIDR4
ETM Peripheral Identification Register #4
0xFD0
32
read-only
0x00000004
PIDR5
ETM Peripheral Identification Register #5
0xFD4
32
read-only
0x00000000
PIDR6
ETM Peripheral Identification Register #6
0xFD8
32
read-only
0x00000000
PIDR7
ETM Peripheral Identification Register #7
0xFDC
32
read-only
0x00000000
PIDR0
ETM Peripheral Identification Register #0
0xFE0
32
read-only
0x00000025
PIDR1
ETM Peripheral Identification Register #1
0xFE4
32
read-only
0x000000B9
PIDR2
ETM Peripheral Identification Register #2
0xFE8
32
read-only
0x0000000B
PIDR3
ETM Peripheral Identification Register #3
0xFEC
32
read-only
0x00000000
CIDR0
ETM Component Identification Register #0
0xFF0
32
read-only
0x0000000D
CIDR1
ETM Component Identification Register #1
0xFF4
32
read-only
0x00000090
CIDR2
ETM Component Identification Register #2
0xFF8
32
read-only
0x00000005
CIDR3
ETM Component Identification Register #3
0xFFC
32
read-only
0x000000B1
TPIU
Trace Port Interface Register
0xE0040000
0
0xFD0
registers
SSPSR
Supported Parallel Port Size Register
0x0
32
read-only
CSPSR
Current Parallel Port Size Register
0x4
32
ACPR
Asynchronous Clock Prescaler Register
0x10
32
PRESCALER
0
13
SPPR
Selected Pin Protocol Register
0xF0
32
TXMODE
0
2
FFSR
Formatter and Flush Status Register
0x300
32
read-only
FlInProg
0
1
FtStopped
1
1
TCPresent
2
1
FtNonStop
3
1
FFCR
Formatter and Flush Control Register
0x304
32
EnFCont
1
1
TrigIn
8
1
FSCR
Formatter Synchronization Counter Register
0x308
32
read-only
TRIGGER
TRIGGER
0xEE8
32
read-only
TRIGGER
0
1
FIFO0
Integration ETM Data
0xEEC
32
read-only
ETM0
0
8
ETM1
8
8
ETM2
16
8
ETM_bytecount
24
2
ETM_ATVALID
26
1
ITM_bytecount
27
2
ITM_ATVALID
29
1
ITATBCTR2
ITATBCTR2
0xEF0
32
read-only
ATREADY
0
1
ITATBCTR0
ITATBCTR0
0xEF8
32
read-only
ATREADY
0
1
FIFO1
Integration ITM Data
0xEFC
32
read-only
ITM0
0
8
ITM1
8
8
ITM2
16
8
ETM_bytecount
24
2
ETM_ATVALID
26
1
ITM_bytecount
27
2
ITM_ATVALID
29
1
ITCTRL
Integration Mode Control
0xF00
32
Mode
0
1
CLAIMSET
Claim tag set
0xFA0
32
CLAIMCLR
Claim tag clear
0xFA4
32
DEVID
TPIU_DEVID
0xFC8
32
read-only
NrTraceInput
0
1
AsynClkIn
5
1
MinBufSz
6
3
PTINVALID
9
1
MANCVALID
10
1
NRZVALID
11
1
DEVTYPE
TPIU_DEVTYPE
0xFCC
32
read-only
SubType
0
4
MajorType
4
4