Microchip Technology Inc. MICROCHIP ATSAML21E18A SAML21 A Microchip ATSAML21E18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 32-pin package Copyright (c) 2018 Microchip Technology Inc.\n \n SPDX-License-Identifier: Apache-2.0\n \n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n \n http://www.apache.org/licenses/LICENSE-2.0\n \n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an "AS IS" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License. CM0+ r0p1 little false false true 2 false 29 system_saml21 8 32 32 read-write 0x00000000 0xFFFFFFFF AC 1.0.0 Analog Comparators AC AC_ 0x43001000 0 0x40 registers AC 23 CTRLA Control A 0x00 8 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 CTRLB Control B 0x01 8 write-only START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 EVCTRL Event Control 0x02 16 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 WINEO0 Window 0 Event Output Enable 4 1 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 INTENCLR Interrupt Enable Clear 0x04 8 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x05 8 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x06 8 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 STATUSA Status A 0x07 8 read-only STATE0 Comparator 0 Current State 0 1 read-only STATE1 Comparator 1 Current State 1 1 read-only WSTATE0 Window 0 Current State 4 2 read-only WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 STATUSB Status B 0x08 8 read-only READY0 Comparator 0 Ready 0 1 read-only READY1 Comparator 1 Ready 1 1 read-only DBGCTRL Debug Control 0x09 8 DBGRUN Debug Run 0 1 WINCTRL Window Control 0x0A 8 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 2 0x1 SCALER%s Scaler n 0x0C 8 VALUE Scaler Value 0 6 2 0x4 COMPCTRL%s Comparator Control n 0x10 32 ENABLE Enable 1 1 SINGLE Single-Shot Mode 2 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 RUNSTDBY Run in Standby 6 1 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 SWAP Swap Inputs and Invert 15 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 MEDLOW Medium low speed 0x1 MEDHIGH Medium high speed 0x2 HIGH High speed 0x3 HYSTEN Hysteresis Enable 19 1 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0x0 HYST70 70mV 0x1 HYST90 90mV 0x2 HYST110 110mV 0x3 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 SYNCBUSY Synchronization Busy 0x20 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only WINCTRL WINCTRL Synchronization Busy 2 1 read-only COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 read-only COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 read-only ADC 1.0.0 Analog Digital Converter ADC ADC_ 0x43000C00 0 0x80 registers ADC 22 CTRLA Control A 0x00 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 ONDEMAND On Demand Control 7 1 CTRLB Control B 0x01 8 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 REFCTRL Reference Control 0x02 8 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 AREFB External Reference 0x4 INTVCC2 VCCANA 0x5 REFCOMP Reference Buffer Offset Compensation Enable 7 1 EVCTRL Event Control 0x03 8 FLUSHEI Flush Event Input Enable 0 1 STARTEI Start Conversion Event Input Enable 1 1 FLUSHINV Flush Event Invert Enable 2 1 STARTINV Satrt Event Invert Enable 3 1 RESRDYEO Result Ready Event Out 4 1 WINMONEO Window Monitor Event Out 5 1 INTENCLR Interrupt Enable Clear 0x04 8 RESRDY Result Ready Interrupt Disable 0 1 OVERRUN Overrun Interrupt Disable 1 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x05 8 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x06 8 RESRDY Result Ready Interrupt Flag 0 1 OVERRUN Overrun Interrupt Flag 1 1 WINMON Window Monitor Interrupt Flag 2 1 SEQSTATUS Sequence Status 0x07 8 read-only SEQSTATE Sequence State 0 5 read-only SEQBUSY Sequence Busy 7 1 read-only INPUTCTRL Input Control 0x08 16 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xa AIN11 ADC AIN11 Pin 0xb AIN12 ADC AIN12 Pin 0xc AIN13 ADC AIN13 Pin 0xd AIN14 ADC AIN14 Pin 0xe AIN15 ADC AIN15 Pin 0xf AIN16 ADC AIN16 Pin 0x10 AIN17 ADC AIN17 Pin 0x11 AIN18 ADC AIN18 Pin 0x12 AIN19 ADC AIN19 Pin 0x13 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 GND Internal ground 0x18 CTRLC Control C 0x0A 16 DIFFMODE Differential Mode 0 1 LEFTADJ Left-Adjusted Result 1 1 FREERUN Free Running Mode 2 1 CORREN Digital Correction Logic Enable 3 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 RESULT > WINLT 0x1 MODE2 RESULT < WINUT 0x2 MODE3 WINLT < RESULT < WINUT 0x3 MODE4 !(WINLT < RESULT < WINUT) 0x4 AVGCTRL Average Control 0x0C 8 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa ADJRES Adjusting Result / Division Coefficient 4 3 SAMPCTRL Sample Time Control 0x0D 8 SAMPLEN Sampling Time Length 0 6 OFFCOMP Comparator Offset Compensation Enable 7 1 WINLT Window Monitor Lower Threshold 0x0E 16 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x10 16 WINUT Window Upper Threshold 0 16 GAINCORR Gain Correction 0x12 16 GAINCORR Gain Correction Value 0 12 OFFSETCORR Offset Correction 0x14 16 OFFSETCORR Offset Correction Value 0 12 SWTRIG Software Trigger 0x18 8 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 DBGCTRL Debug Control 0x1C 8 DBGRUN Debug Run 0 1 SYNCBUSY Synchronization Busy 0x20 16 read-only SWRST SWRST Synchronization Busy 0 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only AVGCTRL AVGCTRL Synchronization Busy 2 1 read-only SAMPCTRL SAMPCTRL Synchronization Busy 3 1 read-only CTRLC CTRLC Synchronization Busy 4 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 5 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 6 1 read-only GAINCORR GAINCORR Synchronization Busy 7 1 read-only WINLT WINLT Synchronization Busy 8 1 read-only WINUT WINUT Synchronization Busy 9 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only RESULT Result 0x24 16 read-only RESULT Result Value 0 16 read-only SEQCTRL Sequence Control 0x28 32 SEQEN Enable Positive Input in the Sequence 0 32 CALIB Calibration 0x2C 16 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 AES 1.0.0 Advanced Encryption Standard AES AES_ 0x42003400 0 0x100 registers AES 26 CTRLA Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 AESMODE AES Modes of operation 2 3 CFBS CFB Types 5 3 KEYSIZE Keysize 8 2 CIPHER Cipher mode 10 1 STARTMODE Start mode 11 1 LOD LOD Enable 12 1 KEYGEN Last key generation 13 1 XORKEY Xor Key operation 14 1 CTYPE Counter measure types 16 4 CTRLB Control B 0x04 8 START Manual Start 0 1 NEWMSG New message 1 1 EOM End of message 2 1 GFMUL GF Multiplication 3 1 INTENCLR Interrupt Enable Clear 0x05 8 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 INTENSET Interrupt Enable Set 0x06 8 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 INTFLAG Interrupt Flag Status 0x07 8 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 DATABUFPTR Data buffer pointer 0x08 8 INDATAPTR Input Data Pointer 0 2 DBGCTRL Debug control 0x09 8 write-only DBGRUN Debug Run 0 1 8 0x4 KEYWORD%s Keyword n 0x0C 32 write-only INDATA Indata 0x38 32 4 0x4 INTVECTV%s Initialisation Vector n 0x3C 32 write-only 4 0x4 HASHKEY%s Hash key n 0x5C 32 4 0x4 GHASH%s Galois Hash n 0x6C 32 CIPLEN Cipher Length 0x80 32 RANDSEED Random Seed 0x84 32 CCL 1.0.0 Configurable Custom Logic CCL CCL_ 0x43001C00 0 0x40 registers CTRL Control 0x0 8 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 2 0x1 SEQCTRL%s SEQ Control x 0x4 8 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0x0 DFF D flip flop 0x1 JK JK flip flop 0x2 LATCH D latch 0x3 RS RS latch 0x4 4 0x4 LUTCTRL%s LUT Control x 0x8 32 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 EDGESEL Edge Selection 7 1 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 DAC 1.0.0 Digital-to-Analog Converter DAC DAC_ 0x42003000 0 0x20 registers DAC 24 CTRLA Control A 0x00 8 SWRST Software Reset 0 1 ENABLE Enable DAC Controller 1 1 CTRLB Control B 0x01 8 DIFF Differential mode enable 0 1 REFSEL Reference Selection for DAC0/1 1 2 REFSELSelect VREFPU External reference unbuffered 0x0 VDDANA Analog supply 0x1 VREFPB External reference buffered 0x2 INTREF Internal bandgap reference 0x3 EVCTRL Event Control 0x02 8 STARTEI0 Start Conversion Event Input DAC 0 0 1 STARTEI1 Start Conversion Event Input DAC 1 1 1 EMPTYEO0 Data Buffer Empty Event Output DAC 0 2 1 EMPTYEO1 Data Buffer Empty Event Output DAC 1 3 1 INVEI0 Enable Invertion of DAC 0 input event 4 1 INVEI1 Enable Invertion of DAC 1 input event 5 1 INTENCLR Interrupt Enable Clear 0x04 8 UNDERRUN0 Underrun Interrupt Enable for DAC 0 0 1 UNDERRUN1 Underrun Interrupt Enable for DAC 1 1 1 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0x05 8 UNDERRUN0 Underrun Interrupt Enable for DAC 0 0 1 UNDERRUN1 Underrun Interrupt Enable for DAC 1 1 1 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0x06 8 UNDERRUN0 DAC 0 Underrun 0 1 UNDERRUN1 DAC 1 Underrun 1 1 EMPTY0 Data Buffer 0 Empty 2 1 EMPTY1 Data Buffer 1 Empty 3 1 STATUS Status 0x07 8 read-only READY0 DAC 0 Startup Ready 0 1 read-only READY1 DAC 1 Startup Ready 1 1 read-only EOC0 DAC 0 End of Conversion 2 1 read-only EOC1 DAC 1 End of Conversion 3 1 read-only SYNCBUSY Synchronization Busy 0x08 32 read-only SWRST Software Reset 0 1 read-only ENABLE DAC Enable Status 1 1 read-only DATA0 Data DAC 0 2 1 read-only DATA1 Data DAC 1 3 1 read-only DATABUF0 Data Buffer DAC 0 4 1 read-only DATABUF1 Data Buffer DAC 1 5 1 read-only 2 0x2 DACCTRL%s DACx Control 0x0C 16 LEFTADJ Left Adjusted Data 0 1 ENABLE Enable DAC0 1 1 CCTRL Current Control 2 2 CCTRLSelect CC100K GCLK_DAC <= 1.2MHz (100kSPS) 0x0 CC1M 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) 0x1 CC12M 6MHz < GCLK_DAC <= 12MHz (1MSPS) 0x2 RUNSTDBY Run in Standby 6 1 DITHER Dithering Mode 7 1 REFRESH Refresh period 8 4 2 0x2 DATA%s Data DAC0 0x10 16 write-only DATA DAC0 Data 0 16 write-only 2 0x2 DATABUF%s Data Buffer DAC0 0x14 16 write-only DATABUF DAC0 Data Buffer 0 16 write-only DBGCTRL Debug Control 0x18 8 DBGRUN Debug Run 0 1 DMAC 2.0.0 Direct Memory Access Controller DMAC DMAC_ 0x44000400 0 0x80 registers DMAC 5 CTRL Control 0x00 16 SWRST Software Reset 0 1 DMAENABLE DMA Enable 1 1 CRCENABLE CRC Enable 2 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 CRCCTRL CRC Control 0x02 16 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0x0 HWORD 16-bit bus transfer 0x1 WORD 32-bit bus transfer 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x0 IO I/O interface 0x1 CRCDATAIN CRC Data Input 0x04 32 CRCDATAIN CRC Data Input 0 32 CRCCHKSUM CRC Checksum 0x08 32 CRCCHKSUM CRC Checksum 0 32 CRCSTATUS CRC Status 0x0C 8 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 read-only DBGCTRL Debug Control 0x0D 8 DBGRUN Debug Run 0 1 QOSCTRL QOS Control 0x0E 8 0x2A WRBQOS Write-Back Quality of Service 0 2 WRBQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 FQOS Fetch Quality of Service 2 2 FQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DQOS Data Transfer Quality of Service 4 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 SWTRIGCTRL Software Trigger Control 0x10 32 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 SWTRIG12 Channel 12 Software Trigger 12 1 SWTRIG13 Channel 13 Software Trigger 13 1 SWTRIG14 Channel 14 Software Trigger 14 1 SWTRIG15 Channel 15 Software Trigger 15 1 PRICTRL0 Priority Control 0 0x14 32 LVLPRI0 Level 0 Channel Priority Number 0 4 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 LVLPRI1 Level 1 Channel Priority Number 8 4 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 LVLPRI2 Level 2 Channel Priority Number 16 4 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 LVLPRI3 Level 3 Channel Priority Number 24 4 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 INTPEND Interrupt Pending 0x20 16 ID Channel ID 0 4 TERR Transfer Error 8 1 TCMPL Transfer Complete 9 1 SUSP Channel Suspend 10 1 FERR Fetch Error 13 1 read-only BUSY Busy 14 1 read-only PEND Pending 15 1 read-only INTSTATUS Interrupt Status 0x24 32 read-only CHINT0 Channel 0 Pending Interrupt 0 1 read-only CHINT1 Channel 1 Pending Interrupt 1 1 read-only CHINT2 Channel 2 Pending Interrupt 2 1 read-only CHINT3 Channel 3 Pending Interrupt 3 1 read-only CHINT4 Channel 4 Pending Interrupt 4 1 read-only CHINT5 Channel 5 Pending Interrupt 5 1 read-only CHINT6 Channel 6 Pending Interrupt 6 1 read-only CHINT7 Channel 7 Pending Interrupt 7 1 read-only CHINT8 Channel 8 Pending Interrupt 8 1 read-only CHINT9 Channel 9 Pending Interrupt 9 1 read-only CHINT10 Channel 10 Pending Interrupt 10 1 read-only CHINT11 Channel 11 Pending Interrupt 11 1 read-only CHINT12 Channel 12 Pending Interrupt 12 1 read-only CHINT13 Channel 13 Pending Interrupt 13 1 read-only CHINT14 Channel 14 Pending Interrupt 14 1 read-only CHINT15 Channel 15 Pending Interrupt 15 1 read-only BUSYCH Busy Channels 0x28 32 read-only BUSYCH0 Busy Channel 0 0 1 read-only BUSYCH1 Busy Channel 1 1 1 read-only BUSYCH2 Busy Channel 2 2 1 read-only BUSYCH3 Busy Channel 3 3 1 read-only BUSYCH4 Busy Channel 4 4 1 read-only BUSYCH5 Busy Channel 5 5 1 read-only BUSYCH6 Busy Channel 6 6 1 read-only BUSYCH7 Busy Channel 7 7 1 read-only BUSYCH8 Busy Channel 8 8 1 read-only BUSYCH9 Busy Channel 9 9 1 read-only BUSYCH10 Busy Channel 10 10 1 read-only BUSYCH11 Busy Channel 11 11 1 read-only BUSYCH12 Busy Channel 12 12 1 read-only BUSYCH13 Busy Channel 13 13 1 read-only BUSYCH14 Busy Channel 14 14 1 read-only BUSYCH15 Busy Channel 15 15 1 read-only PENDCH Pending Channels 0x2C 32 read-only PENDCH0 Pending Channel 0 0 1 read-only PENDCH1 Pending Channel 1 1 1 read-only PENDCH2 Pending Channel 2 2 1 read-only PENDCH3 Pending Channel 3 3 1 read-only PENDCH4 Pending Channel 4 4 1 read-only PENDCH5 Pending Channel 5 5 1 read-only PENDCH6 Pending Channel 6 6 1 read-only PENDCH7 Pending Channel 7 7 1 read-only PENDCH8 Pending Channel 8 8 1 read-only PENDCH9 Pending Channel 9 9 1 read-only PENDCH10 Pending Channel 10 10 1 read-only PENDCH11 Pending Channel 11 11 1 read-only PENDCH12 Pending Channel 12 12 1 read-only PENDCH13 Pending Channel 13 13 1 read-only PENDCH14 Pending Channel 14 14 1 read-only PENDCH15 Pending Channel 15 15 1 read-only ACTIVE Active Channel and Levels 0x30 32 read-only LVLEX0 Level 0 Channel Trigger Request Executing 0 1 read-only LVLEX1 Level 1 Channel Trigger Request Executing 1 1 read-only LVLEX2 Level 2 Channel Trigger Request Executing 2 1 read-only LVLEX3 Level 3 Channel Trigger Request Executing 3 1 read-only ID Active Channel ID 8 5 read-only ABUSY Active Channel Busy 15 1 read-only BTCNT Active Channel Block Transfer Count 16 16 read-only BASEADDR Descriptor Memory Section Base Address 0x34 32 BASEADDR Descriptor Memory Base Address 0 32 WRBADDR Write-Back Memory Section Base Address 0x38 32 WRBADDR Write-Back Memory Base Address 0 32 CHID Channel ID 0x3F 8 ID Channel ID 0 4 CHCTRLA Channel Control A 0x40 8 SWRST Channel Software Reset 0 1 ENABLE Channel Enable 1 1 RUNSTDBY Channel run in standby 6 1 CHCTRLB Channel Control B 0x44 32 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 TRIGSRC Trigger Source 8 6 TRIGSRCSelect DISABLE Only software/event triggers 0x0 TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 TERR Channel Transfer Error 0 1 TCMPL Channel Transfer Complete 1 1 SUSP Channel Suspend 2 1 CHSTATUS Channel Status 0x4F 8 read-only PEND Channel Pending 0 1 read-only BUSY Channel Busy 1 1 read-only FERR Channel Fetch Error 2 1 read-only DSU 2.4.0 Device Service Unit DSU DSU_ 0x41002000 0 0x2000 registers CTRL Control 0x0000 8 write-only SWRST Software Reset 0 1 write-only CRC 32-bit Cyclic Redundancy Code 2 1 write-only MBIST Memory built-in self-test 3 1 write-only CE Chip-Erase 4 1 write-only ARR Auxiliary Row Read 6 1 write-only SMSA Start Memory Stream Access 7 1 write-only STATUSA Status A 0x0001 8 DONE Done 0 1 CRSTEXT CPU Reset Phase Extension 1 1 BERR Bus Error 2 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x0002 8 read-only PROT Protected 0 1 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 ADDR Address 0x0004 32 AMOD Access Mode 0 2 ADDR Address 2 30 LENGTH Length 0x0008 32 LENGTH Length 2 30 DATA Data 0x000C 32 DATA Data 0 32 2 0x4 DCC%s Debug Communication Channel n 0x0010 32 DATA Data 0 32 DID Device Identification 0x0018 32 read-only 0x1081000A DEVSEL Device Select 0 8 read-only REVISION Revision Number 8 4 read-only DIE Die Number 12 4 read-only SERIES Series 16 6 read-only SERIESSelect 0 Cortex-M0+ processor, basic feature set 0x0 1 Cortex-M0+ processor, USB 0x1 FAMILY Family 23 5 read-only FAMILYSelect 0 General purpose microcontroller 0x0 1 PicoPower 0x1 PROCESSOR Processor 28 4 read-only PROCESSORSelect 0 Cortex-M0 0x0 1 Cortex-M0+ 0x1 2 Cortex-M3 0x2 3 Cortex-M4 0x3 2 0x4 DCFG%s Device Configuration 0x00F0 32 DCFG Device Configuration 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only 0x9F0FC002 EPRES Entry Present 0 1 FMT Format 1 1 read-only ADDOFF Address Offset 12 20 read-only ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only 0x00003002 END CoreSight ROM Table End 0x1008 32 read-only END End Marker 0 32 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only SMEMP System Memory Present 0 1 PID4 Peripheral Identification 4 0x1FD0 32 read-only JEPCC JEP-106 Continuation Code 0 4 FKBC 4KB count 4 4 read-only PID5 Peripheral Identification 5 0x1FD4 32 read-only PID6 Peripheral Identification 6 0x1FD8 32 read-only PID7 Peripheral Identification 7 0x1FDC 32 read-only PID0 Peripheral Identification 0 0x1FE0 32 read-only 0x000000D0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only 0x000000FC PARTNBH Part Number High 0 4 JEPIDCL Low part of the JEP-106 Identity Code 4 4 read-only PID2 Peripheral Identification 2 0x1FE8 32 read-only 0x00000009 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 read-only REVISION Revision Number 4 4 read-only PID3 Peripheral Identification 3 0x1FEC 32 read-only CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 read-only CID0 Component Identification 0 0x1FF0 32 read-only PREAMBLEB0 Preamble Byte 0 0 8 read-only CID1 Component Identification 1 0x1FF4 32 read-only 0x0000000D PREAMBLE Preamble 0 4 read-only CCLASS Component Class 4 4 read-only CID2 Component Identification 2 0x1FF8 32 read-only 0x00000010 PREAMBLEB2 Preamble Byte 2 0 8 read-only CID3 Component Identification 3 0x1FFC 32 read-only 0x000000B1 PREAMBLEB3 Preamble Byte 3 0 8 EIC 1.0.0 External Interrupt Controller EIC EIC_ 0x40002400 0 0x40 registers EIC 3 CTRLA Control 0x00 8 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 CKSEL Clock Selection 4 1 NMICTRL NMI Control 0x01 8 NMISENSE NMI Input Sense Configuration 0 3 NMISENSESelect NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 NMIFILTEN NMI Filter Enable 3 1 NMIFLAG NMI Interrupt Flag 0x02 16 NMI NMI Interrupt Flag 0 1 SYNCBUSY Syncbusy register 0x04 32 read-only SWRST Software reset synchronisation 0 1 read-only ENABLE Enable synchronisation 1 1 read-only EVCTRL Event Control 0x08 32 EXTINTEO External Interrupt Event Output Enable 0 16 INTENCLR Interrupt Enable Clear 0x0C 32 EXTINT External Interrupt Disable 0 16 INTENSET Interrupt Enable Set 0x10 32 EXTINT External Interrupt Disable 0 16 INTFLAG Interrupt Flag Status and Clear 0x14 32 EXTINT External Interrupt Flag 0 16 2 0x4 CONFIG%s Configuration n 0x1C 32 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN0 Filter Enable 0 3 1 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN1 Filter Enable 1 7 1 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN2 Filter Enable 2 11 1 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN3 Filter Enable 3 15 1 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN4 Filter Enable 4 19 1 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN5 Filter Enable 5 23 1 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN6 Filter Enable 6 27 1 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN7 Filter Enable 7 31 1 EVSYS 1.0.0 Event System Interface EVSYS EVSYS_ 0x43000000 0 0x400 registers EVSYS 7 CTRLA Control 0x00 8 SWRST Software Reset 0 1 write-only CHSTATUS Channel Status 0x0C 32 read-only USRRDY0 Channel 0 User Ready 0 1 read-only USRRDY1 Channel 1 User Ready 1 1 read-only USRRDY2 Channel 2 User Ready 2 1 read-only USRRDY3 Channel 3 User Ready 3 1 read-only USRRDY4 Channel 4 User Ready 4 1 read-only USRRDY5 Channel 5 User Ready 5 1 read-only USRRDY6 Channel 6 User Ready 6 1 read-only USRRDY7 Channel 7 User Ready 7 1 read-only USRRDY8 Channel 8 User Ready 8 1 read-only USRRDY9 Channel 9 User Ready 9 1 read-only USRRDY10 Channel 10 User Ready 10 1 read-only USRRDY11 Channel 11 User Ready 11 1 read-only CHBUSY0 Channel 0 Busy 16 1 read-only CHBUSY1 Channel 1 Busy 17 1 read-only CHBUSY2 Channel 2 Busy 18 1 read-only CHBUSY3 Channel 3 Busy 19 1 read-only CHBUSY4 Channel 4 Busy 20 1 read-only CHBUSY5 Channel 5 Busy 21 1 read-only CHBUSY6 Channel 6 Busy 22 1 read-only CHBUSY7 Channel 7 Busy 23 1 read-only CHBUSY8 Channel 8 Busy 24 1 read-only CHBUSY9 Channel 9 Busy 25 1 read-only CHBUSY10 Channel 10 Busy 26 1 read-only CHBUSY11 Channel 11 Busy 27 1 read-only INTENCLR Interrupt Enable Clear 0x10 32 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 INTENSET Interrupt Enable Set 0x14 32 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 OVR8 Channel 8 Overrun 8 1 OVR9 Channel 9 Overrun 9 1 OVR10 Channel 10 Overrun 10 1 OVR11 Channel 11 Overrun 11 1 EVD0 Channel 0 Event Detection 16 1 EVD1 Channel 1 Event Detection 17 1 EVD2 Channel 2 Event Detection 18 1 EVD3 Channel 3 Event Detection 19 1 EVD4 Channel 4 Event Detection 20 1 EVD5 Channel 5 Event Detection 21 1 EVD6 Channel 6 Event Detection 22 1 EVD7 Channel 7 Event Detection 23 1 EVD8 Channel 8 Event Detection 24 1 EVD9 Channel 9 Event Detection 25 1 EVD10 Channel 10 Event Detection 26 1 EVD11 Channel 11 Event Detection 27 1 SWEVT Software Event 0x1C 32 write-only CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 CHANNEL8 Channel 8 Software Selection 8 1 CHANNEL9 Channel 9 Software Selection 9 1 CHANNEL10 Channel 10 Software Selection 10 1 CHANNEL11 Channel 11 Software Selection 11 1 12 0x4 CHANNEL%s Channel n 0x20 32 0x00008000 EVGEN Event Generator Selection 0 7 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 RUNSTDBY Run in standby 14 1 ONDEMAND Generic Clock On Demand 15 1 45 0x4 USER%s User Multiplexer n 0x80 32 CHANNEL Channel Event Selection 0 5 GCLK 1.0.0 Generic Clock Generator GCLK GCLK_ 0x40001800 0 0x200 registers CTRLA Control 0x00 8 SWRST Software Reset 0 1 SYNCBUSY Synchronization Busy 0x04 32 read-only SWRST Software Reset Synchroniation Busy bit 0 1 read-only GENCTRL0 Generic Clock Generator Control 0 Synchronization Busy bits 2 1 read-only GENCTRL1 Generic Clock Generator Control 1 Synchronization Busy bits 3 1 read-only GENCTRL2 Generic Clock Generator Control 2 Synchronization Busy bits 4 1 read-only GENCTRL3 Generic Clock Generator Control 3 Synchronization Busy bits 5 1 read-only GENCTRL4 Generic Clock Generator Control 4 Synchronization Busy bits 6 1 read-only GENCTRL5 Generic Clock Generator Control 5 Synchronization Busy bits 7 1 read-only GENCTRL6 Generic Clock Generator Control 6 Synchronization Busy bits 8 1 read-only GENCTRL7 Generic Clock Generator Control 7 Synchronization Busy bits 9 1 read-only GENCTRL8 Generic Clock Generator Control 8 Synchronization Busy bits 10 1 read-only 9 0x4 GENCTRL%s Generic Clock Generator Control 0x20 32 SRC Source Select 0 5 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OOV Output Off Value 10 1 OE Output Enable 11 1 DIVSEL Divide Selection 12 1 RUNSTDBY Run in Standby 13 1 DIV Division Factor 16 16 36 0x4 PCHCTRL%s Peripheral Clock Control 0x80 32 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 CHEN Channel Enable 6 1 WRTLOCK Write Lock 7 1 MCLK 1.0.0 Main Clock MCLK MCLK_ 0x40000400 0 0x80 registers SYSTEM 0 CTRLA Control A 0x00 8 CFDEN Clock Failure Detector Enable 2 1 EMCLK Emergency Clock Select 4 1 INTENCLR Interrupt Enable Clear 0x01 8 CKRDY Clock Ready Interrupt Enable 0 1 CFD Clock Failure Detector Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x02 8 CKRDY Clock Ready Interrupt Enable 0 1 CFD Clock Failure Detector Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x03 8 0x01 CKRDY Clock Ready 0 1 CFD Clock Failure Detector 1 1 CPUDIV CPU Clock Division 0x04 8 0x01 CPUDIV CPU Clock Division Factor 0 8 CPUDIVSelect DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x4 DIV8 Divide by 8 0x8 DIV16 Divide by 16 0x10 DIV32 Divide by 32 0x20 DIV64 Divide by 64 0x40 DIV128 Divide by 128 0x80 LPDIV Low-Power Clock Division 0x05 8 0x01 LPDIV Low-Power Clock Division Factor 0 8 LPDIVSelect DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x4 DIV8 Divide by 8 0x8 DIV16 Divide by 16 0x10 DIV32 Divide by 32 0x20 DIV64 Divide by 64 0x40 DIV128 Divide by 128 0x80 BUPDIV Backup Clock Division 0x06 8 0x01 BUPDIV Backup Clock Division Factor 0 8 BUPDIVSelect DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x4 DIV8 Divide by 8 0x8 DIV16 Divide by 16 0x10 DIV32 Divide by 32 0x20 DIV64 Divide by 64 0x40 DIV128 Divide by 128 0x80 AHBMASK AHB Mask 0x10 32 0x000FFFFF HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 HPB3_ HPB3 AHB Clock Mask 3 1 HPB4_ HPB4 AHB Clock Mask 4 1 DSU_ DSU AHB Clock Mask 5 1 NVMCTRL_ NVMCTRL AHB Clock Mask 8 1 HSRAM_ HSRAM AHB Clock Mask 9 1 LPRAM_ LPRAM AHB Clock Mask 10 1 DMAC_ DMAC AHB Clock Mask 11 1 USB_ USB AHB Clock Mask 12 1 PAC_ PAC AHB Clock Mask 14 1 NVMCTRL_PICACHU_ NVMCTRL_PICACHU AHB Clock Mask 15 1 L2HBRIDGES_H_ L2HBRIDGES_H AHB Clock Mask 16 1 H2LBRIDGES_H_ H2LBRIDGES_H AHB Clock Mask 17 1 HSRAM_AHBSETUPKEEPER_ HSRAM_AHBSETUPKEEPER AHB Clock Mask 18 1 HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_ HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask 19 1 APBAMASK APBA Mask 0x14 32 0x00001FFF PM_ PM APB Clock Enable 0 1 MCLK_ MCLK APB Clock Enable 1 1 RSTC_ RSTC APB Clock Enable 2 1 OSCCTRL_ OSCCTRL APB Clock Enable 3 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 4 1 SUPC_ SUPC APB Clock Enable 5 1 GCLK_ GCLK APB Clock Enable 6 1 WDT_ WDT APB Clock Enable 7 1 RTC_ RTC APB Clock Enable 8 1 EIC_ EIC APB Clock Enable 9 1 PORT_ PORT APB Clock Enable 10 1 APBBMASK APBB Mask 0x18 32 0x00000007 USB_ USB APB Clock Enable 0 1 DSU_ DSU APB Clock Enable 1 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 APBCMASK APBC Mask 0x1C 32 0x00007FFF SERCOM0_ SERCOM0 APB Clock Enable 0 1 SERCOM1_ SERCOM1 APB Clock Enable 1 1 SERCOM2_ SERCOM2 APB Clock Enable 2 1 SERCOM3_ SERCOM3 APB Clock Enable 3 1 TCC0_ TCC0 APB Clock Enable 5 1 TCC1_ TCC1 APB Clock Enable 6 1 TCC2_ TCC2 APB Clock Enable 7 1 TC0_ TC0 APB Clock Enable 8 1 TC1_ TC1 APB Clock Enable 9 1 DAC_ DAC APB Clock Enable 12 1 AES_ AES APB Clock Enable 13 1 TRNG_ TRNG APB Clock Enable 14 1 APBDMASK APBD Mask 0x20 32 0x000000FF EVSYS_ EVSYS APB Clock Enable 0 1 TC4_ TC4 APB Clock Enable 2 1 ADC_ ADC APB Clock Enable 3 1 AC_ AC APB Clock Enable 4 1 PTC_ PTC APB Clock Enable 5 1 OPAMP_ OPAMP APB Clock Enable 6 1 CCL_ CCL APB Clock Enable 7 1 APBEMASK APBE Mask 0x24 32 0x00000009 PAC_ PAC APB Clock Enable 0 1 MTB 1.0.0 Cortex-M0+ Micro-Trace Buffer MTB MTB_ 0x41006000 0 0x1000 registers POSITION MTB Position 0x000 32 WRAP Pointer Value Wraps 2 1 POINTER Trace Packet Location Pointer 3 29 MASTER MTB Master 0x004 32 MASK Maximum Value of the Trace Buffer in SRAM 0 5 TSTARTEN Trace Start Input Enable 5 1 TSTOPEN Trace Stop Input Enable 6 1 SFRWPRIV Special Function Register Write Privilege 7 1 RAMPRIV SRAM Privilege 8 1 HALTREQ Halt Request 9 1 EN Main Trace Enable 31 1 FLOW MTB Flow 0x008 32 AUTOSTOP Auto Stop Tracing 0 1 AUTOHALT Auto Halt Request 1 1 WATERMARK Watermark value 3 29 BASE MTB Base 0x00C 32 read-only ITCTRL MTB Integration Mode Control 0xF00 32 CLAIMSET MTB Claim Set 0xFA0 32 CLAIMCLR MTB Claim Clear 0xFA4 32 LOCKACCESS MTB Lock Access 0xFB0 32 LOCKSTATUS MTB Lock Status 0xFB4 32 read-only AUTHSTATUS MTB Authentication Status 0xFB8 32 read-only DEVARCH MTB Device Architecture 0xFBC 32 read-only DEVID MTB Device Configuration 0xFC8 32 read-only DEVTYPE MTB Device Type 0xFCC 32 read-only PID4 Peripheral Identification 4 0xFD0 32 read-only PID5 Peripheral Identification 5 0xFD4 32 read-only PID6 Peripheral Identification 6 0xFD8 32 read-only PID7 Peripheral Identification 7 0xFDC 32 read-only PID0 Peripheral Identification 0 0xFE0 32 read-only PID1 Peripheral Identification 1 0xFE4 32 read-only PID2 Peripheral Identification 2 0xFE8 32 read-only PID3 Peripheral Identification 3 0xFEC 32 read-only CID0 Component Identification 0 0xFF0 32 read-only CID1 Component Identification 1 0xFF4 32 read-only CID2 Component Identification 2 0xFF8 32 read-only CID3 Component Identification 3 0xFFC 32 read-only NVMCTRL 3.0.1 Non-Volatile Memory Controller NVMCTRL NVMCTRL_ 0x41004000 0 0x80 registers NVMCTRL 4 CTRLA Control A 0x00 16 CMD Command 0 7 CMDSelect ER Erase Row - Erases the row addressed by the ADDR register. 0x2 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x4 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x5 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x6 SF Security Flow Command 0xa WL Write lockbits 0xf RWWEEER RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. 0x1a RWWEEWP RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x1c LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidate all cache lines. 0x46 CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xa5 CTRLB Control B 0x04 32 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0x0 HALF Half Auto Wait State 0x1 DUAL Dual Auto Wait State 0x2 MANW Manual Write 7 1 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x1 DISABLED Auto power reduction disabled. 0x3 FWUP fast wake-up 11 1 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 CACHEDIS Cache Disable 18 1 PARAM NVM Parameter 0x08 32 NVMP NVM Pages 0 16 read-only PSZ Page Size 16 3 read-only PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 RWWEEP RWW EEPROM Pages 20 12 read-only INTENCLR Interrupt Enable Clear 0x0C 8 READY NVM Ready Interrupt Enable 0 1 ERROR Error Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x10 8 READY NVM Ready Interrupt Enable 0 1 ERROR Error Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 READY NVM Ready 0 1 ERROR Error 1 1 STATUS Status 0x18 16 PRM Power Reduction Mode 0 1 read-only LOAD NVM Page Buffer Active Loading 1 1 PROGE Programming Error Status 2 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 SB Security Bit Status 8 1 read-only ADDR Address 0x1C 32 ADDR NVM Address 0 22 LOCK Lock Section 0x20 16 LOCK Region Lock Bits 0 16 read-only OPAMP 1.0.0 Operational Amplifier OPAMP OPAMP_ 0x43001800 0 0x10 registers CTRLA Control A 0x00 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 LPMUX Low-Power Mux 7 1 STATUS Status 0x02 8 read-only READY0 OPAMP 0 Ready 0 1 READY1 OPAMP 1 Ready 1 1 READY2 OPAMP 2 Ready 2 1 3 0x4 OPAMPCTRL%s OPAMP Control n 0x04 32 ENABLE Operational Amplifier Enable 1 1 ANAOUT Analog Output 2 1 BIAS Bias Selection 3 2 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 RES2OUT Resistor ladder To Output 8 1 RES2VCC Resistor ladder To VCC 9 1 RES1EN Resistor 1 Enable 10 1 RES1MUX Resistor 1 Mux 11 2 POTMUX Potentiometer Selection 13 3 MUXPOS Positive Input Mux Selection 16 3 MUXNEG Negative Input Mux Selection 20 3 OSCCTRL 1.0.0 Oscillators Control OSCCTRL OSCCTRL_ 0x40000C00 0 0x80 registers SYSTEM 0 INTENCLR Interrupt Enable Clear 0x00 32 XOSCRDY XOSC Ready Interrupt Enable 0 1 OSC16MRDY OSC16M Ready Interrupt Enable 4 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 16 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 17 1 DPLLLTO DPLL Time Out Interrupt Enable 18 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 19 1 INTENSET Interrupt Enable Set 0x04 32 XOSCRDY XOSC Ready Interrupt Enable 0 1 OSC16MRDY OSC16M Ready Interrupt Enable 4 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 16 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 17 1 DPLLLTO DPLL Time Out Interrupt Enable 18 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 19 1 INTFLAG Interrupt Flag Status and Clear 0x08 32 XOSCRDY XOSC Ready 0 1 OSC16MRDY OSC16M Ready 4 1 DFLLRDY DFLL Ready 8 1 DFLLOOB DFLL Out Of Bounds 9 1 DFLLLCKF DFLL Lock Fine 10 1 DFLLLCKC DFLL Lock Coarse 11 1 DFLLRCS DFLL Reference Clock Stopped 12 1 DPLLLCKR DPLL Lock Rise 16 1 DPLLLCKF DPLL Lock Fall 17 1 DPLLLTO DPLL Timeout 18 1 DPLLLDRTO DPLL Ratio Ready 19 1 STATUS Power and Clocks Status 0x0C 32 read-only XOSCRDY XOSC Ready 0 1 read-only OSC16MRDY OSC16M Ready 4 1 read-only DFLLRDY DFLL Ready 8 1 read-only DFLLOOB DFLL Out Of Bounds 9 1 read-only DFLLLCKF DFLL Lock Fine 10 1 read-only DFLLLCKC DFLL Lock Coarse 11 1 read-only DFLLRCS DFLL Reference Clock Stopped 12 1 read-only DPLLLCKR DPLL Lock Rise 16 1 read-only DPLLLCKF DPLL Lock Fall 17 1 read-only DPLLTO DPLL Timeout 18 1 read-only DPLLLDRTO DPLL Ratio Ready 19 1 read-only XOSCCTRL External Multipurpose Crystal Oscillator (XOSC) Control 0x10 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 GAIN Oscillator Gain 8 3 AMPGC Automatic Amplitude Gain Control 11 1 STARTUP Start-Up Time 12 4 OSC16MCTRL 16MHz Internal Oscillator (OSC16M) Control 0x14 8 0x82 ENABLE Oscillator Enable 1 1 FSEL Oscillator Frequency Select 2 2 FSELSelect 4 4MHz 0x0 8 8MHz 0x1 12 12MHz 0x2 16 16MHz 0x3 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 DFLLCTRL DFLL48M Control 0x18 16 0x0080 ENABLE DFLL Enable 1 1 MODE Operating Mode Selection 2 1 STABLE Stable DFLL Frequency 3 1 LLAW Lose Lock After Wake 4 1 USBCRM USB Clock Recovery Mode 5 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 CCDIS Chill Cycle Disable 8 1 QLDIS Quick Lock Disable 9 1 BPLCKC Bypass Coarse Lock 10 1 WAITLOCK Wait Lock 11 1 DFLLVAL DFLL48M Value 0x1C 32 FINE Fine Value 0 10 COARSE Coarse Value 10 6 DIFF Multiplication Ratio Difference 16 16 read-only DFLLMUL DFLL48M Multiplier 0x20 32 MUL DFLL Multiply Factor 0 16 FSTEP Fine Maximum Step 16 10 CSTEP Coarse Maximum Step 26 6 DFLLSYNC DFLL48M Synchronization 0x24 8 READREQ Read Request 7 1 write-only DPLLCTRLA DPLL Control 0x28 8 0x80 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand 7 1 DPLLRATIO DPLL Ratio Control 0x2C 32 LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLCTRLB Digital Core Configuration 0x30 32 FILTER Proportional Integral Filter Selection 0 2 LPEN Low-Power Enable 2 1 WUF Wake Up Fast 3 1 REFCLK Reference Clock Selection 4 2 LTIME Lock Time 8 3 LBYPASS Lock Bypass 12 1 DIV Clock Divider 16 11 DPLLPRESC DPLL Prescaler 0x34 8 PRESC Output Clock Prescaler 0 2 PRESCSelect DIV1 DPLL output is divided by 1 0x0 DIV2 DPLL output is divided by 2 0x1 DIV4 DPLL output is divided by 4 0x2 DPLLSYNCBUSY DPLL Synchronization Busy 0x38 8 read-only ENABLE DPLL Enable Synchronization Status 1 1 read-only DPLLRATIO DPLL Ratio Synchronization Status 2 1 read-only DPLLPRESC DPLL Prescaler Synchronization Status 3 1 read-only DPLLSTATUS DPLL Status 0x3C 8 read-only LOCK DPLL Lock Status 0 1 read-only CLKRDY DPLL Clock Ready 1 1 read-only OSC32KCTRL 1.0.0 32k Oscillators Control OSC32KCTRL OSC32KCTRL_ 0x40001000 0 0x80 registers SYSTEM 0 INTENCLR Interrupt Enable Clear 0x00 32 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x04 32 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x08 32 XOSC32KRDY XOSC32K Ready 0 1 OSC32KRDY OSC32K Ready 1 1 STATUS Power and Clocks Status 0x0C 32 read-only XOSC32KRDY XOSC32K Ready 0 1 read-only OSC32KRDY OSC32K Ready 1 1 read-only RTCCTRL Clock selection 0x10 32 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0x0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 0x1 OSC1K 1.024kHz from 32.768kHz internal oscillator 0x2 OSC32K 32.768kHz from 32.768kHz internal oscillator 0x3 XOSC1K 1.024kHz from 32.768kHz internal oscillator 0x4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 0x5 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 32 0x00000080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 EN32K 32kHz Output Enable 3 1 EN1K 1kHz Output Enable 4 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 OSC32K 32kHz Internal Oscillator (OSC32K) Control 0x18 32 0x003F0080 ENABLE Oscillator Enable 1 1 EN32K 32kHz Output Enable 2 1 EN1K 1kHz Output Enable 3 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 CALIB Oscillator Calibration 16 7 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 CALIB Oscillator Calibration 8 5 WRTLOCK Write Lock 15 1 PAC 1.0.0 Peripheral Access Controller PAC PAC_ 0x44000000 0 0x80 registers SYSTEM 0 WRCTRL Write control 0x00 32 PERID Peripheral identifier 0 16 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0x0 CLR Clear protection 0x1 SET Set protection 0x2 SETLCK Set and lock protection 0x3 EVCTRL Event control 0x04 8 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x08 8 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x09 8 ERR Peripheral access error interrupt enable 0 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 FLASH_ FLASH 0 1 HSRAMCM0P_ HSRAMCM0P 1 1 HSRAMDSU_ HSRAMDSU 2 1 HPB1_ HPB1 3 1 H2LBRIDGES_ H2LBRIDGES 4 1 HPB0_ HPB0 16 1 HPB2_ HPB2 17 1 HPB3_ HPB3 18 1 HPB4_ HPB4 19 1 LPRAMHS_ LPRAMHS 21 1 LPRAMPICOP_ LPRAMPICOP 22 1 LPRAMDMAC_ LPRAMDMAC 23 1 L2HBRIDGES_ L2HBRIDGES 24 1 HSRAMLP_ HSRAMLP 25 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 PM_ PM 0 1 MCLK_ MCLK 1 1 RSTC_ RSTC 2 1 OSCCTRL_ OSCCTRL 3 1 OSC32KCTRL_ OSC32KCTRL 4 1 SUPC_ SUPC 5 1 GCLK_ GCLK 6 1 WDT_ WDT 7 1 RTC_ RTC 8 1 EIC_ EIC 9 1 PORT_ PORT 10 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 USB_ USB 0 1 DSU_ DSU 1 1 NVMCTRL_ NVMCTRL 2 1 MTB_ MTB 3 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 SERCOM0_ SERCOM0 0 1 SERCOM1_ SERCOM1 1 1 SERCOM2_ SERCOM2 2 1 SERCOM3_ SERCOM3 3 1 TCC0_ TCC0 5 1 TCC1_ TCC1 6 1 TCC2_ TCC2 7 1 TC0_ TC0 8 1 TC1_ TC1 9 1 DAC_ DAC 12 1 AES_ AES 13 1 TRNG_ TRNG 14 1 INTFLAGD Peripheral interrupt flag status - Bridge D 0x20 32 EVSYS_ EVSYS 0 1 TC4_ TC4 2 1 ADC_ ADC 3 1 AC_ AC 4 1 PTC_ PTC 5 1 OPAMP_ OPAMP 6 1 CCL_ CCL 7 1 INTFLAGE Peripheral interrupt flag status - Bridge E 0x24 32 PAC_ PAC 0 1 DMAC_ DMAC 1 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only 0x00001000 PM_ PM APB Protect Enable 0 1 MCLK_ MCLK APB Protect Enable 1 1 RSTC_ RSTC APB Protect Enable 2 1 OSCCTRL_ OSCCTRL APB Protect Enable 3 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 4 1 SUPC_ SUPC APB Protect Enable 5 1 GCLK_ GCLK APB Protect Enable 6 1 WDT_ WDT APB Protect Enable 7 1 RTC_ RTC APB Protect Enable 8 1 EIC_ EIC APB Protect Enable 9 1 PORT_ PORT APB Protect Enable 10 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only 0x00000022 USB_ USB APB Protect Enable 0 1 DSU_ DSU APB Protect Enable 1 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 MTB_ MTB APB Protect Enable 3 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only SERCOM0_ SERCOM0 APB Protect Enable 0 1 SERCOM1_ SERCOM1 APB Protect Enable 1 1 SERCOM2_ SERCOM2 APB Protect Enable 2 1 SERCOM3_ SERCOM3 APB Protect Enable 3 1 TCC0_ TCC0 APB Protect Enable 5 1 TCC1_ TCC1 APB Protect Enable 6 1 TCC2_ TCC2 APB Protect Enable 7 1 TC0_ TC0 APB Protect Enable 8 1 TC1_ TC1 APB Protect Enable 9 1 DAC_ DAC APB Protect Enable 12 1 AES_ AES APB Protect Enable 13 1 TRNG_ TRNG APB Protect Enable 14 1 STATUSD Peripheral write protection status - Bridge D 0x40 32 read-only EVSYS_ EVSYS APB Protect Enable 0 1 TC4_ TC4 APB Protect Enable 2 1 ADC_ ADC APB Protect Enable 3 1 AC_ AC APB Protect Enable 4 1 PTC_ PTC APB Protect Enable 5 1 OPAMP_ OPAMP APB Protect Enable 6 1 CCL_ CCL APB Protect Enable 7 1 STATUSE Peripheral write protection status - Bridge E 0x44 32 read-only PAC_ PAC APB Protect Enable 0 1 DMAC_ DMAC APB Protect Enable 1 1 PM 1.0.0 Power Manager PM PM_ 0x40000000 0 0x80 registers SYSTEM 0 CTRLA Control A 0x00 8 IORET I/O Retention 2 1 SLEEPCFG Sleep Configuration 0x01 8 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE CPU, AHBx, and APBx clocks are OFF 0x2 STANDBY All Clocks are OFF 0x4 BACKUP Only Backup domain is powered ON 0x5 OFF All power domains are powered OFF 0x6 PLCFG Performance Level Configuration 0x02 8 PLSEL Performance Level Select 0 2 PLSELSelect PL0 Performance Level 0 0x0 PL1 Performance Level 1 0x1 PL2 Performance Level 2 0x2 INTENCLR Interrupt Enable Clear 0x04 8 PLRDY Performance Level Interrupt Enable 0 1 write-only INTENSET Interrupt Enable Set 0x05 8 PLRDY Performance Level Ready interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x06 8 PLRDY Performance Level Ready 0 1 STDBYCFG Standby Configuration 0x08 16 PDCFG Power Domain Configuration 0 2 PDCFGSelect DEFAULT All power domains switching is handled by hardware. 0x0 PD0 PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware. 0x1 PD01 PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware. 0x2 PD012 All power domains are forced ACTIVE. 0x3 DPGPD0 Dynamic Power Gating for PD0 4 1 DPGPD1 Dynamic Power Gating for PD1 5 1 AVREGSD Automatic VREG Switching Disable 7 1 LINKPD Linked Power Domain 8 2 LINKPDSelect DEFAULT Power domains are not linked 0x0 PD01 PD0 and PD1 power domains are linked 0x1 PD12 PD1 and PD2 power domains are linked 0x2 PD012 All power domains are linked 0x3 BBIASHS Back Bias for HMCRAMCHS 10 2 BBIASLP Back Bias for HMCRAMCLP 12 2 BBIASPP Back Bias for PicoPram 14 2 PWSAKDLY Power Switch Acknowledge Delay 0x0C 8 DLYVAL Delay Value 0 7 IGNACK Ignore Acknowledge 7 1 PORT 2.0.0 Port Module PORT PORT_ 0x40002800 0 0x200 registers 1 0x80 DIR%s Data Direction 0x00 32 DIR Port Data Direction 0 32 1 0x80 DIRCLR%s Data Direction Clear 0x04 32 DIRCLR Port Data Direction Clear 0 32 1 0x80 DIRSET%s Data Direction Set 0x08 32 DIRSET Port Data Direction Set 0 32 1 0x80 DIRTGL%s Data Direction Toggle 0x0C 32 DIRTGL Port Data Direction Toggle 0 32 1 0x80 OUT%s Data Output Value 0x10 32 OUT Port Data Output Value 0 32 1 0x80 OUTCLR%s Data Output Value Clear 0x14 32 OUTCLR Port Data Output Value Clear 0 32 1 0x80 OUTSET%s Data Output Value Set 0x18 32 OUTSET Port Data Output Value Set 0 32 1 0x80 OUTTGL%s Data Output Value Toggle 0x1C 32 OUTTGL Port Data Output Value Toggle 0 32 1 0x80 IN%s Data Input Value 0x20 32 read-only IN Port Data Input Value 0 32 1 0x80 CTRL%s Control 0x24 32 SAMPLING Input Sampling Mode 0 32 write-only 1 0x80 WRCONFIG%s Write Configuration 0x28 32 write-only PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUXEN Select Peripheral Multiplexer 16 1 INEN Input Enable 17 1 PULLEN Pull Enable 18 1 DRVSTR Output Driver Strength Selection 22 1 PMUX Peripheral Multiplexing Template 24 4 WRPMUX Write PMUX Registers 28 1 WRPINCFG Write PINCFG Registers 30 1 HWSEL Half-Word Select 31 1 1 0x80 EVCTRL%s Event Input Control 0x2C 32 PID0 Port Event Pin Identifier 0 0 5 EVACT0 Port Event Action 0 5 2 PORTEI0 Port Event Enable Input 0 7 1 PID1 Port Event Pin Identifier 1 8 5 EVACT1 Port Event Action 1 13 2 PORTEI1 Port Event Enable Input 1 15 1 PID2 Port Event Pin Identifier 2 16 5 EVACT2 Port Event Action 2 21 2 PORTEI2 Port Event Enable Input 2 23 1 PID3 Port Event Pin Identifier 3 24 5 EVACT3 Port Event Action 3 29 2 PORTEI3 Port Event Enable Input 3 31 1 16 0x1 PMUX0_%s Peripheral Multiplexing n - Group 0 0x30 8 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 32 0x1 PINCFG0_%s Pin Configuration n - Group 0 0x40 8 PMUXEN Select Peripheral Multiplexer 0 1 INEN Input Enable 1 1 PULLEN Pull Enable 2 1 DRVSTR Output Driver Strength Selection 6 1 write-only PORT_IOBUS Port Module (IOBUS) PORT_IOBUS PORT_IOBUS_ 0x60000000 RSTC 1.0.0 Reset Controller RSTC RSTC_ 0x40000800 0 0x20 registers RCAUSE Reset Cause 0x00 8 read-only POR Power On Reset 0 1 BOD12 Brown Out 12 Detector Reset 1 1 BOD33 Brown Out 33 Detector Reset 2 1 EXT External Reset 4 1 WDT Watchdog Reset 5 1 SYST System Reset Request 6 1 BACKUP Backup Reset 7 1 BKUPEXIT Backup Exit Source 0x02 8 read-only EXTWAKE External Wakeup 0 1 read-only RTC Real Timer Counter Interrupt 1 1 read-only BBPS Battery Backup Power Switch 2 1 read-only WKDBCONF Wakeup Debounce Configuration 0x04 8 WKDBCNT Wakeup Debounce Counter 0 5 WKDBCNTSelect OFF No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit. 0x0 2CK32 Input pin shall be active for at least two 32kHz clock period. 0x1 3CK32 Input pin shall be active for at least three 32kHz clock period. 0x2 32CK32 Input pin shall be active for at least 32 32kHz clock period. 0x3 512CK32 Input pin shall be active for at least 512 32kHz clock period. 0x4 4096CK32 Input pin shall be active for at least 4096 32kHz clock period. 0x5 32768CK32 Input pin shall be active for at least 32768 32kHz clock period. 0x6 WKPOL Wakeup Polarity 0x08 16 WKPOL Wakeup Polarity 0 16 WKEN Wakeup Enable 0x0C 16 WKEN Wakeup Enable 0 16 WKCAUSE Wakeup Cause 0x10 16 WKCAUSE Wakeup Cause 0 16 read-only RTC 1.0.0 Real-Time Counter RTC RTC_ 0x40002000 0 0x80 registers RTC 2 MODE0 32-bit Counter with Single 32-bit Compare RtcMode0 0x0 CTRLA MODE0 Control A 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb EVCTRL MODE0 Event Control 0x04 32 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE0 Interrupt Enable Clear 0x08 16 PER0 Periodic Interval 0 Interrupt Enable 0 1 write-only PER1 Periodic Interval 1 Interrupt Enable 1 1 write-only PER2 Periodic Interval 2 Interrupt Enable 2 1 write-only PER3 Periodic Interval 3 Interrupt Enable 3 1 write-only PER4 Periodic Interval 4 Interrupt Enable 4 1 write-only PER5 Periodic Interval 5 Interrupt Enable 5 1 write-only PER6 Periodic Interval 6 Interrupt Enable 6 1 write-only PER7 Periodic Interval 7 Interrupt Enable 7 1 write-only CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE0 Interrupt Enable Set 0x0A 16 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE0 Interrupt Flag Status and Clear 0x0C 16 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 OVF Overflow 15 1 DBGCTRL Debug Control 0x0E 8 DBGRUN Run During Debug 0 1 SYNCBUSY MODE0 Synchronization Busy Status 0x10 32 read-only SWRST Software Reset Busy 0 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only COUNT COUNT Register Busy 3 1 read-only COMP0 COMP 0 Register Busy 5 1 read-only FREQCORR Frequency Correction 0x14 8 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE0 Counter Value 0x18 32 COUNT Counter Value 0 32 1 0x4 COMP%s MODE0 Compare n Value 0x20 32 COMP Compare Value 0 32 4 0x4 GP%s General Purpose 0x40 32 MODE1 16-bit Counter with Two 16-bit Compares MODE0 RtcMode1 0x0 CTRLA MODE1 Control A 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb EVCTRL MODE1 Event Control 0x04 32 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE1 Interrupt Enable Clear 0x08 16 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE1 Interrupt Enable Set 0x0A 16 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0x0C 16 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 DBGCTRL Debug Control 0x0E 8 DBGRUN Run During Debug 0 1 SYNCBUSY MODE1 Synchronization Busy Status 0x10 32 read-only SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 PER PER Register Busy 4 1 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 FREQCORR Frequency Correction 0x14 8 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE1 Counter Value 0x18 16 COUNT Counter Value 0 16 PER MODE1 Counter Period 0x1C 16 PER Counter Period 0 16 2 0x2 COMP%s MODE1 Compare n Value 0x20 16 COMP Compare Value 0 16 4 0x4 GP%s General Purpose 0x40 32 MODE2 Clock/Calendar with Alarm MODE0 RtcMode2 0x0 CTRLA MODE2 Control A 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 CLKREP Clock Representation 6 1 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb EVCTRL MODE2 Event Control 0x04 32 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE2 Interrupt Enable Clear 0x08 16 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE2 Interrupt Enable Set 0x0A 16 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0x0C 16 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 ALARM0 Alarm 0 8 1 OVF Overflow 15 1 DBGCTRL Debug Control 0x0E 8 DBGRUN Run During Debug 0 1 SYNCBUSY MODE2 Synchronization Busy Status 0x10 32 read-only SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 CLOCK CLOCK Register Busy 3 1 ALARM0 ALARM 0 Register Busy 5 1 MASK0 MASK 0 Register Busy 11 1 FREQCORR Frequency Correction 0x14 8 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 CLOCK MODE2 Clock Value 0x18 32 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x0 PM PM when CLKREP in 12-hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 1 0x8 ALARM%s MODE2 Alarm n Value 0x20 32 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM Morning hour 0x0 PM Afternoon hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 1 0x8 MASK%s MODE2 Alarm n Mask 0x24 8 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 4 0x4 GP%s General Purpose 0x40 32 SERCOM0 2.1.0 Serial Communication Interface 0 SERCOM SERCOM_ 0x42000000 0 0x40 registers SERCOM0 8 I2CM I2C Master Mode SercomI2cm 0x0 CTRLA I2CM Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run in Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 MEXTTOEN Master SCL Low Extend Timeout 22 1 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SCLSM SCL Clock Stretch Mode 27 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CM Control B 0x04 32 SMEN Smart Mode Enable 8 1 QCEN Quick Command Enable 9 1 CMD Command 16 2 write-only ACKACT Acknowledge Action 18 1 BAUD I2CM Baud Rate 0x0C 32 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 INTENCLR I2CM Interrupt Enable Clear 0x14 8 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CM Interrupt Enable Set 0x16 8 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CM Interrupt Flag Status and Clear 0x18 8 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 ERROR Combined Error Interrupt 7 1 STATUS I2CM Status 0x1A 16 BUSERR Bus Error 0 1 ARBLOST Arbitration Lost 1 1 RXNACK Received Not Acknowledge 2 1 read-only BUSSTATE Bus State 4 2 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 read-only MEXTTOUT Master SCL Low Extend Timeout 8 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 LENERR Length Error 10 1 SYNCBUSY I2CM Synchronization Busy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only ADDR I2CM Address 0x24 32 ADDR Address Value 0 11 LENEN Length Enable 13 1 HS High Speed Mode 14 1 TENBITEN Ten Bit Addressing Enable 15 1 LEN Length 16 8 DATA I2CM Data 0x28 8 DATA Data Value 0 8 DBGCTRL I2CM Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 I2CS I2C Slave Mode I2CM SercomI2cs 0x0 CTRLA I2CS Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SCLSM SCL Clock Stretch Mode 27 1 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CS Control B 0x04 32 SMEN Smart Mode Enable 8 1 GCMD PMBus Group Command 9 1 AACKEN Automatic Address Acknowledge 10 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only ACKACT Acknowledge Action 18 1 INTENCLR I2CS Interrupt Enable Clear 0x14 8 PREC Stop Received Interrupt Disable 0 1 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CS Interrupt Enable Set 0x16 8 PREC Stop Received Interrupt Enable 0 1 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CS Interrupt Flag Status and Clear 0x18 8 PREC Stop Received Interrupt 0 1 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 STATUS I2CS Status 0x1A 16 BUSERR Bus Error 0 1 COLL Transmit Collision 1 1 RXNACK Received Not Acknowledge 2 1 read-only DIR Read/Write Direction 3 1 read-only SR Repeated Start 4 1 read-only LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 HS High Speed 10 1 SYNCBUSY I2CS Synchronization Busy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only ADDR I2CS Address 0x24 32 GENCEN General Call Address Enable 0 1 ADDR Address Value 1 10 TENBITEN Ten Bit Addressing Enable 15 1 ADDRMASK Address Mask 17 10 DATA I2CS Data 0x28 8 DATA Data Value 0 8 SPI SPI Mode I2CM SercomSpi 0x0 CTRLA SPI Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DIPO Data In Pinout 20 2 FORM Frame Format 24 4 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 CTRLB SPI Control B 0x04 32 CHSIZE Character Size 0 3 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 RXEN Receiver Enable 17 1 BAUD SPI Baud Rate 0x0C 8 BAUD Baud Rate Value 0 8 INTENCLR SPI Interrupt Enable Clear 0x14 8 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPI Interrupt Enable Set 0x16 8 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPI Interrupt Flag Status and Clear 0x18 8 DRE Data Register Empty Interrupt 0 1 read-only TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPI Status 0x1A 16 BUFOVF Buffer Overflow 2 1 SYNCBUSY SPI Synchronization Busy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only CTRLB CTRLB Synchronization Busy 2 1 read-only ADDR SPI Address 0x24 32 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 DATA SPI Data 0x28 32 DATA Data Value 0 9 DBGCTRL SPI Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 USART USART Mode I2CM SercomUsart 0x0 CTRLA USART Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 SAMPR Sample 13 3 TXPO Transmit Data Pinout 16 2 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 CTRLB USART Control B 0x04 32 CHSIZE Character Size 0 3 SBMODE Stop Bit Mode 6 1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 BAUD USART Baud Rate 0x0C 16 BAUD Baud Rate Value 0 16 BAUD_FRAC_MODE USART Baud Rate BAUD 0x0C 16 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRACFP_MODE USART Baud Rate BAUD 0x0C 16 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART Baud Rate BAUD 0x0C 16 BAUD Baud Rate Value 0 16 RXPL USART Receive Pulse Length 0x0E 8 RXPL Receive Pulse Length 0 8 INTENCLR USART Interrupt Enable Clear 0x14 8 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART Interrupt Enable Set 0x16 8 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 DRE Data Register Empty Interrupt 0 1 read-only TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 STATUS USART Status 0x1A 16 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 read-only ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 SYNCBUSY USART Synchronization Busy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only CTRLB CTRLB Synchronization Busy 2 1 read-only DATA USART Data 0x28 16 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 SERCOM1 Serial Communication Interface 1 0x42000400 SERCOM1 9 SERCOM2 Serial Communication Interface 2 0x42000800 SERCOM2 10 SERCOM3 Serial Communication Interface 3 0x42000C00 SERCOM3 11 SUPC 1.0.0 Supply Controller SUPC SUPC_ 0x40001400 0 0x80 registers SYSTEM 0 INTENCLR Interrupt Enable Clear 0x00 32 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 APWSRDY Automatic Power Switch Ready 9 1 VCORERDY VDDCORE Ready 10 1 INTENSET Interrupt Enable Set 0x04 32 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 APWSRDY Automatic Power Switch Ready 9 1 VCORERDY VDDCORE Ready 10 1 INTFLAG Interrupt Flag Status and Clear 0x08 32 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 APWSRDY Automatic Power Switch Ready 9 1 VCORERDY VDDCORE Ready 10 1 STATUS Power and Clocks Status 0x0C 32 read-only BOD33RDY BOD33 Ready 0 1 read-only BOD33DET BOD33 Detection 1 1 read-only B33SRDY BOD33 Synchronization Ready 2 1 read-only BOD12RDY BOD12 Ready 3 1 read-only BOD12DET BOD12 Detection 4 1 read-only B12SRDY BOD12 Synchronization Ready 5 1 read-only VREGRDY Voltage Regulator Ready 8 1 read-only APWSRDY Automatic Power Switch Ready 9 1 read-only VCORERDY VDDCORE Ready 10 1 read-only BBPS Battery Backup Power Switch 11 1 read-only BOD33 BOD33 Control 0x10 32 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INT The BOD33 generates an interrupt 0x2 BKUP The BOD33 puts the device in backup sleep mode if VMON=0 0x3 STDBYCFG Configuration in Standby mode 5 1 RUNSTDBY Run during Standby 6 1 RUNBKUP Configuration in Backup mode 7 1 ACTCFG Configuration in Active mode 8 1 VMON Voltage Monitored in active and standby mode 10 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xa DIV4096 Divide clock by 4096 0xb DIV8192 Divide clock by 8192 0xc DIV16384 Divide clock by 16384 0xd DIV32768 Divide clock by 32768 0xe DIV65536 Divide clock by 65536 0xf LEVEL Threshold Level for VDD 16 6 BKUPLEVEL Threshold Level in backup sleep mode or for VBAT 24 6 BOD12 BOD12 Control 0x14 32 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD12 generates a reset 0x1 INT The BOD12 generates an interrupt 0x2 STDBYCFG Configuration in Standby mode 5 1 RUNSTDBY Run during Standby 6 1 ACTCFG Configuration in Active mode 8 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xa DIV4096 Divide clock by 4096 0xb DIV8192 Divide clock by 8192 0xc DIV16384 Divide clock by 16384 0xd DIV32768 Divide clock by 32768 0xe DIV65536 Divide clock by 65536 0xf LEVEL Threshold Level 16 6 VREG VREG Control 0x18 32 ENABLE Enable 1 1 SEL Voltage Regulator Selection in active mode 2 2 SELSelect LDO LDO selection 0x0 BUCK Buck selection 0x1 SCVREG Switched Cap selection 0x2 RUNSTDBY Run during Standby 6 1 VSVSTEP Voltage Scaling Voltage Step 16 4 VSPER Voltage Scaling Period 24 8 VREF VREF Control 0x1C 32 TSEN Temperature Sensor Output Enable 1 1 VREFOE Voltage Reference Output Enable 2 1 RUNSTDBY Run during Standby 6 1 ONDEMAND On Demand Contrl 7 1 SEL Voltage Reference Selection 16 4 SELSelect 1V0 1.0V voltage reference typical value 0x0 1V1 1.1V voltage reference typical value 0x1 1V2 1.2V voltage reference typical value 0x2 1V25 1.25V voltage reference typical value 0x3 2V0 2.0V voltage reference typical value 0x4 2V2 2.2V voltage reference typical value 0x5 2V4 2.4V voltage reference typical value 0x6 2V5 2.5V voltage reference typical value 0x7 BBPS Battery Backup Power Switch 0x20 32 CONF Battery Backup Configuration 0 2 CONFSelect NONE The backup domain is always supplied by main power 0x0 APWS The power switch is handled by the automatic power switch 0x1 FORCED The backup domain is always supplied by battery backup power 0x2 BOD33 The power switch is handled by the BOD33 0x3 WAKEEN Wake Enable 2 1 PSOKEN Power Supply OK Enable 3 1 BKOUT Backup Output Control 0x24 32 EN Enable Output 0 2 CLR Clear Output 8 2 write-only SET Set Output 16 2 write-only RTCTGL RTC Toggle Output 24 2 BKIN Backup Input Control 0x28 32 read-only BKIN Backup Input Value 0 8 read-only TC0 1.0.0 Basic Timer Counter 0 TC TC_ 0x42002000 0 0x40 registers TC0 17 COUNT8 8-bit Counter Mode TcCount8 0x0 CTRLA Control A 0x00 32 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CTRLBCLR Control B Clear 0x04 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 EVCTRL Event Control 0x06 16 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x08 8 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x09 8 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0x0A 8 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0x0B 8 0x01 STOP Stop Status Flag 0 1 read-only SLAVE Slave Status Flag 1 1 read-only PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0x0C 8 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 DRVCTRL Control C 0x0D 8 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0x0F 8 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT8 Count 0x14 8 COUNT Counter Value 0 8 PER COUNT8 Period 0x1B 8 0xFF PER Period Value 0 8 2 0x1 CC%s COUNT8 Compare and Capture 0x1C 8 CC Counter/Compare Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 0xFF PERBUF Period Buffer Value 0 8 2 0x1 CCBUF%s COUNT8 Compare and Capture Buffer 0x30 8 CCBUF Counter/Compare Buffer Value 0 8 COUNT16 16-bit Counter Mode COUNT8 TcCount16 0x0 CTRLA Control A 0x00 32 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CTRLBCLR Control B Clear 0x04 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 EVCTRL Event Control 0x06 16 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x08 8 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x09 8 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0x0A 8 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0x0B 8 0x01 STOP Stop Status Flag 0 1 read-only SLAVE Slave Status Flag 1 1 read-only PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0x0C 8 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 DRVCTRL Control C 0x0D 8 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0x0F 8 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT16 Count 0x14 16 COUNT Counter Value 0 16 2 0x2 CC%s COUNT16 Compare and Capture 0x1C 16 CC Counter/Compare Value 0 16 2 0x2 CCBUF%s COUNT16 Compare and Capture Buffer 0x30 16 CCBUF Counter/Compare Buffer Value 0 16 COUNT32 32-bit Counter Mode COUNT8 TcCount32 0x0 CTRLA Control A 0x00 32 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CTRLBCLR Control B Clear 0x04 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 EVCTRL Event Control 0x06 16 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x08 8 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x09 8 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0x0A 8 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0x0B 8 0x01 STOP Stop Status Flag 0 1 read-only SLAVE Slave Status Flag 1 1 read-only PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0x0C 8 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 DRVCTRL Control C 0x0D 8 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0x0F 8 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT32 Count 0x14 32 COUNT Counter Value 0 32 2 0x4 CC%s COUNT32 Compare and Capture 0x1C 32 CC Counter/Compare Value 0 32 2 0x4 CCBUF%s COUNT32 Compare and Capture Buffer 0x30 32 CCBUF Counter/Compare Buffer Value 0 32 TC1 Basic Timer Counter 1 0x42002400 TC1 18 TC4 Basic Timer Counter 4 0x43000800 TC4 21 TCC0 2.0.0 Timer Counter Control 0 TCC TCC_ 0x42001400 0 0x090 registers TCC0 14 CTRLA Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 ALOCK Auto Lock 14 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CTRLBCLR Control B Clear 0x04 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 SYNCBUSY Synchronization Busy 0x08 32 read-only SWRST Swrst Busy 0 1 ENABLE Enable Busy 1 1 CTRLB Ctrlb Busy 2 1 STATUS Status Busy 3 1 COUNT Count Busy 4 1 PATT Pattern Busy 5 1 WAVE Wave Busy 6 1 PER Period Busy 7 1 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 FCTRLA Recoverable Fault A Configuration 0x0C 32 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 RESTART Fault A Restart 7 1 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 FILTERVAL Fault A Filter Value 24 4 FCTRLB Recoverable Fault B Configuration 0x10 32 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 RESTART Fault B Restart 7 1 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 FILTERVAL Fault B Filter Value 24 4 WEXCTRL Waveform Extension Configuration 0x14 32 OTMX Output Matrix 0 2 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 DTHS Dead-time High Side Outputs Value 24 8 DRVCTRL Driver Control 0x18 32 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 DBGCTRL Debug Control 0x1E 8 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 EVCTRL Event Control 0x20 32 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 OVFEO Overflow/Underflow Output Event Enable 8 1 TRGEO Retrigger Output Event Enable 9 1 CNTEO Timer/counter Output Event Enable 10 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 INTENCLR Interrupt Enable Clear 0x24 32 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 INTENSET Interrupt Enable Set 0x28 32 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 OVF Overflow 0 1 TRG Retrigger 1 1 CNT Counter 2 1 ERR Error 3 1 UFS Non-Recoverable Update Fault 10 1 DFS Non-Recoverable Debug Fault 11 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 STATUS Status 0x30 32 0x00000001 STOP Stop 0 1 read-only IDX Ramp 1 1 read-only UFS Non-recoverable Update Fault State 2 1 DFS Non-Recoverable Debug Fault State 3 1 SLAVE Slave 4 1 read-only PATTBUFV Pattern Buffer Valid 5 1 WAVEBUFV Wave Buffer Valid 6 1 PERBUFV Period Buffer Valid 7 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTBIN Recoverable Fault B Input 9 1 read-only FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTB Recoverable Fault B State 13 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT1 Non-Recoverable Fault 1 State 15 1 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only COUNT Count 0x34 32 COUNT Counter Value 0 24 COUNT_DITH4 Count COUNT 0x34 32 COUNT Counter Value 4 20 COUNT_DITH5 Count COUNT 0x34 32 COUNT Counter Value 5 19 COUNT_DITH6 Count COUNT 0x34 32 COUNT Counter Value 6 18 PATT Pattern 0x38 16 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 WAVE Waveform Control 0x3C 32 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 CIPEREN Circular period Enable 7 1 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 PER Period 0x40 32 0xFFFFFFFF PER Period Value 0 24 PER_DITH4 Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 4 0x4 CC%s Compare and Capture 0x44 32 CC Channel Compare/Capture Value 0 24 4 0x4 CC%s_DITH4 Compare and Capture CC%s 0x44 32 DITHER Dithering Cycle Number 0 4 CC Channel Compare/Capture Value 4 20 4 0x4 CC%s_DITH5 Compare and Capture CC%s 0x44 32 DITHER Dithering Cycle Number 0 5 CC Channel Compare/Capture Value 5 19 4 0x4 CC%s_DITH6 Compare and Capture CC%s 0x44 32 DITHER Dithering Cycle Number 0 6 CC Channel Compare/Capture Value 6 18 PATTBUF Pattern Buffer 0x64 16 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 WAVEBUF Waveform Control Buffer 0x68 32 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 RAMPB Ramp Mode Buffer 4 2 CIPERENB Circular Period Enable Buffer 7 1 CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 PERBUF Period Buffer 0x6C 32 0xFFFFFFFF PERBUF Period Buffer Value 0 24 PERBUF_DITH4 Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5 Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6 Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 4 0x4 CCBUF%s Compare and Capture Buffer 0x70 32 CCBUF Channel Compare/Capture Buffer Value 0 24 4 0x4 CCBUF%s_DITH4 Compare and Capture Buffer CCBUF%s 0x70 32 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 4 0x4 CCBUF%s_DITH5 Compare and Capture Buffer CCBUF%s 0x70 32 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF Channel Compare/Capture Buffer Value 5 19 4 0x4 CCBUF%s_DITH6 Compare and Capture Buffer CCBUF%s 0x70 32 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF Channel Compare/Capture Buffer Value 6 18 TCC1 Timer Counter Control 1 0x42001800 TCC1 15 TCC2 Timer Counter Control 2 0x42001C00 TCC2 16 TRNG 1.0.0 True Random Generator TRNG TRNG_ 0x42003800 0 0x40 registers TRNG 27 CTRLA Control A 0x00 8 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 EVCTRL Event Control 0x04 8 DATARDYEO Data Ready Event Output 0 1 INTENCLR Interrupt Enable Clear 0x08 8 DATARDY Data Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x09 8 DATARDY Data Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x0A 8 DATARDY Data Ready Interrupt Flag 0 1 DATA Output Data 0x20 32 read-only DATA Output Data 0 32 USB 1.1.0 Universal Serial Bus USB USB_ 0x41000000 0 0x400 registers USB 6 DEVICE USB is Device UsbDevice 0x0 CTRLA Control A 0x000 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby Mode 2 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 SYNCBUSY Synchronization Busy 0x002 8 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only QOSCTRL USB Quality Of Service 0x003 8 0x15 CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 CTRLB DEVICE Control B 0x008 16 0x0001 DETACH Detach 0 1 UPRSM Upstream Resume 1 1 SPDCONF Speed Configuration 2 2 SPDCONFSelect FS FS : Full Speed 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 NREPLY No Reply 4 1 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 OPMODE2 Specific Operational Mode 8 1 GNAK Global NAK 9 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0x0 ACK ACK 0x1 NYET NYET 0x2 STALL STALL 0x3 DADD DEVICE Device Address 0x00A 8 DADD Device Address 0 7 ADDEN Device Address Enable 7 1 STATUS DEVICE Status 0x00C 8 read-only 0x40 SPEED Speed Status 2 2 read-only SPEEDSelect FS Full-speed mode 0x0 HS High-speed mode 0x1 LS Low-speed mode 0x2 LINESTATE USB Line State Status 6 2 read-only LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 FSMSTATUS Finite State Machine Status 0x00D 8 read-only 0x01 FSMSTATE Fine State Machine Status 0 7 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 ON ON (L0). It corresponds to the Idle and Active states 0x2 SUSPEND SUSPEND (L2) 0x4 SLEEP SLEEP (L1) 0x8 DNRESUME DNRESUME. Down Stream Resume. 0x10 UPRESUME UPRESUME. Up Stream Resume. 0x20 RESET RESET. USB lines Reset. 0x40 FNUM DEVICE Device Frame Number 0x010 16 read-only MFNUM Micro Frame Number 0 3 read-only FNUM Frame Number 3 11 read-only FNCERR Frame Number CRC Error 15 1 read-only INTENCLR DEVICE Device Interrupt Enable Clear 0x014 16 SUSPEND Suspend Interrupt Enable 0 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 SOF Start Of Frame Interrupt Enable 2 1 EORST End of Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 EORSM End Of Resume Interrupt Enable 5 1 UPRSM Upstream Resume Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 INTENSET DEVICE Device Interrupt Enable Set 0x018 16 SUSPEND Suspend Interrupt Enable 0 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 SOF Start Of Frame Interrupt Enable 2 1 EORST End of Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 EORSM End Of Resume Interrupt Enable 5 1 UPRSM Upstream Resume Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 INTFLAG DEVICE Device Interrupt Flag 0x01C 16 SUSPEND Suspend 0 1 MSOF Micro Start of Frame in High Speed Mode 1 1 SOF Start Of Frame 2 1 EORST End of Reset 3 1 WAKEUP Wake Up 4 1 EORSM End Of Resume 5 1 UPRSM Upstream Resume 6 1 RAMACER Ram Access 7 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 EPINTSMRY DEVICE End Point Interrupt Summary 0x020 16 read-only EPINT0 End Point 0 Interrupt 0 1 read-only EPINT1 End Point 1 Interrupt 1 1 read-only EPINT2 End Point 2 Interrupt 2 1 read-only EPINT3 End Point 3 Interrupt 3 1 read-only EPINT4 End Point 4 Interrupt 4 1 read-only EPINT5 End Point 5 Interrupt 5 1 read-only EPINT6 End Point 6 Interrupt 6 1 read-only EPINT7 End Point 7 Interrupt 7 1 read-only DESCADD Descriptor Address 0x024 32 DESCADD Descriptor Address Value 0 32 PADCAL USB PAD Calibration 0x028 16 TRANSP USB Pad Transp calibration 0 5 TRANSN USB Pad Transn calibration 6 5 TRIM USB Pad Trim calibration 12 3 8 0x20 EPCFG%s DEVICE End Point Configuration 0x100 8 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 8 0x20 EPSTATUSCLR%s DEVICE End Point Pipe Status Clear 0x104 8 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only CURBK Current Bank Clear 2 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only 8 0x20 EPSTATUSSET%s DEVICE End Point Pipe Status Set 0x105 8 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only CURBK Current Bank Set 2 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only 8 0x20 EPSTATUS%s DEVICE End Point Pipe Status 0x106 8 read-only DTGLOUT Data Toggle Out 0 1 read-only DTGLIN Data Toggle In 1 1 read-only CURBK Current Bank 2 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only 8 0x20 EPINTFLAG%s DEVICE End Point Interrupt Flag 0x107 8 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 8 0x20 EPINTENCLR%s DEVICE End Point Interrupt Clear Flag 0x108 8 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 8 0x20 EPINTENSET%s DEVICE End Point Interrupt Set Flag 0x109 8 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 HOST USB is Host DEVICE UsbHost 0x0 CTRLA Control A 0x000 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby Mode 2 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 SYNCBUSY Synchronization Busy 0x002 8 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only QOSCTRL USB Quality Of Service 0x003 8 0x15 CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 CTRLB HOST Control B 0x008 16 RESUME Send USB Resume 1 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 AUTORESUME Auto Resume Enable 4 1 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 SOFE Start of Frame Generation Enable 8 1 BUSRESET Send USB Reset 9 1 VBUSOK VBUS is OK 10 1 L1RESUME Send L1 Resume 11 1 HSOFC HOST Host Start Of Frame Control 0x00A 8 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 STATUS HOST Status 0x00C 8 SPEED Speed Status 2 2 LINESTATE USB Line State Status 6 2 read-only FSMSTATUS Finite State Machine Status 0x00D 8 read-only 0x01 FSMSTATE Fine State Machine Status 0 7 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 ON ON (L0). It corresponds to the Idle and Active states 0x2 SUSPEND SUSPEND (L2) 0x4 SLEEP SLEEP (L1) 0x8 DNRESUME DNRESUME. Down Stream Resume. 0x10 UPRESUME UPRESUME. Up Stream Resume. 0x20 RESET RESET. USB lines Reset. 0x40 FNUM HOST Host Frame Number 0x010 16 MFNUM Micro Frame Number 0 3 FNUM Frame Number 3 11 FLENHIGH HOST Host Frame Length 0x012 8 read-only FLENHIGH Frame Length 0 8 read-only INTENCLR HOST Host Interrupt Enable Clear 0x014 16 HSOF Host Start Of Frame Interrupt Disable 2 1 RST BUS Reset Interrupt Disable 3 1 WAKEUP Wake Up Interrupt Disable 4 1 DNRSM DownStream to Device Interrupt Disable 5 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 RAMACER Ram Access Interrupt Disable 7 1 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 INTENSET HOST Host Interrupt Enable Set 0x018 16 HSOF Host Start Of Frame Interrupt Enable 2 1 RST Bus Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 DNRSM DownStream to the Device Interrupt Enable 5 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 INTFLAG HOST Host Interrupt Flag 0x01C 16 HSOF Host Start Of Frame 2 1 RST Bus Reset 3 1 WAKEUP Wake Up 4 1 DNRSM Downstream 5 1 UPRSM Upstream Resume from the Device 6 1 RAMACER Ram Access 7 1 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 PINTSMRY HOST Pipe Interrupt Summary 0x020 16 read-only EPINT0 Pipe 0 Interrupt 0 1 read-only EPINT1 Pipe 1 Interrupt 1 1 read-only EPINT2 Pipe 2 Interrupt 2 1 read-only EPINT3 Pipe 3 Interrupt 3 1 read-only EPINT4 Pipe 4 Interrupt 4 1 read-only EPINT5 Pipe 5 Interrupt 5 1 read-only EPINT6 Pipe 6 Interrupt 6 1 read-only EPINT7 Pipe 7 Interrupt 7 1 read-only DESCADD Descriptor Address 0x024 32 DESCADD Descriptor Address Value 0 32 PADCAL USB PAD Calibration 0x028 16 TRANSP USB Pad Transp calibration 0 5 TRANSN USB Pad Transn calibration 6 5 TRIM USB Pad Trim calibration 12 3 8 0x20 PCFG%s HOST End Point Configuration 0x100 8 PTOKEN Pipe Token 0 2 BK Pipe Bank 2 1 PTYPE Pipe Type 3 3 8 0x20 BINTERVAL%s HOST Bus Access Period of Pipe 0x103 8 BITINTERVAL Bit Interval 0 8 8 0x20 PSTATUSCLR%s HOST End Point Pipe Status Clear 0x104 8 write-only DTGL Data Toggle clear 0 1 read-only CURBK Curren Bank clear 2 1 write-only PFREEZE Pipe Freeze Clear 4 1 write-only BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only 8 0x20 PSTATUSSET%s HOST End Point Pipe Status Set 0x105 8 write-only DTGL Data Toggle Set 0 1 write-only CURBK Current Bank Set 2 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only 8 0x20 PSTATUS%s HOST End Point Pipe Status 0x106 8 read-only DTGL Data Toggle 0 1 read-only CURBK Current Bank 2 1 read-only PFREEZE Pipe Freeze 4 1 read-only BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only 8 0x20 PINTFLAG%s HOST Pipe Interrupt Flag 0x107 8 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 PERR Pipe Error Interrupt Flag 3 1 TXSTP Transmit Setup Interrupt Flag 4 1 STALL Stall Interrupt Flag 5 1 8 0x20 PINTENCLR%s HOST Pipe Interrupt Flag Clear 0x108 8 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 PERR Pipe Error Interrupt Disable 3 1 TXSTP Transmit Setup Interrupt Disable 4 1 STALL Stall Inetrrupt Disable 5 1 8 0x20 PINTENSET%s HOST Pipe Interrupt Flag Set 0x109 8 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 PERR Pipe Error Interrupt Enable 3 1 TXSTP Transmit Setup Interrupt Enable 4 1 STALL Stall Interrupt Enable 5 1 WDT 1.0.0 Watchdog Timer WDT WDT_ 0x40001C00 0 0x10 registers WDT 1 CTRLA Control 0x0 8 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 ALWAYSON Always-On 7 1 CONFIG Configuration 0x1 8 0xBB PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb EWCTRL Early Warning Interrupt Control 0x2 8 0x0B EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb INTENCLR Interrupt Enable Clear 0x4 8 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only ENABLE Enable Busy 1 1 read-only WEN Window Enable Busy 2 1 read-only ALWAYSON Always-On Busy 3 1 read-only CLEAR Clear Busy 4 1 read-only CLEAR Clear 0xC 8 write-only CLEAR Watchdog Clear 0 8 write-only CLEARSelect KEY Clear Key 0xa5