bouffalolab bouffalolab BL602 WiFi BT high-performance, 32-bit RV32IMAFC core 8 32 32 0x00000000 0xFFFFFFFF GLB Global register 0x40000000 GLB 32 read-write 0 0x1000 registers clk_cfg0 Clock configuration for processor and bus 0x0 0x6000000f 0xffffffff glb_id read-only 28 31 chip_rdy 27 27 read-only fclk_sw_state 24 26 read-only reg_bclk_div Base clock divider 16 23 reg_hclk_div MCU clock divider 8 15 hbn_root_clk_sel 6 7 read-only reg_pll_sel PLL clock selection (0: 48MHz, 1: 120MHz, 2: 160MHz and 3: 192MHz) 4 5 reg_bclk_en Base clock enable 3 3 reg_hclk_en MCU clock enable 2 2 reg_fclk_en 1 1 reg_pll_en PLL enable 0 0 clk_cfg1 clk_cfg1. 0x4 0x01100001 0xffffffff ble_en Bluetooth clock enable 24 24 ble_clk_sel 16 21 wifi_mac_wt_div WiFi encryption clock divider 4 7 wifi_mac_core_div WiFi core clock divider (0: 80MHz, 1: 40MHz) 0 3 clk_cfg2 Clock configuration for UART and Flash 0x8 0xff8f2b17 0xffffffff dma_clk_en 24 31 ir_clk_en 23 23 ir_clk_div 16 21 sf_clk_sel2 14 15 sf_clk_sel 12 13 sf_clk_en 11 11 sf_clk_div 8 10 hbn_uart_clk_sel 7 7 read-only uart_clk_en 4 4 uart_clk_div 0 2 clk_cfg3 Clock configuration for I2C and SPI 0xC 0x01ff0103 0xffffffff i2c_clk_en 24 24 i2c_clk_div 16 23 spi_clk_en 8 8 spi_clk_div 0 4 swrst_cfg0 swrst_cfg0. 0x10 0x00000000 0xffffffff swrst_s30 8 8 swrst_s20 4 4 swrst_s01 1 1 swrst_s00 0 0 swrst_cfg1 swrst_cfg1. 0x14 0x00000000 0xffffffff swrst_s1a7 23 23 swrst_s1a6 22 22 swrst_s1a5 21 21 swrst_s1a4 20 20 swrst_s1a3 19 19 swrst_s1a2 18 18 swrst_s1a1 17 17 swrst_s1a0 16 16 swrst_s1f 15 15 swrst_s1e 14 14 swrst_s1d 13 13 swrst_s1c 12 12 swrst_s1b 11 11 swrst_s1a 10 10 swrst_s19 9 9 swrst_s18 8 8 swrst_s17 7 7 swrst_s16 6 6 swrst_s15 5 5 swrst_s14 4 4 swrst_s13 3 3 swrst_s12 2 2 swrst_s11 1 1 swrst_s10 0 0 swrst_cfg2 swrst_cfg2. 0x18 0x00000000 0xffffffff pka_clk_sel 24 24 reg_ctrl_reset_dummy 4 7 reg_ctrl_sys_reset 2 2 reg_ctrl_cpu_reset 1 1 reg_ctrl_pwron_rst 0 0 swrst_cfg3 swrst_cfg3. 0x1C 0x00000000 0xffffffff cgen_cfg0 cgen_cfg0. 0x20 0x000000ff 0xffffffff cgen_m 0 7 cgen_cfg1 cgen_cfg1. 0x24 0x00ffffff 0xffffffff cgen_s1a 16 23 cgen_s1 0 15 cgen_cfg2 cgen_cfg2. 0x28 0x00000011 0xffffffff cgen_s3 4 4 cgen_s2 0 0 cgen_cfg3 cgen_cfg3. 0x2C 0x00000000 0xffffffff MBIST_CTL MBIST_CTL. 0x30 0x00000000 0xffffffff reg_mbist_rst_n 31 31 wifi_mbist_mode 4 4 ocram_mbist_mode 3 3 tag_mbist_mode 2 2 hsram_mbist_mode 1 1 irom_mbist_mode 0 0 MBIST_STAT MBIST_STAT. 0x34 0x00000000 0xffffffff read-only wifi_mbist_fail 20 20 ocram_mbist_fail 19 19 tag_mbist_fail 18 18 hsram_mbist_fail 17 17 irom_mbist_fail 16 16 wifi_mbist_done 4 4 ocram_mbist_done 3 3 tag_mbist_done 2 2 hsram_mbist_done 1 1 irom_mbist_done 0 0 bmx_cfg1 bmx_cfg1. 0x50 0x00000000 0xffffffff hbn_apb_cfg 24 31 pds_apb_cfg 16 23 hsel_option 12 15 bmx_gating_dis 10 10 bmx_busy_option_dis 9 9 bmx_err_en 8 8 bmx_arb_mode 4 5 bmx_timeout_en 0 3 bmx_cfg2 bmx_cfg2. 0x54 0x00000000 0xffffffff bmx_dbg_sel 28 31 bmx_err_tz 5 5 read-only bmx_err_dec 4 4 read-only bmx_err_addr_dis BMX address monitor disable 0 0 bmx_err_addr bmx_err_addr. 0x58 0x00000000 0xffffffff read-only bmx_err_addr 0 31 bmx_dbg_out bmx_dbg_out. 0x5C 0x00000000 0xffffffff read-only bmx_dbg_out 0 31 rsv0 rsv0. 0x60 rsvd_31_0 0 31 rsv1 rsv1. 0x64 rsvd_31_0 0 31 rsv2 rsv2. 0x68 rsvd_31_0 0 31 rsv3 rsv3. 0x6C rsvd_31_0 0 31 sram_ret sram_ret. 0x70 0x00000000 0xffffffff reg_sram_ret 0 31 sram_slp sram_slp. 0x74 0x00000000 0xffffffff reg_sram_slp 0 31 sram_parm sram_parm. 0x78 0x0c0c0c0c 0xffffffff reg_sram_parm 0 31 seam_misc seam_misc. 0x7C 0x00000003 0xffffffff em_sel 0 3 glb_parm glb_parm. 0x80 0x00018300 0xffffffff uart_swap_set 24 26 p7_jtag_use_io_2_5 23 23 p6_sdio_use_io_0_5 22 22 p5_dac_test_with_jtag 21 21 p4_adc_test_with_jtag 20 20 p3_cci_use_io_2_5 19 19 p2_dac_test_with_cci 18 18 p1_adc_test_with_cci 17 17 reg_cci_use_sdio_pin 16 16 reg_cci_use_jtag_pin 15 15 reg_spi_0_swap 13 13 reg_spi_0_master_mode 12 12 sel_embedded_sflash 9 9 swap_sflash_io_3_io_0 8 8 jtag_swap_set 2 7 reg_ext_rst_smt 1 1 reg_bd_en 0 0 CPU_CLK_CFG CPU_CLK_CFG. 0x90 0x00080010 0xffffffff debug_ndreset_gate 20 20 cpu_rtc_sel 19 19 cpu_rtc_en 18 18 cpu_rtc_div 0 16 GPADC_32M_SRC_CTRL Clock configuration for GPADC 0xA4 0x00000102 0xffffffff gpadc_32m_div_en 8 8 gpadc_32m_clk_sel 7 7 gpadc_32m_clk_div 0 5 DIG32K_WAKEUP_CTRL DIG32K_WAKEUP_CTRL. 0xA8 0x033e13e8 0xffffffff reg_en_platform_wakeup 31 31 dig_clk_src_sel 28 28 dig_512k_comp 25 25 dig_512k_en 24 24 dig_512k_div 16 22 dig_32k_comp 13 13 dig_32k_en 12 12 dig_32k_div 0 10 WIFI_BT_COEX_CTRL WIFI_BT_COEX_CTRL. 0xAC 0x00000000 0xffffffff en_gpio_bt_coex 12 12 coex_bt_bw 11 11 coex_bt_pti 7 10 coex_bt_channel 0 6 UART_SIG_SEL_0 UART_SIG_SEL_0. 0xC0 0x76543210 0xffffffff uart_sig_7_sel 28 31 uart_sig_6_sel 24 27 uart_sig_5_sel 20 23 uart_sig_4_sel 16 19 uart_sig_3_sel 12 15 uart_sig_2_sel 8 11 uart_sig_1_sel 4 7 uart_sig_0_sel 0 3 DBG_SEL_LL DBG_SEL_LL. 0xD0 0x00000000 0xffffffff reg_dbg_ll_ctrl 0 31 DBG_SEL_LH DBG_SEL_LH. 0xD4 0x00000000 0xffffffff reg_dbg_lh_ctrl 0 31 DBG_SEL_HL DBG_SEL_HL. 0xD8 0x00000000 0xffffffff reg_dbg_hl_ctrl 0 31 DBG_SEL_HH DBG_SEL_HH. 0xDC 0x00000000 0xffffffff reg_dbg_hh_ctrl 0 31 debug debug. 0xE0 0x00000000 0xffffffff debug_i 1 31 read-only debug_oe 0 0 GPIO_CFGCTL0 GPIO0, GPIO1 configuration 0x100 0x11031103 0xffffffff real_gpio_1_func_sel 28 31 read-only GPIO1RealFunctionSelect GLB_GPIO_REAL_MODE_REG Function select is reg_gpio_1_func_sel 0 GLB_GPIO_REAL_MODE_SDIO 1 GLB_GPIO_REAL_MODE_RF 12 GLB_GPIO_REAL_MODE_JTAG 14 GLB_GPIO_REAL_MODE_CCI 15 reg_gpio_1_func_sel 24 27 Function select for GPIO1. GPIO1FunctionSelect SDIO_CMD 1 SF_D2 2 SPI_MOSI_SPI_MISO 4 I2C_SDA 6 UART_SIG1 7 PWM_CH1 8 FEM_GPIO_1 9 ATEST_IP 10 SWGPIO_1 11 E21_TDI 14 reg_gpio_1_pd 21 21 Pull Down Resistor for GPIO1. GPIO1PullDownResistor disabled 0 enabled 1 reg_gpio_1_pu 20 20 Pull Up Resistor for GPIO1. GPIO1PullUpResistor disabled 0 enabled 1 reg_gpio_1_drv 18 19 Driving control enabled for GPIO1. GPIO1Driving disabled 0 enabled 1 reg_gpio_1_smt 17 17 Schmitt trigger enabled for GPIO1. GPIO1Schmitt disabled 0 enabled 1 reg_gpio_1_ie 16 16 Input enable for GPIO1. GPIO1InputEnabled disabled 0 enabled 1 real_gpio_0_func_sel 12 15 read-only GPIO0RealFunctionSelect GLB_GPIO_REAL_MODE_REG Function select is reg_gpio_0_func_sel 0 GLB_GPIO_REAL_MODE_SDIO 1 GLB_GPIO_REAL_MODE_RF 12 GLB_GPIO_REAL_MODE_JTAG 14 GLB_GPIO_REAL_MODE_CCI 15 reg_gpio_0_func_sel 8 11 Function select for GPIO0. GPIO0FunctionSelect SDIO_CLK 1 SF_D1 2 SPI_MOSI_SPI_MISO 4 I2C_SCL 6 UART_SIG0 7 PWM_CH0 8 FEM_GPIO_0 9 ATEST_IN 10 SWGPIO_0 11 E21_TMS 14 reg_gpio_0_pd 5 5 Pull Down Resistor for GPIO0. GPIO0PullDownResistor disabled 0 enabled 1 reg_gpio_0_pu 4 4 Pull Up Resistor for GPIO0. GPIO0PullUpResistor disabled 0 enabled 1 reg_gpio_0_drv 2 3 Driving control for GPIO0. GPIO0Driving disabled 0 enabled 1 reg_gpio_0_smt 1 1 Schmitt trigger enabled for GPIO0. GPIO0Schmitt disabled 0 enabled 1 reg_gpio_0_ie 0 0 GPIO0 input enable. GPIO0InputEnabled disabled 0 enabled 1 GPIO_CFGCTL1 GPIO2, GPIO3 configuration 0x104 0x11031103 0xffffffff real_gpio_3_func_sel 28 31 read-only GPIO3RealFunctionSelect GLB_GPIO_REAL_MODE_REG Function select is reg_gpio_3_func_sel 0 GLB_GPIO_REAL_MODE_SDIO 1 GLB_GPIO_REAL_MODE_RF 12 GLB_GPIO_REAL_MODE_JTAG 14 GLB_GPIO_REAL_MODE_CCI 15 reg_gpio_3_func_sel 24 27 Function select for GPIO3. GPIO3FunctionSelect SDIO_DAT1 1 SPI_SCLK 4 I2C_SDA 6 UART_SIG3 7 PWM_CH3 8 FEM_GPIO_3 9 ATEST_QP 10 SWGPIO_3 11 E21_TDO 14 reg_gpio_3_pd 21 21 Pull Down Resistor for GPIO3. GPIO3PullDownResistor disabled 0 enabled 1 reg_gpio_3_pu 20 20 Pull Up Resistor for GPIO3. GPIO3PullUpResistor disabled 0 enabled 1 reg_gpio_3_drv 18 19 Driving control enabled for GPIO3. GPIO3Driving disabled 0 enabled 1 reg_gpio_3_smt 17 17 Schmitt trigger enabled for GPIO3. GPIO3Schmitt disabled 0 enabled 1 reg_gpio_3_ie 16 16 Input enable for GPIO3. GPIO3InputEnabled disabled 0 enabled 1 real_gpio_2_func_sel 12 15 read-only GPIO2RealFunctionSelect GLB_GPIO_REAL_MODE_REG Function select is reg_gpio_2_func_sel 0 GLB_GPIO_REAL_MODE_SDIO 1 GLB_GPIO_REAL_MODE_RF 12 GLB_GPIO_REAL_MODE_JTAG 14 GLB_GPIO_REAL_MODE_CCI 15 reg_gpio_2_func_sel 8 11 Function select for GPIO2. GPIO2FunctionSelect SDIO_DAT0 1 SF_D3 2 SPI_SS 4 I2C_SCL 6 UART_SIG2 7 PWM_CH2 8 FEM_GPIO_2 9 ATEST_QN 10 SWGPIO_2 11 E21_TCK 14 reg_gpio_2_pd 5 5 Pull Down Resistor for GPIO2. GPIO2PullDownResistor disabled 0 enabled 1 reg_gpio_2_pu 4 4 Pull Up Resistor for GPIO2. GPIO2PullUpResistor disabled 0 enabled 1 reg_gpio_2_drv 2 3 Driving control enabled for GPIO2. GPIO2Driving disabled 0 enabled 1 reg_gpio_2_smt 1 1 Schmitt trigger enabled for GPIO2. GPIO2Schmitt disabled 0 enabled 1 reg_gpio_2_ie 0 0 Input enable for GPIO2. GPIO2InputEnabled disabled 0 enabled 1 GPIO_CFGCTL2 GPIO4, GPIO5 configuration 0x108 0x11031103 0xffffffff real_gpio_5_func_sel 28 31 read-only GPIO5RealFunctionSelect GLB_GPIO_REAL_MODE_REG Function select is reg_gpio_5_func_sel 0 GLB_GPIO_REAL_MODE_SDIO 1 GLB_GPIO_REAL_MODE_RF 12 GLB_GPIO_REAL_MODE_JTAG 14 GLB_GPIO_REAL_MODE_CCI 15 reg_gpio_5_func_sel 24 27 Function select for GPIO5. GPIO5FunctionSelect SDIO_DAT3 1 SPI_MOSI_SPI_MISO 4 I2C_SDA 6 UART_SIG5 7 PWM_CH0 8 FEM_GPIO_1 9 GPIP_CH4 10 SWGPIO_5 11 E21_TDI 14 reg_gpio_5_pd 21 21 Pull Down Resistor for GPIO5. GPIO5PullDownResistor disabled 0 enabled 1 reg_gpio_5_pu 20 20 Pull Up Resistor for GPIO5. GPIO5PullUpResistor disabled 0 enabled 1 reg_gpio_5_drv 18 19 Driving control enabled for GPIO5. GPIO5Driving disabled 0 enabled 1 reg_gpio_5_smt 17 17 Schmitt trigger enabled for GPIO5. GPIO5Schmitt disabled 0 enabled 1 reg_gpio_5_ie 16 16 Input enable for GPIO5. GPIO5InputEnabled disabled 0 enabled 1 real_gpio_4_func_sel 12 15 read-only GPIO4RealFunctionSelect GLB_GPIO_REAL_MODE_REG Function select is reg_gpio_4_func_sel 0 GLB_GPIO_REAL_MODE_SDIO 1 GLB_GPIO_REAL_MODE_RF 12 GLB_GPIO_REAL_MODE_JTAG 14 GLB_GPIO_REAL_MODE_CCI 15 reg_gpio_4_func_sel 8 11 Function select for GPIO4. GPIO4FunctionSelect SDIO_DAT2 1 SPI_MISO_SPI_MOSI 4 I2C_SCL 6 UART_SIG4 7 PWM_CH4 8 FEM_GPIO_0 9 GPIP_CH1 10 SWGPIO_4 11 E21_TMS 14 reg_gpio_4_pd 5 5 Pull Down Resistor for GPIO4. GPIO4PullDownResistor disabled 0 enabled 1 reg_gpio_4_pu 4 4 Pull Up Resistor for GPIO4. GPIO4PullUpResistor disabled 0 enabled 1 reg_gpio_4_drv 2 3 Driving control enabled for GPIO4. GPIO4Driving disabled 0 enabled 1 reg_gpio_4_smt 1 1 Schmitt trigger enabled for GPIO4. GPIO4Schmitt disabled 0 enabled 1 reg_gpio_4_ie 0 0 Input enable for GPIO4. GPIO4InputEnabled disabled 0 enabled 1 GPIO_CFGCTL3 GPIO6, GPIO7 configuration 0x10C 0x0b030b03 0xffffffff reg_gpio_7_func_sel 24 27 Function select for GPIO7. GPIO7FunctionSelect SPI_SCLK 4 I2C_SDA 6 UART_SIG7 7 PWM_CH2 8 FEM_GPIO_3 9 SWGPIO_7 11 E21_TDO 14 reg_gpio_7_pd 21 21 Pull Down Resistor for GPIO7. GPIO7PullDownResistor disabled 0 enabled 1 reg_gpio_7_pu 20 20 Pull Up Resistor for GPIO7. GPIO7PullUpResistor disabled 0 enabled 1 reg_gpio_7_drv 18 19 Driving control enabled for GPIO7. GPIO7Driving disabled 0 enabled 1 reg_gpio_7_smt 17 17 Schmitt trigger enabled for GPIO7. GPIO7Schmitt disabled 0 enabled 1 reg_gpio_7_ie 16 16 Input enable for GPIO7. GPIO7InputEnabled disabled 0 enabled 1 reg_gpio_6_func_sel 8 11 Function select for GPIO6. GPIO6FunctionSelect SPI_SS 4 I2C_SCL 6 UART_SIG6 7 PWM_CH1 8 FEM_GPIO_2 9 GPIP_CH5 10 SWGPIO_6 11 E21_TCK 14 reg_gpio_6_pd 5 5 Pull Down Resistor for GPIO6. GPIO6PullDownResistor disabled 0 enabled 1 reg_gpio_6_pu 4 4 Pull Up Resistor for GPIO6. GPIO6PullUpResistor disabled 0 enabled 1 reg_gpio_6_drv 2 3 Driving control enabled for GPIO6. GPIO6Driving disabled 0 enabled 1 reg_gpio_6_smt 1 1 Schmitt trigger enabled for GPIO6. GPIO6Schmitt disabled 0 enabled 1 reg_gpio_6_ie 0 0 Input enable for GPIO6. GPIO6InputEnabled disabled 0 enabled 1 GPIO_CFGCTL4 GPIO8, GPIO9 configuration 0x110 0x0b030b03 0xffffffff reg_gpio_9_func_sel 24 27 Function select for GPIO9. GPIO9FunctionSelect SPI_MOSI_SPI_MISO 4 I2C_SDA 6 UART_SIG1 7 PWM_CH4 8 FEM_GPIO_1 9 GPIP_CH6_GPIP_CH7 10 SWGPIO_9 11 E21_TDI 14 reg_gpio_9_pd 21 21 Pull Down Resistor for GPIO9. GPIO9PullDownResistor disabled 0 enabled 1 reg_gpio_9_pu 20 20 Pull Up Resistor for GPIO9. GPIO9PullUpResistor disabled 0 enabled 1 reg_gpio_9_drv 18 19 Driving control enabled for GPIO9. GPIO9Driving disabled 0 enabled 1 reg_gpio_9_smt 17 17 Schmitt trigger enabled for GPIO9. GPIO9Schmitt disabled 0 enabled 1 reg_gpio_9_ie 16 16 Input enable for GPIO9. GPIO9InputEnabled disabled 0 enabled 1 reg_gpio_8_func_sel 8 11 Function select for GPIO8. GPIO8FunctionSelect SPI_MISO_SPI_MOSI 4 I2C_SCL 6 UART_SIG0 7 PWM_CH3 8 FEM_GPIO_0 9 SWGPIO_8 11 E21_TMS 14 reg_gpio_8_pd 5 5 Pull Down Resistor for GPIO8. GPIO8PullDownResistor disabled 0 enabled 1 reg_gpio_8_pu 4 4 Pull Up Resistor for GPIO8. GPIO8PullUpResistor disabled 0 enabled 1 reg_gpio_8_drv 2 3 Driving control enabled for GPIO8. GPIO8Driving disabled 0 enabled 1 reg_gpio_8_smt 1 1 Schmitt trigger enabled for GPIO8. GPIO8Schmitt disabled 0 enabled 1 reg_gpio_8_ie 0 0 Input enable for GPIO8. GPIO8InputEnabled disabled 0 enabled 1 GPIO_CFGCTL5 GPIO10, GPIO11 configuration 0x114 0x0e030b03 0xffffffff reg_gpio_11_func_sel 24 27 Function select for GPIO11. GPIO11FunctionSelect SPI_SCLK 4 I2C_SDA 6 UART_SIG3 7 PWM_CH1 8 FEM_GPIO_3 9 IRLED_OUT_GPIP_CH10 10 SWGPIO_11 11 E21_TDO 14 reg_gpio_11_pd 21 21 Pull Down Resistor for GPIO11. GPIO11PullDownResistor disabled 0 enabled 1 reg_gpio_11_pu 20 20 Pull Up Resistor for GPIO11. GPIO11PullUpResistor disabled 0 enabled 1 reg_gpio_11_drv 18 19 Driving control enabled for GPIO11. GPIO11Driving disabled 0 enabled 1 reg_gpio_11_smt 17 17 Schmitt trigger enabled for GPIO11. GPIO11Schmitt disabled 0 enabled 1 reg_gpio_11_ie 16 16 Input enable for GPIO11. GPIO11InputEnabled disabled 0 enabled 1 reg_gpio_10_func_sel 8 11 Function select for GPIO10. GPIO10FunctionSelect SPI_SS 4 I2C_SCL 6 UART_SIG2 7 PWM_CH0 8 FEM_GPIO_2 9 MICBIAS_GPIP_CH8_GPIP_CH9 10 SWGPIO_10 11 E21_TCK 14 reg_gpio_10_pd 5 5 Pull Down Resistor for GPIO10. GPIO10PullDownResistor disabled 0 enabled 1 reg_gpio_10_pu 4 4 Pull Up Resistor for GPIO10. GPIO10PullUpResistor disabled 0 enabled 1 reg_gpio_10_drv 2 3 Driving control enabled for GPIO10. GPIO10Driving disabled 0 enabled 1 reg_gpio_10_smt 1 1 Schmitt trigger enabled for GPIO10. GPIO10Schmitt disabled 0 enabled 1 reg_gpio_10_ie 0 0 Input enable for GPIO10. GPIO10InputEnabled disabled 0 enabled 1 GPIO_CFGCTL6 GPIO12, GPIO13 configuration 0x118 0x0b030e03 0xffffffff reg_gpio_13_func_sel 24 27 Function select for GPIO13. GPIO13FunctionSelect SPI_MOSI_SPI_MISO 4 I2C_SDA 6 UART_SIG5 7 PWM_CH3 8 FEM_GPIO_1 9 GPIP_CH3 10 SWGPIO_13 11 E21_TDI 14 reg_gpio_13_pd 21 21 Pull Down Resistor for GPIO13. GPIO13PullDownResistor disabled 0 enabled 1 reg_gpio_13_pu 20 20 Pull Up Resistor for GPIO13. GPIO13PullUpResistor disabled 0 enabled 1 reg_gpio_13_drv 18 19 Driving control enabled for GPIO13. GPIO13Driving disabled 0 enabled 1 reg_gpio_13_smt 17 17 Schmitt trigger enabled for GPIO13. GPIO13Schmitt disabled 0 enabled 1 reg_gpio_13_ie 16 16 Input enable for GPIO13. GPIO13InputEnabled disabled 0 enabled 1 reg_gpio_12_func_sel 8 11 Function select for GPIO12. GPIO12FunctionSelect SPI_MISO_SPI_MOSI 4 I2C_SCL 6 UART_SIG4 7 PWM_CH2 8 FEM_GPIO_0 9 GPIP_CH0_GPADC_VREF_EXT 10 SWGPIO_12 11 E21_TMS 14 reg_gpio_12_pd 5 5 Pull Down Resistor for GPIO12. GPIO12PullDownResistor disabled 0 enabled 1 reg_gpio_12_pu 4 4 Pull Up Resistor for GPIO12. GPIO12PullUpResistor disabled 0 enabled 1 reg_gpio_12_drv 2 3 Driving control enabled for GPIO12. GPIO12Driving disabled 0 enabled 1 reg_gpio_12_smt 1 1 Schmitt trigger enabled for GPIO12. GPIO12Schmitt disabled 0 enabled 1 reg_gpio_12_ie 0 0 Input enable for GPIO12. GPIO12InputEnabled disabled 0 enabled 1 GPIO_CFGCTL7 GPIO14, GPIO15 configuration 0x11C 0x0b030e03 0xffffffff reg_gpio_15_func_sel 24 27 Function select for GPIO15. GPIO15FunctionSelect SPI_SCLK 4 I2C_SDA 6 UART_SIG7 7 PWM_CH0 8 FEM_GPIO_3 9 PSW_IRRCV_OUT_GPIP_CH11 10 SWGPIO_15 11 E21_TDO 14 reg_gpio_15_pd 21 21 Pull Down Resistor for GPIO15. GPIO15PullDownResistor disabled 0 enabled 1 reg_gpio_15_pu 20 20 Pull Up Resistor for GPIO15. GPIO15PullUpResistor disabled 0 enabled 1 reg_gpio_15_drv 18 19 Driving control enabled for GPIO15. GPIO15Driving disabled 0 enabled 1 reg_gpio_15_smt 17 17 Schmitt trigger enabled for GPIO15. GPIO15Schmitt disabled 0 enabled 1 reg_gpio_15_ie 16 16 Input enable for GPIO15. GPIO15InputEnabled disabled 0 enabled 1 reg_gpio_14_func_sel 8 11 Function select for GPIO14. GPIO14FunctionSelect SPI_SS 4 I2C_SCL 6 UART_SIG6 7 PWM_CH4 8 FEM_GPIO_2 9 GPIP_CH2 10 SWGPIO_14 11 E21_TCK 14 reg_gpio_14_pd 5 5 Pull Down Resistor for GPIO14. GPIO14PullDownResistor disabled 0 enabled 1 reg_gpio_14_pu 4 4 Pull Up Resistor for GPIO14. GPIO14PullUpResistor disabled 0 enabled 1 reg_gpio_14_drv 2 3 Driving control enabled for GPIO14. GPIO14Driving disabled 0 enabled 1 reg_gpio_14_smt 1 1 Schmitt trigger enabled for GPIO14. GPIO14Schmitt disabled 0 enabled 1 reg_gpio_14_ie 0 0 Input enable for GPIO14. GPIO14InputEnabled disabled 0 enabled 1 GPIO_CFGCTL8 GPIO16, GPIO17 configuration 0x120 0x0e030b03 0xffffffff reg_gpio_17_func_sel 24 27 Function select for GPIO17. GPIO17FunctionSelect SF_D3 2 SPI_MOSI_SPI_MISO 4 I2C_SDA 6 UART_SIG1 7 PWM_CH2 8 FEM_GPIO_1 9 PMIP_DC_TP_OUT 10 SWGPIO_17 11 E21_TDI 14 reg_gpio_17_pd 21 21 Pull Down Resistor for GPIO17. GPIO17PullDownResistor disabled 0 enabled 1 reg_gpio_17_pu 20 20 Pull Up Resistor for GPIO17. GPIO17PullUpResistor disabled 0 enabled 1 reg_gpio_17_drv 18 19 Driving control enabled for GPIO17. GPIO17Driving disabled 0 enabled 1 reg_gpio_17_smt 17 17 Schmitt trigger enabled for GPIO17. GPIO17Schmitt disabled 0 enabled 1 reg_gpio_17_ie 16 16 Input enable for GPIO17. GPIO17InputEnabled disabled 0 enabled 1 reg_gpio_16_func_sel 8 11 Function select for GPIO16. GPIO16FunctionSelect SPI_MISO_SPI_MOSI 4 I2C_SCL 6 UART_SIG0 7 PWM_CH1 8 FEM_GPIO_0 9 SWGPIO_16 11 E21_TMS 14 reg_gpio_16_pd 5 5 Pull Down Resistor for GPIO16. GPIO16PullDownResistor disabled 0 enabled 1 reg_gpio_16_pu 4 4 Pull Up Resistor for GPIO16. GPIO16PullUpResistor disabled 0 enabled 1 reg_gpio_16_drv 2 3 Driving control enabled for GPIO16. GPIO16Driving disabled 0 enabled 1 reg_gpio_16_smt 1 1 Schmitt trigger enabled for GPIO16. GPIO16Schmitt disabled 0 enabled 1 reg_gpio_16_ie 0 0 Input enable for GPIO16. GPIO16InputEnabled disabled 0 enabled 1 GPIO_CFGCTL9 GPIO18, GPIO19 configuration 0x124 0x0b030b03 0xffffffff reg_gpio_19_func_sel 24 27 Function select for GPIO19. GPIO19FunctionSelect SF_D1 2 SPI_SCLK 4 I2C_SDA 6 UART_SIG3 7 PWM_CH4 8 FEM_GPIO_3 9 SWGPIO_19 11 E21_TDO 14 reg_gpio_19_pd 21 21 Pull Down Resistor for GPIO19. GPIO19PullDownResistor disabled 0 enabled 1 reg_gpio_19_pu 20 20 Pull Up Resistor for GPIO19. GPIO19PullUpResistor disabled 0 enabled 1 reg_gpio_19_drv 18 19 Driving control enabled for GPIO19. GPIO19Driving disabled 0 enabled 1 reg_gpio_19_smt 17 17 Schmitt trigger enabled for GPIO19. GPIO19Schmitt disabled 0 enabled 1 reg_gpio_19_ie 16 16 Input enable for GPIO19. GPIO19InputEnabled disabled 0 enabled 1 reg_gpio_18_func_sel 8 11 Function select for GPIO18. GPIO18FunctionSelect SF_D2 2 SPI_SS 4 I2C_SCL 6 UART_SIG2 7 PWM_CH3 8 FEM_GPIO_2 9 SWGPIO_18 11 E21_TCK 14 reg_gpio_18_pd 5 5 Pull Down Resistor for GPIO18. GPIO18PullDownResistor disabled 0 enabled 1 reg_gpio_18_pu 4 4 Pull Up Resistor for GPIO18. GPIO18PullUpResistor disabled 0 enabled 1 reg_gpio_18_drv 2 3 Driving control enabled for GPIO18. GPIO18Driving disabled 0 enabled 1 reg_gpio_18_smt 1 1 Schmitt trigger enabled for GPIO18. GPIO18Schmitt disabled 0 enabled 1 reg_gpio_18_ie 0 0 Input enable for GPIO18. GPIO18InputEnabled disabled 0 enabled 1 GPIO_CFGCTL10 GPIO20, GPIO21 configuration 0x128 0x0b030b03 0xffffffff reg_gpio_21_func_sel 24 27 Function select for GPIO21. GPIO21FunctionSelect SF_CS 2 SPI_MOSI_SPI_MISO 4 I2C_SDA 6 UART_SIG5 7 PWM_CH1 8 FEM_GPIO_1 9 SWGPIO_21 11 E21_TDI 14 reg_gpio_21_pd 21 21 Pull Down Resistor for GPIO21. GPIO21PullDownResistor disabled 0 enabled 1 reg_gpio_21_pu 20 20 Pull Up Resistor for GPIO21. GPIO21PullUpResistor disabled 0 enabled 1 reg_gpio_21_drv 18 19 Driving control enabled for GPIO21. GPIO21Driving disabled 0 enabled 1 reg_gpio_21_smt 17 17 Schmitt trigger enabled for GPIO21. GPIO21Schmitt disabled 0 enabled 1 reg_gpio_21_ie 16 16 Input enable for GPIO21. GPIO21InputEnabled disabled 0 enabled 1 reg_gpio_20_func_sel 8 11 Function select for GPIO20. GPIO20FunctionSelect SF_D0 2 SPI_MISO_SPI_MOSI 4 I2C_SCL 6 UART_SIG4 7 PWM_CH0 8 FEM_GPIO_0 9 SWGPIO_20 11 E21_TMS 14 reg_gpio_20_pd 5 5 Pull Down Resistor for GPIO20. GPIO20PullDownResistor disabled 0 enabled 1 reg_gpio_20_pu 4 4 Pull Up Resistor for GPIO20. GPIO20PullUpResistor disabled 0 enabled 1 reg_gpio_20_drv 2 3 Driving control enabled for GPIO20. GPIO20Driving disabled 0 enabled 1 reg_gpio_20_smt 1 1 Schmitt trigger enabled for GPIO20. GPIO20Schmitt disabled 0 enabled 1 reg_gpio_20_ie 0 0 Input enable for GPIO20. GPIO20InputEnabled disabled 0 enabled 1 GPIO_CFGCTL11 GPIO22, GPIO23 configuration 0x12C 0x00030b03 0xffffffff reg_gpio_23_pd 21 21 Pull Down Resistor for GPIO23. GPIO23PullDownResistor disabled 0 enabled 1 reg_gpio_23_pu 20 20 Pull Up Resistor for GPIO23. GPIO23PullUpResistor disabled 0 enabled 1 reg_gpio_23_drv 18 19 Driving control enabled for GPIO23. GPIO23Driving disabled 0 enabled 1 reg_gpio_23_smt 17 17 Schmitt trigger enabled for GPIO23. GPIO23Schmitt disabled 0 enabled 1 reg_gpio_23_ie 16 16 Input enable for GPIO23. GPIO23InputEnabled disabled 0 enabled 1 reg_gpio_22_func_sel 8 11 Function select for GPIO22. GPIO22FunctionSelect SF_CLK_OUT 2 SPI_SS 4 I2C_SCL 6 UART_SIG6 7 PWM_CH2 8 FEM_GPIO_2 9 SWGPIO_22 11 E21_TCK 14 reg_gpio_22_pd 5 5 Pull Down Resistor for GPIO22. GPIO22PullDownResistor disabled 0 enabled 1 reg_gpio_22_pu 4 4 Pull Up Resistor for GPIO22. GPIO22PullUpResistor disabled 0 enabled 1 reg_gpio_22_drv 2 3 Driving control enabled for GPIO22. GPIO22Driving disabled 0 enabled 1 reg_gpio_22_smt 1 1 Schmitt trigger enabled for GPIO22. GPIO22Schmitt disabled 0 enabled 1 reg_gpio_22_ie 0 0 Input enable for GPIO22. GPIO22InputEnabled disabled 0 enabled 1 GPIO_CFGCTL12 GPIO24, GPIO25 configuration 0x130 0x00030023 0xffffffff reg_gpio_25_pd 21 21 Pull Down Resistor for GPIO25. GPIO25PullDownResistor disabled 0 enabled 1 reg_gpio_25_pu 20 20 Pull Up Resistor for GPIO25. GPIO25PullUpResistor disabled 0 enabled 1 reg_gpio_25_drv 18 19 Driving control enabled for GPIO25. GPIO25Driving disabled 0 enabled 1 reg_gpio_25_smt 17 17 Schmitt trigger enabled for GPIO25. GPIO25Schmitt disabled 0 enabled 1 reg_gpio_25_ie 16 16 Input enable for GPIO25. GPIO25InputEnabled disabled 0 enabled 1 reg_gpio_24_pd 5 5 Pull Down Resistor for GPIO24. GPIO24PullDownResistor disabled 0 enabled 1 reg_gpio_24_pu 4 4 Pull Up Resistor for GPIO24. GPIO24PullUpResistor disabled 0 enabled 1 reg_gpio_24_drv 2 3 Driving control enabled for GPIO24. GPIO24Driving disabled 0 enabled 1 reg_gpio_24_smt 1 1 Schmitt trigger enabled for GPIO24. GPIO24Schmitt disabled 0 enabled 1 reg_gpio_24_ie 0 0 Input enable for GPIO24. GPIO24InputEnabled disabled 0 enabled 1 GPIO_CFGCTL13 GPIO26, GPIO27 configuration 0x134 0x00030003 0xffffffff reg_gpio_27_pd 21 21 Pull Down Resistor for GPIO27. GPIO27PullDownResistor disabled 0 enabled 1 reg_gpio_27_pu 20 20 Pull Up Resistor for GPIO27. GPIO27PullUpResistor disabled 0 enabled 1 reg_gpio_27_drv 18 19 Driving control enabled for GPIO27. GPIO27Driving disabled 0 enabled 1 reg_gpio_27_smt 17 17 Schmitt trigger enabled for GPIO27. GPIO27Schmitt disabled 0 enabled 1 reg_gpio_27_ie 16 16 Input enable for GPIO27. GPIO27InputEnabled disabled 0 enabled 1 reg_gpio_26_pd 5 5 Pull Down Resistor for GPIO26. GPIO26PullDownResistor disabled 0 enabled 1 reg_gpio_26_pu 4 4 Pull Up Resistor for GPIO26. GPIO26PullUpResistor disabled 0 enabled 1 reg_gpio_26_drv 2 3 Driving control enabled for GPIO26. GPIO26Driving disabled 0 enabled 1 reg_gpio_26_smt 1 1 Schmitt trigger enabled for GPIO26. GPIO26Schmitt disabled 0 enabled 1 reg_gpio_26_ie 0 0 Input enable for GPIO26. GPIO26InputEnabled disabled 0 enabled 1 GPIO_CFGCTL14 GPIO28 configuration 0x138 0x00000003 0xffffffff reg_gpio_28_pd 5 5 Pull Down Resistor for GPIO28. GPIO28PullDownResistor disabled 0 enabled 1 reg_gpio_28_pu 4 4 Pull Up Resistor for GPIO28. GPIO28PullUpResistor disabled 0 enabled 1 reg_gpio_28_drv 2 3 Driving control enabled for GPIO28. GPIO28Driving disabled 0 enabled 1 reg_gpio_28_smt 1 1 Schmitt trigger enabled for GPIO28. GPIO28Schmitt disabled 0 enabled 1 reg_gpio_28_ie 0 0 Input enable for GPIO28. GPIO28InputEnabled disabled 0 enabled 1 GPIO_CFGCTL30 Input register for all GPIO pins. Input Enabled bit must be set in configuration register to work. 0x180 read-only 0x00000000 0xffffffff reg_gpio_22_i 22 22 Input register for GPIO22. GPIO22Input disabled 0 enabled 1 reg_gpio_21_i 21 21 Input register for GPIO21. GPIO21Input disabled 0 enabled 1 reg_gpio_20_i 20 20 Input register for GPIO20. GPIO20Input disabled 0 enabled 1 reg_gpio_19_i 19 19 Input register for GPIO19. GPIO19Input disabled 0 enabled 1 reg_gpio_18_i 18 18 Input register for GPIO18. GPIO18Input disabled 0 enabled 1 reg_gpio_17_i 17 17 Input register for GPIO17. GPIO17Input disabled 0 enabled 1 reg_gpio_16_i 16 16 Input register for GPIO16. GPIO16Input disabled 0 enabled 1 reg_gpio_15_i 15 15 Input register for GPIO15. GPIO15Input disabled 0 enabled 1 reg_gpio_14_i 14 14 Input register for GPIO14. GPIO14Input disabled 0 enabled 1 reg_gpio_13_i 13 13 Input register for GPIO13. GPIO13Input disabled 0 enabled 1 reg_gpio_12_i 12 12 Input register for GPIO12. GPIO12Input disabled 0 enabled 1 reg_gpio_11_i 11 11 Input register for GPIO11. GPIO11Input disabled 0 enabled 1 reg_gpio_10_i 10 10 Input register for GPIO10. GPIO10Input disabled 0 enabled 1 reg_gpio_9_i 9 9 Input register for GPIO9. GPIO9Input disabled 0 enabled 1 reg_gpio_8_i 8 8 Input register for GPIO8. GPIO8Input disabled 0 enabled 1 reg_gpio_7_i 7 7 Input register for GPIO7. GPIO7Input disabled 0 enabled 1 reg_gpio_6_i 6 6 Input register for GPIO6. GPIO6Input disabled 0 enabled 1 reg_gpio_5_i 5 5 Input register for GPIO5. GPIO5Input disabled 0 enabled 1 reg_gpio_4_i 4 4 Input register for GPIO4. GPIO4Input disabled 0 enabled 1 reg_gpio_3_i 3 3 Input register for GPIO3. GPIO3Input disabled 0 enabled 1 reg_gpio_2_i 2 2 Input register for GPIO2. GPIO2Input disabled 0 enabled 1 reg_gpio_1_i 1 1 Input register for GPIO1. GPIO1Input disabled 0 enabled 1 reg_gpio_0_i 0 0 GPIO_CFGCTL31 Reserved according to SDK. 0x184 GPIO_CFGCTL32 Output register for all GPIO pins. Output Enabled bit must be set in Output Enable register to work. 0x188 0x00000000 0xffffffff reg_gpio_22_o 22 22 Output register for GPIO22. GPIO22Output disabled 0 enabled 1 reg_gpio_21_o 21 21 Output register for GPIO21. GPIO21Output disabled 0 enabled 1 reg_gpio_20_o 20 20 Output register for GPIO20. GPIO20Output disabled 0 enabled 1 reg_gpio_19_o 19 19 Output register for GPIO19. GPIO19Output disabled 0 enabled 1 reg_gpio_18_o 18 18 Output register for GPIO18. GPIO18Output disabled 0 enabled 1 reg_gpio_17_o 17 17 Output register for GPIO17. GPIO17Output disabled 0 enabled 1 reg_gpio_16_o 16 16 Output register for GPIO16. GPIO16Output disabled 0 enabled 1 reg_gpio_15_o 15 15 Output register for GPIO15. GPIO15Output disabled 0 enabled 1 reg_gpio_14_o 14 14 Output register for GPIO14. GPIO14Output disabled 0 enabled 1 reg_gpio_13_o 13 13 Output register for GPIO13. GPIO13Output disabled 0 enabled 1 reg_gpio_12_o 12 12 Output register for GPIO12. GPIO12Output disabled 0 enabled 1 reg_gpio_11_o 11 11 Output register for GPIO11. GPIO11Output disabled 0 enabled 1 reg_gpio_10_o 10 10 Output register for GPIO10. GPIO10Output disabled 0 enabled 1 reg_gpio_9_o 9 9 Output register for GPIO9. GPIO9Output disabled 0 enabled 1 reg_gpio_8_o 8 8 Output register for GPIO8. GPIO8Output disabled 0 enabled 1 reg_gpio_7_o 7 7 Output register for GPIO7. GPIO7Output disabled 0 enabled 1 reg_gpio_6_o 6 6 Output register for GPIO6. GPIO6Output disabled 0 enabled 1 reg_gpio_5_o 5 5 Output register for GPIO5. GPIO5Output disabled 0 enabled 1 reg_gpio_4_o 4 4 Output register for GPIO4. GPIO4Output disabled 0 enabled 1 reg_gpio_3_o 3 3 Output register for GPIO3. GPIO3Output disabled 0 enabled 1 reg_gpio_2_o 2 2 Output register for GPIO2. GPIO2Output disabled 0 enabled 1 reg_gpio_1_o 1 1 Output register for GPIO1. GPIO1Output disabled 0 enabled 1 reg_gpio_0_o 0 0 Output register for GPIO0. GPIO0Output disabled 0 enabled 1 GPIO_CFGCTL33 Reserved according to SDK. 0x18C GPIO_CFGCTL34 Output enable register for GPIO. 0x190 0x00000000 0xffffffff reg_gpio_22_oe 22 22 Output enable register for GPIO22. GPIO22OutputEnable disabled 0 enabled 1 reg_gpio_21_oe 21 21 Output enable register for GPIO21. GPIO21OutputEnable disabled 0 enabled 1 reg_gpio_20_oe 20 20 Output enable register for GPIO20. GPIO20OutputEnable disabled 0 enabled 1 reg_gpio_19_oe 19 19 Output enable register for GPIO19. GPIO19OutputEnable disabled 0 enabled 1 reg_gpio_18_oe 18 18 Output enable register for GPIO18. GPIO18OutputEnable disabled 0 enabled 1 reg_gpio_17_oe 17 17 Output enable register for GPIO17. GPIO17OutputEnable disabled 0 enabled 1 reg_gpio_16_oe 16 16 Output enable register for GPIO16. GPIO16OutputEnable disabled 0 enabled 1 reg_gpio_15_oe 15 15 Output enable register for GPIO15. GPIO15OutputEnable disabled 0 enabled 1 reg_gpio_14_oe 14 14 Output enable register for GPIO14. GPIO14OutputEnable disabled 0 enabled 1 reg_gpio_13_oe 13 13 Output enable register for GPIO13. GPIO13OutputEnable disabled 0 enabled 1 reg_gpio_12_oe 12 12 Output enable register for GPIO12. GPIO12OutputEnable disabled 0 enabled 1 reg_gpio_11_oe 11 11 Output enable register for GPIO11. GPIO11OutputEnable disabled 0 enabled 1 reg_gpio_10_oe 10 10 Output enable register for GPIO10. GPIO10OutputEnable disabled 0 enabled 1 reg_gpio_9_oe 9 9 Output enable register for GPIO9. GPIO9OutputEnable disabled 0 enabled 1 reg_gpio_8_oe 8 8 Output enable register for GPIO8. GPIO8OutputEnable disabled 0 enabled 1 reg_gpio_7_oe 7 7 Output enable register for GPIO7. GPIO7OutputEnable disabled 0 enabled 1 reg_gpio_6_oe 6 6 Output enable register for GPIO6. GPIO6OutputEnable disabled 0 enabled 1 reg_gpio_5_oe 5 5 Output enable register for GPIO5. GPIO5OutputEnable disabled 0 enabled 1 reg_gpio_4_oe 4 4 Output enable register for GPIO4. GPIO4OutputEnable disabled 0 enabled 1 reg_gpio_3_oe 3 3 Output enable register for GPIO3. GPIO3OutputEnable disabled 0 enabled 1 reg_gpio_2_oe 2 2 Output enable register for GPIO2. GPIO2OutputEnable disabled 0 enabled 1 reg_gpio_1_oe 1 1 Output enable register for GPIO1. GPIO1OutputEnable disabled 0 enabled 1 reg_gpio_0_oe 0 0 Output enable register for GPIO0. GPIO0OutputEnable disabled 0 enabled 1 GPIO_CFGCTL35 Reserved according to SDK. 0x194 GPIO_INT_MASK1 Interrupt masking register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins. 0x1A0 0xffffffff 0xffffffff reg_gpio_0_mask 0 0 Mask register for GPIO0. GPIO0Mask unmasked 0 masked 1 reg_gpio_1_mask 1 1 Mask register for GPIO1. GPIO1Mask unmasked 0 masked 1 reg_gpio_2_mask 2 2 Mask register for GPIO2. GPIO2Mask unmasked 0 masked 1 reg_gpio_3_mask 3 3 Mask register for GPIO3. GPIO3Mask unmasked 0 masked 1 reg_gpio_4_mask 4 4 Mask register for GPIO4. GPIO4Mask unmasked 0 masked 1 reg_gpio_5_mask 5 5 Mask register for GPIO5. GPIO5Mask unmasked 0 masked 1 reg_gpio_6_mask 6 6 Mask register for GPIO6. GPIO6Mask unmasked 0 masked 1 reg_gpio_7_mask 7 7 Mask register for GPIO7. GPIO7Mask unmasked 0 masked 1 reg_gpio_8_mask 8 8 Mask register for GPIO8. GPIO8Mask unmasked 0 masked 1 reg_gpio_9_mask 9 9 Mask register for GPIO9. GPIO9Mask unmasked 0 masked 1 reg_gpio_10_mask 10 10 Mask register for GPIO10. GPIO10Mask unmasked 0 masked 1 reg_gpio_11_mask 11 11 Mask register for GPIO11. GPIO11Mask unmasked 0 masked 1 reg_gpio_12_mask 12 12 Mask register for GPIO12. GPIO12Mask unmasked 0 masked 1 reg_gpio_13_mask 13 13 Mask register for GPIO13. GPIO13Mask unmasked 0 masked 1 reg_gpio_14_mask 14 14 Mask register for GPIO14. GPIO14Mask unmasked 0 masked 1 reg_gpio_15_mask 15 15 Mask register for GPIO15. GPIO15Mask unmasked 0 masked 1 reg_gpio_16_mask 16 16 Mask register for GPIO16. GPIO16Mask unmasked 0 masked 1 reg_gpio_17_mask 17 17 Mask register for GPIO17. GPIO17Mask unmasked 0 masked 1 reg_gpio_18_mask 18 18 Mask register for GPIO18. GPIO18Mask unmasked 0 masked 1 reg_gpio_19_mask 19 19 Mask register for GPIO19. GPIO19Mask unmasked 0 masked 1 reg_gpio_20_mask 20 20 Mask register for GPIO20. GPIO20Mask unmasked 0 masked 1 reg_gpio_21_mask 21 21 Mask register for GPIO21. GPIO21Mask unmasked 0 masked 1 reg_gpio_22_mask 22 22 Mask register for GPIO22. GPIO22Mask unmasked 0 masked 1 reg_gpio_23_mask 23 23 Mask register for GPIO23. GPIO23Mask unmasked 0 masked 1 reg_gpio_24_mask 24 24 Mask register for GPIO24. GPIO24Mask unmasked 0 masked 1 reg_gpio_25_mask 25 25 Mask register for GPIO25. GPIO25Mask unmasked 0 masked 1 reg_gpio_26_mask 26 26 Mask register for GPIO26. GPIO26Mask unmasked 0 masked 1 reg_gpio_27_mask 27 27 Mask register for GPIO27. GPIO27Mask unmasked 0 masked 1 reg_gpio_28_mask 28 28 Mask register for GPIO28. GPIO28Mask unmasked 0 masked 1 GPIO_INT_STAT1 Interrupt status register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins. 0x1A8 read-only 0x00000000 0xffffffff reg_gpio_0_interrupt_status 0 0 Interrupt status register for GPIO0. GPIO0InterruptStatus reset 0 set 1 reg_gpio_1_interrupt_status 1 1 Interrupt status register for GPIO1. GPIO1InterruptStatus reset 0 set 1 reg_gpio_2_interrupt_status 2 2 Interrupt status register for GPIO2. GPIO2InterruptStatus reset 0 set 1 reg_gpio_3_interrupt_status 3 3 Interrupt status register for GPIO3. GPIO3InterruptStatus reset 0 set 1 reg_gpio_4_interrupt_status 4 4 Interrupt status register for GPIO4. GPIO4InterruptStatus reset 0 set 1 reg_gpio_5_interrupt_status 5 5 Interrupt status register for GPIO5. GPIO5InterruptStatus reset 0 set 1 reg_gpio_6_interrupt_status 6 6 Interrupt status register for GPIO6. GPIO6InterruptStatus reset 0 set 1 reg_gpio_7_interrupt_status 7 7 Interrupt status register for GPIO7. GPIO7InterruptStatus reset 0 set 1 reg_gpio_8_interrupt_status 8 8 Interrupt status register for GPIO8. GPIO8InterruptStatus reset 0 set 1 reg_gpio_9_interrupt_status 9 9 Interrupt status register for GPIO9. GPIO9InterruptStatus reset 0 set 1 reg_gpio_10_interrupt_status 10 10 Interrupt status register for GPIO10. GPIO10InterruptStatus reset 0 set 1 reg_gpio_11_interrupt_status 11 11 Interrupt status register for GPIO11. GPIO11InterruptStatus reset 0 set 1 reg_gpio_12_interrupt_status 12 12 Interrupt status register for GPIO12. GPIO12InterruptStatus reset 0 set 1 reg_gpio_13_interrupt_status 13 13 Interrupt status register for GPIO13. GPIO13InterruptStatus reset 0 set 1 reg_gpio_14_interrupt_status 14 14 Interrupt status register for GPIO14. GPIO14InterruptStatus reset 0 set 1 reg_gpio_15_interrupt_status 15 15 Interrupt status register for GPIO15. GPIO15InterruptStatus reset 0 set 1 reg_gpio_16_interrupt_status 16 16 Interrupt status register for GPIO16. GPIO16InterruptStatus reset 0 set 1 reg_gpio_17_interrupt_status 17 17 Interrupt status register for GPIO17. GPIO17InterruptStatus reset 0 set 1 reg_gpio_18_interrupt_status 18 18 Interrupt status register for GPIO18. GPIO18InterruptStatus reset 0 set 1 reg_gpio_19_interrupt_status 19 19 Interrupt status register for GPIO19. GPIO19InterruptStatus reset 0 set 1 reg_gpio_20_interrupt_status 20 20 Interrupt status register for GPIO20. GPIO20InterruptStatus reset 0 set 1 reg_gpio_21_interrupt_status 21 21 Interrupt status register for GPIO21. GPIO21InterruptStatus reset 0 set 1 reg_gpio_22_interrupt_status 22 22 Interrupt status register for GPIO22. GPIO22InterruptStatus reset 0 set 1 reg_gpio_23_interrupt_status 23 23 Interrupt status register for GPIO23. GPIO23InterruptStatus reset 0 set 1 reg_gpio_24_interrupt_status 24 24 Interrupt status register for GPIO24. GPIO24InterruptStatus reset 0 set 1 reg_gpio_25_interrupt_status 25 25 Interrupt status register for GPIO25. GPIO25InterruptStatus reset 0 set 1 reg_gpio_26_interrupt_status 26 26 Interrupt status register for GPIO26. GPIO26InterruptStatus reset 0 set 1 reg_gpio_27_interrupt_status 27 27 Interrupt status register for GPIO27. GPIO27InterruptStatus reset 0 set 1 reg_gpio_28_interrupt_status 28 28 Interrupt status register for GPIO28. GPIO28InterruptStatus reset 0 set 1 GPIO_INT_CLR1 Interrupt clearing register. 0x1B0 0x00000000 0xffffffff reg_gpio_0_interrupt_clear 0 0 Interrupt clearing register for GPIO0. GPIO0InterruptClear no_clear 0 clear 1 reg_gpio_1_interrupt_clear 1 1 Interrupt clearing register for GPIO1. GPIO1InterruptClear no_clear 0 clear 1 reg_gpio_2_interrupt_clear 2 2 Interrupt clearing register for GPIO2. GPIO2InterruptClear no_clear 0 clear 1 reg_gpio_3_interrupt_clear 3 3 Interrupt clearing register for GPIO3. GPIO3InterruptClear no_clear 0 clear 1 reg_gpio_4_interrupt_clear 4 4 Interrupt clearing register for GPIO4. GPIO4InterruptClear no_clear 0 clear 1 reg_gpio_5_interrupt_clear 5 5 Interrupt clearing register for GPIO5. GPIO5InterruptClear no_clear 0 clear 1 reg_gpio_6_interrupt_clear 6 6 Interrupt clearing register for GPIO6. GPIO6InterruptClear no_clear 0 clear 1 reg_gpio_7_interrupt_clear 7 7 Interrupt clearing register for GPIO7. GPIO7InterruptClear no_clear 0 clear 1 reg_gpio_8_interrupt_clear 8 8 Interrupt clearing register for GPIO8. GPIO8InterruptClear no_clear 0 clear 1 reg_gpio_9_interrupt_clear 9 9 Interrupt clearing register for GPIO9. GPIO9InterruptClear no_clear 0 clear 1 reg_gpio_10_interrupt_clear 10 10 Interrupt clearing register for GPIO10. GPIO10InterruptClear no_clear 0 clear 1 reg_gpio_11_interrupt_clear 11 11 Interrupt clearing register for GPIO11. GPIO11InterruptClear no_clear 0 clear 1 reg_gpio_12_interrupt_clear 12 12 Interrupt clearing register for GPIO12. GPIO12InterruptClear no_clear 0 clear 1 reg_gpio_13_interrupt_clear 13 13 Interrupt clearing register for GPIO13. GPIO13InterruptClear no_clear 0 clear 1 reg_gpio_14_interrupt_clear 14 14 Interrupt clearing register for GPIO14. GPIO14InterruptClear no_clear 0 clear 1 reg_gpio_15_interrupt_clear 15 15 Interrupt clearing register for GPIO15. GPIO15InterruptClear no_clear 0 clear 1 reg_gpio_16_interrupt_clear 16 16 Interrupt clearing register for GPIO16. GPIO16InterruptClear no_clear 0 clear 1 reg_gpio_17_interrupt_clear 17 17 Interrupt clearing register for GPIO17. GPIO17InterruptClear no_clear 0 clear 1 reg_gpio_18_interrupt_clear 18 18 Interrupt clearing register for GPIO18. GPIO18InterruptClear no_clear 0 clear 1 reg_gpio_19_interrupt_clear 19 19 Interrupt clearing register for GPIO19. GPIO19InterruptClear no_clear 0 clear 1 reg_gpio_20_interrupt_clear 20 20 Interrupt clearing register for GPIO20. GPIO20InterruptClear no_clear 0 clear 1 reg_gpio_21_interrupt_clear 21 21 Interrupt clearing register for GPIO21. GPIO21InterruptClear no_clear 0 clear 1 reg_gpio_22_interrupt_clear 22 22 Interrupt clearing register for GPIO22. GPIO22InterruptClear no_clear 0 clear 1 reg_gpio_23_interrupt_clear 23 23 Interrupt clearing register for GPIO23. GPIO23InterruptClear no_clear 0 clear 1 reg_gpio_24_interrupt_clear 24 24 Interrupt clearing register for GPIO24. GPIO24InterruptClear no_clear 0 clear 1 reg_gpio_25_interrupt_clear 25 25 Interrupt clearing register for GPIO25. GPIO25InterruptClear no_clear 0 clear 1 reg_gpio_26_interrupt_clear 26 26 Interrupt clearing register for GPIO26. GPIO26InterruptClear no_clear 0 clear 1 reg_gpio_27_interrupt_clear 27 27 Interrupt clearing register for GPIO27. GPIO27InterruptClear no_clear 0 clear 1 reg_gpio_28_interrupt_clear 28 28 Interrupt clearing register for GPIO28. GPIO28InterruptClear no_clear 0 clear 1 GPIO_INT_MODE_SET1 GPIO interrupt trigger and control register for GPIO0-GPIO9. 0x1C0 0x00000000 0xffffffff reg_gpio_0_interrupt_trigger_mode 0 1 Interrupt trigger mode register for GPIO0. GPIO0TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_0_interrupt_control_mode 2 2 Interrupt control mode register for GPIO0. GPIO0ControlMode synchronous 0 asynchronous 1 reg_gpio_1_interrupt_trigger_mode 3 4 Interrupt trigger mode register for GPIO1. GPIO1TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_1_interrupt_control_mode 5 5 Interrupt control mode register for GPIO1. GPIO1ControlMode synchronous 0 asynchronous 1 reg_gpio_2_interrupt_trigger_mode 6 7 Interrupt trigger mode register for GPIO2. GPIO2TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_2_interrupt_control_mode 8 8 Interrupt control mode register for GPIO2. GPIO2ControlMode synchronous 0 asynchronous 1 reg_gpio_3_interrupt_trigger_mode 9 10 Interrupt trigger mode register for GPIO3. GPIO3TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_3_interrupt_control_mode 11 11 Interrupt control mode register for GPIO3. GPIO3ControlMode synchronous 0 asynchronous 1 reg_gpio_4_interrupt_trigger_mode 12 13 Interrupt trigger mode register for GPIO4. GPIO4TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_4_interrupt_control_mode 14 14 Interrupt control mode register for GPIO4. GPIO4ControlMode synchronous 0 asynchronous 1 reg_gpio_5_interrupt_trigger_mode 15 16 Interrupt trigger mode register for GPIO5. GPIO5TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_5_interrupt_control_mode 17 17 Interrupt control mode register for GPIO5. GPIO5ControlMode synchronous 0 asynchronous 1 reg_gpio_6_interrupt_trigger_mode 18 19 Interrupt trigger mode register for GPIO6. GPIO6TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_6_interrupt_control_mode 20 20 Interrupt control mode register for GPIO6. GPIO6ControlMode synchronous 0 asynchronous 1 reg_gpio_7_interrupt_trigger_mode 21 22 Interrupt trigger mode register for GPIO7. GPIO7TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_7_interrupt_control_mode 23 23 Interrupt control mode register for GPIO7. GPIO7ControlMode synchronous 0 asynchronous 1 reg_gpio_8_interrupt_trigger_mode 24 25 Interrupt trigger mode register for GPIO8. GPIO8TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_8_interrupt_control_mode 26 26 Interrupt control mode register for GPIO8. GPIO8ControlMode synchronous 0 asynchronous 1 reg_gpio_9_interrupt_trigger_mode 27 28 Interrupt trigger mode register for GPIO9. GPIO9TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_9_interrupt_control_mode 29 29 Interrupt control mode register for GPIO9. GPIO9ControlMode synchronous 0 asynchronous 1 GPIO_INT_MODE_SET2 GPIO interrupt trigger and control register for GPIO10-GPIO19. 0x1C4 0x00000000 0xffffffff reg_gpio_10_interrupt_trigger_mode 0 1 Interrupt trigger mode register for GPIO10. GPIO10TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_10_interrupt_control_mode 2 2 Interrupt control mode register for GPIO10. GPIO10ControlMode synchronous 0 asynchronous 1 reg_gpio_11_interrupt_trigger_mode 3 4 Interrupt trigger mode register for GPIO11. GPIO11TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_11_interrupt_control_mode 5 5 Interrupt control mode register for GPIO11. GPIO11ControlMode synchronous 0 asynchronous 1 reg_gpio_12_interrupt_trigger_mode 6 7 Interrupt trigger mode register for GPIO12. GPIO12TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_12_interrupt_control_mode 8 8 Interrupt control mode register for GPIO12. GPIO12ControlMode synchronous 0 asynchronous 1 reg_gpio_13_interrupt_trigger_mode 9 10 Interrupt trigger mode register for GPIO13. GPIO13TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_13_interrupt_control_mode 11 11 Interrupt control mode register for GPIO13. GPIO13ControlMode synchronous 0 asynchronous 1 reg_gpio_14_interrupt_trigger_mode 12 13 Interrupt trigger mode register for GPIO14. GPIO14TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_14_interrupt_control_mode 14 14 Interrupt control mode register for GPIO14. GPIO14ControlMode synchronous 0 asynchronous 1 reg_gpio_15_interrupt_trigger_mode 15 16 Interrupt trigger mode register for GPIO15. GPIO15TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_15_interrupt_control_mode 17 17 Interrupt control mode register for GPIO15. GPIO15ControlMode synchronous 0 asynchronous 1 reg_gpio_16_interrupt_trigger_mode 18 19 Interrupt trigger mode register for GPIO16. GPIO16TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_16_interrupt_control_mode 20 20 Interrupt control mode register for GPIO16. GPIO16ControlMode synchronous 0 asynchronous 1 reg_gpio_17_interrupt_trigger_mode 21 22 Interrupt trigger mode register for GPIO17. GPIO17TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_17_interrupt_control_mode 23 23 Interrupt control mode register for GPIO17. GPIO17ControlMode synchronous 0 asynchronous 1 reg_gpio_18_interrupt_trigger_mode 24 25 Interrupt trigger mode register for GPIO18. GPIO18TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_18_interrupt_control_mode 26 26 Interrupt control mode register for GPIO18. GPIO18ControlMode synchronous 0 asynchronous 1 reg_gpio_19_interrupt_trigger_mode 27 28 Interrupt trigger mode register for GPIO19. GPIO19TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_19_interrupt_control_mode 29 29 Interrupt control mode register for GPIO19. GPIO19ControlMode synchronous 0 asynchronous 1 GPIO_INT_MODE_SET3 GPIO interrupt trigger and control register for GPIO20-GPIO29. 0x1C8 0x00000000 0xffffffff reg_gpio_20_interrupt_trigger_mode 0 1 Interrupt trigger mode register for GPIO20. GPIO20TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_20_interrupt_control_mode 2 2 Interrupt control mode register for GPIO20. GPIO20ControlMode synchronous 0 asynchronous 1 reg_gpio_21_interrupt_trigger_mode 3 4 Interrupt trigger mode register for GPIO21. GPIO21TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_21_interrupt_control_mode 5 5 Interrupt control mode register for GPIO21. GPIO21ControlMode synchronous 0 asynchronous 1 reg_gpio_22_interrupt_trigger_mode 6 7 Interrupt trigger mode register for GPIO22. GPIO22TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_22_interrupt_control_mode 8 8 Interrupt control mode register for GPIO22. GPIO22ControlMode synchronous 0 asynchronous 1 reg_gpio_23_interrupt_trigger_mode 9 10 Interrupt trigger mode register for GPIO23. GPIO23TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_23_interrupt_control_mode 11 11 Interrupt control mode register for GPIO23. GPIO23ControlMode synchronous 0 asynchronous 1 reg_gpio_24_interrupt_trigger_mode 12 13 Interrupt trigger mode register for GPIO24. GPIO24TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_24_interrupt_control_mode 14 14 Interrupt control mode register for GPIO24. GPIO24ControlMode synchronous 0 asynchronous 1 reg_gpio_25_interrupt_trigger_mode 15 16 Interrupt trigger mode register for GPIO25. GPIO25TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_25_interrupt_control_mode 17 17 Interrupt control mode register for GPIO25. GPIO25ControlMode synchronous 0 asynchronous 1 reg_gpio_26_interrupt_trigger_mode 18 19 Interrupt trigger mode register for GPIO26. GPIO26TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_26_interrupt_control_mode 20 20 Interrupt control mode register for GPIO26. GPIO26ControlMode synchronous 0 asynchronous 1 reg_gpio_27_interrupt_trigger_mode 21 22 Interrupt trigger mode register for GPIO27. GPIO27TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_27_interrupt_control_mode 23 23 Interrupt control mode register for GPIO27. GPIO27ControlMode synchronous 0 asynchronous 1 reg_gpio_28_interrupt_trigger_mode 24 25 Interrupt trigger mode register for GPIO28. GPIO28TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_28_interrupt_control_mode 26 26 Interrupt control mode register for GPIO28. GPIO28ControlMode synchronous 0 asynchronous 1 reg_gpio_29_interrupt_trigger_mode 27 28 Interrupt trigger mode register for GPIO29. GPIO29TriggerMode negative_pulse 0 positive_pulse 1 negative_level 2 positive_level 3 reg_gpio_29_interrupt_control_mode 29 29 Interrupt control mode register for GPIO29. GPIO29ControlMode synchronous 0 asynchronous 1 led_driver led_driver. 0x224 0x00000080 0xffffffff pu_leddrv 31 31 ir_rx_gpio_sel 8 9 leddrv_ibias 4 7 led_din_polarity_sel 2 2 led_din_sel 1 1 led_din_reg 0 0 gpdac_ctrl gpdac_ctrl. 0x308 0x00000003 0xffffffff gpdac_reserved 24 31 gpdac_test_sel 9 11 gpdac_ref_sel 8 8 gpdac_test_en 7 7 gpdacb_rstn_ana 1 1 gpdaca_rstn_ana 0 0 gpdac_actrl gpdac_actrl. 0x30C 0x000c0000 0xffffffff gpdac_a_outmux 20 22 gpdac_a_rng 18 19 gpdac_ioa_en 1 1 gpdac_a_en 0 0 gpdac_bctrl gpdac_bctrl. 0x310 0x000c0000 0xffffffff gpdac_b_outmux 20 22 gpdac_b_rng 18 19 gpdac_iob_en 1 1 gpdac_b_en 0 0 gpdac_data gpdac_data. 0x314 0x00000000 0xffffffff gpdac_a_data 16 25 gpdac_b_data 0 9 tzc_glb_ctrl_0 tzc_glb_ctrl_0. 0xF00 0x00000000 0xffffffff read-only tzc_glb_clk_lock 31 31 tzc_glb_mbist_lock 30 30 tzc_glb_dbg_lock 29 29 tzc_glb_bmx_lock 28 28 tzc_glb_l2c_lock 27 27 tzc_glb_sram_lock 26 26 tzc_glb_misc_lock 25 25 tzc_glb_ctrl_ungated_ap_lock 15 15 tzc_glb_ctrl_sys_reset_lock 14 14 tzc_glb_ctrl_cpu_reset_lock 13 13 tzc_glb_ctrl_pwron_rst_lock 12 12 tzc_glb_swrst_s30_lock 8 8 tzc_glb_swrst_s01_lock 1 1 tzc_glb_swrst_s00_lock 0 0 tzc_glb_ctrl_1 tzc_glb_ctrl_1. 0xF04 0x00000000 0xffffffff read-only tzc_glb_swrst_s1f_lock 31 31 tzc_glb_swrst_s1e_lock 30 30 tzc_glb_swrst_s1d_lock 29 29 tzc_glb_swrst_s1c_lock 28 28 tzc_glb_swrst_s1b_lock 27 27 tzc_glb_swrst_s1a_lock 26 26 tzc_glb_swrst_s19_lock 25 25 tzc_glb_swrst_s18_lock 24 24 tzc_glb_swrst_s17_lock 23 23 tzc_glb_swrst_s16_lock 22 22 tzc_glb_swrst_s15_lock 21 21 tzc_glb_swrst_s14_lock 20 20 tzc_glb_swrst_s13_lock 19 19 tzc_glb_swrst_s12_lock 18 18 tzc_glb_swrst_s11_lock 17 17 tzc_glb_swrst_s10_lock 16 16 tzc_glb_swrst_s2f_lock 15 15 tzc_glb_swrst_s2e_lock 14 14 tzc_glb_swrst_s2d_lock 13 13 tzc_glb_swrst_s2c_lock 12 12 tzc_glb_swrst_s2b_lock 11 11 tzc_glb_swrst_s2a_lock 10 10 tzc_glb_swrst_s29_lock 9 9 tzc_glb_swrst_s28_lock 8 8 tzc_glb_swrst_s27_lock 7 7 tzc_glb_swrst_s26_lock 6 6 tzc_glb_swrst_s25_lock 5 5 tzc_glb_swrst_s24_lock 4 4 tzc_glb_swrst_s23_lock 3 3 tzc_glb_swrst_s22_lock 2 2 tzc_glb_swrst_s21_lock 1 1 tzc_glb_swrst_s20_lock 0 0 tzc_glb_ctrl_2 tzc_glb_ctrl_2. 0xF08 0x00000000 0xffffffff read-only tzc_glb_gpio_28_lock 28 28 tzc_glb_gpio_27_lock 27 27 tzc_glb_gpio_26_lock 26 26 tzc_glb_gpio_25_lock 25 25 tzc_glb_gpio_24_lock 24 24 tzc_glb_gpio_23_lock 23 23 tzc_glb_gpio_22_lock 22 22 tzc_glb_gpio_21_lock 21 21 tzc_glb_gpio_20_lock 20 20 tzc_glb_gpio_19_lock 19 19 tzc_glb_gpio_18_lock 18 18 tzc_glb_gpio_17_lock 17 17 tzc_glb_gpio_16_lock 16 16 tzc_glb_gpio_15_lock 15 15 tzc_glb_gpio_14_lock 14 14 tzc_glb_gpio_13_lock 13 13 tzc_glb_gpio_12_lock 12 12 tzc_glb_gpio_11_lock 11 11 tzc_glb_gpio_10_lock 10 10 tzc_glb_gpio_9_lock 9 9 tzc_glb_gpio_8_lock 8 8 tzc_glb_gpio_7_lock 7 7 tzc_glb_gpio_6_lock 6 6 tzc_glb_gpio_5_lock 5 5 tzc_glb_gpio_4_lock 4 4 tzc_glb_gpio_3_lock 3 3 tzc_glb_gpio_2_lock 2 2 tzc_glb_gpio_1_lock 1 1 tzc_glb_gpio_0_lock 0 0 tzc_glb_ctrl_3 Reserved according to SDK. 0xF0C RF RF control 0x40001000 rf 32 read-write 0 0x1000 registers rf_rev Silicon revision 0x0 hw_rev 16 23 fw_rev 8 15 rf_id 0 7 rf_fsm_ctrl_hw Digital Control 0x4 rf_rc_state_value 28 30 rf_fsm_st_int_set 24 24 rf_fsm_st_int_clr 20 20 rf_fsm_st_int 16 16 rf_fsm_st_int_sel 12 14 rf_rc_state_dbg_en 11 11 rf_rc_state_dbg 8 10 rf_fsm_state 4 6 rf_fsm_t2r_cal_mode 2 3 rf_fsm_ctrl_en 1 1 rf_fsm_ctrl_sw rfsm status reg 0x8 lo_unlocked 20 20 inc_cal_timeout 16 16 full_cal_en 12 12 rf_fsm_sw_st_vld 8 8 rf_fsm_sw_st 0 4 rfctrl_hw_en Control logic switch 0xC adda_ctrl_hw 12 12 rbb_pkdet_out_rstn_ctrl_hw 11 11 rbb_pkdet_en_ctrl_hw 10 10 sdm_ctrl_hw 9 9 inc_fcal_ctrl_en_hw 8 8 inc_acal_ctrl_en_hw 7 7 lo_ctrl_hw 6 6 trxcal_ctrl_hw 5 5 rbb_bw_ctrl_hw 4 4 lna_ctrl_hw 3 3 tx_gain_ctrl_hw 2 2 rx_gain_ctrl_hw 1 1 pu_ctrl_hw 0 0 temp_comp temp_comp. 0x10 temp_comp_en 16 16 const_fcal 8 15 const_acal 0 7 rfcal_status rfcal_status. 0x14 dpd_status 30 31 tenscal_status 28 29 pwdet_cal_status 26 27 riqcal_status_resv 24 25 tiqcal_status_resv 22 23 lo_leakcal_status 20 21 rccal_status 18 19 tos_status 16 17 ros_status 14 15 clkpll_cal_status 12 13 inc_acal_status 10 11 inc_fcal_status 8 9 acal_status 6 7 fcal_status 4 5 adc_oscal_status 2 3 rcal_status 0 1 rfcal_status2 rfcal_status2. 0x18 dl_rfcal_table_status 0 1 rfcal_ctrlen Calibration mode register 0x1C dpd_en 17 17 tsencal_en 16 16 pwdet_cal_en 15 15 riqcal_en 14 14 tiqcal_en 13 13 lo_leakcal_en 12 12 rccal_en 11 11 toscal_en 10 10 roscal_en 9 9 clkpll_cal_en 8 8 roscal_inc_en 7 7 acal_inc_en 6 6 fcal_inc_en 5 5 acal_en 4 4 fcal_en 3 3 dl_rfcal_table_en 2 2 adc_oscal_en 1 1 rcal_en_resv 0 0 rfcal_stateen rf calibration state enabl in full cal list 0x20 rfcal_level 30 31 dpd_sten 16 16 tsencal_sten 15 15 pwdet_cal_sten 14 14 riqcal_sten 13 13 tiqcal_sten 12 12 lo_leakcal_sten 11 11 rccal_sten 10 10 toscal_sten_resv 9 9 roscal_sten 8 8 clkpll_cal_sten 7 7 inc_acal_sten 6 6 inc_fcal_sten 5 5 acal_sten 4 4 fcal_sten 3 3 dl_rfcal_table_sten 2 2 adc_oscal_sten 1 1 rcal_sten_resv 0 0 saradc_resv SARADC Control Registers 0x24 rf_base_ctrl1 ZRF Control register 0 0x28 mbg_trim 27 28 pud_pa_dly 14 15 pud_iref_dly 12 13 pud_vco_dly 10 11 ppu_lead 8 9 lo_sdm_rst_dly 2 3 aupll_sdm_rst_dly 0 1 rf_base_ctrl2 ZRF Control register 0 0x2C pucr1 pucr1. 0x30 pu_tosdac 31 31 pu_pwrmx 30 30 pu_rosdac 29 29 pu_pkdet 28 28 trsw_en 26 26 pu_txbuf 25 25 pu_rxbuf 24 24 pu_osmx 23 23 pu_pfd 22 22 pu_fbdv 21 21 pu_vco 20 20 pu_dac 19 19 pu_tbb 18 18 pu_tmx 17 17 pu_pa 16 16 pu_op_atest 15 15 pu_adc 14 14 adc_clk_en 13 13 pu_adda_ldo 12 12 pu_rbb 11 11 pu_rmx 10 10 pu_rmxgm 9 9 pu_lna 8 8 pu_sfreg 0 0 pucr1_hw read only from hardware logic 0x34 pu_tosdac_hw 31 31 pu_rosdac_hw 29 29 pu_pkdet_hw 28 28 trsw_en_hw 26 26 pu_txbuf_hw 25 25 pu_rxbuf_hw 24 24 pu_osmx_hw 23 23 pu_pfd_hw 22 22 pu_fbdv_hw 21 21 pu_vco_hw 20 20 pu_dac_hw 19 19 pu_tbb_hw 18 18 pu_tmx_hw 17 17 pu_pa_hw 16 16 pu_adc_hw 14 14 adc_clk_en_hw 13 13 pu_adda_ldo_hw 12 12 pu_rbb_hw 11 11 pu_rmx_hw 10 10 pu_rmxgm_hw 9 9 pu_lna_hw 8 8 pu_sfreg_hw 0 0 pucr2 pucr2. 0x38 pucr2_hw pucr2_hw. 0x3C ppu_ctrl_hw ppu_ctrl_hw. 0x40 ppu_txbuf_hw 25 25 ppu_rxbuf_hw 24 24 ppu_osmx_hw 23 23 ppu_pfd_hw 22 22 ppu_fbdv_hw 21 21 ppu_vco_hw 20 20 ppu_rbb_hw 11 11 ppu_rmxgm_hw 9 9 ppu_lna_hw 8 8 pud_ctrl_hw pud_ctrl_hw. 0x44 pud_vco_hw 20 20 trx_gain1 gain control1 0x48 gc_tbb_boost 28 29 gc_tbb 20 24 gc_tmx 16 18 gc_rbb2 12 14 gc_rbb1 8 9 gc_rmxgm 4 5 gc_lna 0 2 trx_gain_hw trx gain hardware readback 0x4C gc_tbb_boost_hw 28 29 gc_tbb_hw 20 24 gc_tmx_hw 16 18 gc_rbb2_hw 12 14 gc_rbb1_hw 8 9 gc_rmxgm_hw 4 5 gc_lna_hw 0 2 ten_dc dc test register 0x50 ten_lodist 27 27 ten_lf 26 26 ten_pfdcp 25 25 ten_vco 24 24 ten_dac_q 22 22 ten_dac_i 21 21 ten_adc 20 20 ten_tbb 19 19 ten_atest 18 18 ten_bq 17 17 ten_tia 16 16 ten_tmx 15 15 ten_pa 14 14 ten_rrf_1 13 13 ten_rrf_0 12 12 ten_clkpll_sfreg 9 9 ten_clkpll 8 8 dc_tp_clkpll_en 4 4 dc_tp_en 3 3 tmux 0 2 ten_dig digital test register 0x54 rf_dtest_en 23 23 dtest_pull_down 9 9 dten_lo_fref 8 8 dten_lo_fsdm 6 6 dten_clkpll_fin 5 5 dten_clkpll_fref 4 4 dten_clkpll_fsdm 3 3 dten_clkpll_clk32m 2 2 dten_clkpll_clk96m 1 1 dten_clkpll_postdiv_clk 0 0 ten_ac ac test register 0x58 atest_in_en_i 23 23 atest_in_en_q 22 22 atest_out_en_i 21 21 atest_out_en_q 20 20 atest_gain_r5 16 18 atest_gain_r6 14 15 atest_gain_r7 12 13 atest_gain_r8 10 11 atest_gain_r9 8 9 atest_in_en 6 6 atest_in_trx_sw 5 5 atest_dac_en 4 4 atest_op_cc 0 3 pmip_mv2aon pmip_mv2aon. 0x5C cip RX normal bias mode registers 0x60 vg13_sel 2 3 vg11_sel 0 1 pa1 pa1. 0x64 pa_att_gc 28 31 pa_pwrmx_bm 24 26 pa_pwrmx_dac_pn_switch 22 22 pa_pwrmx_osdac 18 21 pa_lz_bias_en 17 17 pa_ib_fix 16 16 pa_half_on 15 15 pa_vbcas 12 14 pa_vbcore 8 11 pa_iet 4 7 pa_etb_en 3 3 pa_iaq 0 2 pa2 RX normal bias mode registers 0x68 pa_ib_fix_hw 17 17 pa_half_on_hw 16 16 pa_vbcas_hw 12 14 pa_vbcore_hw 8 11 pa_iet_hw 4 7 pa_etb_en_hw 3 3 tmx tmx. 0x6C tx_tsense_en 16 16 tmx_bm_cas_bulk 12 14 tmx_bm_cas 8 10 tmx_bm_sw 4 6 tmx_cs 0 2 tbb tbb. 0x70 tbb_tosdac_i 24 29 tbb_tosdac_q 16 21 tbb_atest_out_en 15 15 tbb_iq_bias_short 14 14 tbb_cflt 12 13 tbb_vcm 8 9 tbb_bm_cg 4 5 tbb_bm_sf 0 1 lna lna. 0x74 lna_lg_gsel 24 26 lna_cap_lg 20 21 lna_rfb_match 16 18 lna_load_csw_hw 12 15 lna_load_csw 8 11 lna_bm_hw 4 7 lna_bm 0 3 rmxgm rmxgm. 0x78 rmxgm_10m_mode_en 8 8 rmxgm_bm 4 6 rmx_bm 0 2 rbb1 rbb1. 0x7C rosdac_range 31 31 rosdac_i_hw 24 29 rosdac_q_hw 16 21 rosdac_i 8 13 rosdac_q 0 5 rbb2 rbb2. 0x80 rbb_cap1_fc_i 24 29 rbb_cap1_fc_q 16 21 rbb_cap2_fc_i 8 13 rbb_cap2_fc_q 0 5 rbb3 rbb3. 0x84 pwr_det_en 31 31 rxiqcal_en 28 28 rbb_bw 24 25 rbb_tia_iqbias_short 21 21 rbb_bq_iqbias_short 20 20 rbb_vcm 16 17 rbb_bm_op 12 14 rbb_deq 8 9 rbb_bt_fif_tune 5 6 rbb_bt_mode 4 4 rbb_bt_mode_hw 0 0 rbb4 rbb4. 0x88 pkdet_out_latch 24 24 pkdet_out_raw 20 20 rbb_pkdet_en_hw 16 16 rbb_pkdet_out_rstn_hw 12 12 rbb_pkdet_en 8 8 rbb_pkdet_out_rstn 4 4 rbb_pkdet_vth 0 3 adda1 adda1. 0x8C adda_ldo_dvdd_sel_hw 24 26 adda_ldo_dvdd_sel 20 22 adda_ldo_byps 16 16 dac_clk_sync_inv 13 13 dac_rccalsel 12 12 dac_clk_sel 8 9 dac_bias_sel 4 5 dac_dvdd_sel 0 1 adda2 adda2. 0x90 adc_clk_div_sel 28 28 adc_clk_inv 24 24 adc_clk_sync_inv 20 20 adc_gt_rm 16 16 adc_sar_ascal_en 12 12 adc_dvdd_sel 8 9 adc_dly_ctl 4 5 adc_vref_sel 0 1 vco1 vco1. 0xA0 lo_vco_idac_cw_hw 24 28 lo_vco_idac_cw 16 20 lo_vco_freq_cw_hw 8 15 lo_vco_freq_cw 0 7 vco2 vco2. 0xA4 acal_inc_en_hw 16 16 acal_vco_ud 12 12 acal_vref_cw 8 10 lo_vco_short_idac_filter 6 6 lo_vco_short_vbias_filter 5 5 lo_vco_idac_boot 4 4 lo_vco_vbias_cw 0 1 vco3 vco3. 0xA8 fcal_cnt_op 16 31 fcal_div 0 15 vco4 vco4. 0xAC fcal_inc_vctrl_ud 24 25 fcal_cnt_rdy 20 20 fcal_inc_large_range 16 16 fcal_inc_en_hw 8 8 fcal_cnt_start 4 4 pfdcp pfdcp. 0xB0 lo_pfd_rst_csd_hw 29 29 lo_pfd_rst_csd 28 28 lo_pfd_rvdd_boost 24 24 lo_cp_hiz 20 20 lo_cp_opamp_en 16 16 lo_cp_ota_en 12 12 lo_cp_startup_en 8 8 lo_cp_sel_hw 4 4 lo_cp_sel 0 0 lo lo. 0xB4 lo_slipped_up 24 24 lo_slipped_dn 20 20 lo_lf_r4_short 18 18 lo_lf_r4 16 17 lo_lf_cz 14 15 lo_lf_rz 12 13 lo_lf_cz_hw 8 9 lo_lf_r4_hw 4 5 lo_lf_rz_hw 0 1 fbdv fbdv. 0xB8 lo_fbdv_rst_hw 20 20 lo_fbdv_rst 16 16 lo_fbdv_sel_fb_clk 12 13 lo_fbdv_sel_sample_clk 8 9 lo_fbdv_halfstep_en 4 4 lo_fbdv_halfstep_en_hw 0 0 lodist lodist. 0xBC lo_lodist_rxbuf_stre 28 28 lo_lodist_txbuf_stre 24 24 lo_osmx_cap 20 23 lo_osmx_capbank_bias 16 17 lo_osmx_vbuf_stre 12 12 lo_osmx_fix_cap 8 8 lo_osmx_en_xgm 4 4 lo_osmx_xgm_boost 0 0 sdm1 sdm1. 0xC0 lo_sdm_flag 20 20 lo_sdm_rstb_hw 17 17 lo_sdm_rstb 16 16 lo_sdm_bypass 12 12 lo_sdm_dither_sel 8 9 lo_sdm_bypass_hw 4 4 lo_sdm_dither_sel_hw 0 1 sdm2 sdm2. 0xC4 lo_sdmin 0 29 sdm3 sdm3. 0xC8 lo_sdmin_hw 0 29 rf_resv_reg_0 rf_resv_reg_0. 0xEC rf_reserved0 0 31 rf_resv_reg_1 rf_resv_reg_1. 0xF0 rf_reserved1 0 31 rf_resv_reg_2 rf_resv_reg_2. 0xF4 rf_reserved2 0 31 rrf_gain_index1 rrf_gain_index1. 0xF8 gain_ctrl5_gc_lna 27 29 gain_ctrl5_gc_rmxgm 25 26 gain_ctrl4_gc_lna 22 24 gain_ctrl4_gc_rmxgm 20 21 gain_ctrl3_gc_lna 17 19 gain_ctrl3_gc_rmxgm 15 16 gain_ctrl2_gc_lna 12 14 gain_ctrl2_gc_rmxgm 10 11 gain_ctrl1_gc_lna 7 9 gain_ctrl1_gc_rmxgm 5 6 gain_ctrl0_gc_lna 2 4 gain_ctrl0_gc_rmxgm 0 1 rrf_gain_index2 rrf_gain_index2. 0xFC gain_ctrl6_gc_lna 12 14 gain_ctrl6_gc_rmxgm 10 11 gain_ctrl7_gc_lna 7 9 gain_ctrl7_gc_rmxgm 5 6 gain_ctrl8_gc_lna 2 4 gain_ctrl8_gc_rmxgm 0 1 lna_ctrl_hw_mux lna_ctrl_hw_mux. 0x100 lna_load_csw_lg 12 15 lna_load_csw_hg 8 11 lna_bm_lg 4 7 lna_bm_hg 0 3 rbb_gain_index1 rbb_gain_index1. 0x104 gain_ctrl3_gc_rbb2 28 30 gain_ctrl3_gc_rbb1 24 25 gain_ctrl2_gc_rbb2 20 22 gain_ctrl2_gc_rbb1 16 17 gain_ctrl1_gc_rbb2 12 14 gain_ctrl1_gc_rbb1 8 9 gain_ctrl0_gc_rbb2 4 6 gain_ctrl0_gc_rbb1 0 1 rbb_gain_index2 rbb_gain_index2. 0x108 gain_ctrl7_gc_rbb2 28 30 gain_ctrl7_gc_rbb1 24 25 gain_ctrl6_gc_rbb2 20 22 gain_ctrl6_gc_rbb1 16 17 gain_ctrl5_gc_rbb2 12 14 gain_ctrl5_gc_rbb1 8 9 gain_ctrl4_gc_rbb2 4 6 gain_ctrl4_gc_rbb1 0 1 rbb_gain_index3 rbb_gain_index3. 0x10C gain_ctrl11_gc_rbb2 28 30 gain_ctrl11_gc_rbb1 24 25 gain_ctrl10_gc_rbb2 20 22 gain_ctrl10_gc_rbb1 16 17 gain_ctrl9_gc_rbb2 12 14 gain_ctrl9_gc_rbb1 8 9 gain_ctrl8_gc_rbb2 4 6 gain_ctrl8_gc_rbb1 0 1 rbb_gain_index4 rbb_gain_index4. 0x110 gain_ctrl15_gc_rbb2 28 30 gain_ctrl15_gc_rbb1 24 25 gain_ctrl14_gc_rbb2 20 22 gain_ctrl14_gc_rbb1 16 17 gain_ctrl13_gc_rbb2 12 14 gain_ctrl13_gc_rbb1 8 9 gain_ctrl12_gc_rbb2 4 6 gain_ctrl12_gc_rbb1 0 1 rbb_gain_index5 rbb_gain_index5. 0x114 gain_ctrl16_gc_rbb2 4 6 gain_ctrl16_gc_rbb1 0 1 tbb_gain_index1 tbb_gain_index1. 0x118 gain_ctrl1_gc_tbb_boost 30 31 gain_ctrl1_dac_bias_sel 28 29 gain_ctrl1_gc_tmx 24 26 gain_ctrl1_gc_tbb 16 20 gain_ctrl0_gc_tbb_boost 14 15 gain_ctrl0_dac_bias_sel 12 13 gain_ctrl0_gc_tmx 8 10 gain_ctrl0_gc_tbb 0 4 tbb_gain_index2 tbb_gain_index2. 0x11C gain_ctrl3_gc_tbb_boost 30 31 gain_ctrl3_dac_bias_sel 28 29 gain_ctrl3_gc_tmx 24 26 gain_ctrl3_gc_tbb 16 20 gain_ctrl2_gc_tbb_boost 14 15 gain_ctrl2_dac_bias_sel 12 13 gain_ctrl2_gc_tmx 8 10 gain_ctrl2_gc_tbb 0 4 tbb_gain_index3 tbb_gain_index3. 0x120 gain_ctrl5_gc_tbb_boost 30 31 gain_ctrl5_dac_bias_sel 28 29 gain_ctrl5_gc_tmx 24 26 gain_ctrl5_gc_tbb 16 20 gain_ctrl4_gc_tbb_boost 14 15 gain_ctrl4_dac_bias_sel 12 13 gain_ctrl4_gc_tmx 8 10 gain_ctrl4_gc_tbb 0 4 tbb_gain_index4 tbb_gain_index4. 0x124 gain_ctrl7_gc_tbb_boost 30 31 gain_ctrl7_dac_bias_sel 28 29 gain_ctrl7_gc_tmx 24 26 gain_ctrl7_gc_tbb 16 20 gain_ctrl6_gc_tbb_boost 14 15 gain_ctrl6_dac_bias_sel 12 13 gain_ctrl6_gc_tmx 8 10 gain_ctrl6_gc_tbb 0 4 pa_reg_ctrl_hw1 pa_reg_ctrl_hw1. 0x128 pa_vbcas_11n 20 22 pa_vbcore_11n 16 19 pa_iet_11n 12 15 pa_reg_ctrl_hw2 pa_reg_ctrl_hw2. 0x12C pa_vbcas_11b 20 22 pa_vbcore_11b 16 19 pa_iet_11b 12 15 pa_vbcas_11g 8 10 pa_vbcore_11g 4 7 pa_iet_11g 0 3 pa_reg_wifi_ctrl_hw pa_reg_wifi_ctrl_hw. 0x130 pa_ib_fix_wifi 16 16 pa_etb_en_wifi 8 8 pa_half_on_wifi 0 0 adda_reg_ctrl_hw adda_reg_ctrl_hw. 0x134 adda_ldo_dvdd_sel_tx 4 6 adda_ldo_dvdd_sel_rx 0 2 lo_reg_ctrl_hw1 lo_reg_ctrl_hw1. 0x138 lo_lf_r4_tx 24 25 lo_lf_r4_rx 20 21 lo_lf_rz_tx 16 17 lo_lf_rz_rx 12 13 lo_lf_cz_tx 8 9 lo_lf_cz_rx 4 5 lo_cp_sel_tx 3 3 lo_cp_sel_rx 2 2 lo_fbdv_halfstep_en_tx 1 1 lo_fbdv_halfstep_en_rx 0 0 lo_cal_ctrl_hw1 lo_cal_ctrl_hw1. 0x13C lo_vco_freq_cw_2408 24 31 lo_vco_idac_cw_2408 16 20 lo_vco_freq_cw_2404 8 15 lo_vco_idac_cw_2404 0 4 lo_cal_ctrl_hw2 lo_cal_ctrl_hw2. 0x140 lo_vco_freq_cw_2416 24 31 lo_vco_idac_cw_2416 16 20 lo_vco_freq_cw_2412 8 15 lo_vco_idac_cw_2412 0 4 lo_cal_ctrl_hw3 lo_cal_ctrl_hw3. 0x144 lo_vco_freq_cw_2424 24 31 lo_vco_idac_cw_2424 16 20 lo_vco_freq_cw_2420 8 15 lo_vco_idac_cw_2420 0 4 lo_cal_ctrl_hw4 lo_cal_ctrl_hw4. 0x148 lo_vco_freq_cw_2432 24 31 lo_vco_idac_cw_2432 16 20 lo_vco_freq_cw_2428 8 15 lo_vco_idac_cw_2428 0 4 lo_cal_ctrl_hw5 lo_cal_ctrl_hw5. 0x14C lo_vco_freq_cw_2440 24 31 lo_vco_idac_cw_2440 16 20 lo_vco_freq_cw_2436 8 15 lo_vco_idac_cw_2436 0 4 lo_cal_ctrl_hw6 lo_cal_ctrl_hw6. 0x150 lo_vco_freq_cw_2448 24 31 lo_vco_idac_cw_2448 16 20 lo_vco_freq_cw_2444 8 15 lo_vco_idac_cw_2444 0 4 lo_cal_ctrl_hw7 lo_cal_ctrl_hw7. 0x154 lo_vco_freq_cw_2456 24 31 lo_vco_idac_cw_2456 16 20 lo_vco_freq_cw_2452 8 15 lo_vco_idac_cw_2452 0 4 lo_cal_ctrl_hw8 lo_cal_ctrl_hw8. 0x158 lo_vco_freq_cw_2464 24 31 lo_vco_idac_cw_2464 16 20 lo_vco_freq_cw_2460 8 15 lo_vco_idac_cw_2460 0 4 lo_cal_ctrl_hw9 lo_cal_ctrl_hw9. 0x15C lo_vco_freq_cw_2472 24 31 lo_vco_idac_cw_2472 16 20 lo_vco_freq_cw_2468 8 15 lo_vco_idac_cw_2468 0 4 lo_cal_ctrl_hw10 lo_cal_ctrl_hw10. 0x160 lo_vco_freq_cw_2480 24 31 lo_vco_idac_cw_2480 16 20 lo_vco_freq_cw_2476 8 15 lo_vco_idac_cw_2476 0 4 lo_cal_ctrl_hw11 lo_cal_ctrl_hw11. 0x164 lo_vco_freq_cw_2484 8 15 lo_vco_idac_cw_2484 0 4 rosdac_ctrl_hw1 rosdac_ctrl_hw1. 0x168 rosdac_q_gc1 24 29 rosdac_i_gc1 16 21 rosdac_q_gc0 8 13 rosdac_i_gc0 0 5 rosdac_ctrl_hw2 rosdac_ctrl_hw2. 0x16C rosdac_q_gc3 24 29 rosdac_i_gc3 16 21 rosdac_q_gc2 8 13 rosdac_i_gc2 0 5 rxiq_ctrl_hw1 rxiq_ctrl_hw1. 0x170 rx_iq_gain_comp_gc0 16 26 rx_iq_phase_comp_gc0 0 9 rxiq_ctrl_hw2 rxiq_ctrl_hw2. 0x174 rx_iq_gain_comp_gc1 16 26 rx_iq_phase_comp_gc1 0 9 rxiq_ctrl_hw3 rxiq_ctrl_hw3. 0x178 rx_iq_gain_comp_gc2 16 26 rx_iq_phase_comp_gc2 0 9 rxiq_ctrl_hw4 rxiq_ctrl_hw4. 0x17C rx_iq_gain_comp_gc3 16 26 rx_iq_phase_comp_gc3 0 9 tosdac_ctrl_hw1 tosdac_ctrl_hw1. 0x180 tbb_tosdac_q_gc1 24 29 tbb_tosdac_i_gc1 16 21 tbb_tosdac_q_gc0 8 13 tbb_tosdac_i_gc0 0 5 tosdac_ctrl_hw2 tosdac_ctrl_hw2. 0x184 tbb_tosdac_q_gc3 24 29 tbb_tosdac_i_gc3 16 21 tbb_tosdac_q_gc2 8 13 tbb_tosdac_i_gc2 0 5 tosdac_ctrl_hw3 tosdac_ctrl_hw3. 0x188 tbb_tosdac_q_gc5 24 29 tbb_tosdac_i_gc5 16 21 tbb_tosdac_q_gc4 8 13 tbb_tosdac_i_gc4 0 5 tosdac_ctrl_hw4 tosdac_ctrl_hw4. 0x18C tbb_tosdac_q_gc7 24 29 tbb_tosdac_i_gc7 16 21 tbb_tosdac_q_gc6 8 13 tbb_tosdac_i_gc6 0 5 tx_iq_gain_hw0 tx_iq_gain_hw0. 0x190 tx_iq_gain_comp_gc0 16 26 tx_iq_phase_comp_gc0 0 9 tx_iq_gain_hw1 tx_iq_gain_hw1. 0x194 tx_iq_gain_comp_gc1 16 26 tx_iq_phase_comp_gc1 0 9 tx_iq_gain_hw2 tx_iq_gain_hw2. 0x198 tx_iq_gain_comp_gc2 16 26 tx_iq_phase_comp_gc2 0 9 tx_iq_gain_hw3 tx_iq_gain_hw3. 0x19C tx_iq_gain_comp_gc3 16 26 tx_iq_phase_comp_gc3 0 9 tx_iq_gain_hw4 tx_iq_gain_hw4. 0x1A0 tx_iq_gain_comp_gc4 16 26 tx_iq_phase_comp_gc4 0 9 tx_iq_gain_hw5 tx_iq_gain_hw5. 0x1A4 tx_iq_gain_comp_gc5 16 26 tx_iq_phase_comp_gc5 0 9 tx_iq_gain_hw6 tx_iq_gain_hw6. 0x1A8 tx_iq_gain_comp_gc6 16 26 tx_iq_phase_comp_gc6 0 9 tx_iq_gain_hw7 tx_iq_gain_hw7. 0x1AC tx_iq_gain_comp_gc7 16 26 tx_iq_phase_comp_gc7 0 9 lo_sdm_ctrl_hw1 lo_sdm_ctrl_hw1. 0x1B0 lo_sdm_dither_sel_wlan_2484 26 27 lo_sdm_dither_sel_wlan_2472 24 25 lo_sdm_dither_sel_wlan_2467 22 23 lo_sdm_dither_sel_wlan_2462 20 21 lo_sdm_dither_sel_wlan_2457 18 19 lo_sdm_dither_sel_wlan_2452 16 17 lo_sdm_dither_sel_wlan_2447 14 15 lo_sdm_dither_sel_wlan_2442 12 13 lo_sdm_dither_sel_wlan_2437 10 11 lo_sdm_dither_sel_wlan_2432 8 9 lo_sdm_dither_sel_wlan_2427 6 7 lo_sdm_dither_sel_wlan_2422 4 5 lo_sdm_dither_sel_wlan_2417 2 3 lo_sdm_dither_sel_wlan_2412 0 1 lo_sdm_ctrl_hw2 lo_sdm_ctrl_hw2. 0x1B4 lo_sdm_dither_sel_ble_2432 30 31 lo_sdm_dither_sel_ble_2430 28 29 lo_sdm_dither_sel_ble_2428 26 27 lo_sdm_dither_sel_ble_2426 24 25 lo_sdm_dither_sel_ble_2424 22 23 lo_sdm_dither_sel_ble_2422 20 21 lo_sdm_dither_sel_ble_2420 18 19 lo_sdm_dither_sel_ble_2418 16 17 lo_sdm_dither_sel_ble_2416 14 15 lo_sdm_dither_sel_ble_2414 12 13 lo_sdm_dither_sel_ble_2412 10 11 lo_sdm_dither_sel_ble_2410 8 9 lo_sdm_dither_sel_ble_2408 6 7 lo_sdm_dither_sel_ble_2406 4 5 lo_sdm_dither_sel_ble_2404 2 3 lo_sdm_dither_sel_ble_2402 0 1 lo_sdm_ctrl_hw3 lo_sdm_ctrl_hw3. 0x1B8 lo_sdm_dither_sel_ble_2464 30 31 lo_sdm_dither_sel_ble_2462 28 29 lo_sdm_dither_sel_ble_2460 26 27 lo_sdm_dither_sel_ble_2458 24 25 lo_sdm_dither_sel_ble_2456 22 23 lo_sdm_dither_sel_ble_2454 20 21 lo_sdm_dither_sel_ble_2452 18 19 lo_sdm_dither_sel_ble_2450 16 17 lo_sdm_dither_sel_ble_2448 14 15 lo_sdm_dither_sel_ble_2446 12 13 lo_sdm_dither_sel_ble_2444 10 11 lo_sdm_dither_sel_ble_2442 8 9 lo_sdm_dither_sel_ble_2440 6 7 lo_sdm_dither_sel_ble_2438 4 5 lo_sdm_dither_sel_ble_2436 2 3 lo_sdm_dither_sel_ble_2434 0 1 lo_sdm_ctrl_hw4 lo_sdm_ctrl_hw4. 0x1BC lo_sdm_dither_sel_ble_tx 16 17 lo_sdm_dither_sel_ble_2480 14 15 lo_sdm_dither_sel_ble_2478 12 13 lo_sdm_dither_sel_ble_2476 10 11 lo_sdm_dither_sel_ble_2474 8 9 lo_sdm_dither_sel_ble_2472 6 7 lo_sdm_dither_sel_ble_2470 4 5 lo_sdm_dither_sel_ble_2468 2 3 lo_sdm_dither_sel_ble_2466 0 1 lo_sdm_ctrl_hw5 lo_sdm_ctrl_hw5. 0x1C0 lo_sdm_bypass_mode 12 17 lo_center_freq_mhz 0 11 lo_sdm_ctrl_hw6 lo_sdm_ctrl_hw6. 0x1C4 lo_sdmin_center 0 28 lo_sdm_ctrl_hw7 lo_sdm_ctrl_hw7. 0x1C8 lo_sdmin_1m 0 19 lo_sdm_ctrl_hw8 lo_sdm_ctrl_hw8. 0x1CC lo_sdmin_if 0 19 rbb_bw_ctrl_hw rbb_bw_ctrl_hw. 0x1D0 rbb_bt_mode_ble 0 0 singen_ctrl0 singen_ctrl0. 0x20C singen_en 31 31 singen_clkdiv_n 29 30 singen_unsign_en 28 28 singen_inc_step0 16 25 singen_inc_step1 0 9 singen_ctrl1 singen_ctrl1. 0x210 singen_mode_i 28 31 singen_clkdiv_i 16 25 singen_mode_q 12 15 singen_clkdiv_q 0 9 singen_ctrl2 singen_ctrl2. 0x214 singen_start_addr0_i 22 31 singen_start_addr1_i 12 21 singen_gain_i 0 10 singen_ctrl3 singen_ctrl3. 0x218 singen_start_addr0_q 22 31 singen_start_addr1_q 12 21 singen_gain_q 0 10 singen_ctrl4 singen_ctrl4. 0x21C singen_fix_en_i 28 28 singen_fix_i 16 27 singen_fix_en_q 12 12 singen_fix_q 0 11 rfif_dfe_ctrl0 rfif_dfe_ctrl0. 0x220 test_sel 28 31 bbmode_4s_en 27 27 bbmode_4s 26 26 wifimode_4s_en 25 25 wifimode_4s 23 24 rf_ch_ind_ble_4s_en 22 22 rf_ch_ind_ble_4s 15 21 pad_dac_clkout_inv_en 14 14 pad_adc_clkout_inv_en 13 13 tx_test_sel 11 12 rx_test_sel 9 10 tx_dfe_en_4s_en 8 8 tx_dfe_en_4s 7 7 rx_dfe_en_4s_en 6 6 rx_dfe_en_4s 5 5 rfckg_dac_afifo_inv 4 4 rfckg_adc_clkout_sel 3 3 rfckg_adc_afifo_inv 2 2 rfckg_txclk_4s_on 1 1 rfckg_rxclk_4s_on 0 0 rfif_test_read rfif_test_read. 0x224 test_read 0 31 rfif_dig_ctrl rfif_dig_ctrl. 0x228 rfif_ppud_manaual_en 30 30 rfif_ppud_cnt1 25 29 rfif_ppud_cnt2 16 24 rfif_int_lo_unlocked_mask 3 3 rfckg_rxclk_div2_mode 2 2 test_gc_from_pad_en 1 1 test_from_pad_en 0 0 rf_data_temp_0 rf_data_temp_0. 0x22C rf_data_temp_0 0 31 rf_data_temp_1 rf_data_temp_1. 0x230 rf_data_temp_1 0 31 rf_data_temp_2 rf_data_temp_2. 0x234 rf_data_temp_2 0 31 rf_data_temp_3 rf_data_temp_3. 0x238 rf_data_temp_3 0 31 rf_sram_ctrl0 rf_sram_ctrl0. 0x23C rf_sram_ext_clr 19 19 rf_sram_swap 18 18 rf_sram_link_mode 16 17 rf_sram_link_dly 0 15 rf_sram_ctrl1 rf_sram_ctrl1. 0x240 rf_sram_adc_done_cnt 16 31 rf_sram_adc_sts_clr 3 3 rf_sram_adc_loop_en 2 2 rf_sram_adc_en 1 1 rf_sram_adc_done 0 0 rf_sram_ctrl2 rf_sram_ctrl2. 0x244 rf_sram_adc_addr_start 16 31 rf_sram_adc_addr_end 0 15 rf_sram_ctrl3 rf_sram_ctrl3. 0x248 rf_sram_adc_sts 0 31 rf_sram_ctrl4 rf_sram_ctrl4. 0x24C rf_sram_dac_done_cnt 16 31 rf_sram_dac_sts_clr 3 3 rf_sram_dac_loop_en 2 2 rf_sram_dac_en 1 1 rf_sram_dac_done 0 0 rf_sram_ctrl5 rf_sram_ctrl5. 0x250 rf_sram_dac_addr_start 16 31 rf_sram_dac_addr_end 0 15 rf_sram_ctrl6 rf_sram_ctrl6. 0x254 rf_sram_dac_sts 0 31 rf_ical_ctrl0 rf_ical_ctrl0. 0x258 rf_ical_f_ud_inv_en 31 31 rf_ical_a_ud_inv_en 30 30 rf_ical_f_cnt_n 20 29 rf_ical_a_cnt_n 10 19 rf_ical_r_cnt_n 0 9 rf_ical_ctrl1 rf_ical_ctrl1. 0x25C rf_ical_r_os_i 20 29 rf_ical_r_os_q 10 19 rf_ical_r_avg_n 0 4 rf_ical_ctrl2 rf_ical_ctrl2. 0x260 rf_ical_period_n 0 15 rf_fsm_ctrl0 rf_fsm_ctrl0. 0x264 rf_ch_ind_wifi 0 11 rf_fsm_ctrl1 rf_fsm_ctrl1. 0x268 rf_fsm_pu_pa_dly_n 20 29 rf_fsm_lo_rdy_sbclr 19 19 rf_fsm_lo_rdy_4s_1 18 18 rf_fsm_lo_rdy_rst 17 17 rf_fsm_lo_rdy 16 16 rf_fsm_lo_time 0 15 rf_fsm_ctrl2 rf_fsm_ctrl2. 0x26C rf_fsm_dfe_rx_dly_n 20 29 rf_fsm_dfe_tx_dly_n 10 19 rf_trx_ble_4s_en 6 6 rf_trx_sw_ble_4s 5 5 rf_trx_en_ble_4s 4 4 rf_fsm_st_dbg_en 3 3 rf_fsm_st_dbg 0 2 rf_pkdet_ctrl0 rf_pkdet_ctrl0. 0x270 pkdet_out_mode 5 5 pkdet_out_cnt_en 4 4 pkdet_out_cnt_sts 0 3 dfe_ctrl_0 dfe_ctrl_0. 0x600 tx_dvga_gain_ctrl_hw 31 31 tx_dvga_gain_qdb 24 30 tx_iqc_gain_en 23 23 tx_iqc_gain 12 22 tx_iqc_phase_en 10 10 tx_iqc_phase 0 9 dfe_ctrl_1 dfe_ctrl_1. 0x604 tx_dac_iq_swap 31 31 tx_dac_dat_format 30 30 tx_dac_os_q 16 27 tx_dac_os_i 0 11 dfe_ctrl_2 dfe_ctrl_2. 0x608 rx_adc_iq_swap 31 31 rx_adc_dat_format 30 30 rx_adc_low_pow_en 29 29 rx_adc_dce_flt_en 28 28 rx_adc_os_q 16 25 rx_adc_os_i 0 9 dfe_ctrl_3 dfe_ctrl_3. 0x60C rx_adc_4s_q_en 26 26 rx_adc_4s_q_val 16 25 rx_adc_4s_i_en 10 10 rx_adc_4s_i_val 0 9 dfe_ctrl_4 dfe_ctrl_4. 0x610 rx_pf_i_en 31 31 rx_pf_q_en 30 30 rx_pf_th1 16 25 rx_pf_th2 0 9 dfe_ctrl_5 dfe_ctrl_5. 0x614 rx_iqc_gain_en 23 23 rx_iqc_gain 12 22 rx_iqc_phase_en 10 10 rx_iqc_phase 0 9 dfe_ctrl_6 dfe_ctrl_6. 0x618 rx_pm_in_sel 30 31 rx_pm_en 29 29 rx_pm_done 28 28 rx_pm_freqshift_en 20 20 rx_pm_freqshift_cw 0 19 dfe_ctrl_7 dfe_ctrl_7. 0x61C rx_pm_acc_len 16 31 rx_pm_start_ofs 0 15 dfe_ctrl_8 dfe_ctrl_8. 0x620 rx_pm_iqacc_i 0 24 dfe_ctrl_9 dfe_ctrl_9. 0x624 rx_pm_iqacc_q 0 24 dfe_ctrl_10 dfe_ctrl_10. 0x628 dfe_dac_raw_q 16 26 dfe_dac_raw_i 0 10 dfe_ctrl_11 dfe_ctrl_11. 0x62C dfe_adc_raw_q 16 25 dfe_adc_raw_i 0 9 dfe_ctrl_12 dfe_ctrl_12. 0x630 tx_dvga_gain_qdb_gc3 24 30 tx_dvga_gain_qdb_gc2 16 22 tx_dvga_gain_qdb_gc1 8 14 tx_dvga_gain_qdb_gc0 0 6 dfe_ctrl_13 dfe_ctrl_13. 0x634 tx_dvga_gain_qdb_gc7 24 30 tx_dvga_gain_qdb_gc6 16 22 tx_dvga_gain_qdb_gc5 8 14 tx_dvga_gain_qdb_gc4 0 6 dfe_ctrl_14 dfe_ctrl_14. 0x638 tx_dvga_gain_qdb_gc11 24 30 tx_dvga_gain_qdb_gc10 16 22 tx_dvga_gain_qdb_gc9 8 14 tx_dvga_gain_qdb_gc8 0 6 dfe_ctrl_15 dfe_ctrl_15. 0x63C tx_dvga_gain_qdb_gc15 24 30 tx_dvga_gain_qdb_gc14 16 22 tx_dvga_gain_qdb_gc13 8 14 tx_dvga_gain_qdb_gc12 0 6 dfe_ctrl_16 dfe_ctrl_16. 0x640 rf_tbb_ind_gc7 28 30 rf_tbb_ind_gc6 24 26 rf_tbb_ind_gc5 20 22 rf_tbb_ind_gc4 16 18 rf_tbb_ind_gc3 12 14 rf_tbb_ind_gc2 8 10 rf_tbb_ind_gc1 4 6 rf_tbb_ind_gc0 0 2 dfe_ctrl_17 dfe_ctrl_17. 0x644 rf_tbb_ind_gc15 28 30 rf_tbb_ind_gc14 24 26 rf_tbb_ind_gc13 20 22 rf_tbb_ind_gc12 16 18 rf_tbb_ind_gc11 12 14 rf_tbb_ind_gc10 8 10 rf_tbb_ind_gc9 4 6 rf_tbb_ind_gc8 0 2 dfe_ctrl_18 dfe_ctrl_18. 0x648 tx_dvga_gain_qdb_ble_gc2 16 22 tx_dvga_gain_qdb_ble_gc1 8 14 tx_dvga_gain_qdb_ble_gc0 0 6 GPIP Universal DAC/ADC/ACOMP interface control 0x40002000 GPIP 32 read-write 0 0x1000 registers gpadc_config gpadc_config. 0x0 0x00000000 0xffffffff rsvd_31_24 24 31 gpadc_fifo_thl 22 23 gpadc_fifo_data_count 16 21 read-only gpadc_fifo_underrun_mask 14 14 gpadc_fifo_overrun_mask 13 13 gpadc_rdy_mask 12 12 gpadc_fifo_underrun_clr 10 10 gpadc_fifo_overrun_clr 9 9 gpadc_rdy_clr 8 8 gpadc_fifo_underrun 6 6 read-only gpadc_fifo_overrun 5 5 read-only gpadc_rdy 4 4 read-only gpadc_fifo_full 3 3 read-only gpadc_fifo_ne 2 2 read-only gpadc_fifo_clr 1 1 gpadc_dma_en 0 0 gpadc_dma_rdata gpadc_dma_rdata. 0x4 0x00000000 0xffffffff read-only rsvd_31_26 26 31 gpadc_dma_rdata 0 25 gpdac_config gpdac_config. 0x40 0x00000000 0xffffffff rsvd_31_24 24 31 gpdac_ch_b_sel 20 23 gpdac_ch_a_sel 16 19 gpdac_mode 8 10 dsm_mode 4 5 gpdac_en2 1 1 gpdac_en 0 0 gpdac_dma_config gpdac_dma_config. 0x44 0x00000000 0xffffffff gpdac_dma_format 4 5 gpdac_dma_tx_en 0 0 gpdac_dma_wdata gpdac_dma_wdata. 0x48 0x00000000 0xffffffff write-only gpdac_dma_wdata 0 31 gpdac_tx_fifo_status gpdac_tx_fifo_status. 0x4C 0x00000040 0xffffffff read-only TxFifoWrPtr 8 9 TxFifoRdPtr 4 6 tx_cs 2 3 tx_fifo_full 1 1 tx_fifo_empty 0 0 SEC_DBG SEC_DBG. 0x40003000 SEC_DBG 32 read-write 0 0x1000 registers sd_chip_id_low sd_chip_id_low. 0x0 0x00000000 0xffffffff read-only sd_chip_id_low 0 31 sd_chip_id_high sd_chip_id_high. 0x4 0x00000000 0xffffffff read-only sd_chip_id_high 0 31 sd_wifi_mac_low sd_wifi_mac_low. 0x8 0x00000000 0xffffffff read-only sd_wifi_mac_low 0 31 sd_wifi_mac_high sd_wifi_mac_high. 0xC 0x00000000 0xffffffff read-only sd_wifi_mac_high 0 31 sd_dbg_pwd_low sd_dbg_pwd_low. 0x10 0x00000000 0xffffffff sd_dbg_pwd_low 0 31 sd_dbg_pwd_high sd_dbg_pwd_high. 0x14 0x00000000 0xffffffff sd_dbg_pwd_high 0 31 sd_status sd_status. 0x18 0x00000000 0xffffffff sd_dbg_ena 28 31 read-only sd_dbg_mode 24 27 read-only sd_dbg_pwd_cnt 4 23 read-only sd_dbg_cci_clk_sel 3 3 sd_dbg_cci_read_en 2 2 sd_dbg_pwd_trig 1 1 sd_dbg_pwd_busy 0 0 read-only sd_dbg_reserved sd_dbg_reserved. 0x1C sd_dbg_reserved 0 31 SEC_ENG SEC_ENG. 0x40004000 SEC_ENG 32 read-write 0 0x1000 registers se_sha_0_ctrl se_sha_0_ctrl. 0x0 0x00000000 0xffffffff se_sha_0_msg_len 16 31 se_sha_0_link_mode 15 15 se_sha_0_int_mask 11 11 se_sha_0_int_set_1t 10 10 se_sha_0_int_clr_1t 9 9 se_sha_0_int 8 8 read-only se_sha_0_hash_sel 6 6 se_sha_0_en 5 5 se_sha_0_mode 2 4 se_sha_0_trig_1t 1 1 se_sha_0_busy 0 0 read-only se_sha_0_msa se_sha_0_msa. 0x4 0x00000000 0xffffffff se_sha_0_msa 0 31 se_sha_0_status se_sha_0_status. 0x8 0x00000041 0xffffffff read-only se_sha_0_status 0 31 se_sha_0_endian se_sha_0_endian. 0xC 0x00000001 0xffffffff se_sha_0_dout_endian 0 0 se_sha_0_hash_l_0 se_sha_0_hash_l_0. 0x10 0x00000000 0xffffffff read-only se_sha_0_hash_l_0 0 31 se_sha_0_hash_l_1 se_sha_0_hash_l_1. 0x14 0x00000000 0xffffffff read-only se_sha_0_hash_l_1 0 31 se_sha_0_hash_l_2 se_sha_0_hash_l_2. 0x18 0x00000000 0xffffffff read-only se_sha_0_hash_l_2 0 31 se_sha_0_hash_l_3 se_sha_0_hash_l_3. 0x1C 0x00000000 0xffffffff read-only se_sha_0_hash_l_3 0 31 se_sha_0_hash_l_4 se_sha_0_hash_l_4. 0x20 0x00000000 0xffffffff read-only se_sha_0_hash_l_4 0 31 se_sha_0_hash_l_5 se_sha_0_hash_l_5. 0x24 0x00000000 0xffffffff read-only se_sha_0_hash_l_5 0 31 se_sha_0_hash_l_6 se_sha_0_hash_l_6. 0x28 0x00000000 0xffffffff read-only se_sha_0_hash_l_6 0 31 se_sha_0_hash_l_7 se_sha_0_hash_l_7. 0x2C 0x00000000 0xffffffff read-only se_sha_0_hash_l_7 0 31 se_sha_0_hash_h_0 se_sha_0_hash_h_0. 0x30 0x00000000 0xffffffff read-only se_sha_0_hash_h_0 0 31 se_sha_0_hash_h_1 se_sha_0_hash_h_1. 0x34 0x00000000 0xffffffff read-only se_sha_0_hash_h_1 0 31 se_sha_0_hash_h_2 se_sha_0_hash_h_2. 0x38 0x00000000 0xffffffff read-only se_sha_0_hash_h_2 0 31 se_sha_0_hash_h_3 se_sha_0_hash_h_3. 0x3C 0x00000000 0xffffffff read-only se_sha_0_hash_h_3 0 31 se_sha_0_hash_h_4 se_sha_0_hash_h_4. 0x40 0x00000000 0xffffffff read-only se_sha_0_hash_h_4 0 31 se_sha_0_hash_h_5 se_sha_0_hash_h_5. 0x44 0x00000000 0xffffffff read-only se_sha_0_hash_h_5 0 31 se_sha_0_hash_h_6 se_sha_0_hash_h_6. 0x48 0x00000000 0xffffffff read-only se_sha_0_hash_h_6 0 31 se_sha_0_hash_h_7 se_sha_0_hash_h_7. 0x4C 0x00000000 0xffffffff read-only se_sha_0_hash_h_7 0 31 se_sha_0_link se_sha_0_link. 0x50 0x00000000 0xffffffff se_sha_0_lca 0 31 se_sha_0_ctrl_prot se_sha_0_ctrl_prot. 0xFC 0x00000007 0xffffffff se_sha_id1_en 2 2 se_sha_id0_en 1 1 se_sha_prot_en 0 0 se_aes_0_ctrl se_aes_0_ctrl. 0x100 0x00000000 0xffffffff se_aes_0_msg_len 16 31 se_aes_0_link_mode 15 15 se_aes_0_iv_sel 14 14 se_aes_0_block_mode 12 13 se_aes_0_int_mask 11 11 se_aes_0_int_set_1t 10 10 se_aes_0_int_clr_1t 9 9 se_aes_0_int 8 8 read-only se_aes_0_hw_key_en 7 7 se_aes_0_dec_key_sel 6 6 se_aes_0_dec_en 5 5 se_aes_0_mode 3 4 se_aes_0_en 2 2 se_aes_0_trig_1t 1 1 se_aes_0_busy 0 0 read-only se_aes_0_msa se_aes_0_msa. 0x104 0x00000000 0xffffffff se_aes_0_msa 0 31 se_aes_0_mda se_aes_0_mda. 0x108 0x00000000 0xffffffff se_aes_0_mda 0 31 se_aes_0_status se_aes_0_status. 0x10C 0x00000100 0xffffffff read-only se_aes_0_status 0 31 se_aes_0_iv_0 se_aes_0_iv_0. 0x110 0x00000000 0xffffffff se_aes_0_iv_0 0 31 se_aes_0_iv_1 se_aes_0_iv_1. 0x114 0x00000000 0xffffffff se_aes_0_iv_1 0 31 se_aes_0_iv_2 se_aes_0_iv_2. 0x118 0x00000000 0xffffffff se_aes_0_iv_2 0 31 se_aes_0_iv_3 se_aes_0_iv_3. 0x11C 0x00000000 0xffffffff se_aes_0_iv_3 0 31 se_aes_0_key_0 se_aes_0_key_0. 0x120 0x00000000 0xffffffff se_aes_0_key_0 0 31 se_aes_0_key_1 se_aes_0_key_1. 0x124 0x00000000 0xffffffff se_aes_0_key_1 0 31 se_aes_0_key_2 se_aes_0_key_2. 0x128 0x00000000 0xffffffff se_aes_0_key_2 0 31 se_aes_0_key_3 se_aes_0_key_3. 0x12C 0x00000000 0xffffffff se_aes_0_key_3 0 31 se_aes_0_key_4 se_aes_0_key_4. 0x130 0x00000000 0xffffffff se_aes_0_key_4 0 31 se_aes_0_key_5 se_aes_0_key_5. 0x134 0x00000000 0xffffffff se_aes_0_key_5 0 31 se_aes_0_key_6 se_aes_0_key_6. 0x138 0x00000000 0xffffffff se_aes_0_key_6 0 31 se_aes_0_key_7 se_aes_0_key_7. 0x13C 0x00000000 0xffffffff se_aes_0_key_7 0 31 se_aes_0_key_sel_0 se_aes_0_key_sel_0. 0x140 0x00000000 0xffffffff se_aes_0_key_sel_0 0 1 se_aes_0_key_sel_1 se_aes_0_key_sel_1. 0x144 0x00000000 0xffffffff se_aes_0_key_sel_1 0 1 se_aes_0_endian se_aes_0_endian. 0x148 0x0000000f 0xffffffff se_aes_0_ctr_len 30 31 se_aes_0_iv_endian 3 3 se_aes_0_key_endian 2 2 se_aes_0_din_endian 1 1 se_aes_0_dout_endian 0 0 se_aes_0_sboot se_aes_0_sboot. 0x14C 0x00000000 0xffffffff se_aes_0_sboot_key_sel 0 0 se_aes_0_link se_aes_0_link. 0x150 0x00000000 0xffffffff se_aes_0_lca 0 31 se_aes_0_ctrl_prot se_aes_0_ctrl_prot. 0x1FC 0x00000007 0xffffffff se_aes_id1_en 2 2 se_aes_id0_en 1 1 se_aes_prot_en 0 0 se_trng_0_ctrl_0 se_trng_0_ctrl_0. 0x200 0x00000000 0xffffffff se_trng_0_manual_en 15 15 se_trng_0_manual_reseed 14 14 se_trng_0_manual_fun_sel 13 13 se_trng_0_int_mask 11 11 se_trng_0_int_set_1t 10 10 se_trng_0_int_clr_1t 9 9 se_trng_0_int 8 8 read-only se_trng_0_ht_error 4 4 read-only se_trng_0_dout_clr_1t 3 3 se_trng_0_en 2 2 se_trng_0_trig_1t 1 1 se_trng_0_busy 0 0 read-only se_trng_0_status se_trng_0_status. 0x204 0x00100020 0xffffffff read-only se_trng_0_status 0 31 se_trng_0_dout_0 se_trng_0_dout_0. 0x208 0x00000000 0xffffffff read-only se_trng_0_dout_0 0 31 se_trng_0_dout_1 se_trng_0_dout_1. 0x20C 0x00000000 0xffffffff read-only se_trng_0_dout_1 0 31 se_trng_0_dout_2 se_trng_0_dout_2. 0x210 0x00000000 0xffffffff read-only se_trng_0_dout_2 0 31 se_trng_0_dout_3 se_trng_0_dout_3. 0x214 0x00000000 0xffffffff read-only se_trng_0_dout_3 0 31 se_trng_0_dout_4 se_trng_0_dout_4. 0x218 0x00000000 0xffffffff read-only se_trng_0_dout_4 0 31 se_trng_0_dout_5 se_trng_0_dout_5. 0x21C 0x00000000 0xffffffff read-only se_trng_0_dout_5 0 31 se_trng_0_dout_6 se_trng_0_dout_6. 0x220 0x00000000 0xffffffff read-only se_trng_0_dout_6 0 31 se_trng_0_dout_7 se_trng_0_dout_7. 0x224 0x00000000 0xffffffff read-only se_trng_0_dout_7 0 31 se_trng_0_test se_trng_0_test. 0x228 0x00000000 0xffffffff se_trng_0_ht_alarm_n 4 11 se_trng_0_ht_dis 3 3 se_trng_0_cp_bypass 2 2 se_trng_0_cp_test_en 1 1 se_trng_0_test_en 0 0 se_trng_0_ctrl_1 se_trng_0_ctrl_1. 0x22C 0x0000ffff 0xffffffff se_trng_0_reseed_n_lsb 0 31 se_trng_0_ctrl_2 se_trng_0_ctrl_2. 0x230 0x000000ff 0xffffffff se_trng_0_reseed_n_msb 0 15 se_trng_0_ctrl_3 se_trng_0_ctrl_3. 0x234 0x837a4203 0xffffffff se_trng_0_rosc_dis 31 31 Used to be called 'se_trng_0_rosc_en', but the SDK calls it 'se_trng_0_rosc_dis'. se_trng_0_ht_od_en 26 26 se_trng_0_ht_apt_c 16 25 se_trng_0_ht_rct_c 8 15 se_trng_0_cp_ratio 0 7 se_trng_0_test_out_0 se_trng_0_test_out_0. 0x240 0x00000000 0xffffffff read-only se_trng_0_test_out_0 0 31 se_trng_0_test_out_1 se_trng_0_test_out_1. 0x244 0x00000000 0xffffffff read-only se_trng_0_test_out_1 0 31 se_trng_0_test_out_2 se_trng_0_test_out_2. 0x248 0x00000000 0xffffffff read-only se_trng_0_test_out_2 0 31 se_trng_0_test_out_3 se_trng_0_test_out_3. 0x24C 0x00000000 0xffffffff read-only se_trng_0_test_out_3 0 31 se_trng_0_ctrl_prot se_trng_0_ctrl_prot. 0x2FC 0x00000007 0xffffffff se_trng_id1_en 2 2 se_trng_id0_en 1 1 se_trng_prot_en 0 0 se_pka_0_ctrl_0 se_pka_0_ctrl_0. 0x300 0x00000000 0xffffffff se_pka_0_status 17 31 read-only se_pka_0_status_clr_1t 16 16 se_pka_0_ram_clr_md 13 13 se_pka_0_endian 12 12 se_pka_0_int_mask 11 11 se_pka_0_int_set 10 10 se_pka_0_int_clr_1t 9 9 se_pka_0_int 8 8 read-only se_pka_0_prot_md 4 7 se_pka_0_en 3 3 se_pka_0_busy 2 2 read-only se_pka_0_done_clr_1t 1 1 se_pka_0_done 0 0 read-only se_pka_0_seed se_pka_0_seed. 0x30C 0x00000000 0xffffffff se_pka_0_seed 0 31 se_pka_0_ctrl_1 se_pka_0_ctrl_1. 0x310 0x00000005 0xffffffff se_pka_0_hbypass 3 3 se_pka_0_hburst 0 2 se_pka_0_rw se_pka_0_rw. 0x340 0x00000000 0xffffffff se_pka_0_rw_burst se_pka_0_rw_burst. 0x360 0x00000000 0xffffffff se_pka_0_ctrl_prot se_pka_0_ctrl_prot. 0x3FC 0x00000007 0xffffffff se_pka_id1_en 2 2 se_pka_id0_en 1 1 se_pka_prot_en 0 0 se_cdet_0_ctrl_0 se_cdet_0_ctrl_0. 0x400 0x21640004 0xffffffff se_cdet_0_g_loop_min 24 31 se_cdet_0_g_loop_max 16 23 se_cdet_0_status 2 15 read-only se_cdet_0_error 1 1 read-only se_cdet_0_en 0 0 se_cdet_0_ctrl_1 se_cdet_0_ctrl_1. 0x404 0x00ff0332 0xffffffff se_cdet_0_g_slp_n 16 23 se_cdet_0_t_dly_n 8 15 se_cdet_0_t_loop_n 0 7 se_cdet_0_ctrl_prot se_cdet_0_ctrl_prot. 0x4FC 0x00000007 0xffffffff se_cdet_id1_en 2 2 se_cdet_id0_en 1 1 se_cdet_prot_en 0 0 se_gmac_0_ctrl_0 se_gmac_0_ctrl_0. 0x500 0x00007000 0xffffffff se_gmac_0_x_endian 14 14 se_gmac_0_h_endian 13 13 se_gmac_0_t_endian 12 12 se_gmac_0_int_mask 11 11 se_gmac_0_int_set_1t 10 10 se_gmac_0_int_clr_1t 9 9 se_gmac_0_int 8 8 read-only se_gmac_0_en 2 2 se_gmac_0_trig_1t 1 1 se_gmac_0_busy 0 0 read-only se_gmac_0_lca se_gmac_0_lca. 0x504 0x00000000 0xffffffff se_gmac_0_lca 0 31 se_gmac_0_status se_gmac_0_status. 0x508 0xf1000000 0xffffffff read-only se_gmac_0_status 0 31 se_gmac_0_ctrl_prot se_gmac_0_ctrl_prot. 0x5FC 0x00000007 0xffffffff se_gmac_id1_en 2 2 se_gmac_id0_en 1 1 se_gmac_prot_en 0 0 se_ctrl_prot_rd se_ctrl_prot_rd. 0xF00 0x00777777 0xffffffff read-only se_dbg_dis 31 31 se_gmac_id1_en_rd 22 22 se_gmac_id0_en_rd 21 21 se_gmac_prot_en_rd 20 20 se_cdet_id1_en_rd 18 18 se_cdet_id0_en_rd 17 17 se_cdet_prot_en_rd 16 16 se_pka_id1_en_rd 14 14 se_pka_id0_en_rd 13 13 se_pka_prot_en_rd 12 12 se_trng_id1_en_rd 10 10 se_trng_id0_en_rd 9 9 se_trng_prot_en_rd 8 8 se_aes_id1_en_rd 6 6 se_aes_id0_en_rd 5 5 se_aes_prot_en_rd 4 4 se_sha_id1_en_rd 2 2 se_sha_id0_en_rd 1 1 se_sha_prot_en_rd 0 0 se_ctrl_reserved_0 se_ctrl_reserved_0. 0xF04 se_ctrl_reserved_0 0 31 se_ctrl_reserved_1 se_ctrl_reserved_1. 0xF08 se_ctrl_reserved_1 0 31 se_ctrl_reserved_2 se_ctrl_reserved_2. 0xF0C se_ctrl_reserved_2 0 31 TZC_SEC TZC_SEC. 0x40005000 TZC_SEC 32 read-write 0 0x1000 registers tzc_rom_ctrl tzc_rom_ctrl. 0x40 0x00000f0f 0xffffffff tzc_sboot_done 28 31 tzc_rom1_r1_lock 27 27 tzc_rom1_r0_lock 26 26 tzc_rom0_r1_lock 25 25 tzc_rom0_r0_lock 24 24 tzc_rom1_r1_en 19 19 tzc_rom1_r0_en 18 18 tzc_rom0_r1_en 17 17 tzc_rom0_r0_en 16 16 tzc_rom1_r1_id1_en 11 11 tzc_rom1_r0_id1_en 10 10 tzc_rom0_r1_id1_en 9 9 tzc_rom0_r0_id1_en 8 8 tzc_rom1_r1_id0_en 3 3 tzc_rom1_r0_id0_en 2 2 tzc_rom0_r1_id0_en 1 1 tzc_rom0_r0_id0_en 0 0 tzc_rom0_r0 tzc_rom0_r0. 0x44 0x0000ffff 0xffffffff tzc_rom0_r0_start 16 31 tzc_rom0_r0_end 0 15 tzc_rom0_r1 tzc_rom0_r1. 0x48 0x0000ffff 0xffffffff tzc_rom0_r1_start 16 31 tzc_rom0_r1_end 0 15 tzc_rom1_r0 tzc_rom1_r0. 0x4C 0x0000ffff 0xffffffff tzc_rom1_r0_start 16 31 tzc_rom1_r0_end 0 15 tzc_rom1_r1 tzc_rom1_r1. 0x50 0x0000ffff 0xffffffff tzc_rom1_r1_start 16 31 tzc_rom1_r1_end 0 15 TZC_NSEC TZC_NSEC. 0x40006000 TZC_NSEC 32 read-write 0 0x1000 registers tzc_rom_ctrl tzc_rom_ctrl. 0x40 0x00000f0f 0xffffffff read-only tzc_sboot_done 28 31 tzc_rom1_r1_lock 27 27 tzc_rom1_r0_lock 26 26 tzc_rom0_r1_lock 25 25 tzc_rom0_r0_lock 24 24 tzc_rom1_r1_en 19 19 tzc_rom1_r0_en 18 18 tzc_rom0_r1_en 17 17 tzc_rom0_r0_en 16 16 tzc_rom1_r1_id1_en 11 11 tzc_rom1_r0_id1_en 10 10 tzc_rom0_r1_id1_en 9 9 tzc_rom0_r0_id1_en 8 8 tzc_rom1_r1_id0_en 3 3 tzc_rom1_r0_id0_en 2 2 tzc_rom0_r1_id0_en 1 1 tzc_rom0_r0_id0_en 0 0 tzc_rom0_r0 tzc_rom0_r0. 0x44 0x0000ffff 0xffffffff read-only tzc_rom0_r0_start 16 31 tzc_rom0_r0_end 0 15 tzc_rom0_r1 tzc_rom0_r1. 0x48 0x0000ffff 0xffffffff read-only tzc_rom0_r1_start 16 31 tzc_rom0_r1_end 0 15 tzc_rom1_r0 tzc_rom1_r0. 0x4C 0x0000ffff 0xffffffff read-only tzc_rom1_r0_start 16 31 tzc_rom1_r0_end 0 15 tzc_rom1_r1 tzc_rom1_r1. 0x50 0x0000ffff 0xffffffff read-only tzc_rom1_r1_start 16 31 tzc_rom1_r1_end 0 15 EF_DATA_0 EF_DATA_0 0x40007000 EF_DATA_0 32 read-write 0 0x80 registers ef_cfg_0 ef_cfg_0. 0x0 0x00000000 0xffffffff ef_dbg_mode 28 31 ef_dbg_jtag_0_dis 26 27 ef_dbg_jtag_1_dis 24 25 ef_efuse_dbg_dis 23 23 ef_se_dbg_dis 22 22 ef_cpu_rst_dbg_dis 21 21 ef_cpu1_dis 20 20 ef_sf_dis 19 19 ef_cam_dis 18 18 ef_0_key_enc_en 17 17 ef_wifi_dis 16 16 ef_ble_dis 15 15 ef_sdu_dis 14 14 ef_sw_usage_1 12 13 ef_boot_sel 8 11 ef_cpu0_enc_en 7 7 ef_cpu1_enc_en 6 6 ef_sboot_en 4 5 ef_sboot_sign_mode 2 3 ef_sf_aes_mode 0 1 ef_dbg_pwd_low ef_dbg_pwd_low. 0x4 0x00000000 0xffffffff ef_dbg_pwd_low 0 31 ef_dbg_pwd_high ef_dbg_pwd_high. 0x8 0x00000000 0xffffffff ef_dbg_pwd_high 0 31 ef_ana_trim_0 ef_ana_trim_0. 0xC 0x00000000 0xffffffff ef_ana_trim_0 0 31 ef_sw_usage_0 ef_sw_usage_0. 0x10 0x00000000 0xffffffff ef_sw_usage_0 0 31 ef_wifi_mac_low ef_wifi_mac_low. 0x14 0x00000000 0xffffffff ef_wifi_mac_low 0 31 ef_wifi_mac_high ef_wifi_mac_high. 0x18 0x00000000 0xffffffff ef_wifi_mac_high 0 31 ef_key_slot_0_w0 ef_key_slot_0_w0. 0x1C 0x00000000 0xffffffff ef_key_slot_0_w0 0 31 ef_key_slot_0_w1 ef_key_slot_0_w1. 0x20 0x00000000 0xffffffff ef_key_slot_0_w1 0 31 ef_key_slot_0_w2 ef_key_slot_0_w2. 0x24 0x00000000 0xffffffff ef_key_slot_0_w2 0 31 ef_key_slot_0_w3 ef_key_slot_0_w3. 0x28 0x00000000 0xffffffff ef_key_slot_0_w3 0 31 ef_key_slot_1_w0 ef_key_slot_1_w0. 0x2C 0x00000000 0xffffffff ef_key_slot_1_w0 0 31 ef_key_slot_1_w1 ef_key_slot_1_w1. 0x30 0x00000000 0xffffffff ef_key_slot_1_w1 0 31 ef_key_slot_1_w2 ef_key_slot_1_w2. 0x34 0x00000000 0xffffffff ef_key_slot_1_w2 0 31 ef_key_slot_1_w3 ef_key_slot_1_w3. 0x38 0x00000000 0xffffffff ef_key_slot_1_w3 0 31 ef_key_slot_2_w0 ef_key_slot_2_w0. 0x3C 0x00000000 0xffffffff ef_key_slot_2_w0 0 31 ef_key_slot_2_w1 ef_key_slot_2_w1. 0x40 0x00000000 0xffffffff ef_key_slot_2_w1 0 31 ef_key_slot_2_w2 ef_key_slot_2_w2. 0x44 0x00000000 0xffffffff ef_key_slot_2_w2 0 31 ef_key_slot_2_w3 ef_key_slot_2_w3. 0x48 0x00000000 0xffffffff ef_key_slot_2_w3 0 31 ef_key_slot_3_w0 ef_key_slot_3_w0. 0x4C 0x00000000 0xffffffff ef_key_slot_3_w0 0 31 ef_key_slot_3_w1 ef_key_slot_3_w1. 0x50 0x00000000 0xffffffff ef_key_slot_3_w1 0 31 ef_key_slot_3_w2 ef_key_slot_3_w2. 0x54 0x00000000 0xffffffff ef_key_slot_3_w2 0 31 ef_key_slot_3_w3 ef_key_slot_3_w3. 0x58 0x00000000 0xffffffff ef_key_slot_3_w3 0 31 ef_key_slot_4_w0 ef_key_slot_4_w0. 0x5C 0x00000000 0xffffffff ef_key_slot_4_w0 0 31 ef_key_slot_4_w1 ef_key_slot_4_w1. 0x60 0x00000000 0xffffffff ef_key_slot_4_w1 0 31 ef_key_slot_4_w2 ef_key_slot_4_w2. 0x64 0x00000000 0xffffffff ef_key_slot_4_w2 0 31 ef_key_slot_4_w3 ef_key_slot_4_w3. 0x68 0x00000000 0xffffffff ef_key_slot_4_w3 0 31 ef_key_slot_5_w0 ef_key_slot_5_w0. 0x6C 0x00000000 0xffffffff ef_key_slot_5_w0 0 31 ef_key_slot_5_w1 ef_key_slot_5_w1. 0x70 0x00000000 0xffffffff ef_key_slot_5_w1 0 31 ef_key_slot_5_w2 ef_key_slot_5_w2. 0x74 0x00000000 0xffffffff ef_key_slot_5_w2 0 31 ef_key_slot_5_w3 ef_key_slot_5_w3. 0x78 0x00000000 0xffffffff ef_key_slot_5_w3 0 31 ef_data_0_lock ef_data_0_lock. 0x7C 0x00000000 0xffffffff rd_lock_key_slot_5 31 31 rd_lock_key_slot_4 30 30 rd_lock_key_slot_3 29 29 rd_lock_key_slot_2 28 28 rd_lock_key_slot_1 27 27 rd_lock_key_slot_0 26 26 rd_lock_dbg_pwd 25 25 wr_lock_key_slot_5_h 24 24 wr_lock_key_slot_4_h 23 23 wr_lock_key_slot_3 22 22 wr_lock_key_slot_2 21 21 wr_lock_key_slot_1 20 20 wr_lock_key_slot_0 19 19 wr_lock_wifi_mac 18 18 wr_lock_sw_usage_0 17 17 wr_lock_dbg_pwd 16 16 wr_lock_boot_mode 15 15 wr_lock_key_slot_5_l 14 14 wr_lock_key_slot_4_l 13 13 ef_ana_trim_1 0 12 EF_DATA_1 EF_DATA_1. 0x40007080 EF_DATA_1 32 read-write 0 0x64 registers reg_key_slot_6_w0 reg_key_slot_6_w0. 0x00 0x00000000 0xffffffff reg_key_slot_6_w0 0 31 reg_key_slot_6_w1 reg_key_slot_6_w1. 0x04 0x00000000 0xffffffff reg_key_slot_6_w1 0 31 reg_key_slot_6_w2 reg_key_slot_6_w2. 0x08 0x00000000 0xffffffff reg_key_slot_6_w2 0 31 reg_key_slot_6_w3 reg_key_slot_6_w3. 0x0C 0x00000000 0xffffffff reg_key_slot_6_w3 0 31 reg_key_slot_7_w0 reg_key_slot_7_w0. 0x10 0x00000000 0xffffffff reg_key_slot_7_w0 0 31 reg_key_slot_7_w1 reg_key_slot_7_w1. 0x14 0x00000000 0xffffffff reg_key_slot_7_w1 0 31 reg_key_slot_7_w2 reg_key_slot_7_w2. 0x18 0x00000000 0xffffffff reg_key_slot_7_w2 0 31 reg_key_slot_7_w3 reg_key_slot_7_w3. 0x1C 0x00000000 0xffffffff reg_key_slot_7_w3 0 31 reg_key_slot_8_w0 reg_key_slot_8_w0. 0x20 0x00000000 0xffffffff reg_key_slot_8_w0 0 31 reg_key_slot_8_w1 reg_key_slot_8_w1. 0x24 0x00000000 0xffffffff reg_key_slot_8_w1 0 31 reg_key_slot_8_w2 reg_key_slot_8_w2. 0x28 0x00000000 0xffffffff reg_key_slot_8_w2 0 31 reg_key_slot_8_w3 reg_key_slot_8_w3. 0x2C 0x00000000 0xffffffff reg_key_slot_8_w3 0 31 reg_key_slot_9_w0 reg_key_slot_9_w0. 0x30 0x00000000 0xffffffff reg_key_slot_9_w0 0 31 reg_key_slot_9_w1 reg_key_slot_9_w1. 0x34 0x00000000 0xffffffff reg_key_slot_9_w1 0 31 reg_key_slot_9_w2 reg_key_slot_9_w2. 0x38 0x00000000 0xffffffff reg_key_slot_9_w2 0 31 reg_key_slot_9_w3 reg_key_slot_9_w3. 0x3C 0x00000000 0xffffffff reg_key_slot_9_w3 0 31 reg_key_slot_10_w0 reg_key_slot_10_w0. 0x40 0x00000000 0xffffffff reg_key_slot_10_w1 reg_key_slot_10_w1. 0x44 0x00000000 0xffffffff reg_key_slot_10_w2 reg_key_slot_10_w2. 0x48 0x00000000 0xffffffff reg_key_slot_10_w3 reg_key_slot_10_w3. 0x4C 0x00000000 0xffffffff reg_key_slot_11_w0 reg_key_slot_11_w0. 0x50 0x00000000 0xffffffff reg_key_slot_11_w1 reg_key_slot_11_w1. 0x54 0x00000000 0xffffffff reg_key_slot_11_w2 reg_key_slot_11_w2. 0x58 0x00000000 0xffffffff reg_key_slot_11_w3 reg_key_slot_11_w3. 0x5C 0x00000000 0xffffffff reg_data_1_lock reg_data_1_lock. 0x60 0x00000000 0xffffffff rd_lock_key_slot_9 29 29 rd_lock_key_slot_8 28 28 rd_lock_key_slot_7 27 27 rd_lock_key_slot_6 26 26 RESERVED_25_16 16 25 wr_lock_key_slot_9 13 13 wr_lock_key_slot_8 12 12 wr_lock_key_slot_7 11 11 wr_lock_key_slot_6 10 10 RESERVED_9_0 0 9 EF_CTRL eFuse memory control 0x40007800 EF_CTRL 32 read-write 0 0x218 registers ef_if_ctrl_0 ef_if_ctrl_0. 0x000 0x00240003 0xffffffff ef_if_prot_code_cyc 24 31 ef_if_0_int_set 22 22 ef_if_0_int_clr 21 21 ef_if_0_int 20 20 read-only ef_if_cyc_modify_lock 19 19 ef_if_auto_rd_en 18 18 ef_clk_sahb_data_gate 17 17 ef_if_por_dig 16 16 ef_if_prot_code_ctrl 8 15 ef_clk_sahb_data_sel 7 7 ef_if_0_cyc_modify 6 6 ef_if_0_manual_en 5 5 ef_if_0_trig 4 4 ef_if_0_rw 3 3 ef_if_0_busy 2 2 read-only ef_if_0_autoload_done 1 1 read-only ef_if_0_autoload_p1_done 0 0 read-only ef_if_cyc_0 ef_if_cyc_0. 0x004 0x16000040 0xffffffff ef_if_cyc_pd_cs_s 24 31 ef_if_cyc_cs 18 23 ef_if_cyc_rd_adr 12 17 ef_if_cyc_rd_dat 6 11 ef_if_cyc_rd_dmy 0 5 ef_if_cyc_1 ef_if_cyc_1. 0x008 0x00206609 0xffffffff ef_if_cyc_pd_cs_h 26 31 ef_if_cyc_ps_cs 20 25 ef_if_cyc_wr_adr 14 19 ef_if_cyc_pp 6 13 ef_if_cyc_pi 0 5 ef_if_0_manual ef_if_0_manual. 0x00C 0x0000e400 0xffffffff ef_if_prot_code_manual 24 31 ef_if_0_q 16 23 read-only ef_if_csb 15 15 ef_if_load 14 14 ef_if_pgenb 13 13 ef_if_strobe 12 12 ef_if_ps 11 11 ef_if_pd 10 10 ef_if_a 0 9 ef_if_0_status ef_if_0_status. 0x010 0x0000e400 0xffffffff ef_if_0_status 0 31 read-only ef_if_cfg_0 ef_if_cfg_0. 0x014 0x00000000 0xffffffff read-only ef_if_dbg_mode 28 31 ef_if_dbg_jtag_0_dis 26 27 ef_if_dbg_jtag_1_dis 24 25 ef_if_efuse_dbg_dis 23 23 ef_if_se_dbg_dis 22 22 ef_if_cpu_rst_dbg_dis 21 21 ef_if_cpu1_dis 20 20 ef_if_sf_dis 19 19 ef_if_cam_dis 18 18 ef_if_0_key_enc_en 17 17 ef_if_wifi_dis 16 16 ef_if_ble_dis 15 15 ef_if_sdu_dis 14 14 ef_if_sw_usage_1 12 13 ef_if_boot_sel 8 11 ef_if_cpu0_enc_en 7 7 ef_if_cpu1_enc_en 6 6 ef_if_sboot_en 4 5 ef_if_sboot_sign_mode 2 3 ef_if_sf_aes_mode 0 1 ef_sw_cfg_0 ef_sw_cfg_0. 0x018 ef_sw_dbg_mode 28 31 ef_sw_dbg_jtag_0_dis 26 27 ef_sw_dbg_jtag_1_dis 24 25 ef_sw_efuse_dbg_dis 23 23 ef_sw_se_dbg_dis 22 22 ef_sw_cpu_rst_dbg_dis 21 21 ef_sw_cpu1_dis 20 20 ef_sw_sf_dis 19 19 ef_sw_cam_dis 18 18 ef_sw_0_key_enc_en 17 17 ef_sw_wifi_dis 16 16 ef_sw_ble_dis 15 15 ef_sw_sdu_dis 14 14 ef_sw_sw_usage_1 12 13 ef_sw_cpu0_enc_en 7 7 ef_sw_cpu1_enc_en 6 6 ef_sw_sboot_en 4 5 ef_sw_sboot_sign_mode 2 3 ef_sw_sf_aes_mode 0 1 ef_reserved ef_reserved. 0x01C ef_reserved 0 31 ef_if_ana_trim_0 ef_if_ana_trim_0. 0x020 0x00000000 0xffffffff ef_if_ana_trim_0 0 31 read-only ef_if_sw_usage_0 ef_if_sw_usage_0. 0x024 0x00000000 0xffffffff ef_if_sw_usage_0 0 31 read-only ef_crc_ctrl_0 ef_crc_ctrl_0. 0x200 0x00ff0224 0xffffffff ef_crc_slp_n 16 31 ef_crc_lock 11 11 ef_crc_int_set 10 10 ef_crc_int_clr 9 9 ef_crc_int 8 8 read-only ef_crc_din_endian 7 7 ef_crc_dout_endian 6 6 ef_crc_dout_inv_en 5 5 ef_crc_error 4 4 read-only ef_crc_mode 3 3 ef_crc_en 2 2 ef_crc_trig 1 1 ef_crc_busy 0 0 read-only ef_crc_ctrl_1 ef_crc_ctrl_1. 0x204 0xffffffff 0xffffffff ef_crc_data_0_en 0 31 ef_crc_ctrl_2 ef_crc_ctrl_2. 0x208 0xffffffff 0xffffffff ef_crc_data_1_en 0 31 ef_crc_ctrl_3 ef_crc_ctrl_3. 0x20C 0xffffffff 0xffffffff ef_crc_iv 0 31 ef_crc_ctrl_4 ef_crc_ctrl_4. 0x210 0xc2a8fa9d 0xffffffff ef_crc_golden 0 31 ef_crc_ctrl_5 ef_crc_ctrl_5. 0x214 0xffffffff 0xffffffff ef_crc_dout 0 31 read-only CCI CCI. 0x40008000 CCI 32 read-write 0 0x1000 registers cci_cfg cci_cfg. 0x0 0x00000221 0xffffffff reg_mcci_clk_inv 9 9 reg_scci_clk_inv 8 8 cfg_cci1_pre_read 7 7 reg_div_m_cci_sclk 5 6 reg_m_cci_sclk_en 4 4 cci_mas_hw_mode 3 3 cci_mas_sel_cci2 2 2 cci_slv_sel_cci2 1 1 cci_en 0 0 cci_addr cci_addr. 0x4 0x00000000 0xffffffff apb_cci_addr 0 31 cci_wdata cci_wdata. 0x8 0x00000000 0xffffffff apb_cci_wdata 0 31 cci_rdata cci_rdata. 0xC 0x00000000 0xffffffff apb_cci_rdata 0 31 read-only cci_ctl cci_ctl. 0x10 0x00000000 0xffffffff ahb_state 2 3 read-only cci_read_flag 1 1 read-only cci_write_flag 0 0 read-only L1C Cache control 0x40009000 L1C 32 read-write 0 0x1000 registers l1c_config l1c_config. 0x0 0x06000f00 0xffffffff wrap_dis 26 26 early_resp_dis 25 25 l1c_bmx_busy_option_dis 24 24 l1c_bmx_timeout_en 20 23 l1c_bmx_arb_mode 16 17 l1c_bmx_err_en 15 15 l1c_bypass 14 14 irom_2t_access 12 12 l1c_way_dis 8 11 l1c_invalid_done 3 3 read-only l1c_invalid_en 2 2 l1c_cnt_en 1 1 l1c_cacheable 0 0 hit_cnt_lsb hit_cnt_lsb. 0x4 0x00000000 0xffffffff read-only hit_cnt_lsb 0 31 hit_cnt_msb hit_cnt_msb. 0x8 0x00000000 0xffffffff read-only hit_cnt_msb 0 31 miss_cnt miss_cnt. 0xC 0x00000000 0xffffffff read-only miss_cnt 0 31 l1c_range l1c_range. 0x10 0x00000000 0xffffffff l1c_bmx_err_addr_en l1c_bmx_err_addr_en. 0x200 0x00000000 0xffffffff l1c_hsel_option 16 19 l1c_bmx_err_tz 5 5 read-only l1c_bmx_err_dec 4 4 read-only l1c_bmx_err_addr_dis 0 0 l1c_bmx_err_addr l1c_bmx_err_addr. 0x204 0x00000000 0xffffffff read-only l1c_bmx_err_addr 0 31 irom1_misr_dataout_0 irom1_misr_dataout_0. 0x208 0x00000000 0xffffffff read-only irom1_misr_dataout_0 0 31 irom1_misr_dataout_1 irom1_misr_dataout_1. 0x20C 0x00000000 0xffffffff cpu_clk_gate cpu_clk_gate. 0x210 0x00000000 0xffffffff force_e21_clock_on_2 2 2 force_e21_clock_on_1 1 1 force_e21_clock_on_0 0 0 UART UART control 0x4000A000 UART 32 read-write 0 0x90 registers utx_config utx_config. 0x0 0x00001700 0xffffffff cr_utx_len 16 31 cr_utx_bit_cnt_p 12 13 cr_utx_bit_cnt_d 8 10 cr_utx_ir_inv 7 7 cr_utx_ir_en 6 6 cr_utx_prt_sel 5 5 cr_utx_prt_en 4 4 cr_utx_frm_en 2 2 cr_utx_cts_en 1 1 cr_utx_en 0 0 urx_config urx_config. 0x4 0x00000700 0xffffffff cr_urx_len 16 31 cr_urx_deg_cnt 12 15 cr_urx_deg_en 11 11 cr_urx_bit_cnt_d 8 10 cr_urx_ir_inv 7 7 cr_urx_ir_en 6 6 cr_urx_prt_sel 5 5 cr_urx_prt_en 4 4 cr_urx_abr_en 3 3 cr_urx_rts_sw_val 2 2 cr_urx_rts_sw_mode 1 1 cr_urx_en 0 0 uart_bit_prd uart_bit_prd. 0x8 0x00ff00ff 0xffffffff cr_urx_bit_prd 16 31 cr_utx_bit_prd 0 15 data_config data_config. 0xC 0x00000000 0xffffffff cr_uart_bit_inv 0 0 utx_ir_position utx_ir_position. 0x10 0x009f0070 0xffffffff cr_utx_ir_pos_p 16 31 cr_utx_ir_pos_s 0 15 urx_ir_position urx_ir_position. 0x14 0x0000006f 0xffffffff cr_urx_ir_pos_s 0 15 urx_rto_timer urx_rto_timer. 0x18 0x0000000f 0xffffffff cr_urx_rto_value 0 7 uart_int_sts UART interrupt status 0x20 0x00000000 0xffffffff read-only urx_fer_int 7 7 utx_fer_int 6 6 urx_pce_int 5 5 urx_rto_int 4 4 urx_fifo_int 3 3 utx_fifo_int 2 2 urx_end_int 1 1 utx_end_int 0 0 uart_int_mask UART interrupt mask 0x24 0x000000ff 0xffffffff cr_urx_fer_mask 7 7 cr_utx_fer_mask 6 6 cr_urx_pce_mask 5 5 cr_urx_rto_mask 4 4 cr_urx_fifo_mask 3 3 cr_utx_fifo_mask 2 2 cr_urx_end_mask 1 1 cr_utx_end_mask 0 0 uart_int_clear UART interrupt clear 0x28 0x00000000 0xffffffff rsvd_7 7 7 rsvd_6 6 6 cr_urx_pce_clr 5 5 cr_urx_rto_clr 4 4 rsvd_3 3 3 rsvd_2 2 2 cr_urx_end_clr 1 1 cr_utx_end_clr 0 0 uart_int_en UART interrupt enable 0x2C 0x000000ff 0xffffffff cr_urx_fer_en 7 7 cr_utx_fer_en 6 6 cr_urx_pce_en 5 5 cr_urx_rto_en 4 4 cr_urx_fifo_en 3 3 cr_utx_fifo_en 2 2 cr_urx_end_en 1 1 cr_utx_end_en 0 0 uart_status uart_status. 0x30 0x00000000 0xffffffff read-only sts_urx_bus_busy 1 1 sts_utx_bus_busy 0 0 sts_urx_abr_prd sts_urx_abr_prd. 0x34 0x00000000 0xffffffff read-only sts_urx_abr_prd_0x55 16 31 sts_urx_abr_prd_start 0 15 uart_fifo_config_0 uart_fifo_config_0. 0x80 0x00000000 0xffffffff rx_fifo_underflow 7 7 read-only rx_fifo_overflow 6 6 read-only tx_fifo_underflow 5 5 read-only tx_fifo_overflow 4 4 read-only rx_fifo_clr 3 3 tx_fifo_clr 2 2 uart_dma_rx_en 1 1 uart_dma_tx_en 0 0 uart_fifo_config_1 uart_fifo_config_1. 0x84 0x00000020 0xffffffff rx_fifo_th 24 28 tx_fifo_th 16 20 rx_fifo_cnt 8 13 read-only tx_fifo_cnt 0 5 read-only uart_fifo_wdata uart_fifo_wdata. 0x88 0x00000000 0xffffffff write-only uart_fifo_wdata 0 7 uart_fifo_rdata uart_fifo_rdata. 0x8C 0x00000000 0xffffffff read-only uart_fifo_rdata 0 7 SPI SPI master / slave control 0x4000A200 SPI 32 read-write 0 0x90 registers spi_config spi_config. 0x0 0x00000000 0xffffffff cr_spi_deg_cnt 12 15 cr_spi_deg_en 11 11 cr_spi_m_cont_en 9 9 cr_spi_rxd_ignr_en 8 8 cr_spi_byte_inv 7 7 cr_spi_bit_inv 6 6 cr_spi_sclk_ph 5 5 cr_spi_sclk_pol 4 4 cr_spi_frame_size 2 3 cr_spi_s_en 1 1 cr_spi_m_en 0 0 spi_int_sts spi_int_sts. 0x4 0x3f003f00 0xffffffff cr_spi_fer_en 29 29 cr_spi_txu_en 28 28 cr_spi_sto_en 27 27 cr_spi_rxf_en 26 26 cr_spi_txf_en 25 25 cr_spi_end_en 24 24 rsvd_21 21 21 cr_spi_txu_clr 20 20 cr_spi_sto_clr 19 19 rsvd_18 18 18 rsvd_17 17 17 cr_spi_end_clr 16 16 cr_spi_fer_mask 13 13 cr_spi_txu_mask 12 12 cr_spi_sto_mask 11 11 cr_spi_rxf_mask 10 10 cr_spi_txf_mask 9 9 cr_spi_end_mask 8 8 spi_fer_int 5 5 read-only spi_txu_int 4 4 read-only spi_sto_int 3 3 read-only spi_rxf_int 2 2 read-only spi_txf_int 1 1 read-only spi_end_int 0 0 read-only spi_bus_busy spi_bus_busy. 0x8 0x00000000 0xffffffff read-only sts_spi_bus_busy 0 0 spi_prd_0 spi_prd_0. 0x10 0x0f0f0f0f 0xffffffff cr_spi_prd_d_ph_1 24 31 cr_spi_prd_d_ph_0 16 23 cr_spi_prd_p 8 15 cr_spi_prd_s 0 7 spi_prd_1 spi_prd_1. 0x14 0x0000000f 0xffffffff cr_spi_prd_i 0 7 spi_rxd_ignr spi_rxd_ignr. 0x18 0x00000000 0xffffffff cr_spi_rxd_ignr_s 16 20 cr_spi_rxd_ignr_p 0 4 spi_sto_value spi_sto_value. 0x1C 0x00000fff 0xffffffff cr_spi_sto_value 0 11 spi_fifo_config_0 spi_fifo_config_0. 0x80 0x00000000 0xffffffff rx_fifo_underflow 7 7 read-only rx_fifo_overflow 6 6 read-only tx_fifo_underflow 5 5 read-only tx_fifo_overflow 4 4 read-only rx_fifo_clr 3 3 tx_fifo_clr 2 2 spi_dma_rx_en 1 1 spi_dma_tx_en 0 0 spi_fifo_config_1 spi_fifo_config_1. 0x84 0x00000004 0xffffffff rx_fifo_th 24 25 tx_fifo_th 16 17 rx_fifo_cnt 8 10 read-only tx_fifo_cnt 0 2 read-only spi_fifo_wdata spi_fifo_wdata. 0x88 0x00000000 0xffffffff write-only spi_fifo_wdata 0 31 spi_fifo_rdata spi_fifo_rdata. 0x8C 0x00000000 0xffffffff read-only spi_fifo_rdata 0 31 I2C I2C control 0x4000A300 I2C 32 read-write 0 0x100 registers i2c_config i2c_config. 0x0 0x0000000a 0xffffffff cr_i2c_deg_cnt 28 31 cr_i2c_pkt_len 16 23 cr_i2c_slv_addr 8 14 cr_i2c_sub_addr_bc 5 6 cr_i2c_sub_addr_en 4 4 cr_i2c_scl_sync_en 3 3 cr_i2c_deg_en 2 2 cr_i2c_pkt_dir 1 1 cr_i2c_m_en 0 0 i2c_int_sts i2c_int_sts. 0x4 0x3f003f00 0xffffffff cr_i2c_fer_en 29 29 cr_i2c_arb_en 28 28 cr_i2c_nak_en 27 27 cr_i2c_rxf_en 26 26 cr_i2c_txf_en 25 25 cr_i2c_end_en 24 24 rsvd_21 21 21 cr_i2c_arb_clr 20 20 cr_i2c_nak_clr 19 19 rsvd_18 18 18 rsvd_17 17 17 cr_i2c_end_clr 16 16 cr_i2c_fer_mask 13 13 cr_i2c_arb_mask 12 12 cr_i2c_nak_mask 11 11 cr_i2c_rxf_mask 10 10 cr_i2c_txf_mask 9 9 cr_i2c_end_mask 8 8 i2c_fer_int 5 5 read-only i2c_arb_int 4 4 read-only i2c_nak_int 3 3 read-only i2c_rxf_int 2 2 read-only i2c_txf_int 1 1 read-only i2c_end_int 0 0 read-only i2c_sub_addr i2c_sub_addr. 0x8 0x00000000 0xffffffff cr_i2c_sub_addr_b3 24 31 cr_i2c_sub_addr_b2 16 23 cr_i2c_sub_addr_b1 8 15 cr_i2c_sub_addr_b0 0 7 i2c_bus_busy i2c_bus_busy. 0xC 0x00000000 0xffffffff cr_i2c_bus_busy_clr 1 1 sts_i2c_bus_busy 0 0 read-only i2c_prd_start i2c_prd_start. 0x10 0x0f0f0f0f 0xffffffff cr_i2c_prd_s_ph_3 24 31 cr_i2c_prd_s_ph_2 16 23 cr_i2c_prd_s_ph_1 8 15 cr_i2c_prd_s_ph_0 0 7 i2c_prd_stop i2c_prd_stop. 0x14 0x0f0f0f0f 0xffffffff cr_i2c_prd_p_ph_3 24 31 cr_i2c_prd_p_ph_2 16 23 cr_i2c_prd_p_ph_1 8 15 cr_i2c_prd_p_ph_0 0 7 i2c_prd_data i2c_prd_data. 0x18 0x0f0f0f0f 0xffffffff cr_i2c_prd_d_ph_3 24 31 cr_i2c_prd_d_ph_2 16 23 cr_i2c_prd_d_ph_1 8 15 cr_i2c_prd_d_ph_0 0 7 i2c_fifo_config_0 i2c_fifo_config_0. 0x80 0x00000000 0xffffffff rx_fifo_underflow 7 7 read-only rx_fifo_overflow 6 6 read-only tx_fifo_underflow 5 5 read-only tx_fifo_overflow 4 4 read-only rx_fifo_clr 3 3 tx_fifo_clr 2 2 i2c_dma_rx_en 1 1 i2c_dma_tx_en 0 0 i2c_fifo_config_1 i2c_fifo_config_1. 0x84 0x00000002 0xffffffff rx_fifo_th 24 24 tx_fifo_th 16 16 rx_fifo_cnt 8 9 read-only tx_fifo_cnt 0 1 read-only i2c_fifo_wdata i2c_fifo_wdata. 0x88 0x00000000 0xffffffff write-only i2c_fifo_wdata 0 31 i2c_fifo_rdata i2c_fifo_rdata. 0x8C 0x00000000 0xffffffff read-only i2c_fifo_rdata 0 31 PWM Pulse width modulation control 0x4000A400 PWM 32 read-write 0 0xB8 registers pwm_int_config pwm_int_config. 0x0 0x00000000 0xffffffff pwm_int_clear 8 13 write-only pwm_interrupt_sts 0 5 read-only pwm0_clkdiv pwm0_clkdiv. 0x20 0x00000000 0xffffffff pwm_clk_div 0 15 pwm0_thre1 pwm0_thre1. 0x24 0x00000000 0xffffffff pwm_thre1 0 15 pwm0_thre2 pwm0_thre2. 0x28 0x00000000 0xffffffff pwm_thre2 0 15 pwm0_period pwm0_period. 0x2C 0x00000000 0xffffffff pwm_period 0 15 pwm0_config pwm0_config. 0x30 0x00000008 0xffffffff pwm_sts_top 7 7 read-only pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm0_interrupt pwm0_interrupt. 0x34 0x00000000 0xffffffff pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm1_clkdiv pwm1_clkdiv. 0x40 0x00000000 0xffffffff pwm_clk_div 0 15 pwm1_thre1 pwm1_thre1. 0x44 0x00000000 0xffffffff pwm_thre1 0 15 pwm1_thre2 pwm1_thre2. 0x48 0x00000000 0xffffffff pwm_thre2 0 15 pwm1_period pwm1_period. 0x4C 0x00000000 0xffffffff pwm_period 0 15 pwm1_config pwm1_config. 0x50 0x00000008 0xffffffff pwm_sts_top 7 7 read-only pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm1_interrupt pwm1_interrupt. 0x54 0x00000000 0xffffffff pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm2_clkdiv pwm2_clkdiv. 0x60 0x00000000 0xffffffff pwm_clk_div 0 15 pwm2_thre1 pwm2_thre1. 0x64 0x00000000 0xffffffff pwm_thre1 0 15 pwm2_thre2 pwm2_thre2. 0x68 0x00000000 0xffffffff pwm_thre2 0 15 pwm2_period pwm2_period. 0x6C 0x00000000 0xffffffff pwm_period 0 15 pwm2_config pwm2_config. 0x70 0x00000008 0xffffffff pwm_sts_top 7 7 read-only pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm2_interrupt pwm2_interrupt. 0x74 0x00000000 0xffffffff pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm3_clkdiv pwm3_clkdiv. 0x80 0x00000000 0xffffffff pwm_clk_div 0 15 pwm3_thre1 pwm3_thre1. 0x84 0x00000000 0xffffffff pwm_thre1 0 15 pwm3_thre2 pwm3_thre2. 0x88 0x00000000 0xffffffff pwm_thre2 0 15 pwm3_period pwm3_period. 0x8C 0x00000000 0xffffffff pwm_period 0 15 pwm3_config pwm3_config. 0x90 0x00000008 0xffffffff pwm_sts_top 7 7 read-only pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm3_interrupt pwm3_interrupt. 0x94 0x00000000 0xffffffff pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm4_clkdiv pwm4_clkdiv. 0xA0 0x00000000 0xffffffff pwm_clk_div 0 15 pwm4_thre1 pwm4_thre1. 0xA4 0x00000000 0xffffffff pwm_thre1 0 15 pwm4_thre2 pwm4_thre2. 0xA8 0x00000000 0xffffffff pwm_thre2 0 15 pwm4_period pwm4_period. 0xAC 0x00000000 0xffffffff pwm_period 0 15 pwm4_config pwm4_config. 0xB0 0x00000008 0xffffffff pwm_sts_top 7 7 read-only pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm4_interrupt pwm4_interrupt. 0xB4 0x00000000 0xffffffff pwm_int_enable 16 16 pwm_int_period_cnt 0 15 TIMER Timer control 0x4000A500 TIMER 32 read-write 0 0xC0 registers TCCR TCCR. 0x0 0x00000000 0xffffffff cs_wdt 8 9 RESERVED_7 7 7 cs_2 5 6 RESERVED_4 4 4 cs_1 2 3 TMR2_0 TMR2_0. 0x10 0xffffffff 0xffffffff tmr 0 31 TMR2_1 TMR2_1. 0x14 0xffffffff 0xffffffff tmr 0 31 TMR2_2 TMR2_2. 0x18 0xffffffff 0xffffffff tmr 0 31 TMR3_0 TMR3_0. 0x1C 0xffffffff 0xffffffff tmr 0 31 TMR3_1 TMR3_1. 0x20 0xffffffff 0xffffffff tmr 0 31 TMR3_2 TMR3_2. 0x24 0xffffffff 0xffffffff tmr 0 31 TCR2 TCR2. 0x2C 0x00000000 0xffffffff read-only tcr 0 31 TCR3 TCR3. 0x30 0x00000000 0xffffffff read-only tcr3_counter 0 31 TMSR2 TMSR2. 0x38 0x00000000 0xffffffff read-only tmsr_2 2 2 tmsr_1 1 1 tmsr_0 0 0 TMSR3 TMSR3. 0x3C 0x00000000 0xffffffff read-only tmsr_2 2 2 tmsr_1 1 1 tmsr_0 0 0 TIER2 TIER2. 0x44 0x00000000 0xffffffff tier_2 2 2 tier_1 1 1 tier_0 0 0 TIER3 TIER3. 0x48 0x00000000 0xffffffff tier_2 2 2 tier_1 1 1 tier_0 0 0 TPLVR2 TPLVR2. 0x50 0x00000000 0xffffffff tplvr 0 31 TPLVR3 TPLVR3. 0x54 0x00000000 0xffffffff tplvr 0 31 TPLCR2 TPLCR2. 0x5C 0x00000000 0xffffffff tplcr 0 1 TPLCR3 TPLCR3. 0x60 0x00000000 0xffffffff tplcr 0 1 WMER WMER. 0x64 0x00000000 0xffffffff wrie 1 1 we 0 0 WMR WMR. 0x68 0x0000ffff 0xffffffff wmr 0 15 WVR WVR. 0x6C 0x00000000 0xffffffff read-only wvr 0 15 WSR WSR. 0x70 0x00000000 0xffffffff wts 0 0 TICR2 TICR2. 0x78 0x00000000 0xffffffff write-only tclr_2 2 2 tclr_1 1 1 tclr_0 0 0 TICR3 TICR3. 0x7C 0x00000000 0xffffffff write-only tclr_2 2 2 tclr_1 1 1 tclr_0 0 0 WICR WICR. 0x80 0x00000000 0xffffffff write-only wiclr 0 0 TCER TCER. 0x84 0x00000000 0xffffffff timer3_en 2 2 timer2_en 1 1 TCMR TCMR. 0x88 0x00000000 0xffffffff timer3_mode 2 2 timer2_mode 1 1 TILR2 TILR2. 0x90 0x00000000 0xffffffff tilr_2 2 2 tilr_1 1 1 tilr_0 0 0 TILR3 TILR3. 0x94 0x00000000 0xffffffff tilr_2 2 2 tilr_1 1 1 tilr_0 0 0 WCR WCR. 0x98 0x00000000 0xffffffff write-only wcr 0 0 WFAR WFAR. 0x9C 0x00000000 0xffffffff write-only wfar 0 15 WSAR WSAR. 0xA0 0x00000000 0xffffffff write-only wsar 0 15 TCVWR2 TCVWR2. 0xA8 0x00000000 0xffffffff read-only tcvwr 0 31 TCVWR3 TCVWR3. 0xAC 0x00000000 0xffffffff read-only tcvwr 0 31 TCVSYN2 TCVSYN2. 0xB4 0x00000000 0xffffffff read-only tcvsyn2 0 31 TCVSYN3 TCVSYN3. 0xB8 0x00000000 0xffffffff read-only tcvsyn3 0 31 TCDR TCDR. 0xBC 0x00000000 0xffffffff wcdr 24 31 tcdr3 16 23 tcdr2 8 15 IR Infrared remote control 0x4000A600 IR 32 read-write 0 0xC8 registers irtx_config irtx_config. 0x0 0x0001f510 0xffffffff cr_irtx_data_num 12 17 cr_irtx_tail_hl_inv 11 11 cr_irtx_tail_en 10 10 cr_irtx_head_hl_inv 9 9 cr_irtx_head_en 8 8 cr_irtx_logic1_hl_inv 6 6 cr_irtx_logic0_hl_inv 5 5 cr_irtx_data_en 4 4 cr_irtx_swm_en 3 3 cr_irtx_mod_en 2 2 cr_irtx_out_inv 1 1 cr_irtx_en 0 0 irtx_int_sts irtx_int_sts. 0x4 0x01000100 0xffffffff cr_irtx_end_en 24 24 cr_irtx_end_clr 16 16 cr_irtx_end_mask 8 8 irtx_end_int 0 0 read-only irtx_data_word0 irtx_data_word0. 0x8 0x00000000 0xffffffff cr_irtx_data_word0 0 31 irtx_data_word1 irtx_data_word1. 0xC 0x00000000 0xffffffff cr_irtx_data_word1 0 31 irtx_pulse_width irtx_pulse_width. 0x10 0x22110464 0xffffffff cr_irtx_mod_ph1_w 24 31 cr_irtx_mod_ph0_w 16 23 cr_irtx_pw_unit 0 11 irtx_pw irtx_pw. 0x14 0x007f2000 0xffffffff cr_irtx_tail_ph1_w 28 31 cr_irtx_tail_ph0_w 24 27 cr_irtx_head_ph1_w 20 23 cr_irtx_head_ph0_w 16 19 cr_irtx_logic1_ph1_w 12 15 cr_irtx_logic1_ph0_w 8 11 cr_irtx_logic0_ph1_w 4 7 cr_irtx_logic0_ph0_w 0 3 irtx_swm_pw_0 irtx_swm_pw_0. 0x40 0x00000000 0xffffffff cr_irtx_swm_pw_0 0 31 irtx_swm_pw_1 irtx_swm_pw_1. 0x44 0x00000000 0xffffffff cr_irtx_swm_pw_1 0 31 irtx_swm_pw_2 irtx_swm_pw_2. 0x48 0x00000000 0xffffffff cr_irtx_swm_pw_2 0 31 irtx_swm_pw_3 irtx_swm_pw_3. 0x4C 0x00000000 0xffffffff cr_irtx_swm_pw_3 0 31 irtx_swm_pw_4 irtx_swm_pw_4. 0x50 0x00000000 0xffffffff cr_irtx_swm_pw_4 0 31 irtx_swm_pw_5 irtx_swm_pw_5. 0x54 0x00000000 0xffffffff cr_irtx_swm_pw_5 0 31 irtx_swm_pw_6 irtx_swm_pw_6. 0x58 0x00000000 0xffffffff cr_irtx_swm_pw_6 0 31 irtx_swm_pw_7 irtx_swm_pw_7. 0x5C 0x00000000 0xffffffff cr_irtx_swm_pw_7 0 31 irrx_config irrx_config. 0x80 0x00000002 0xffffffff cr_irrx_deg_cnt 8 11 cr_irrx_deg_en 4 4 cr_irrx_mode 2 3 cr_irrx_in_inv 1 1 cr_irrx_en 0 0 irrx_int_sts irrx_int_sts. 0x84 0x01000100 0xffffffff cr_irrx_end_en 24 24 cr_irrx_end_clr 16 16 cr_irrx_end_mask 8 8 irrx_end_int 0 0 read-only irrx_pw_config irrx_pw_config. 0x88 0x23270d47 0xffffffff cr_irrx_end_th 16 31 cr_irrx_data_th 0 15 irrx_data_count irrx_data_count. 0x90 0x00000000 0xffffffff sts_irrx_data_cnt 0 6 read-only irrx_data_word0 irrx_data_word0. 0x94 0x00000000 0xffffffff sts_irrx_data_word0 0 31 read-only irrx_data_word1 irrx_data_word1. 0x98 0x00000000 0xffffffff sts_irrx_data_word1 0 31 read-only irrx_swm_fifo_config_0 irrx_swm_fifo_config_0. 0xC0 0x00000000 0xffffffff rx_fifo_cnt 4 10 read-only rx_fifo_underflow 3 3 read-only rx_fifo_overflow 2 2 read-only rx_fifo_clr 0 0 irrx_swm_fifo_rdata irrx_swm_fifo_rdata. 0xC4 0x00000000 0xffffffff read-only rx_fifo_rdata 0 15 CKS Checksum engine 0x4000A700 CKS 32 read-write 0 0x10 registers cks_config cks_config. 0x0 0x00000000 0xffffffff cr_cks_byte_swap Endianness. 1 1 CKSByteSwap little_endian Little endian. 0 big_endian Big endian. 1 cr_cks_clr 0 0 data_in Checksum data in 0x4 0x00000000 0xffffffff data_in 0 7 write-only cks_out Checksum value out 0x8 0x0000ffff 0xffffffff cks_out 0 15 read-only SF_CTRL Flash control 0x4000B000 SF_CTRL 32 read-write 0 0x1000 registers sf_ctrl_0 sf_ctrl_0. 0x0 0x1ad2001c 0xffffffff sf_id 24 31 sf_aes_iv_endian 23 23 sf_aes_key_endian 22 22 sf_aes_ctr_plus_en 21 21 sf_aes_dout_endian 20 20 sf_aes_dly_mode 19 19 sf_if_int_set 18 18 sf_if_int_clr 17 17 sf_if_int 16 16 read-only sf_if_read_dly_en 11 11 sf_if_read_dly_n 8 10 sf_clk_sahb_sram_sel 5 5 sf_clk_out_inv_sel 4 4 sf_clk_out_gate_en 3 3 sf_clk_sf_rx_inv_sel 2 2 sf_ctrl_1 sf_ctrl_1. 0x4 0xf3600000 0xffffffff sf_ahb2sram_en 31 31 sf_ahb2sif_en 30 30 sf_if_en 29 29 sf_if_fn_sel 28 28 sf_ahb2sif_stop 27 27 sf_ahb2sif_stopped 26 26 read-only sf_if_reg_wp 25 25 sf_if_reg_hold 24 24 sf_if_0_ack_lat 20 22 sf_if_sr_int_set 18 18 sf_if_sr_int_en 17 17 sf_if_sr_int 16 16 read-only sf_if_sr_pat 8 15 sf_if_sr_pat_mask 0 7 sf_if_sahb_0 sf_if_sahb_0. 0x8 0x00000000 0xffffffff sf_if_0_qpi_mode_en 31 31 sf_if_0_spi_mode 28 30 sf_if_0_cmd_en 27 27 sf_if_0_adr_en 26 26 sf_if_0_dmy_en 25 25 sf_if_0_dat_en 24 24 sf_if_0_dat_rw 23 23 sf_if_0_cmd_byte 20 22 sf_if_0_adr_byte 17 19 sf_if_0_dmy_byte 12 16 sf_if_0_dat_byte 2 11 sf_if_0_trig 1 1 sf_if_busy 0 0 read-only sf_if_sahb_1 sf_if_sahb_1. 0xC 0x00000000 0xffffffff sf_if_0_cmd_buf_0 0 31 sf_if_sahb_2 sf_if_sahb_2. 0x10 0x00000000 0xffffffff sf_if_0_cmd_buf_1 0 31 sf_if_iahb_0 sf_if_iahb_0. 0x14 0x0d040000 0xffffffff sf_if_1_qpi_mode_en 31 31 sf_if_1_spi_mode 28 30 sf_if_1_cmd_en 27 27 sf_if_1_adr_en 26 26 sf_if_1_dmy_en 25 25 sf_if_1_dat_en 24 24 sf_if_1_dat_rw 23 23 sf_if_1_cmd_byte 20 22 sf_if_1_adr_byte 17 19 sf_if_1_dmy_byte 12 16 sf_if_iahb_1 sf_if_iahb_1. 0x18 0x03000000 0xffffffff sf_if_1_cmd_buf_0 0 31 sf_if_iahb_2 sf_if_iahb_2. 0x1C 0x00000000 0xffffffff sf_if_1_cmd_buf_1 0 31 sf_if_status_0 sf_if_status_0. 0x20 0x00000000 0xffffffff read-only sf_if_status_0 0 31 sf_if_status_1 sf_if_status_1. 0x24 0x20000000 0xffffffff read-only sf_if_status_1 0 31 sf_aes sf_aes. 0x28 0x00000040 0xffffffff sf_aes_status 5 31 read-only sf_aes_pref_busy 4 4 read-only sf_aes_pref_trig 3 3 sf_aes_mode 1 2 sf_aes_en 0 0 sf_ahb2sif_status sf_ahb2sif_status. 0x2C 0x10000003 0xffffffff read-only sf_ahb2sif_status 0 31 sf_if_io_dly_0 sf_if_io_dly_0. 0x30 0x00000000 0xffffffff sf_dqs_do_dly_sel 30 31 sf_dqs_di_dly_sel 28 29 sf_dqs_oe_dly_sel 26 27 sf_clk_out_dly_sel 8 9 sf_cs_dly_sel 0 1 sf_if_io_dly_1 sf_if_io_dly_1. 0x34 0x00000000 0xffffffff sf_io_0_do_dly_sel 16 17 sf_io_0_di_dly_sel 8 9 sf_io_0_oe_dly_sel 0 1 sf_if_io_dly_2 sf_if_io_dly_2. 0x38 0x00000000 0xffffffff sf_io_1_do_dly_sel 16 17 sf_io_1_di_dly_sel 8 9 sf_io_1_oe_dly_sel 0 1 sf_if_io_dly_3 sf_if_io_dly_3. 0x3C 0x00000000 0xffffffff sf_io_2_do_dly_sel 16 17 sf_io_2_di_dly_sel 8 9 sf_io_2_oe_dly_sel 0 1 sf_if_io_dly_4 sf_if_io_dly_4. 0x40 0x00000000 0xffffffff sf_io_3_do_dly_sel 16 17 sf_io_3_di_dly_sel 8 9 sf_io_3_oe_dly_sel 0 1 sf_reserved sf_reserved. 0x44 sf_reserved 0 31 sf2_if_io_dly_0 sf2_if_io_dly_0. 0x48 0x00000000 0xffffffff sf2_dqs_do_dly_sel 30 31 sf2_dqs_di_dly_sel 28 29 sf2_dqs_oe_dly_sel 26 27 sf2_clk_out_dly_sel 8 9 sf2_cs_dly_sel 0 1 sf2_if_io_dly_1 sf2_if_io_dly_1. 0x4C 0x00000000 0xffffffff sf2_io_0_do_dly_sel 16 17 sf2_io_0_di_dly_sel 8 9 sf2_io_0_oe_dly_sel 0 1 sf2_if_io_dly_2 sf2_if_io_dly_2. 0x50 0x00000000 0xffffffff sf2_io_1_do_dly_sel 16 17 sf2_io_1_di_dly_sel 8 9 sf2_io_1_oe_dly_sel 0 1 sf2_if_io_dly_3 sf2_if_io_dly_3. 0x54 0x00000000 0xffffffff sf2_io_2_do_dly_sel 16 17 sf2_io_2_di_dly_sel 8 9 sf2_io_2_oe_dly_sel 0 1 sf2_if_io_dly_4 sf2_if_io_dly_4. 0x58 0x00000000 0xffffffff sf2_io_3_do_dly_sel 16 17 sf2_io_3_di_dly_sel 8 9 sf2_io_3_oe_dly_sel 0 1 sf3_if_io_dly_0 sf3_if_io_dly_0. 0x5C 0x00000000 0xffffffff sf3_dqs_do_dly_sel 30 31 sf3_dqs_di_dly_sel 28 29 sf3_dqs_oe_dly_sel 26 27 sf3_clk_out_dly_sel 8 9 sf3_cs_dly_sel 0 1 sf3_if_io_dly_1 sf3_if_io_dly_1. 0x60 0x00000000 0xffffffff sf3_io_0_do_dly_sel 16 17 sf3_io_0_di_dly_sel 8 9 sf3_io_0_oe_dly_sel 0 1 sf3_if_io_dly_2 sf3_if_io_dly_2. 0x64 0x00000000 0xffffffff sf3_io_1_do_dly_sel 16 17 sf3_io_1_di_dly_sel 8 9 sf3_io_1_oe_dly_sel 0 1 sf3_if_io_dly_3 sf3_if_io_dly_3. 0x68 0x00000000 0xffffffff sf3_io_2_do_dly_sel 16 17 sf3_io_2_di_dly_sel 8 9 sf3_io_2_oe_dly_sel 0 1 sf3_if_io_dly_4 sf3_if_io_dly_4. 0x6C 0x00000000 0xffffffff sf3_io_3_do_dly_sel 16 17 sf3_io_3_di_dly_sel 8 9 sf3_io_3_oe_dly_sel 0 1 sf_ctrl_2 sf_ctrl_2. 0x70 0x00000000 0xffffffff sf_if_dqs_en 5 5 sf_if_dtr_en 4 4 sf_if_pad_sel_lock 3 3 sf_if_pad_sel 0 1 sf_ctrl_3 sf_ctrl_3. 0x74 0x20000046 0xffffffff sf_if_1_ack_lat 29 31 sf_cmds_wrap_mode 10 10 sf_cmds_wrap_q_ini 9 9 sf_cmds_bt_en 8 8 sf_cmds_bt_dly 5 7 sf_cmds_en 4 4 sf_cmds_wrap_len 0 3 sf_if_iahb_3 sf_if_iahb_3. 0x78 0x8d840000 0xffffffff sf_if_2_qpi_mode_en 31 31 sf_if_2_spi_mode 28 30 sf_if_2_cmd_en 27 27 sf_if_2_adr_en 26 26 sf_if_2_dmy_en 25 25 sf_if_2_dat_en 24 24 sf_if_2_dat_rw 23 23 sf_if_2_cmd_byte 20 22 sf_if_2_adr_byte 17 19 sf_if_2_dmy_byte 12 16 sf_if_iahb_4 sf_if_iahb_4. 0x7C 0x38000000 0xffffffff sf_if_2_cmd_buf_0 0 31 sf_if_iahb_5 sf_if_iahb_5. 0x80 0x00000000 0xffffffff sf_if_2_cmd_buf_1 0 31 sf_if_iahb_6 sf_if_iahb_6. 0x84 0x80000000 0xffffffff sf_if_3_qpi_mode_en 31 31 sf_if_3_spi_mode 28 30 sf_if_3_cmd_byte 20 22 sf_if_iahb_7 sf_if_iahb_7. 0x88 0xc0000000 0xffffffff sf_if_3_cmd_buf_0 0 31 sf_ctrl_prot_en_rd sf_ctrl_prot_en_rd. 0x100 0x00000007 0xffffffff read-only sf_dbg_dis 31 31 sf_if_0_trig_wr_lock 30 30 sf_ctrl_id1_en_rd 2 2 sf_ctrl_id0_en_rd 1 1 sf_ctrl_prot_en_rd 0 0 sf_ctrl_prot_en sf_ctrl_prot_en. 0x104 0x00000007 0xffffffff sf_ctrl_id1_en 2 2 sf_ctrl_id0_en 1 1 sf_ctrl_prot_en 0 0 sf_aes_key_r0_0 sf_aes_key_r0_0. 0x200 0x00000000 0xffffffff sf_aes_key_r0_0 0 31 sf_aes_key_r0_1 sf_aes_key_r0_1. 0x204 0x00000000 0xffffffff sf_aes_key_r0_1 0 31 sf_aes_key_r0_2 sf_aes_key_r0_2. 0x208 0x00000000 0xffffffff sf_aes_key_r0_2 0 31 sf_aes_key_r0_3 sf_aes_key_r0_3. 0x20C 0x00000000 0xffffffff sf_aes_key_r0_3 0 31 sf_aes_key_r0_4 sf_aes_key_r0_4. 0x210 0x00000000 0xffffffff sf_aes_key_r0_4 0 31 sf_aes_key_r0_5 sf_aes_key_r0_5. 0x214 0x00000000 0xffffffff sf_aes_key_r0_5 0 31 sf_aes_key_r0_6 sf_aes_key_r0_6. 0x218 0x00000000 0xffffffff sf_aes_key_r0_6 0 31 sf_aes_key_r0_7 sf_aes_key_r0_7. 0x21C 0x00000000 0xffffffff sf_aes_key_r0_7 0 31 sf_aes_iv_r0_w0 sf_aes_iv_r0_w0. 0x220 0x00000000 0xffffffff sf_aes_iv_r0_w0 0 31 sf_aes_iv_r0_w1 sf_aes_iv_r0_w1. 0x224 0x00000000 0xffffffff sf_aes_iv_r0_w1 0 31 sf_aes_iv_r0_w2 sf_aes_iv_r0_w2. 0x228 0x00000000 0xffffffff sf_aes_iv_r0_w2 0 31 sf_aes_iv_r0_w3 sf_aes_iv_r0_w3. 0x22C 0x00000000 0xffffffff sf_aes_iv_r0_w3 0 31 sf_aes_cfg_r0 sf_aes_cfg_r0. 0x230 0x00003fff 0xffffffff sf_aes_region_r0_lock 31 31 sf_aes_region_r0_en 30 30 sf_aes_region_r0_hw_key_en 29 29 sf_aes_region_r0_start 14 27 sf_aes_region_r0_end 0 13 sf_aes_key_r1_0 sf_aes_key_r1_0. 0x300 0x00000000 0xffffffff sf_aes_key_r1_0 0 31 sf_aes_key_r1_1 sf_aes_key_r1_1. 0x304 0x00000000 0xffffffff sf_aes_key_r1_1 0 31 sf_aes_key_r1_2 sf_aes_key_r1_2. 0x308 0x00000000 0xffffffff sf_aes_key_r1_2 0 31 sf_aes_key_r1_3 sf_aes_key_r1_3. 0x30C 0x00000000 0xffffffff sf_aes_key_r1_3 0 31 sf_aes_key_r1_4 sf_aes_key_r1_4. 0x310 0x00000000 0xffffffff sf_aes_key_r1_4 0 31 sf_aes_key_r1_5 sf_aes_key_r1_5. 0x314 0x00000000 0xffffffff sf_aes_key_r1_5 0 31 sf_aes_key_r1_6 sf_aes_key_r1_6. 0x318 0x00000000 0xffffffff sf_aes_key_r1_6 0 31 sf_aes_key_r1_7 sf_aes_key_r1_7. 0x31C 0x00000000 0xffffffff sf_aes_key_r1_7 0 31 sf_aes_iv_r1_w0 sf_aes_iv_r1_w0. 0x320 0x00000000 0xffffffff sf_aes_iv_r1_w0 0 31 sf_aes_iv_r1_w1 sf_aes_iv_r1_w1. 0x324 0x00000000 0xffffffff sf_aes_iv_r1_w1 0 31 sf_aes_iv_r1_w2 sf_aes_iv_r1_w2. 0x328 0x00000000 0xffffffff sf_aes_iv_r1_w2 0 31 sf_aes_iv_r1_w3 sf_aes_iv_r1_w3. 0x32C 0x00000000 0xffffffff sf_aes_iv_r1_w3 0 31 sf_aes_r1 sf_aes_r1. 0x330 0x00003fff 0xffffffff sf_aes_r1_lock 31 31 sf_aes_r1_en 30 30 sf_aes_r1_hw_key_en 29 29 sf_aes_r1_start 14 27 sf_aes_r1_end 0 13 sf_aes_key_r2_0 sf_aes_key_r2_0. 0x400 0x00000000 0xffffffff sf_aes_key_r2_0 0 31 sf_aes_key_r2_1 sf_aes_key_r2_1. 0x404 0x00000000 0xffffffff sf_aes_key_r2_1 0 31 sf_aes_key_r2_2 sf_aes_key_r2_2. 0x408 0x00000000 0xffffffff sf_aes_key_r2_2 0 31 sf_aes_key_r2_3 sf_aes_key_r2_3. 0x40C 0x00000000 0xffffffff sf_aes_key_r2_3 0 31 sf_aes_key_r2_4 sf_aes_key_r2_4. 0x410 0x00000000 0xffffffff sf_aes_key_r2_4 0 31 sf_aes_key_r2_5 sf_aes_key_r2_5. 0x414 0x00000000 0xffffffff sf_aes_key_r2_5 0 31 sf_aes_key_r2_6 sf_aes_key_r2_6. 0x418 0x00000000 0xffffffff sf_aes_key_r2_6 0 31 sf_aes_key_r2_7 sf_aes_key_r2_7. 0x41C 0x00000000 0xffffffff sf_aes_key_r2_7 0 31 sf_aes_iv_r2_w0 sf_aes_iv_r2_w0. 0x420 0x00000000 0xffffffff sf_aes_iv_r2_w0 0 31 sf_aes_iv_r2_w1 sf_aes_iv_r2_w1. 0x424 0x00000000 0xffffffff sf_aes_iv_r2_w1 0 31 sf_aes_iv_r2_w2 sf_aes_iv_r2_w2. 0x428 0x00000000 0xffffffff sf_aes_iv_r2_w2 0 31 sf_aes_iv_r2_w3 sf_aes_iv_r2_w3. 0x42C 0x00000000 0xffffffff sf_aes_iv_r2_w3 0 31 sf_aes_r2 sf_aes_r2. 0x430 0x00003fff 0xffffffff sf_aes_r2_lock 31 31 sf_aes_r2_en 30 30 sf_aes_r2_hw_key_en 29 29 sf_aes_r2_start 14 27 sf_aes_r2_end 0 13 sf_id0_offset sf_id0_offset. 0x434 0x00000000 0xffffffff sf_id0_offset 0 23 sf_id1_offset sf_id1_offset. 0x438 0x00000000 0xffffffff sf_id1_offset 0 23 DMA DMA control 0x4000C000 DMA 32 read-write 0 0x1000 registers DMA_IntStatus DMA_IntStatus. 0x0 0x00000000 0xffffffff IntStatus 0 7 read-only DMA_IntTCStatus DMA_IntTCStatus. 0x4 0x00000000 0xffffffff IntTCStatus 0 7 read-only DMA_IntTCClear DMA_IntTCClear. 0x8 0x00000000 0xffffffff IntTCClear 0 7 write-only DMA_IntErrorStatus DMA_IntErrorStatus. 0xC 0x00000000 0xffffffff IntErrorStatus 0 7 read-only DMA_IntErrClr DMA_IntErrClr. 0x10 0x00000000 0xffffffff IntErrClr 0 7 write-only DMA_RawIntTCStatus DMA_RawIntTCStatus. 0x14 0x00000000 0xffffffff RawIntTCStatus 0 7 read-only DMA_RawIntErrorStatus DMA_RawIntErrorStatus. 0x18 0x00000000 0xffffffff RawIntErrorStatus 0 7 read-only DMA_EnbldChns DMA_EnbldChns. 0x1C 0x00000000 0xffffffff EnabledChannels 0 7 read-only DMA_SoftBReq DMA_SoftBReq. 0x20 0x00000000 0xffffffff SoftBReq 0 31 DMA_SoftSReq DMA_SoftSReq. 0x24 0x00000000 0xffffffff SoftSReq 0 31 DMA_SoftLBReq DMA_SoftLBReq. 0x28 0x00000000 0xffffffff SoftLBReq 0 31 DMA_SoftLSReq DMA_SoftLSReq. 0x2C 0x00000000 0xffffffff SoftLSReq 0 31 DMA_Top_Config DMA_Top_Config. 0x30 0x00000000 0xffffffff M 1 1 E 0 0 DMA_Sync DMA_Sync. 0x34 0x00000000 0xffffffff DMA_Sync 0 31 DMA_C0SrcAddr DMA_C0SrcAddr. 0x100 0x00000000 0xffffffff SrcAddr 0 31 DMA_C0DstAddr DMA_C0DstAddr. 0x104 0x00000000 0xffffffff DstAddr 0 31 DMA_C0LLI DMA_C0LLI. 0x108 0x00000000 0xffffffff LLI 0 31 DMA_C0Control DMA_C0Control. 0x10C 0x0c489000 0xffffffff I 31 31 Prot 28 30 DI 27 27 SI 26 26 SLargerD 24 24 DWidth 21 23 SWidth 18 20 DBSize 15 17 SBSize 12 14 TransferSize 0 11 DMA_C0Config DMA_C0Config. 0x110 0x00000000 0xffffffff LLICounter 20 29 read-only H 18 18 A 17 17 read-only L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C1SrcAddr DMA_C1SrcAddr. 0x200 0x00000000 0xffffffff SrcAddr 0 31 DMA_C1DstAddr DMA_C1DstAddr. 0x204 0x00000000 0xffffffff DstAddr 0 31 DMA_C1LLI DMA_C1LLI. 0x208 0x00000000 0xffffffff LLI 2 31 DMA_C1Control DMA_C1Control. 0x20C 0x0c489000 0xffffffff I 31 31 Prot 28 30 DI 27 27 SI 26 26 DWidth 21 23 SWidth 18 20 DBSize 15 17 SBSize 12 14 TransferSize 0 11 DMA_C1Config DMA_C1Config. 0x210 0x00000000 0xffffffff H 18 18 A 17 17 read-only L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C2SrcAddr DMA_C2SrcAddr. 0x300 0x00000000 0xffffffff SrcAddr 0 31 DMA_C2DstAddr DMA_C2DstAddr. 0x304 0x00000000 0xffffffff DstAddr 0 31 DMA_C2LLI DMA_C2LLI. 0x308 0x00000000 0xffffffff LLI 2 31 DMA_C2Control DMA_C2Control. 0x30C 0x0c489000 0xffffffff I 31 31 Prot 28 30 DI 27 27 SI 26 26 DWidth 21 23 SWidth 18 20 DBSize 15 17 SBSize 12 14 TransferSize 0 11 DMA_C2Config DMA_C2Config. 0x310 0x00000000 0xffffffff H 18 18 A 17 17 read-only L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C3SrcAddr DMA_C3SrcAddr. 0x400 0x00000000 0xffffffff SrcAddr 0 31 DMA_C3DstAddr DMA_C3DstAddr. 0x404 0x00000000 0xffffffff DstAddr 0 31 DMA_C3LLI DMA_C3LLI. 0x408 0x00000000 0xffffffff LLI 2 31 DMA_C3Control DMA_C3Control. 0x40C 0x0c489000 0xffffffff I 31 31 Prot 28 30 DI 27 27 SI 26 26 DWidth 21 23 SWidth 18 20 DBSize 15 17 SBSize 12 14 TransferSize 0 11 DMA_C3Config DMA_C3Config. 0x410 0x00000000 0xffffffff H 18 18 A 17 17 read-only L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 PDS Sleep control (power-down sleep) 0x4000E000 PDS 32 read-write 0 0x1000 registers PDS_CTL PDS_CTL. 0x0 0x1a006b00 0xffffffff cr_pds_ctrl_pll 30 31 cr_pds_ctrl_rf 28 29 cr_pds_ldo_vol 24 27 cr_pds_pd_ldo11 22 22 cr_np_wfi_mask 21 21 cr_pds_ldo_vsel_en 18 18 cr_pds_rc32m_off_dis 17 17 cr_pds_rst_soc_en 16 16 cr_pds_soc_enb_force_on 15 15 cr_pds_pd_xtal 14 14 cr_pds_pwr_off 13 13 cr_pds_wait_xtal_rdy 12 12 cr_pds_iso_en 11 11 cr_pds_mem_stby 9 9 cr_pds_gate_clk 8 8 cr_pds_pd_bg_sys 5 5 cr_pds_pd_dcdc18 4 4 cr_wifi_pds_save_state 3 3 cr_xtal_force_off 2 2 cr_sleep_forever 1 1 pds_start_ps 0 0 PDS_TIME1 PDS_TIME1. 0x4 0x00000ca8 0xffffffff cr_sleep_duration 0 31 PDS_INT PDS_INT. 0xC 0x00000000 0xffffffff cr_pds_int_clr 16 16 cr_pds_pll_done_int_mask 11 11 cr_pds_rf_done_int_mask 10 10 cr_pds_irq_in_dis 9 9 cr_pds_wake_int_mask 8 8 ro_pds_pll_done_int 3 3 read-only ro_pds_rf_done_int 2 2 read-only ro_pds_irq_in 1 1 read-only ro_pds_wake_int 0 0 read-only PDS_CTL2 PDS_CTL2. 0x10 0x00000000 0xffffffff cr_pds_force_wb_gate_clk 18 18 cr_pds_force_np_gate_clk 16 16 cr_pds_force_wb_mem_stby 14 14 cr_pds_force_np_mem_stby 12 12 cr_pds_force_wb_pds_rst 10 10 cr_pds_force_np_pds_rst 8 8 cr_pds_force_wb_iso_en 6 6 cr_pds_force_np_iso_en 4 4 cr_pds_force_wb_pwr_off 2 2 cr_pds_force_np_pwr_off 0 0 PDS_CTL3 PDS_CTL3. 0x14 0x49000000 0xffffffff cr_pds_misc_iso_en 30 30 cr_pds_wb_iso_en 27 27 cr_pds_np_iso_en 24 24 cr_pds_force_misc_gate_clk 13 13 cr_pds_force_misc_mem_stby 10 10 cr_pds_force_misc_pds_rst 7 7 cr_pds_force_misc_iso_en 4 4 cr_pds_force_misc_pwr_off 1 1 PDS_CTL4 PDS_CTL4. 0x18 0x0f00f00f 0xffffffff cr_pds_misc_gate_clk 27 27 cr_pds_misc_mem_stby 26 26 cr_pds_misc_reset 25 25 cr_pds_misc_pwr_off 24 24 cr_pds_wb_gate_clk 15 15 cr_pds_wb_mem_stby 14 14 cr_pds_wb_reset 13 13 cr_pds_wb_pwr_off 12 12 cr_pds_np_gate_clk 3 3 cr_pds_np_mem_stby 2 2 cr_pds_np_reset 1 1 cr_pds_np_pwr_off 0 0 pds_stat pds_stat. 0x1C 0x00000000 0xffffffff read-only ro_pds_pll_state 16 17 ro_pds_rf_state 8 11 ro_pds_state 0 3 pds_ram1 pds_ram1. 0x20 0x00000000 0xffffffff cr_np_sram_pwr 0 7 rc32m_ctrl0 rc32m_ctrl0. 0x300 0x18080018 0xffffffff rc32m_code_fr_ext 22 29 rc32m_pd 21 21 rc32m_cal_en 20 20 rc32m_ext_code_en 19 19 rc32m_refclk_half 18 18 rc32m_allow_cal 17 17 rc32m_dig_code_fr_cal 6 13 read-only rc32m_cal_precharge 5 5 read-only rc32m_cal_div 3 4 rc32m_cal_inprogress 2 2 read-only rc32m_rdy 1 1 read-only rc32m_cal_done 0 0 read-only rc32m_ctrl1 rc32m_ctrl1. 0x304 0x00000000 0xffffffff rc32m_reserved 24 31 rc32m_clk_force_on 4 4 rc32m_clk_inv 3 3 rc32m_clk_soft_rst 2 2 rc32m_soft_rst 1 1 rc32m_test_en 0 0 pu_rst_clkpll pu_rst_clkpll. 0x400 0x000001f0 0xffffffff pu_clkpll 10 10 pu_clkpll_sfreg 9 9 clkpll_pu_cp 8 8 clkpll_pu_pfd 7 7 clkpll_pu_clamp_op 6 6 clkpll_pu_fbdv 5 5 clkpll_pu_postdiv 4 4 clkpll_reset_refdiv 3 3 clkpll_reset_fbdv 2 2 clkpll_reset_postdiv 1 1 clkpll_sdm_reset 0 0 clkpll_top_ctrl clkpll_top_ctrl. 0x404 0x01100414 0xffffffff clkpll_vg13_sel 24 25 clkpll_vg11_sel 20 21 clkpll_refclk_sel 16 16 clkpll_xtal_rc32m_sel 12 12 clkpll_refdiv_ratio 8 11 clkpll_postdiv 0 6 clkpll_cp clkpll_cp. 0x408 0x00000741 0xffffffff clkpll_cp_opamp_en 10 10 clkpll_cp_startup_en 9 9 clkpll_int_frac_sw 8 8 clkpll_icp_1u 6 7 clkpll_icp_5u 4 5 clkpll_sel_cp_bias 0 0 clkpll_rz clkpll_rz. 0x40C 0x0005a020 0xffffffff clkpll_rz 16 18 clkpll_cz 14 15 clkpll_c3 12 13 clkpll_r4_short 8 8 clkpll_r4 4 5 clkpll_c4_en 0 0 clkpll_fbdv clkpll_fbdv. 0x410 0x00000005 0xffffffff clkpll_sel_fb_clk 2 3 clkpll_sel_sample_clk 0 1 clkpll_vco clkpll_vco. 0x414 0x00000007 0xffffffff clkpll_shrtr 3 3 clkpll_vco_speed 0 2 clkpll_sdm clkpll_sdm. 0x418 0x10600000 0xffffffff clkpll_sdm_bypass 29 29 clkpll_sdm_flag 28 28 clkpll_dither_sel 24 25 clkpll_sdmin 0 23 clkpll_output_en clkpll_output_en. 0x41C 0x00000100 0xffffffff clkpll_en_div2_480m 9 9 clkpll_en_32m 8 8 clkpll_en_48m 7 7 clkpll_en_80m 6 6 clkpll_en_96m 5 5 clkpll_en_120m 4 4 clkpll_en_160m 3 3 clkpll_en_192m 2 2 clkpll_en_240m 1 1 clkpll_en_480m 0 0 HBN Deep Sleep Control (Hibernation) 0x4000F000 HBN 32 read-write 0 0x1000 registers HBN_CTL HBN_CTL. 0x0 0x00d50000 0xffffffff hbn_state 28 31 read-only sram_slp 27 27 read-only sram_slp_option 26 26 pwr_on_option 25 25 rtc_dly_option 24 24 pu_dcdc18_aon 23 23 hbn_ldo11_aon_vout_sel 19 22 hbn_ldo11_rt_vout_sel 15 18 hbn_dis_pwr_off_ldo11_rt 14 14 hbn_dis_pwr_off_ldo11 13 13 sw_rst 12 12 pwrdn_hbn_rtc 11 11 pwrdn_hbn_core 9 9 trap_mode 8 8 read-only hbn_mode 7 7 write-only rtc_ctl 0 6 HBN_TIME_L HBN_TIME_L. 0x4 0x00000000 0xffffffff hbn_time_l 0 31 HBN_TIME_H HBN_TIME_H. 0x8 0x00000000 0xffffffff hbn_time_h 0 7 RTC_TIME_L RTC_TIME_L. 0xC 0x00000000 0xffffffff read-only rtc_time_latch_l 0 31 RTC_TIME_H RTC_TIME_H. 0x10 0x00000000 0xffffffff rtc_time_latch 31 31 write-only rtc_time_latch_h 0 7 read-only HBN_IRQ_MODE HBN_IRQ_MODE. 0x14 0x03010105 0xffffffff pin_wakeup_en 27 27 pin_wakeup_sel 24 26 irq_acomp1_en 22 23 irq_acomp0_en 20 21 irq_bor_en 18 18 reg_en_hw_pu_pd 16 16 reg_aon_pad_ie_smt 8 8 hbn_pin_wakeup_mask 3 4 hbn_pin_wakeup_mode 0 2 HBN_IRQ_STAT HBN_IRQ_STAT. 0x18 0x00000000 0xffffffff read-only irq_stat 0 31 HBN_IRQ_CLR HBN_IRQ_CLR. 0x1C 0x00000000 0xffffffff write-only irq_clr 0 31 HBN_PIR_CFG HBN_PIR_CFG. 0x20 0x00000000 0xffffffff gpadc_nosync 9 9 gpadc_cgen 8 8 pir_en 7 7 pir_dis 4 5 pir_lpf_sel 2 2 pir_hpf_sel 0 1 HBN_PIR_VTH HBN_PIR_VTH. 0x24 0x000003ff 0xffffffff pir_vth 0 13 HBN_PIR_INTERVAL HBN_PIR_INTERVAL. 0x28 0x00000a3d 0xffffffff pir_interval 0 11 HBN_BOR_CFG HBN_BOR_CFG. 0x2C 0x00000002 0xffffffff r_bor_out 3 3 read-only pu_bor 2 2 bor_vth 1 1 bor_sel 0 0 HBN_GLB HBN_GLB. 0x30 0xaa0a0020 0xffffffff sw_ldo11_aon_vout_sel 28 31 sw_ldo11_rt_vout_sel 24 27 sw_ldo11soc_vout_sel_aon 16 19 hbn_pu_rc32k 5 5 hbn_f32k_sel 3 4 hbn_uart_clk_sel 2 2 hbn_root_clk_sel 0 1 HBN_SRAM HBN_SRAM. 0x34 0x00000000 0xffffffff retram_slp 7 7 retram_ret 6 6 HBN_RSV0 HBN_RSV0. 0x100 0x00000000 0xffffffff HBN_RSV0 0 31 HBN_RSV1 HBN_RSV1. 0x104 0xffffffff 0xffffffff HBN_RSV1 0 31 HBN_RSV2 HBN_RSV2. 0x108 0x00000000 0xffffffff HBN_RSV2 0 31 HBN_RSV3 HBN_RSV3. 0x10C 0xffffffff 0xffffffff HBN_RSV3 0 31 rc32k_ctrl0 rc32k_ctrl0. 0x200 0x5008801b 0xffffffff rc32k_code_fr_ext 22 31 rc32k_cal_en 20 20 rc32k_ext_code_en 19 19 rc32k_allow_cal 18 18 rc32k_vref_dly 16 17 rc32k_dig_code_fr_cal 6 15 read-only rc32k_cal_precharge 5 5 read-only rc32k_cal_div 3 4 rc32k_cal_inprogress 2 2 read-only rc32k_rdy 1 1 read-only rc32k_cal_done 0 0 read-only xtal32k xtal32k. 0x204 0x000f0228 0xffffffff pu_xtal32k 19 19 pu_xtal32k_buf 18 18 xtal32k_ac_cap_short 17 17 xtal32k_capbank 11 16 xtal32k_inv_stre 9 10 xtal32k_otf_short 8 8 xtal32k_outbuf_stre 7 7 xtal32k_reg 5 6 xtal32k_amp_ctrl 3 4 xtal32k_ext_sel 2 2 AON Always-ON periherals 0x40010000 AON 32 read-write 0 0x144 registers aon aon. 0x000 0x00400000 0xffffffff sw_pu_ldo11_rt 22 22 ldo11_rt_pulldown_sel 21 21 ldo11_rt_pulldown 20 20 pu_aon_dc_tbuf 12 12 aon_resv 0 7 aon_common aon_common. 0x004 0x00000000 0xffffffff ten_cip_misc_aon 20 20 ten_mbg_aon 19 19 dten_xtal_aon 18 18 ten_xtal_aon 17 17 ten_ldo15rf_aon 16 16 ten_bg_sys_aon 12 12 ten_dcdc18_1_aon 11 11 ten_dcdc18_0_aon 10 10 ten_ldo11soc_aon 9 9 ten_vddcore_aon 8 8 ten_xtal32k 6 6 dten_xtal32k 5 5 ten_aon 4 4 tmux_aon 0 2 aon_misc aon_misc. 0x008 0x00000003 0xffffffff sw_wb_en_aon 1 1 sw_soc_en_aon 0 0 bg_sys_top bg_sys_top. 0x010 0x00001100 0xffffffff bg_sys_start_ctrl_aon 12 12 pu_bg_sys_aon 8 8 pmip_resv 0 7 dcdc18_top_0 dcdc18_top_0. 0x014 0x8a580736 0xffffffff dcdc18_rdy_aon 31 31 read-only dcdc18_sstart_time_aon 28 29 dcdc18_osc_inhibit_t2_aon 27 27 dcdc18_slow_osc_aon 26 26 dcdc18_stop_osc_aon 25 25 dcdc18_slope_curr_sel_aon 20 24 dcdc18_osc_freq_trim_aon 16 19 dcdc18_osc_2m_mode_aon 12 12 dcdc18_vpfm_aon 8 11 dcdc18_vout_sel_aon 1 5 dcdc18_top_1 dcdc18_top_1. 0x018 0x18180048 0xffffffff dcdc18_pulldown_aon 29 29 dcdc18_en_antiring_aon 28 28 dcdc18_cfb_sel_aon 24 27 dcdc18_chf_sel_aon 20 23 dcdc18_rc_sel_aon 16 19 dcdc18_nonoverlap_td_aon 8 12 dcdc18_zvs_td_opt_aon 4 6 dcdc18_cs_delay_aon 1 3 dcdc18_force_cs_zvs_aon 0 0 ldo11soc_and_dctest ldo11soc_and_dctest. 0x01C 0x70001811 0xffffffff pmip_dc_tp_out_en_aon 31 31 pu_vddcore_misc_aon 30 30 ldo11soc_power_good_aon 29 29 read-only ldo11soc_rdy_aon 28 28 read-only ldo11soc_cc_aon 24 25 ldo11soc_vth_sel_aon 12 13 ldo11soc_pulldown_sel_aon 11 11 ldo11soc_pulldown_aon 10 10 ldo11soc_sstart_delay_aon 8 9 ldo11soc_sstart_sel_aon 4 4 pu_ldo11soc_aon 0 0 psw_irrcv psw_irrcv. 0x020 0x00000000 0xffffffff pu_ir_psw_aon 0 0 rf_top_aon rf_top_aon. 0x080 0x00020137 0xffffffff ldo15rf_bypass_aon 28 28 ldo15rf_cc_aon 24 25 ldo15rf_vout_sel_aon 16 18 ldo15rf_pulldown_sel_aon 13 13 ldo15rf_pulldown_aon 12 12 ldo15rf_sstart_delay_aon 9 10 ldo15rf_sstart_sel_aon 8 8 pu_xtal_aon 5 5 pu_xtal_buf_aon 4 4 pu_sfreg_aon 2 2 pu_ldo15rf_aon 1 1 pu_mbg_aon 0 0 xtal_cfg xtal_cfg. 0x084 0xb410f0f0 0xffffffff xtal_rdy_sel_aon 30 31 xtal_gm_boost_aon 28 29 xtal_capcode_in_aon 22 27 xtal_capcode_out_aon 16 21 xtal_amp_ctrl_aon 14 15 xtal_sleep_aon 13 13 xtal_fast_startup_aon 12 12 xtal_buf_hp_aon 8 11 xtal_buf_en_aon 4 7 xtal_ext_sel_aon 3 3 xtal_capcode_extra_aon 2 2 xtal_bk_aon 0 1 tsen tsen. 0x088 0x78ff08ff 0xffffffff xtal_rdy_int_sel_aon 30 31 xtal_inn_cfg_en_aon 29 29 xtal_rdy 28 28 read-only tsen_refcode_rfcal 16 27 tsen_refcode_corner 0 11 acomp0_ctrl acomp0_ctrl. 0x100 0x00000000 0xffffffff acomp0_muxen 26 26 acomp0_pos_sel 22 25 acomp0_neg_sel 18 21 acomp0_level_sel 12 17 acomp0_bias_prog 10 11 acomp0_hyst_selp 7 9 acomp0_hyst_seln 4 6 acomp0_en 0 0 acomp1_ctrl acomp1_ctrl. 0x104 0x00000000 0xffffffff acomp1_muxen 26 26 acomp1_pos_sel 22 25 acomp1_neg_sel 18 21 acomp1_level_sel 12 17 acomp1_bias_prog 10 11 acomp1_hyst_selp 7 9 acomp1_hyst_seln 4 6 acomp1_en 0 0 acomp_ctrl acomp_ctrl. 0x108 0x00000003 0xffffffff acomp_reserved 24 31 acomp0_out_raw 19 19 read-only acomp1_out_raw 17 17 read-only acomp0_test_sel 12 13 acomp1_test_sel 10 11 acomp0_test_en 9 9 acomp1_test_en 8 8 acomp0_rstn_ana 1 1 acomp1_rstn_ana 0 0 gpadc_reg_cmd gpadc_reg_cmd. 0x10C 0x00000f78 0xffffffff gpadc_sen_test_en 30 30 gpadc_sen_sel 28 29 gpadc_chip_sen_pu 27 27 gpadc_micboost_32db_en 23 23 gpadc_mic_pga2_gain 21 22 gpadc_mic1_diff 20 20 gpadc_mic2_diff 19 19 gpadc_dwa_en 18 18 gpadc_byp_micboost 16 16 gpadc_micpga_en 15 15 gpadc_micbias_en 14 14 gpadc_neg_gnd 13 13 gpadc_pos_sel 8 12 gpadc_neg_sel 3 7 gpadc_soft_rst 2 2 gpadc_conv_start 1 1 gpadc_global_en 0 0 gpadc_reg_config1 gpadc_reg_config1. 0x110 0x000c0002 0xffffffff gpadc_v18_sel 29 30 gpadc_v11_sel 27 28 gpadc_dither_en 26 26 gpadc_scan_en 25 25 gpadc_scan_length 21 24 gpadc_clk_div_ratio 18 20 gpadc_clk_ana_inv 17 17 gpadc_res_sel 2 4 gpadc_cont_conv_en 1 1 gpadc_cal_os_en 0 0 gpadc_reg_config2 gpadc_reg_config2. 0x114 0x00019100 0xffffffff gpadc_tsvbe_low 31 31 gpadc_dly_sel 28 30 gpadc_pga1_gain 25 27 gpadc_pga2_gain 22 24 gpadc_test_sel 19 21 gpadc_test_en 18 18 gpadc_bias_sel 17 17 gpadc_chop_mode 15 16 gpadc_pga_vcmi_en 14 14 gpadc_pga_en 13 13 gpadc_pga_os_cal 9 12 gpadc_pga_vcm 7 8 gpadc_ts_en 6 6 gpadc_tsext_sel 5 5 gpadc_vbat_en 4 4 gpadc_vref_sel 3 3 gpadc_diff_mode 2 2 gpadc_reg_scn_pos1 adc converation sequence 1 0x118 0x1ef7bdef 0xffffffff gpadc_scan_pos_5 25 29 gpadc_scan_pos_4 20 24 gpadc_scan_pos_3 15 19 gpadc_scan_pos_2 10 14 gpadc_scan_pos_1 5 9 gpadc_scan_pos_0 0 4 gpadc_reg_scn_pos2 adc converation sequence 2 0x11C 0x1ef7bdef 0xffffffff gpadc_scan_pos_11 25 29 gpadc_scan_pos_10 20 24 gpadc_scan_pos_9 15 19 gpadc_scan_pos_8 10 14 gpadc_scan_pos_7 5 9 gpadc_scan_pos_6 0 4 gpadc_reg_scn_neg1 adc converation sequence 3 0x120 0x1ef7bdef 0xffffffff gpadc_scan_neg_5 25 29 gpadc_scan_neg_4 20 24 gpadc_scan_neg_3 15 19 gpadc_scan_neg_2 10 14 gpadc_scan_neg_1 5 9 gpadc_scan_neg_0 0 4 gpadc_reg_scn_neg2 adc converation sequence 4 0x124 0x1ef7bdef 0xffffffff gpadc_scan_neg_11 25 29 gpadc_scan_neg_10 20 24 gpadc_scan_neg_9 15 19 gpadc_scan_neg_8 10 14 gpadc_scan_neg_7 5 9 gpadc_scan_neg_6 0 4 gpadc_reg_status gpadc_reg_status. 0x128 0x00000000 0xffffffff gpadc_reserved 16 31 gpadc_data_rdy 0 0 read-only gpadc_reg_isr gpadc_reg_isr. 0x12C 0x00000000 0xffffffff gpadc_pos_satur_mask 9 9 gpadc_neg_satur_mask 8 8 gpadc_pos_satur_clr 5 5 gpadc_neg_satur_clr 4 4 gpadc_pos_satur 1 1 read-only gpadc_neg_satur 0 0 read-only gpadc_reg_result gpadc_reg_result. 0x130 0x01ef0000 0xffffffff gpadc_data_out 0 25 read-only gpadc_reg_raw_result gpadc_reg_raw_result. 0x134 0x00000000 0xffffffff gpadc_raw_data 0 11 read-only gpadc_reg_define gpadc_reg_define. 0x138 0x00000000 0xffffffff gpadc_os_cal_data 0 15 hbncore_resv0 hbncore_resv0. 0x13C 0x00000000 0xffffffff hbncore_resv0_data 0 31 hbncore_resv1 hbncore_resv1. 0x140 0xffffffff 0xffffffff hbncore_resv1_data 0 31