Bouffalo Lab bouffalolab BL616/BL618 1.0 Bouffalo BL616/BL618 chip series Copyright (c) 2023 Bouffalo Lab bl616-pac is licensed under Mulan PSL v2. You can use this software according to the terms and conditions of the Mulan PSL v2. You may obtain a copy of Mulan PSL v2 at: http://license.coscl.org.cn/MulanPSL2 THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. See the Mulan PSL v2 for more details. 8 64 32 read-write 0x00000000 0xFFFFFFFF GLB Global configuration register 0x20000000 0 0x1000 registers chip_inform Chip information register 0x000 ready Chip ready signal 27 27 version Peripheral version 28 31 2 0x04 interrupt_state[%s] Chip interrupt state register 0x050 2 0x04 interrupt_mask[%s] Chip interrupt mask register 0x058 2 0x04 interrupt_clear[%s] Chip clear interrupt register 0x060 clock_config_0 System clock configuration register 0 0x090 pll Enable or disable Phase-Locked Loop 0 0 fclk Enable or disable fast clock 1 1 hclk Enable or disable hibernate clock 2 2 bclk Enable or disable bus clock 3 3 root_clk_source Set source of root clock 6 7 hclk_divide Set divide factor of hibernate clock 8 15 bclk_divide Set divide factor of bus clock 16 23 clock_config_1 System clock configuration register 1 0x094 bus_config_0 Bus configuration register 0 0x0A0 gpadc_config General Purpose Analog-to-digital convert configuration 0x110 gpdac_config_0 General Purpose Digital-to-analog convert configuration 0 0x120 gpdac_config_1 General Purpose Digital-to-analog convert configuration 1 0x124 gpdac_config_2 General Purpose Digital-to-analog convert configuration 2 0x128 gpdac_config_3 General Purpose Digital-to-analog convert configuration 3 0x12C dma_config_0 Direct Memory Access configuration 0 0x130 dma_config_1 Direct Memory Access configuration 1 0x134 dma_config_2 Direct Memory Access configuration 2 0x138 ir_config_0 Infrared configuration register 0 0x140 ir_config_1 Infrared configuration register 1 0x144 uart_config Universal Asynchronous Receiver/Transmitter configuration 0x150 clock_divide Peripheral clock divide factor 0 2 clock_enable Peripheral level clock gate enable 4 4 hibernate_clock_source Reads clock source from hibernate registers 7 7 read-only hibernate_clock_source_2 Reads clock source from hibernate registers 22 22 read-only uart_signal_0 Universal Asynchronous Receiver/Transmitter signal configuration 0 0x154 true 8 4 function_0[%s] Select peripheral function for UART signal %s 0 7 Function uart0_rts UART0 Request-to-Send flow control 0 uart0_cts UART0 Clear-to-Send flow control 1 uart0_txd UART0 transmit data 2 uart0_rxd UART0 receive data 3 uart1_rts UART1 Request-to-Send flow control 4 uart1_cts UART1 Clear-to-Send flow control 5 uart1_txd UART1 transmit data 6 uart1_rxd UART1 receive data 7 uart_signal_1 Universal Asynchronous Receiver/Transmitter signal configuration 1 0x158 true 4 4 function_1[%s] Select peripheral function for UART signal %s (offset by 8) 0 7 flash_config Serial flash configuration 0x170 clock_divide Peripheral clock divide factor 8 10 clock_enable Peripheral level clock gate enable 11 11 clock_source_0 Peripheral clock source register 0 12 13 clock_source_1 Peripheral clock source register 1 14 15 i2c_config Inter-Integrated Circuit bus configuration 0x180 clock_divide Peripheral clock divide factor 16 23 clock_enable Peripheral level clock gate enable 24 24 clock_source Peripheral clock source register 25 25 i2s_config Inter-IC Sound configuration 0x190 spi_config Serial Peripheral Interface configuration 0x1B0 clock_divide Peripheral clock divide factor 0 4 clock_enable Peripheral level clock gate enable 8 8 clock_source Peripheral clock source register 9 9 pin_swap Swap Serial Peripheral Interface pin signals 16 19 pwm_config Pulse-Width configuration 0x1E0 dbi_config MIPI Display Bus Interface clock configuration 0x1F0 clock_divide Peripheral clock divide factor 0 4 clock_enable Peripheral level clock gate enable 8 8 clock_source Peripheral clock source register 9 9 digit_clock_0 Digital clock configuration 0 0x250 digit_clock_1 Digital clock configuration 1 0x254 digit_clock_2 Digital clock configuration 2 0x258 radio_config Radio frequency configuration register 0x260 debug_config_0 Debug configuration register 0 0x2E0 debug_config_1 Debug configuration register 1 0x2E4 debug_config_2 Debug configuration register 2 0x2E8 debug_config_3 Debug configuration register 3 0x2EC debug_config_4 Debug configuration register 4 0x2F0 self_test_0 Machine Built-in Self Test register 0 0x300 self_test_1 Machine Built-in Self Test register 1 0x304 audio_config_0 Audio configuration register 0 0x340 audio_config_1 Audio configuration register 1 0x344 emac_config Ethernet Media Access Control configuration 0x390 sdh_config Secure Digital host configuration 0x430 permit_config Permission control peripheral configuration 0x490 psram_config Pseudo Static Random-Access Memory configuration 0x620 wifi_pll_config_0 Wireless Fidelity Phase-Locked Loop configuration 0 0x810 wifi_pll_config_1 Wireless Fidelity Phase-Locked Loop configuration 1 0x814 wifi_pll_config_2 Wireless Fidelity Phase-Locked Loop configuration 2 0x818 wifi_pll_config_3 Wireless Fidelity Phase-Locked Loop configuration 3 0x81C wifi_pll_config_4 Wireless Fidelity Phase-Locked Loop configuration 4 0x820 wifi_pll_config_5 Wireless Fidelity Phase-Locked Loop configuration 5 0x824 wifi_pll_config_6 Wireless Fidelity Phase-Locked Loop configuration 6 0x828 wifi_pll_config_7 Wireless Fidelity Phase-Locked Loop configuration 7 0x82C wifi_pll_config_8 Wireless Fidelity Phase-Locked Loop configuration 8 0x830 wifi_pll_config_9 Wireless Fidelity Phase-Locked Loop configuration 9 0x834 wifi_pll_config_10 Wireless Fidelity Phase-Locked Loop configuration 10 0x838 wifi_pll_config_11 Wireless Fidelity Phase-Locked Loop configuration 11 0x83C wifi_pll_config_12 Wireless Fidelity Phase-Locked Loop configuration 12 0x840 wifi_pll_config_13 Wireless Fidelity Phase-Locked Loop configuration 13 0x844 wifi_pll_config_14 Wireless Fidelity Phase-Locked Loop configuration 14 0x848 ldo18 1.8-V Low Dropout Linear Regulator configuration 0x884 35 0x04 gpio_config[%s] Generic Purpose Input/Output config 0x8C4 pin_mode Pin input/output mode switch 30 31 PinMode output_value Output by `output_value` field 0 set_clear Output set by `output_set` and `output_clear` fields 1 dma_output_value Source from GPIO DMA, output by `output_value` 2 dma_set_clear Source from GPIO DMA, set by `output_set` and `output_clear` 3 input_value Input value read-only 28 28 output_clear Clear output value to 0\n\n When sets and clears at the same, only set will take effect. write-only 26 26 output_set Set output value to 1\n\n When sets and clears at the same, only set will take effect. write-only 25 25 output_value Output value 24 24 interrupt_mask Pin interrupt mask 22 22 interrupt_state Pin interrupt state read-only 21 21 interrupt_clear Clear pin interrupt flag 20 20 interrupt_mode Select pin interrupt mode 16 19 InterruptMode sync_falling_edge Synchronous interrupt in falling edge 0 sync_rising_edge Synchronous interrupt in rising edge 1 sync_low_level Synchronous interrupt in low level 2 sync_high_level Synchronous interrupt in high level 3 sync_both_edges Synchronous interrupt in both rising and falling edges 4 async_falling_edge Asynchronous interrupt in falling edge 8 async_rising_edge Asynchronous interrupt in rising edge 9 async_low_level Asynchronous interrupt in low level 10 async_high_level Asynchronous interrupt in high level 11 alternate Pin alternate function switch 8 12 Alternate sdh Secure Digital host 0 spi0 Serial Peripheral Interface 0 1 flash Flash control 2 i2s0 Inter-IC Sound 0 3 pdm Pulse Density Modulation 4 i2c0 Inter-Integrated Circuit bus 0 5 i2c1 Inter-Integrated Circuit bus 1 6 uart0 Universal Asynchronous Receiver/Transmitter 0 7 emac Ethernet Media Access Control 8 cam ?? 9 analog ?? 10 gpio Generic Purpose Input/Output 11 sdio ?? 12 pwm0 Pulse-Width Modulation module 0 16 jtag ?? 17 uart1 Universal Asynchronous Receiver/Transmitter 1 18 pwm1 Pulse-Width Modulation 1 19 spi1 Serial Peripheral Interface 1 20 i2s1 Inter-IC Sound 1 21 dbi_b ?? 22 dbi_c ?? 23 qspi ?? 24 apwm Audio Pulse-Width Modulation 25 clock_out Clock output 31 output_function Enable output signal 6 6 pull_down Enable internal pull-down 5 5 pull_up Enable internal pull-up 4 4 drive Drive strength 2 3 schmitt Enable schmitt trigger 1 1 input_function Enable input signal 0 0 2 0x04 gpio_input[%s] Read value from Generic Purpose Input/Output pins 0xAC4 2 0x04 gpio_output[%s] Write value to Generic Purpose Input/Output pins 0xAE4 2 0x04 gpio_set[%s] Set pin output value to high 0xAEC 2 0x04 gpio_clear[%s] Set pin output value to low 0xAF4 GPIP Generic DAC and ADC interface control 0x20002000 0 0x1000 registers gpadc_config Generic Analog-to-Digital Converter register 0x00 gpadc_dma_read DMA data output of Generic Analog-to-Digital Converter 0x04 gpdac_config Generic Digital-to-Analog Converter register 0x40 gpdac_dma_config Digital-to-Analog Converter DMA configuration 0x44 gpdac_dma_write DMA data input of Generic Digital-to-Analog Converter 0x48 gpdac_fifo_state Transmit FIFO state of Generic Digital-to-Analog Converter 0x4C AGC Automatic Gain Control 0x20002C00 0 0x1000 registers todo ?? 0 SEC Digest, Encryption and Signing accelerator 0x20004000 0 0x1000 registers todo ?? 0 PERMIT Peripheral and memory access permission 0x20005000 0 0x1000 registers todo ?? 0 2 0x100 UART[%s] Universal Asynchronous Receiver Transmitter 0x2000A000 read-write 0 0x100 registers transmit_config Transmit configuration register 0x00 0x00008f00 0xffffffff transfer_length Length of words per UART transmit transfer\n\n This field is ignored when `freerun` mode is enabled. 16 31 break_bits Number of break bits for LIN protocol 13 15 stop_bits Number of stop bits 11 12 true zero_p_five 0.5 stop bits 0 one 1 stop bit 1 one_p_five 1.5 stop bits 2 two 2 stop bits 3 word_length Bit count for each transmit data word 8 10 true five Each word includes 5 bits 4 six Each word includes 6 bits 5 seven Each word includes 7 bits 6 eight Each word includes 8 bits 7 ir_inverse Inverse transmit signal output in IR mode 7 7 true inverse Inverse transmit input in IR mode 1 no_inverse Don't inverse transmit input in IR mode 0 ir_transmit Enable IR transmit mode 6 6 true enable Enable IR transmit mode 1 disable Disable IR transmit mode 0 parity_mode Select transmit parity mode if enabled 5 5 true odd Odd parity if `parity_enable` is set 1 even Even parity if `parity_enable` is set 0 parity_enable Enable transmit parity check 4 4 true enable Enable transmit parity check 1 disable Disable transmit parity check 0 lin_transmit Local Interconnect Network protocol enable 3 3 true enable Enable Local Interconnect Network protocol 1 disable Disable Local Interconnect Network protocol 0 freerun Enable freerun mode 2 2 true enable Enable freerun mode 1 disable Disable freerun mode 0 cts Enable Clear-to-Send flow control signal 1 1 true enable Enable Clear-to-Send flow control signal 1 disable Disable Clear-to-Send flow control signal 0 function Enable transmit function 0 0 true enable Enable UART receive function signal 1 disable Disable UART receive function signal 0 receive_config Receive configuration register 0x04 0x00000700 0xffffffff transfer_length Length of words per UART receive transfer 16 31 deglitch_cycle De-glitch function cycle count 12 15 deglitch_enable Enable receive de-glitch function 11 11 true enable Enable de-glitch function upon receive 1 disable Disable de-glitch function upon receive 0 word_length Bit count for each receive data word 8 10 true five Each word includes 5 bits 4 six Each word includes 6 bits 5 seven Each word includes 7 bits 6 eight Each word includes 8 bits 7 ir_inverse Inverse receive signal output in IR mode 7 7 true inverse Inverse receive input in IR mode 1 no_inverse Don't inverse receive input in IR mode 0 ir_receive Enable IR receive mode 6 6 true enable Enable IR receive mode 1 disable Disable IR receive mode 0 parity_mode Select receive parity mode if enabled 5 5 true odd Odd parity if `parity_enable` is set 1 even Even parity if `parity_enable` is set 0 parity_enable Enable receive parity check 4 4 true enable Enable receive parity check 1 disable Disable receive parity check 0 lin_receive Local Interconnect Network protocol enable 3 3 true enable Enable Local Interconnect Network protocol 1 disable Disable Local Interconnect Network protocol 0 auto_baudrate Enable receive auto baudrate detection 1 1 true enable Enable auto baudrate upon receive 1 disable Disable auto baudrate upon receive 0 function Enable receive function 0 0 true enable Enable UART receive function signal 1 disable Disable UART receive function signal 0 bit_period Bit period control register 0x08 0x00ff00ff 0xffffffff receive Period of each receive bit\n\n Add 1 to this value and divide by clock to get receive baudrate. 16 31 transmit Period of each transmit bit\n\n Add 1 to this value and divide by clock to get transmit baudrate. 0 15 data_config Data configuration register 0x0C 0x00000000 0xffffffff true bit_order Enable bit inverse in each data word 0 0 inverse Each byte is sent out MSB-first 1 no_inverse Each byte is sent out LSB-first 0 transmit_position IR-mode transmit position control 0x10 0x009f0070 0xffffffff stop Stop position of transmit IR pulse 16 31 start Start position of transmit IR pulse 0 15 receive_position IR-mode receive position control 0x14 0x0000006f 0xffffffff start Start position of received pulse recovered from IR signal 0 15 receive_timeout Receive Time-Out interrupt control 0x18 0x0000000f 0xffffffff value Timeout interrupt triggering value by bits received 0 7 signal_override Manual override of flow control signal 0x1C 0x00000000 0xffffffff true rts_value Value to override Request-to-Send signal if override is enabled 3 3 SignalAssert high Assert this signal 1 low Deassert this signal 0 rts_signal Enable manual override of Request-to-Send flow control signal 2 2 OverrideEnable enable Enable manual override of this signal 1 disable Disable manual override of this signal 0 transmit_value Value to override transmit signal if override is enabled 1 1 transmit_signal Enable manual override of transmit signal 0 0 interrupt_state Interrupt state register 0x20 0x00000004 0xffffffff read-only true auto_baudrate_five_five Receive auto baudrate detection finished using 0x55 occurred 11 11 InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 auto_baudrate_start_bit Receive auto baudrate detection finished using start bit occurred 10 10 receive_byte_count Receive byte count reached occurred 9 9 receive_sync_error Receive LIN mode synchronization field error occurred 8 8 receive_fifo_error Receive FIFO overflow or underflow occurred 7 7 transmit_fifo_error Transmit FIFO overflow or underflow occurred 6 6 receive_parity Receive parity check failure occurred 5 5 receive_timeout Receive timed-out interrupt occurred 4 4 receive_fifo_ready Receive FIFO ready signal raised 3 3 transmit_fifo_ready Transmit FIFO ready signal raised 2 2 receive_transfer Receive transfer finish signal raised 1 1 transmit_transfer Transmit transfer finish signal raised 0 0 interrupt_mask Interrupt mask register 0x24 0x00000fff 0xffffffff true auto_baudrate_five_five Receive auto baudrate detection finished using 0x55 occurred 11 11 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 auto_baudrate_start_bit Receive auto baudrate detection finished using start bit interrupt mask 10 10 receive_byte_count Receive byte count reached interrupt mask 9 9 receive_sync_error Receive LIN mode synchronization field error interrupt mask 8 8 receive_fifo_error Receive FIFO overflow or underflow interrupt mask 7 7 transmit_fifo_error Transmit FIFO overflow or underflow interrupt mask 6 6 receive_parity Receive parity check failure interrupt mask 5 5 receive_timeout Receive timed-out interrupt mask 4 4 receive_fifo_ready Receive FIFO ready signal interrupt mask 3 3 transmit_fifo_ready Transmit FIFO ready signal interrupt mask 2 2 receive_transfer Receive transfer finish signal interrupt mask 1 1 transmit_transfer Transmit transfer finish signal interrupt mask 0 0 interrupt_clear Clear interrupt register 0x28 0x00000000 0xffffffff write-only true auto_baudrate_five_five Write 1 to clear receive auto baudrate detection finished using 0x55 11 11 InterruptClear clear Write 1 to clear interrupt state 0x1 auto_baudrate_start_bit Write 1 to clear receive auto baudrate detection finished using start bit 10 10 receive_byte_count Write 1 to clear receive byte count reached 9 9 receive_sync_error Write 1 to clear receive LIN mode synchronization field error 8 8 receive_parity Write 1 to clear receive parity check failure 5 5 receive_timeout Write 1 to clear receive timed-out 4 4 receive_transfer Write 1 to clear receive transfer finish signal 1 1 transmit_transfer Write 1 to clear transmit transfer finish signal 0 0 interrupt_enable Interrupt enable register 0x2C 0x000000ff 0xffffffff true auto_baudrate_five_five Receive auto baudrate detection finished using 0x55 interrupt enable 11 11 InterruptEnable enable Enable interrupt 1 disable Disable interrupt 0 auto_baudrate_start_bit Receive auto baudrate detection finished using start bit interrupt enable 10 10 receive_byte_count Receive byte count reached interrupt enable 9 9 receive_sync_error Receive LIN mode synchronization field error interrupt enable 8 8 receive_fifo_error Receive FIFO overflow or underflow interrupt enable 7 7 transmit_fifo_error Transmit FIFO overflow or underflow interrupt enable 6 6 receive_parity Receive parity check failure interrupt enable 5 5 receive_timeout Receive timed-out interrupt enable 4 4 receive_fifo_ready Receive FIFO ready signal interrupt enable 3 3 transmit_fifo_ready Transmit FIFO ready signal interrupt enable 2 2 receive_transfer Receive transfer signal interrupt enable 1 1 transmit_transfer Transmit transfer signal interrupt enable 0 0 bus_state Bus state register 0x30 0x00000000 0xffffffff read-only receive_busy Indicates that UART receive bus is busy 1 1 BusBusy busy Bus is busy 1 idle Bus is not busy 0 transmit_busy Indicates that UART transmit bus is busy 0 0 auto_baudrate Auto baudrate detection register 0x34 0x00000000 0xffffffff read-only by_five_five Bit period of auto baudrate detection using codeword 0x55 16 31 by_start_bit Bit period of auto baudrate detection using start bit 0 15 pulse_tolerance Pulse width tolerance for auto baudrate 0x48 0x00000003 0xffffffff true by_five_five Pulse width tolerance of auto baudrate detection using codeword 0x55 0 7 rs485_transmit RS-485 mode transmit configuration 0x54 0x00000002 0xffffffff polarity RS-485 pin polarity of Driver Enable (DE) pin 1 1 Polarity active_high Driver Enable (DE) pin is active high 1 active_low Driver Enable (DE) pin is active low 0 function RS-485 transceiver mode enable 0 0 enable Enable RS-485 transceiver mode\n\n The peripheral is connected to RS-485 transceiver, and RTS signal output becomes Driver Enable (DE) signal. 1 disable Disable RS-485 transceiver mode\n\n The peripheral operates as normal UART. 0 fifo_config_0 FIFO configuration register 0 0x80 0x00000000 0xffffffff true receive_underflow Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`. 7 7 read-only HasUnderflow not_underflow No FIFO buffer underflow 0 underflow Has FIFO buffer underflow 1 receive_overflow Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`. 6 6 read-only HasOverflow not_overflow No FIFO buffer overflow 0 overflow Has FIFO buffer overflow 1 transmit_underflow Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`. 5 5 read-only transmit_overflow Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`. 4 4 read-only receive_clear Clears receive FIFO overflow and underflow flags 3 3 write-only FlagClear clear Write 1 to clear fifo flags 0x1 transmit_clear Clears transmit FIFO overflow and underflow flags 2 2 write-only receive_dma Enable signal of receive DMA interface 1 1 DmaEnable enable Enable DMA interface 0x1 disable Disable DMA interface 0x0 transmit_dma Enable signal of transmit DMA interface 0 0 fifo_config_1 FIFO configuration register 1 0x84 0x00000020 0xffffffff receive_threshold Receive FIFO threshold\n\n DMA request will not be asserted if `receive_available` is less than this value 24 28 transmit_threshold Transmit FIFO threshold\n\n DMA request will not be asserted if `transmit_available` is less than this value 16 20 receive_count Count of available data in receive FIFO 8 13 read-only transmit_count Count of available data in transmit FIFO 0 5 read-only data_write FIFO write data register 0x88 0x00000000 0xffffffff write-only value Write data to FIFO 0 7 data_read FIFO read data register 0x8C 0x00000000 0xffffffff read-only value Read data from FIFO 0 7 1 0x100 SPI[%s] Serial Peripheral Interface 0x2000A200 0 0x100 registers config Function configuration register 0x00 interrupt_state Interrupt enables, masks and states 0x04 bus_busy Bus busy state indicator 0x08 period_control Duration of control signals 0x10 period_interval Interval bitween frames 0x14 ignore_index Receive ignore index configuration 0x18 timeout Slave mode transmit timeout values 0x1c fifo_config_0 FIFO configuration register 0 0x80 fifo_config_1 FIFO configuration register 1 0x84 data_write FIFO write data register 0x88 data_read FIFO read data register 0x8C 2 0x600 I2C[%s] Inter-Integrated Circuit bus 0x2000A300 0 0x100 registers config Function configuration register 0x00 0x0000000a 0xffffffff deglitch_cycle De-glitch function cycle count 28 31 packet_length Byte count for each packet 16 23 slave_address I2C transaction slave address 8 14 sub_address_length Byte count for I2C sub-address 5 6 true one Sub-addresses include 1 byte 0 two Sub-addresses include 2 bytes 1 three Sub-addresses include 3 bytes 2 four Sub-addresses include 4 bytes 3 sub_address_enable Enable sub-address fields 4 4 true enable Enable sub-address fields 1 disable Disable sub-address fields 0 clock_synchronize Enable I2C clock synchronization\n\n Enable this bit to support multi-master and clock-stretching. It should not be turned-off normally. 3 3 true enable Enable clock synchronization 1 disable Disable clock synchronization 0 deglitch_enable Enable de-glitch function on all input pins 2 2 true enable Enable de-glitch function on inputs 1 disable Disable de-glitch function on inputs 0 transfer_direction Packet transfer direction 1 1 true write Write from master side 0 read Read from master side 1 master_enable Enable signal of I2C master function\n\n Asserting this bit will trigger the transaction, and should be de-asserted after finish. 0 0 true enable Enable I2C master function 1 disable Disable I2C master function 0 interrupt Interrupt enables, states and masks 0x04 0x3f003f00 0xffffffff true fifo_error_enable Transmit or receive FIFO error interrupt enable 29 29 InterruptEnable enable Enable interrupt 1 disable Disable interrupt 0 arbitrate_lost_enable Arbitration lost interrupt enable 28 28 not_acknowledged_enable Not-acknowledged response interrupt enable 27 27 receive_fifo_ready_enable Receive FIFO ready interrupt enable 26 26 transmit_fifo_ready_enable Transmit FIFO ready interrupt enable 25 25 transfer_end_enable Transfer ended interrupt enable 24 24 arbitrate_lost_clear Write 1 to clear arbitration lost 20 20 write-only InterruptClear clear Write 1 to clear interrupt state 0x1 not_acknowledged_clear Write 1 to clear not-acknowledged response 19 19 write-only transfer_end_clear Write 1 to clear transfer ended 16 16 write-only fifo_error_mask Transmit or receive FIFO error interrupt mask 13 13 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 arbitrate_lost_mask Arbitration lost interrupt mask 12 12 not_acknowledged_mask Not-acknowledged response interrupt mask 11 11 receive_fifo_ready_mask Receive FIFO ready interrupt mask 10 10 transmit_fifo_ready_mask Transmit FIFO ready interrupt mask 9 9 transfer_end_mask Transfer ended interrupt mask 8 8 fifo_error_state Transmit or receive FIFO error interrupt state\n\n Auto cleared when FIFO overflow or underflow error flag is cleared. 5 5 read-only InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 arbitrate_lost_state Arbitration lost interrupt state 4 4 read-only not_acknowledged_state Not-acknowledged response interrupt state 3 3 read-only receive_fifo_ready_state Receive FIFO ready interrupt state\n\n Auto cleared when data is popped from receive FIFO. 2 2 read-only transmit_fifo_ready_state Transmit FIFO ready interrupt state\n\n Auto cleared when data is pushed into transmit FIFO. 1 1 read-only transfer_end_state Transfer ended interrupt state 0 0 read-only sub_address Register address of slave device 0x08 0x00000000 0xffffffff 4 8 byte[%s] I2C sub-address byte %s 0 7 read-write bus_busy Bus busy state indicator 0x0C 0x00000000 0xffffffff true force_clear Force clear I2C bus busy state\n\n Not for normal use; only use when I2C bus hangs 1 1 write-only clear Write 1 to force clear busy flag 0x1 busy Indicator to I2C bus busy signal 0 0 read-only busy Bus is busy 1 idle Bus is not busy 0 period_start Duration of start phase 0x10 0x0f0f0f0f 0xffffffff 4 8 phase[%s] Length of start condition phase %s 0 7 read-write period_stop Duration of stop phase 0x14 0x0f0f0f0f 0xffffffff 4 8 phase[%s] Length of stop condition phase %s 0 7 read-write period_data Duration of data phase 0x18 0x0f0f0f0f 0xffffffff 4 8 phase[%s] Length of data condition phase %s 0 7 read-write fifo_config_0 FIFO configuration register 0 0x80 0x00000000 0xffffffff true receive_underflow Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`. 7 7 read-only HasUnderflow not_underflow No FIFO buffer underflow 0 underflow Has FIFO buffer underflow 1 receive_overflow Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`. 6 6 read-only HasOverflow not_overflow No FIFO buffer overflow 0 overflow Has FIFO buffer overflow 1 transmit_underflow Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`. 5 5 read-only transmit_overflow Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`. 4 4 read-only receive_clear Clears receive FIFO overflow and underflow flags 3 3 write-only FlagClear clear Write 1 to clear fifo flags 0x1 transmit_clear Clears transmit FIFO overflow and underflow flags 2 2 write-only receive_dma Enable signal of receive DMA interface 1 1 DmaEnable enable Enable DMA interface 0x1 disable Disable DMA interface 0x0 transmit_dma Enable signal of transmit DMA interface 0 0 fifo_config_1 FIFO configuration register 1 0x84 0x00000002 0xffffffff receive_threshold Receive FIFO threshold\n\n DMA request will not be asserted if `receive_available` is less than this value 24 24 transmit_threshold Transmit FIFO threshold\n\n DMA request will not be asserted if `transmit_available` is less than this value 16 16 receive_count Count of available data in receive FIFO 8 9 read-only transmit_count Count of available data in transmit FIFO 0 1 read-only data_write FIFO write data register 0x88 0x00000000 0xffffffff write-only value Write data to FIFO 0 7 data_read FIFO read data register 0x8C 0x00000000 0xffffffff read-only value Read data from FIFO 0 7 PWM Pulse-Width Modulation module 0x2000A400 0 0x100 registers interrupt_config Interrupt state and clear register 0x00 2 0x40 group[%s] Pulse-Width Modulation channel group 0x40 config Peripheral group configuration 0x00 clock_select Select group clock source 30 31 true ClockSource xtal External crystal as clock source 0 bclk Bus clock as clock source 1 f32k 32-kHz clock source 2 stop_state Is this peripheral stopped? 29 29 stop_mode Mode to stop this peripheral 28 28 stop_function Enable or disable stop function 27 27 external_polarity Polarity for external pin break function 26 26 external_break Enable external pin signal break 25 25 software_break Enable software signal break 24 24 adc_trigger_source Select channel in Analog-to-Digital Converter to interact with this peripheral\n\n **This field only works with PWM0.** PWM1 does not have this feature. 20 23 stop_on_repeat Enable or disable stop on one repeat cycle completed 19 19 channel Channel configuration register 0x04 4 4 positive_signal[%s] Enable or disable positive signal for channel 0 0 4 4 positive_idle[%s] Idle state of positive signal 1 1 4 4 negative_signal[%s] Enable or disable negative signal for channel 2 2 4 4 negative_idle[%s] Idle state of negative signal 3 3 4 2 positive_polarity[%s] Polarity of positive signal 16 16 4 2 negative_polarity[%s] Polarity of negative signal 17 17 4 2 positive_break[%s] Break state on positive signal of this channel 24 24 4 2 negative_break[%s] Break state on negative signal of this channel 25 25 period Pulse clock period register 0x08 interrupt_cycles If internal counter reaches this cycle count, it interrupts 0 15 repeat_cycles How many clock cycles a Pulse-Width Modulation cycle includes 16 31 dead_time Dead time for each channel 0x0C 4 8 channel[%s] Dead time for each channel in cycles 0 7 4 0x04 threshold[%s] Channel internal counter threshold 0x10 high Highest value for internal counter that sets positive signal to 1 and negative to 0 16 31 low Lowest value for internal counter that sets positive signal to 1 and negative to 0 0 15 interrupt_state Interrupt state register 0x20 0x00000000 0xffffffff read-only true 4 2 threshold_low[%s] Intenal counter for channel have exceeded low threshold 0 0 InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 4 2 threshold_high[%s] Intenal counter for channel have exceeded high threshold 1 1 interrupt_period Intenal counter for channel have exceeded interrupt cycle threshold 8 8 external_break External break signal occurred 9 9 repeat Peripheral group have completed one repeat cycle 10 10 interrupt_mask Interrupt mask register 0x24 0x0000007f 0xffffffff true 4 2 threshold_low[%s] Intenal counter for channel have exceeded low threshold 0 0 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 4 2 threshold_high[%s] Intenal counter for channel have exceeded high threshold 1 1 interrupt_period Intenal counter for channel have exceeded interrupt cycle threshold 8 8 external_break External break signal occurred 9 9 repeat Peripheral group have completed one repeat cycle 10 10 interrupt_clear Clear interrupt register 0x28 0x00000000 0xffffffff write-only true 4 2 threshold_low[%s] Intenal counter for channel have exceeded low threshold 0 0 InterruptClear clear Write 1 to clear interrupt state 0x1 4 2 threshold_high[%s] Intenal counter for channel have exceeded high threshold 1 1 interrupt_period Intenal counter for channel have exceeded interrupt cycle threshold 8 8 external_break External break signal occurred 9 9 repeat Peripheral group have completed one repeat cycle 10 10 interrupt_enable Interrupt enable register 0x2C 0x0000007f 0xffffffff true 4 2 threshold_low[%s] Intenal counter for channel have exceeded low threshold 0 0 InterruptEnable enable Enable interrupt 1 disable Disable interrupt 0 4 2 threshold_high[%s] Intenal counter for channel have exceeded high threshold 1 1 interrupt_period Intenal counter for channel have exceeded interrupt cycle threshold 8 8 external_break External break signal occurred 9 9 repeat Peripheral group have completed one repeat cycle 10 10 TIMER Timer control 0x2000A500 0 0x1000 registers todo ?? 0 IR Infrared receiver module 0x2000A600 0 0x100 registers transmit_config ?? 0x00 transmit_interrupt ?? 0x04 2 0x04 transmit_data[%s] ?? 0x08 transmit_width ?? 0x10 receive_config ?? 0x80 receive_interrupt ?? 0x84 receive_width ?? 0x88 receive_bit_count ?? 0x90 2 0x04 receive_data[%s] ?? 0x94 CRC Checksum peripheral 0x2000A700 0 0x100 registers config Configuration register 0x0 clear Write 1 to clear internal checksum states 0 0 write-only true Clear clear Write 1 to clear internal states 0x1 endian Sets endian of input data 1 1 true Endian little Little endian 0 big Big endian 1 input Data input register 0x4 write-only data Write data value into checksum calculator 0 31 output Checksum output register 0x8 read-only checksum Read checksum from peripheral 0 15 DBI MIPI Display Bus Interface 0x2000A800 0 0x100 registers todo ?? 0 ISO11898 ISO 11898 communication protocol 0x2000AA00 0 0x100 registers todo ?? 0 I2S Inter-IC Sound controller 0x2000AB00 0 0x100 registers config Function configuration register 0x00 interrupt_state Interrupt enables, masks and states 0x04 base_clock Base clock divider 0x10 0x00010001 0xffffffff divide_high Higher half of base clock dividing factor 16 27 read-write divide_low Lower half of base clock dividing factor 0 11 read-write fifo_config_0 FIFO configuration register 0 0x80 0x00000000 0xffffffff left_justified 10 10 swap_left_right 9 9 merge_left_right 8 8 receive_underflow Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`. 7 7 read-only true HasUnderflow not_underflow No FIFO buffer underflow 0 underflow Has FIFO buffer underflow 1 receive_overflow Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`. 6 6 read-only true HasOverflow not_overflow No FIFO buffer overflow 0 overflow Has FIFO buffer overflow 1 transmit_underflow Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`. 5 5 read-only true transmit_overflow Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`. 4 4 read-only true receive_clear Clears receive FIFO overflow and underflow flags 3 3 write-only true FlagClear clear Write 1 to clear fifo flags 0x1 transmit_clear Clears transmit FIFO overflow and underflow flags 2 2 write-only true receive_dma Enable signal of receive DMA interface 1 1 true DmaEnable enable Enable DMA interface 0x1 disable Disable DMA interface 0x0 transmit_dma Enable signal of transmit DMA interface 0 0 true fifo_config_1 FIFO configuration register 1 0x84 0x00000010 0xffffffff receive_threshold Receive FIFO threshold\n\n DMA request will not be asserted if `receive_available` is less than this value 24 27 transmit_threshold Transmit FIFO threshold\n\n DMA request will not be asserted if `transmit_available` is less than this value 16 19 receive_count Count of available data in receive FIFO 8 12 read-only transmit_count Count of available data in transmit FIFO 0 4 read-only data_write FIFO write data register 0x88 0x00000000 0xffffffff write-only value Write data to FIFO 0 7 data_read FIFO read data register 0x8C 0x00000000 0xffffffff read-only value Read data from FIFO 0 7 AUADC Analog-to-Digital or Pulse-Density audio input 0x2000AC00 0 0x100 registers clock Peripheral clock control register 0x00 interface_0 Interface control register 0 0x04 finite_impulse Finite Impulse Response control 0x08 high_pass High-Pass Filter control register 0x0C interface_1 Interface control register 1 0x10 pulse_width Pulse-Width Modulator control 0x1C volume Volume control register 0x38 analog_0 Analog signal configuration 0 0x60 analog_1 Analog signal configuration 1 0x64 command Analog-to-Digital Converter commands 0x68 sample_data Analog-to-Digital Converter sample output 0x6C fifo_control Controls audio input FIFO 0x80 fifo_state Gets states of audio input FIFO 0x84 fifo_data Reads data from audio input FIFO 0x88 FLASH Quad Serial Flash control 0x2000B000 0 0x100 registers todo ?? 0 DMA Direct Memory Access module 0x2000C000 0 0x1000 registers interrupt_state ?? 0x00 terminate_state ?? 0x04 terminate_clear ?? 0x08 error_state ?? 0x0C error_clear ?? 0x10 terminate_state_raw ?? 0x14 error_state_raw ?? 0x18 channel_state ?? 0x1C burst_request ?? 0x20 single_request ?? 0x24 last_burst_request ?? 0x28 last_single_request ?? 0x2C config ?? 0x30 function Enable or disable DMA peripheral 0 0 synchronize ?? 0x34 4 0x100 channel[%s] Direct Memory Access channel 0x100 source Source address 0x00 destination Destination address 0x04 linked_list Linked list buffer base address 0x08 base_address Base address of first linked list item, must be aligned to 4 bytes 0 31 control Control register 0x0C config Configuration register 0x10 linked_list_counter ?? 20 29 halt ?? 17 17 active ?? read-only 16 16 lock ?? 16 16 terminate_mask Mask terminal count interrupt 15 15 error_mask Mask error interrupt 14 14 flow_control Set data direction for this channel 11 13 destination_peripheral Set destination peripheral for this DMA channel 6 10 source_peripheral Set source peripheral for this DMA channel 1 5 function Enable or disable DMA channel 0 0 SDU Secure Digital User interface 0x2000D000 0 0x100 registers todo ?? 0 PDS Power-Down Sleep control 0x2000E000 0 0x1000 registers touch_config ?? 0xA00 touch_channel ?? 0xA04 touch_process ?? 0xA08 touch_sleep ?? 0xA0C touch_delay ?? 0xA10 6 0x04 touch_force[%s] ?? 0xA14 3 0x04 touch_voltage[%s] ?? 0xA2C 12 0x04 touch_raw[%s] ?? 0xA38 touch_interrupt_0 ?? 0xACC touch_interrupt_1 ?? 0xAD0 HBN Hibernate (Deep sleep) control 0x2000F000 0 0x800 registers control Miscellaneous control register 0x00 time_lo Low bits of hibernate time 0x04 time_hi High bits of hibernate time 0x08 rtc_time_lo Low bits of Real-Time Clock time 0x0C rtc_time_hi High bits of Real-Time Clock time 0x10 interrupt_mode Hibernate interrupt contol 0x14 interrupt_state Hibernate interrupt state 0x18 interrupt_clear Clear hibernate interrupt 0x1C global Global hibernate configuration 0x30 sram Static Random-Access Memory hibernate control 0x34 rc32k 32-kHz internal RC oscillator control 0x200 xtal32k External crystal oscillator control 0x204 rtc_control_0 Real-Time Clock control and reset register 0 0x208 rtc_control_1 Real-Time Clock control and reset register 1 0x20C PSRAM Pseudo Static Random Access Memory control 0x20052000 0 0x100 registers todo ?? 0 AUDAC Pulse-Width or Digital-to-Analog audio output 0x20055000 0 0x1000 registers clock Clock control register 0x00 state Peripheral state register 0x04 volume_0 Volume control register 0 0x08 volume_1 Volume control register 1 0x0C zero_signal Zero signal detection 0x10 config Delta-Sigma and mixer control 0x14 fifo_control Controls audio output FIFO 0x8C fifo_state Gets states of audio output FIFO 0x90 fifo_data Writes data into audio output FIFO 0x94 EFUSE eFuse memory control 0x20056000 0 0x1000 registers todo ?? 0 1 0x1000 DVP[%s] Digital Video Port control 0x20057000 0 0x1000 registers todo ?? 0 MJPEG Motion JPEG encoder 0x20059000 0 0x1000 registers todo ?? 0 SDH Secure Digital host control 0x20060000 0 0x1000 registers todo ?? 0 EMAC Ethernet Media Access Control 0x20070000 0 0x1000 registers mode Interface enables and configurations 0x00 interrupt_source Interrupt source register 0x04 0x00000000 0xffffffff read-write oneToClear control_receive Control frame received interrupt state 6 6 InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 control_transmit Control frame transmitted interrupt state 5 5 busy Lack of buffer interrupt state 4 4 receive_error Receive error interrupt state 3 3 frame_received Frame received interrupt state 2 2 transmit_error Transmit error interrupt state 1 1 buffer_transmitted Buffer transmitted interrupt state 0 0 interrupt_mask Interrupt mask register 0x08 0x00000000 0xffffffff read-write true control_receive Control frame received interrupt mask 6 6 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 control_transmit Control frame transmitted interrupt mask 5 5 busy Lack of buffer interrupt mask 4 4 receive_error Receive error interrupt mask 3 3 frame_received Frame received interrupt mask 2 2 transmit_error Transmit error interrupt mask 1 1 buffer_transmitted Buffer transmitted interrupt mask 0 0 backed_gap Back-to-back inter-packet gap register 0x0C non_backed_gap_1 Non back-to-back inter-packet gap register 1 0x10 non_backed_gap_2 Non back-to-back inter-packet gap register 2 0x14 frame_length Minimum and maximum ethernet frame length 0x18 collision Collision time window and maximum retries 0x1C transmit_buffer Transmit buffer descriptor 0x20 flow_control Control frame function register 0x24 mii_mode MII clock divider and premable enable 0x28 mii_command MII control data, read and scan state 0x2C mii_address Physical layer bus address 0x30 control_write Write data to MII physcial layer 0x34 control_read Read data from MII physcial layer 0x38 mii_state MII bus and link layer state 0x3C 2 0x04 mac_address[%s] Media Access Control address 0x40 2 0x04 hash[%s] Hash register 0x48 transmit_control Transmit control register 0x50 USB Universal Serial Bus host 0x20072000 0 0x1000 registers capability Host Controller Capability Registers 0x000 operation Host Controller Operational Registers 0x010