Bouffalo Lab bouffalolab BL702 WiFi BT 1.0 BL702 BLE + Zigbee combo chipset 8 32 0x20 0x00000000 0xFFFFFFFF glb Global Register glb 0x40000000 0x20 read-write 0x0 0x1000 registers clk_cfg0 clk_cfg0. 0x0 glb_id 28 31 chip_rdy 27 27 fclk_sw_state 24 26 reg_bclk_div 16 23 reg_hclk_div 8 15 hbn_root_clk_sel 6 7 reg_pll_sel 4 5 reg_bclk_en 3 3 reg_hclk_en 2 2 reg_fclk_en 1 1 reg_pll_en 0 0 clk_cfg1 clk_cfg1. 0x4 reg_cam_ref_clk_div 30 31 reg_cam_ref_clk_src_sel 29 29 reg_cam_ref_clk_en 28 28 m154_zbEn 25 25 ble_en 24 24 ble_clk_sel 16 21 reg_i2s_0_ref_clk_oe 14 14 reg_i2s0_clk_en 13 13 reg_i2s_clk_sel 12 12 dll_48m_div_en 9 9 usb_clk_en 8 8 qdec_clk_sel 7 7 qdec_clk_div 0 4 clk_cfg2 clk_cfg2. 0x8 dma_clk_en 24 31 ir_clk_en 23 23 ir_clk_div 16 21 sf_clk_sel2 14 15 sf_clk_sel 12 13 sf_clk_en 11 11 sf_clk_div 8 10 hbn_uart_clk_sel 7 7 uart_clk_en 4 4 uart_clk_div 0 2 clk_cfg3 clk_cfg3. 0xC chip_clk_out_1_sel 30 31 chip_clk_out_0_sel 28 29 i2c_clk_en 24 24 i2c_clk_div 16 23 cfg_inv_eth_rx_clk 10 10 cfg_inv_rf_test_clk_o 9 9 spi_clk_en 8 8 cfg_inv_eth_tx_clk 7 7 cfg_inv_eth_ref_clk_o 6 6 cfg_sel_eth_ref_clk_o 5 5 spi_clk_div 0 4 swrst_cfg0 swrst_cfg0. 0x10 swrst_s30 8 8 swrst_s20 4 4 swrst_s01 1 1 swrst_s00 0 0 swrst_cfg1 swrst_cfg1. 0x14 swrst_s1ae 30 30 swrst_s1ad 29 29 swrst_s1ac 28 28 swrst_s1ab 27 27 swrst_s1aa 26 26 swrst_s1a9 25 25 swrst_s1a8 24 24 swrst_s1a7 23 23 swrst_s1a6 22 22 swrst_s1a5 21 21 swrst_s1a4 20 20 swrst_s1a3 19 19 swrst_s1a2 18 18 swrst_s1a1 17 17 swrst_s1a0 16 16 swrst_s1f 15 15 swrst_s1e 14 14 swrst_s1d 13 13 swrst_s1c 12 12 swrst_s1b 11 11 swrst_s1a 10 10 swrst_s19 9 9 swrst_s18 8 8 swrst_s17 7 7 swrst_s16 6 6 swrst_s15 5 5 swrst_s14 4 4 swrst_s13 3 3 swrst_s12 2 2 swrst_s11 1 1 swrst_s10 0 0 swrst_cfg2 swrst_cfg2. 0x18 pka_clk_sel 24 24 reg_ctrl_reset_dummy 4 7 reg_ctrl_sys_reset 2 2 reg_ctrl_cpu_reset 1 1 reg_ctrl_pwron_rst 0 0 swrst_cfg3 swrst_cfg3. 0x1C cgen_cfg0 cgen_cfg0. 0x20 cgen_m 0 7 cgen_cfg1 cgen_cfg1. 0x24 GLB GLB 0 1 read-write MIX MIX 1 1 read-write GPIP gpip (gpadc, gpdac) clock ungate enable 2 1 read-write SEC_DBG sec_dbg clock ungate enable 3 1 read-write SEC sec_eng clock ungate enable 4 1 read-write TZ1 TZC clock ungate enable 5 1 read-write TZ2 TZC2 clock ungate enable 6 1 read-write EFUSE ef_ctrl clock ungate enable 7 1 read-write CCI CCI (efuse?) 8 1 read-write L1C L1C (efuse?) 9 1 read-write S1A_ALL S1A_ALL (efuse?) 10 1 read-write SFC sf_ctrl clock ungate enable 11 1 read-write DMA DMA clock ungate enable 12 1 read-write EMAC EMAC clock ungate enable 13 1 read-write PDS_HBN_AON_HBNRAM DS_HBN_AON_HBNRAM 14 1 read-write RSVD0F RSVD0F 15 1 read-write UART0 uart0 clock ungate enable 16 1 read-write UART1 uart1 clock ungate enable 17 1 read-write SPI spi clock ungate enable 18 1 read-write I2C i2c clock ungate enable 19 1 read-write PWM pwm clock ungate enable 20 1 read-write TMR timer clock ungate enable 21 1 read-write IRR ir_remote clock ungate enable 22 1 read-write CKS checksum clock ungate enable 23 1 read-write QDEC qdec0 clock ungate enable 24 1 read-write KYS KYS 25 1 read-write I2S i2s and qdec2 clock ungate enable 26 1 read-write RSVD1B RSVD1B 27 1 read-write USB usb clock ungate enable 28 1 read-write CAM CAM 29 1 read-write MJPEG MJPEG 30 1 read-write MAX MAX 31 1 read-write cgen_cfg2 cgen_cfg2. 0x28 cgen_s3 4 4 cgen_s2 0 0 cgen_cfg3 cgen_cfg3. 0x2C MBIST_CTL MBIST_CTL. 0x30 reg_mbist_rst_n 31 31 em_ram_mbist_mode 5 5 ocram_mbist_mode 4 4 tag_mbist_mode 3 3 hsram_cache_mbist_mode 2 2 hsram_mem_mbist_mode 1 1 irom_mbist_mode 0 0 MBIST_STAT MBIST_STAT. 0x34 em_ram_mbist_fail 21 21 ocram_mbist_fail 20 20 tag_mbist_fail 19 19 hsram_cache_mbist_fail 18 18 hsram_mem_mbist_fail 17 17 irom_mbist_fail 16 16 em_ram_mbist_done 5 5 ocram_mbist_done 4 4 tag_mbist_done 3 3 hsram_cache_mbist_done 2 2 hsram_mem_mbist_done 1 1 irom_mbist_done 0 0 bmx_cfg1 bmx_cfg1. 0x50 hbn_apb_cfg 24 31 pds_apb_cfg 16 23 hsel_option 12 15 bmx_gating_dis 10 10 bmx_busy_option_dis 9 9 bmx_err_en 8 8 bmx_arb_mode 4 5 bmx_timeout_en 0 3 bmx_cfg2 bmx_cfg2. 0x54 bmx_dbg_sel 28 31 reg_w_thre_l1c 10 11 reg_w_thre_bmx 8 9 bmx_err_tz 5 5 bmx_err_dec 4 4 bmx_err_addr_dis 0 0 bmx_err_addr bmx_err_addr. 0x58 bmx_err_addr 0 31 bmx_dbg_out bmx_dbg_out. 0x5C bmx_dbg_out 0 31 rsv0 rsv0. 0x60 rsvd_31_0 0 31 rsv1 rsv1. 0x64 rsvd_31_0 0 31 rsv2 rsv2. 0x68 rsvd_31_0 0 31 rsv3 rsv3. 0x6C rsvd_31_0 0 31 sram_ret sram_ret. 0x70 reg_sram_ret 0 31 sram_slp sram_slp. 0x74 reg_sram_slp 0 31 sram_parm sram_parm. 0x78 reg_sram_parm 0 31 seam_misc seam_misc. 0x7C em_sel 0 3 glb_parm glb_parm. 0x80 pin_sel_emac_cam 31 31 reg_ext_rst_smt 30 30 reg_kys_drv_val 29 29 uart_swap_set 24 27 p6_jtag_use_io_0_2_7 23 23 p5_dac_test_with_jtag 21 21 p4_adc_test_with_jtag 20 20 p3_cci_use_io_0_2_7 19 19 p2_dac_test_with_cci 18 18 p1_adc_test_with_cci 17 17 reg_cci_use_jtag_pin 16 16 reg_spi_0_swap 13 13 reg_spi_0_master_mode 12 12 cfg_flash_scenario 10 11 cfg_sflash2_swap_cs_io2 9 9 cfg_sflash2_swap_io0_io3 8 8 jtag_swap_set 0 7 PDM_CLK_CTRL PDM_CLK_CTRL. 0x84 reg_pdm0_clk_en 7 7 reg_pdm0_clk_div 0 5 GPIO_USE_PSRAM__IO GPIO_USE_PSRAM__IO. 0x88 cfg_gpio_use_psram_io 0 5 CPU_CLK_CFG CPU_CLK_CFG. 0x90 debug_ndreset_gate 20 20 cpu_rtc_sel 19 19 cpu_rtc_en 18 18 cpu_rtc_div 0 16 GPADC_32M_SRC_CTRL GPADC_32M_SRC_CTRL. 0xA4 gpadc_32m_div_en 8 8 gpadc_32m_clk_sel 7 7 gpadc_32m_clk_div 0 5 DIG32K_WAKEUP_CTRL DIG32K_WAKEUP_CTRL. 0xA8 reg_en_platform_wakeup 31 31 dig_clk_src_sel 28 29 dig_512k_comp 25 25 dig_512k_en 24 24 dig_512k_div 16 22 dig_32k_comp 13 13 dig_32k_en 12 12 dig_32k_div 0 10 WIFI_BT_COEX_CTRL WIFI_BT_COEX_CTRL. 0xAC en_gpio_bt_coex 12 12 coex_bt_bw 11 11 coex_bt_pti 7 10 coex_bt_channel 0 6 BZ_COEX_CTRL BZ_COEX_CTRL. 0xB0 coex_arb 28 31 ble_tx_abort_dis 27 27 ble_rx_abort_dis 26 26 m154_tx_abort_dis 25 25 m154_rx_abort_dis 24 24 coex_force_ch 16 22 coex_option 15 15 force_ble_win 14 14 force_m154_win 13 13 coex_pri 12 12 bz_abort_pol 11 11 bz_active_pol 10 10 bz_pri_pol 9 9 bz_pri_en 8 8 bz_pri_thr 4 7 m154_rx_ignore 3 3 ble_rx_ignore 2 2 wlan_en 1 1 coex_en 0 0 UART_SIG_SEL_0 UART_SIG_SEL_0. 0xC0 uart_sig_7_sel 28 31 uart_sig_6_sel 24 27 uart_sig_5_sel 20 23 uart_sig_4_sel 16 19 uart_sig_3_sel 12 15 uart_sig_2_sel 8 11 uart_sig_1_sel 4 7 uart_sig_0_sel 0 3 DBG_SEL_LL DBG_SEL_LL. 0xD0 reg_dbg_ll_ctrl 0 31 DBG_SEL_LH DBG_SEL_LH. 0xD4 reg_dbg_lh_ctrl 0 31 DBG_SEL_HL DBG_SEL_HL. 0xD8 reg_dbg_hl_ctrl 0 31 DBG_SEL_HH DBG_SEL_HH. 0xDC reg_dbg_hh_ctrl 0 31 debug debug. 0xE0 debug_i 1 31 debug_oe 0 0 GPIO_CFGCTL0 GPIO_CFGCTL0. 0x100 reg_gpio_1_func_sel 24 28 reg_gpio_1_pd 21 21 reg_gpio_1_pu 20 20 reg_gpio_1_drv 18 19 reg_gpio_1_smt 17 17 reg_gpio_1_ie 16 16 reg_gpio_0_func_sel 8 12 reg_gpio_0_pd 5 5 reg_gpio_0_pu 4 4 reg_gpio_0_drv 2 3 reg_gpio_0_smt 1 1 reg_gpio_0_ie 0 0 GPIO_CFGCTL1 GPIO_CFGCTL1. 0x104 reg_gpio_3_func_sel 24 28 reg_gpio_3_pd 21 21 reg_gpio_3_pu 20 20 reg_gpio_3_drv 18 19 reg_gpio_3_smt 17 17 reg_gpio_3_ie 16 16 reg_gpio_2_func_sel 8 12 reg_gpio_2_pd 5 5 reg_gpio_2_pu 4 4 reg_gpio_2_drv 2 3 reg_gpio_2_smt 1 1 reg_gpio_2_ie 0 0 GPIO_CFGCTL2 GPIO_CFGCTL2. 0x108 reg_gpio_5_func_sel 24 28 reg_gpio_5_pd 21 21 reg_gpio_5_pu 20 20 reg_gpio_5_drv 18 19 reg_gpio_5_smt 17 17 reg_gpio_5_ie 16 16 reg_gpio_4_func_sel 8 12 reg_gpio_4_pd 5 5 reg_gpio_4_pu 4 4 reg_gpio_4_drv 2 3 reg_gpio_4_smt 1 1 reg_gpio_4_ie 0 0 GPIO_CFGCTL3 GPIO_CFGCTL3. 0x10C reg_gpio_7_func_sel 24 28 reg_gpio_7_pd 21 21 reg_gpio_7_pu 20 20 reg_gpio_7_drv 18 19 reg_gpio_7_smt 17 17 reg_gpio_7_ie 16 16 reg_gpio_6_func_sel 8 12 reg_gpio_6_pd 5 5 reg_gpio_6_pu 4 4 reg_gpio_6_drv 2 3 reg_gpio_6_smt 1 1 reg_gpio_6_ie 0 0 GPIO_CFGCTL4 GPIO_CFGCTL4. 0x110 reg_gpio_9_func_sel 24 28 reg_gpio_9_pd 21 21 reg_gpio_9_pu 20 20 reg_gpio_9_drv 18 19 reg_gpio_9_smt 17 17 reg_gpio_9_ie 16 16 reg_gpio_8_func_sel 8 12 reg_gpio_8_pd 5 5 reg_gpio_8_pu 4 4 reg_gpio_8_drv 2 3 reg_gpio_8_smt 1 1 reg_gpio_8_ie 0 0 GPIO_CFGCTL5 GPIO_CFGCTL5. 0x114 reg_gpio_11_func_sel 24 28 reg_gpio_11_pd 21 21 reg_gpio_11_pu 20 20 reg_gpio_11_drv 18 19 reg_gpio_11_smt 17 17 reg_gpio_11_ie 16 16 reg_gpio_10_func_sel 8 12 reg_gpio_10_pd 5 5 reg_gpio_10_pu 4 4 reg_gpio_10_drv 2 3 reg_gpio_10_smt 1 1 reg_gpio_10_ie 0 0 GPIO_CFGCTL6 GPIO_CFGCTL6. 0x118 reg_gpio_13_func_sel 24 28 reg_gpio_13_pd 21 21 reg_gpio_13_pu 20 20 reg_gpio_13_drv 18 19 reg_gpio_13_smt 17 17 reg_gpio_13_ie 16 16 reg_gpio_12_func_sel 8 12 reg_gpio_12_pd 5 5 reg_gpio_12_pu 4 4 reg_gpio_12_drv 2 3 reg_gpio_12_smt 1 1 reg_gpio_12_ie 0 0 GPIO_CFGCTL7 GPIO_CFGCTL7. 0x11C reg_gpio_15_func_sel 24 28 reg_gpio_15_pd 21 21 reg_gpio_15_pu 20 20 reg_gpio_15_drv 18 19 reg_gpio_15_smt 17 17 reg_gpio_15_ie 16 16 reg_gpio_14_func_sel 8 12 reg_gpio_14_pd 5 5 reg_gpio_14_pu 4 4 reg_gpio_14_drv 2 3 reg_gpio_14_smt 1 1 reg_gpio_14_ie 0 0 GPIO_CFGCTL8 GPIO_CFGCTL8. 0x120 reg_gpio_17_func_sel 24 28 reg_gpio_17_pd 21 21 reg_gpio_17_pu 20 20 reg_gpio_17_drv 18 19 reg_gpio_17_smt 17 17 reg_gpio_17_ie 16 16 reg_gpio_16_func_sel 8 12 reg_gpio_16_pd 5 5 reg_gpio_16_pu 4 4 reg_gpio_16_drv 2 3 reg_gpio_16_smt 1 1 reg_gpio_16_ie 0 0 GPIO_CFGCTL9 GPIO_CFGCTL9. 0x124 reg_gpio_19_func_sel 24 28 reg_gpio_19_pd 21 21 reg_gpio_19_pu 20 20 reg_gpio_19_drv 18 19 reg_gpio_19_smt 17 17 reg_gpio_19_ie 16 16 reg_gpio_18_func_sel 8 12 reg_gpio_18_pd 5 5 reg_gpio_18_pu 4 4 reg_gpio_18_drv 2 3 reg_gpio_18_smt 1 1 reg_gpio_18_ie 0 0 GPIO_CFGCTL10 GPIO_CFGCTL10. 0x128 reg_gpio_21_func_sel 24 28 reg_gpio_21_pd 21 21 reg_gpio_21_pu 20 20 reg_gpio_21_drv 18 19 reg_gpio_21_smt 17 17 reg_gpio_21_ie 16 16 reg_gpio_20_func_sel 8 12 reg_gpio_20_pd 5 5 reg_gpio_20_pu 4 4 reg_gpio_20_drv 2 3 reg_gpio_20_smt 1 1 reg_gpio_20_ie 0 0 GPIO_CFGCTL11 GPIO_CFGCTL11. 0x12C reg_gpio_23_func_sel 24 28 reg_gpio_23_pd 21 21 reg_gpio_23_pu 20 20 reg_gpio_23_drv 18 19 reg_gpio_23_smt 17 17 reg_gpio_23_ie 16 16 reg_gpio_22_func_sel 8 12 reg_gpio_22_pd 5 5 reg_gpio_22_pu 4 4 reg_gpio_22_drv 2 3 reg_gpio_22_smt 1 1 reg_gpio_22_ie 0 0 GPIO_CFGCTL12 GPIO_CFGCTL12. 0x130 reg_gpio_25_func_sel 24 28 reg_gpio_25_pd 21 21 reg_gpio_25_pu 20 20 reg_gpio_25_drv 18 19 reg_gpio_25_smt 17 17 reg_gpio_25_ie 16 16 reg_gpio_24_func_sel 8 12 reg_gpio_24_pd 5 5 reg_gpio_24_pu 4 4 reg_gpio_24_drv 2 3 reg_gpio_24_smt 1 1 reg_gpio_24_ie 0 0 GPIO_CFGCTL13 GPIO_CFGCTL13. 0x134 reg_gpio_27_func_sel 24 28 reg_gpio_27_pd 21 21 reg_gpio_27_pu 20 20 reg_gpio_27_drv 18 19 reg_gpio_27_smt 17 17 reg_gpio_27_ie 16 16 reg_gpio_26_func_sel 8 12 reg_gpio_26_pd 5 5 reg_gpio_26_pu 4 4 reg_gpio_26_drv 2 3 reg_gpio_26_smt 1 1 reg_gpio_26_ie 0 0 GPIO_CFGCTL14 GPIO_CFGCTL14. 0x138 reg_gpio_29_func_sel 24 28 reg_gpio_29_pd 21 21 reg_gpio_29_pu 20 20 reg_gpio_29_drv 18 19 reg_gpio_29_smt 17 17 reg_gpio_29_ie 16 16 reg_gpio_28_func_sel 8 12 reg_gpio_28_pd 5 5 reg_gpio_28_pu 4 4 reg_gpio_28_drv 2 3 reg_gpio_28_smt 1 1 reg_gpio_28_ie 0 0 GPIO_CFGCTL15 GPIO_CFGCTL15. 0x13C reg_gpio_31_func_sel 24 28 reg_gpio_31_pd 21 21 reg_gpio_31_pu 20 20 reg_gpio_31_drv 18 19 reg_gpio_31_smt 17 17 reg_gpio_31_ie 16 16 reg_gpio_30_func_sel 8 12 reg_gpio_30_pd 5 5 reg_gpio_30_pu 4 4 reg_gpio_30_drv 2 3 reg_gpio_30_smt 1 1 reg_gpio_30_ie 0 0 GPIO_CFGCTL16 GPIO_CFGCTL16. 0x140 reg_gpio_33_pd 21 21 reg_gpio_33_pu 20 20 reg_gpio_33_drv 18 19 reg_gpio_33_smt 17 17 reg_gpio_33_ie 16 16 reg_gpio_32_pd 5 5 reg_gpio_32_pu 4 4 reg_gpio_32_drv 2 3 reg_gpio_32_smt 1 1 reg_gpio_32_ie 0 0 GPIO_CFGCTL17 GPIO_CFGCTL17. 0x144 reg_gpio_35_pd 21 21 reg_gpio_35_pu 20 20 reg_gpio_35_drv 18 19 reg_gpio_35_smt 17 17 reg_gpio_35_ie 16 16 reg_gpio_34_pd 5 5 reg_gpio_34_pu 4 4 reg_gpio_34_drv 2 3 reg_gpio_34_smt 1 1 reg_gpio_34_ie 0 0 GPIO_CFGCTL18 GPIO_CFGCTL18. 0x148 reg_gpio_37_pd 21 21 reg_gpio_37_pu 20 20 reg_gpio_37_drv 18 19 reg_gpio_37_smt 17 17 reg_gpio_37_ie 16 16 reg_gpio_36_pd 5 5 reg_gpio_36_pu 4 4 reg_gpio_36_drv 2 3 reg_gpio_36_smt 1 1 reg_gpio_36_ie 0 0 GPIO_CFGCTL30 GPIO_CFGCTL30. 0x180 reg_gpio_31_i 31 31 reg_gpio_30_i 30 30 reg_gpio_29_i 29 29 reg_gpio_28_i 28 28 reg_gpio_27_i 27 27 reg_gpio_26_i 26 26 reg_gpio_25_i 25 25 reg_gpio_24_i 24 24 reg_gpio_23_i 23 23 reg_gpio_22_i 22 22 reg_gpio_21_i 21 21 reg_gpio_20_i 20 20 reg_gpio_19_i 19 19 reg_gpio_18_i 18 18 reg_gpio_17_i 17 17 reg_gpio_16_i 16 16 reg_gpio_15_i 15 15 reg_gpio_14_i 14 14 reg_gpio_13_i 13 13 reg_gpio_12_i 12 12 reg_gpio_11_i 11 11 reg_gpio_10_i 10 10 reg_gpio_9_i 9 9 reg_gpio_8_i 8 8 reg_gpio_7_i 7 7 reg_gpio_6_i 6 6 reg_gpio_5_i 5 5 reg_gpio_4_i 4 4 reg_gpio_3_i 3 3 reg_gpio_2_i 2 2 reg_gpio_1_i 1 1 reg_gpio_0_i 0 0 GPIO_CFGCTL31 GPIO_CFGCTL31. 0x184 GPIO_CFGCTL32 GPIO_CFGCTL32. 0x188 reg_gpio_31_o 31 31 reg_gpio_30_o 30 30 reg_gpio_29_o 29 29 reg_gpio_28_o 28 28 reg_gpio_27_o 27 27 reg_gpio_26_o 26 26 reg_gpio_25_o 25 25 reg_gpio_24_o 24 24 reg_gpio_23_o 23 23 reg_gpio_22_o 22 22 reg_gpio_21_o 21 21 reg_gpio_20_o 20 20 reg_gpio_19_o 19 19 reg_gpio_18_o 18 18 reg_gpio_17_o 17 17 reg_gpio_16_o 16 16 reg_gpio_15_o 15 15 reg_gpio_14_o 14 14 reg_gpio_13_o 13 13 reg_gpio_12_o 12 12 reg_gpio_11_o 11 11 reg_gpio_10_o 10 10 reg_gpio_9_o 9 9 reg_gpio_8_o 8 8 reg_gpio_7_o 7 7 reg_gpio_6_o 6 6 reg_gpio_5_o 5 5 reg_gpio_4_o 4 4 reg_gpio_3_o 3 3 reg_gpio_2_o 2 2 reg_gpio_1_o 1 1 reg_gpio_0_o 0 0 GPIO_CFGCTL33 GPIO_CFGCTL33. 0x18C GPIO_CFGCTL34 GPIO_CFGCTL34. 0x190 reg_gpio_31_oe 31 31 reg_gpio_30_oe 30 30 reg_gpio_29_oe 29 29 reg_gpio_28_oe 28 28 reg_gpio_27_oe 27 27 reg_gpio_26_oe 26 26 reg_gpio_25_oe 25 25 reg_gpio_24_oe 24 24 reg_gpio_23_oe 23 23 reg_gpio_22_oe 22 22 reg_gpio_21_oe 21 21 reg_gpio_20_oe 20 20 reg_gpio_19_oe 19 19 reg_gpio_18_oe 18 18 reg_gpio_17_oe 17 17 reg_gpio_16_oe 16 16 reg_gpio_15_oe 15 15 reg_gpio_14_oe 14 14 reg_gpio_13_oe 13 13 reg_gpio_12_oe 12 12 reg_gpio_11_oe 11 11 reg_gpio_10_oe 10 10 reg_gpio_9_oe 9 9 reg_gpio_8_oe 8 8 reg_gpio_7_oe 7 7 reg_gpio_6_oe 6 6 reg_gpio_5_oe 5 5 reg_gpio_4_oe 4 4 reg_gpio_3_oe 3 3 reg_gpio_2_oe 2 2 reg_gpio_1_oe 1 1 reg_gpio_0_oe 0 0 GPIO_CFGCTL35 GPIO_CFGCTL35. 0x194 GPIO_INT_MASK1 GPIO_INT_MASK1. 0x1A0 reg_gpio_int_mask1 0 31 GPIO_INT_STAT1 GPIO_INT_STAT1. 0x1A8 gpio_int_stat1 0 31 GPIO_INT_CLR1 GPIO_INT_CLR1. 0x1B0 reg_gpio_int_clr1 0 31 GPIO_INT_MODE_SET1 GPIO_INT_MODE_SET1. 0x1C0 reg_gpio_int_mode_set1 0 29 GPIO_INT_MODE_SET2 GPIO_INT_MODE_SET2. 0x1C4 reg_gpio_int_mode_set2 0 29 GPIO_INT_MODE_SET3 GPIO_INT_MODE_SET3. 0x1C8 reg_gpio_int_mode_set3 0 29 GPIO_INT_MODE_SET4 GPIO_INT_MODE_SET4. 0x1CC reg_gpio_int_mode_set4 0 5 GPIO_INT2_MASK1 GPIO_INT2_MASK1. 0x1D0 reg_gpio_int2_mask1 0 31 GPIO_INT2_STAT1 GPIO_INT2_STAT1. 0x1D4 gpio_int2_stat1 0 31 GPIO_INT2_CLR1 GPIO_INT2_CLR1. 0x1D8 reg_gpio_int2_clr1 0 31 GPIO_INT2_MODE_SET1 GPIO_INT2_MODE_SET1. 0x1DC reg_gpio_int2_mode_set1 0 29 GPIO_INT2_MODE_SET2 GPIO_INT2_MODE_SET2. 0x1E0 reg_gpio_int2_mode_set2 0 29 GPIO_INT2_MODE_SET3 GPIO_INT2_MODE_SET3. 0x1E4 reg_gpio_int2_mode_set3 0 29 GPIO_INT2_MODE_SET4 GPIO_INT2_MODE_SET4. 0x1E8 reg_gpio_int2_mode_set4 0 5 dll dll. 0x200 ppu_dll 31 31 pu_dll 30 30 dll_reset 29 29 dll_refclk_sel 28 28 dll_cp_hiz 23 23 dll_cp_op_en 22 22 dll_delay_sel 20 21 dll_post_div 16 19 dll_vctrl_force_en 15 15 dll_prechg_en 14 14 dll_prechg_reg 13 13 dll_prechg_sel 12 12 dll_vctrl_sel 8 10 dll_clk_57p6M_en 7 7 dll_clk_96M_en 6 6 dll_clk_144M_en 5 5 dll_clk_288M_en 4 4 dll_clk_mmdiv_en 3 3 ten_dll 2 2 dtest_en_dll_outclk 1 1 dtest_en_dll_refclk 0 0 led_driver led_driver. 0x224 pu_leddrv 31 31 leddrv_out_en 28 29 ir_rx_gpio_sel 8 11 leddrv_ibias 4 7 led_din_polarity_sel 2 2 led_din_sel 1 1 led_din_reg 0 0 usb_xcvr usb_xcvr. 0x228 usb_rcv 27 27 usb_vip 26 26 usb_vim 25 25 usb_bd 24 24 pu_usb 23 23 usb_sus 22 22 usb_spd 21 21 usb_enum 20 20 usb_data_convert 16 16 usb_oeb 14 14 usb_oeb_reg 13 13 usb_oeb_sel 12 12 usb_rout_pmos 8 10 usb_rout_nmos 4 6 pu_usb_ldo 3 3 usb_ldo_vfb 0 2 usb_xcvr_config usb_xcvr_config. 0x22C usb_slewrate_p_rise 28 30 usb_slewrate_p_fall 24 26 usb_slewrate_m_rise 20 22 usb_slewrate_m_fall 16 18 usb_res_pullup_tune 12 14 reg_usb_use_ctrl 11 11 usb_str_drv 8 10 reg_usb_use_xcvr 7 7 usb_bd_vth 4 6 usb_v_hys_p 2 3 usb_v_hys_m 0 1 gpdac_ctrl gpdac_ctrl. 0x308 gpdac_reserved 24 31 gpdac_test_sel 9 11 gpdac_ref_sel 8 8 gpdac_test_en 7 7 gpdacb_rstn_ana 1 1 gpdaca_rstn_ana 0 0 gpdac_actrl gpdac_actrl. 0x30C gpdac_a_outmux 20 22 gpdac_a_rng 18 19 gpdac_ioa_en 1 1 gpdac_a_en 0 0 gpdac_bctrl gpdac_bctrl. 0x310 gpdac_b_outmux 20 22 gpdac_b_rng 18 19 gpdac_iob_en 1 1 gpdac_b_en 0 0 gpdac_data gpdac_data. 0x314 gpdac_a_data 16 25 gpdac_b_data 0 9 chip_revision chip_revision. 0xE00 chip_rev 0 3 tzc_glb_ctrl_0 tzc_glb_ctrl_0. 0xF00 tzc_glb_clk_lock 31 31 tzc_glb_mbist_lock 30 30 tzc_glb_dbg_lock 29 29 tzc_glb_bmx_lock 28 28 tzc_glb_l2c_lock 27 27 tzc_glb_sram_lock 26 26 tzc_glb_misc_lock 25 25 tzc_glb_ctrl_ungated_ap_lock 15 15 tzc_glb_ctrl_sys_reset_lock 14 14 tzc_glb_ctrl_cpu_reset_lock 13 13 tzc_glb_ctrl_pwron_rst_lock 12 12 tzc_glb_swrst_s30_lock 8 8 tzc_glb_swrst_s01_lock 1 1 tzc_glb_swrst_s00_lock 0 0 tzc_glb_ctrl_1 tzc_glb_ctrl_1. 0xF04 tzc_glb_swrst_s1f_lock 31 31 tzc_glb_swrst_s1e_lock 30 30 tzc_glb_swrst_s1d_lock 29 29 tzc_glb_swrst_s1c_lock 28 28 tzc_glb_swrst_s1b_lock 27 27 tzc_glb_swrst_s1a_lock 26 26 tzc_glb_swrst_s19_lock 25 25 tzc_glb_swrst_s18_lock 24 24 tzc_glb_swrst_s17_lock 23 23 tzc_glb_swrst_s16_lock 22 22 tzc_glb_swrst_s15_lock 21 21 tzc_glb_swrst_s14_lock 20 20 tzc_glb_swrst_s13_lock 19 19 tzc_glb_swrst_s12_lock 18 18 tzc_glb_swrst_s11_lock 17 17 tzc_glb_swrst_s10_lock 16 16 tzc_glb_swrst_s2f_lock 15 15 tzc_glb_swrst_s2e_lock 14 14 tzc_glb_swrst_s2d_lock 13 13 tzc_glb_swrst_s2c_lock 12 12 tzc_glb_swrst_s2b_lock 11 11 tzc_glb_swrst_s2a_lock 10 10 tzc_glb_swrst_s29_lock 9 9 tzc_glb_swrst_s28_lock 8 8 tzc_glb_swrst_s27_lock 7 7 tzc_glb_swrst_s26_lock 6 6 tzc_glb_swrst_s25_lock 5 5 tzc_glb_swrst_s24_lock 4 4 tzc_glb_swrst_s23_lock 3 3 tzc_glb_swrst_s22_lock 2 2 tzc_glb_swrst_s21_lock 1 1 tzc_glb_swrst_s20_lock 0 0 tzc_glb_ctrl_2 tzc_glb_ctrl_2. 0xF08 tzc_glb_gpio_31_lock 31 31 tzc_glb_gpio_30_lock 30 30 tzc_glb_gpio_29_lock 29 29 tzc_glb_gpio_28_lock 28 28 tzc_glb_gpio_27_lock 27 27 tzc_glb_gpio_26_lock 26 26 tzc_glb_gpio_25_lock 25 25 tzc_glb_gpio_24_lock 24 24 tzc_glb_gpio_23_lock 23 23 tzc_glb_gpio_22_lock 22 22 tzc_glb_gpio_21_lock 21 21 tzc_glb_gpio_20_lock 20 20 tzc_glb_gpio_19_lock 19 19 tzc_glb_gpio_18_lock 18 18 tzc_glb_gpio_17_lock 17 17 tzc_glb_gpio_16_lock 16 16 tzc_glb_gpio_15_lock 15 15 tzc_glb_gpio_14_lock 14 14 tzc_glb_gpio_13_lock 13 13 tzc_glb_gpio_12_lock 12 12 tzc_glb_gpio_11_lock 11 11 tzc_glb_gpio_10_lock 10 10 tzc_glb_gpio_9_lock 9 9 tzc_glb_gpio_8_lock 8 8 tzc_glb_gpio_7_lock 7 7 tzc_glb_gpio_6_lock 6 6 tzc_glb_gpio_5_lock 5 5 tzc_glb_gpio_4_lock 4 4 tzc_glb_gpio_3_lock 3 3 tzc_glb_gpio_2_lock 2 2 tzc_glb_gpio_1_lock 1 1 tzc_glb_gpio_0_lock 0 0 tzc_glb_ctrl_3 tzc_glb_ctrl_3. 0xF0C tzc_glb_gpio_37_lock 5 5 tzc_glb_gpio_36_lock 4 4 tzc_glb_gpio_35_lock 3 3 tzc_glb_gpio_34_lock 2 2 tzc_glb_gpio_33_lock 1 1 tzc_glb_gpio_32_lock 0 0 rf rf. rf 0x40001000 0x20 read-write 0x0 0x1000 registers rf_rev Silicon revision 0x0 hw_rev 16 23 fw_rev 8 15 rf_rev 0 7 dsp_readback dsp_readback. 0x4 rbb_bw_ind_ctrl_hw 31 31 rbb_bw_ind 30 30 rbb_ind_ctrl_hw 29 29 rbb_ind 24 28 ch_ind_ctrl_hw 23 23 ch_ind 16 22 rbb_bw_ind_hw 14 14 rbb_ind_hw 9 13 ch_ind_hw 2 8 rf_ctrl_source Control logic switch 0x8 vco_idac_ctrl_hw 28 28 inc_fcal_en_ctrl_hw 24 24 lo_fcw_ctrl_hw 20 20 rbb_bw_ctrl_hw 16 16 kcal_ratio_ctrl_hw 12 12 rosdac_ctrl_rccal 9 9 rosdac_ctrl_hw 8 8 gain_ctrl_rx_hw 4 4 gain_ctrl_tx_hw 3 3 pu_ctrl_hw 0 0 rf_cal_state_ctrl rf calibration state enable in full cal list 0xC inc_roscal_state_en 7 7 inc_acal_state_en 6 6 inc_fcal_state_en 5 5 rccal_state_en 4 4 roscal_state_en 3 3 kcal_state_en 2 2 acal_state_en 1 1 fcal_state_en 0 0 rf_cal_switch_ctrl Calibration mode register 0x10 inc_fcal_en_hw 17 17 inc_fcal_en 16 16 inc_acal_en 12 12 rccal_en 8 8 kcal_en 4 4 acal_en 0 0 rf_cal_status rf_cal_status. 0x14 dl_rfcal_table_status 30 31 rccal_status 8 9 roscal_status 6 7 kcal_status 4 5 acal_status 2 3 pu_delay_confg pu_delay_confg. 0x18 adpll_reset_width 20 21 lo_reset_width 16 17 lo_reset_delay 12 13 pud_delay 4 5 ppu_lead 0 1 pucr_reg Register control of power up signals 0x100 rst_fbdv 27 27 rst_lotpm_hfp 26 26 rst_adpll 25 25 pa_seri_cap_en 24 24 rx_bypass_en 23 23 pu_pa 22 22 pu_lna 21 21 pu_rmx 20 20 pu_rbb 19 19 pu_rbb_pkdet 18 18 pu_rosdac 17 17 pu_rxadc 16 16 rxadc_clk_en 15 15 pu_lodist_body_bias 14 14 pu_vco_ldo 13 13 pu_vco 12 12 pu_fbdv 11 11 pu_fbdv_buf 10 10 lotpm_hfp_clk_en 9 9 lotpm_lfp_bypass 8 8 lotpm_hfp_bypass 7 7 adpll_clk_en 6 6 pu_adpll_adc 5 5 pu_adpll_sfreg 4 4 pu_dtc 3 3 pu_rxbuf 2 2 pu_txbuf 1 1 lodist_tx_en 0 0 pucr_sb Power up setting in SB state 0x104 pa_seri_cap_en_sb 24 24 rx_bypass_en_sb 23 23 pu_pa_sb 22 22 pu_lna_sb 21 21 pu_rmx_sb 20 20 pu_rbb_sb 19 19 pu_rbb_pkdet_sb 18 18 pu_rosdac_sb 17 17 pu_rxadc_sb 16 16 rxadc_clk_en_sb 15 15 pu_lodist_body_bias_sb 14 14 pu_vco_ldo_sb 13 13 pu_vco_sb 12 12 pu_fbdv_sb 11 11 pu_fbdv_buf_sb 10 10 lotpm_hfp_clk_en_sb 9 9 lotpm_lfp_bypass_sb 8 8 lotpm_hfp_bypass_sb 7 7 adpll_clk_en_sb 6 6 pu_adpll_adc_sb 5 5 pu_adpll_sfreg_sb 4 4 pu_dtc_sb 3 3 pu_rxbuf_sb 2 2 pu_txbuf_sb 1 1 lodist_tx_en_sb 0 0 pucr_lotx Power up in LOTX state 0x108 pa_seri_cap_en_lotx 24 24 rx_bypass_en_lotx 23 23 pu_pa_lotx 22 22 pu_lna_lotx 21 21 pu_rmx_lotx 20 20 pu_rbb_lotx 19 19 pu_rbb_pkdet_lotx 18 18 pu_rosdac_lotx 17 17 pu_rxadc_lotx 16 16 rxadc_clk_en_lotx 15 15 pu_lodist_body_bias_lotx 14 14 pu_vco_ldo_lotx 13 13 pu_vco_lotx 12 12 pu_fbdv_lotx 11 11 pu_fbdv_buf_lotx 10 10 lotpm_hfp_clk_en_lotx 9 9 lotpm_lfp_bypass_lotx 8 8 lotpm_hfp_bypass_lotx 7 7 adpll_clk_en_lotx 6 6 pu_adpll_adc_lotx 5 5 pu_adpll_sfreg_lotx 4 4 pu_dtc_lotx 3 3 pu_rxbuf_lotx 2 2 pu_txbuf_lotx 1 1 lodist_tx_en_lotx 0 0 pucr_lorx Power up in LORX state 0x10C pa_seri_cap_en_lorx 24 24 rx_bypass_en_lorx 23 23 pu_pa_lorx 22 22 pu_lna_lorx 21 21 pu_rmx_lorx 20 20 pu_rbb_lorx 19 19 pu_rbb_pkdet_lorx 18 18 pu_rosdac_lorx 17 17 pu_rxadc_lorx 16 16 rxadc_clk_en_lorx 15 15 pu_lodist_body_bias_lorx 14 14 pu_vco_ldo_lorx 13 13 pu_vco_lorx 12 12 pu_fbdv_lorx 11 11 pu_fbdv_buf_lorx 10 10 lotpm_hfp_clk_en_lorx 9 9 lotpm_lfp_bypass_lorx 8 8 lotpm_hfp_bypass_lorx 7 7 adpll_clk_en_lorx 6 6 pu_adpll_adc_lorx 5 5 pu_adpll_sfreg_lorx 4 4 pu_dtc_lorx 3 3 pu_rxbuf_lorx 2 2 pu_txbuf_lorx 1 1 lodist_tx_en_lorx 0 0 pucr_tx Power up in TX state 0x110 pa_seri_cap_en_tx 24 24 rx_bypass_en_tx 23 23 pu_pa_tx 22 22 pu_lna_tx 21 21 pu_rmx_tx 20 20 pu_rbb_tx 19 19 pu_rbb_pkdet_tx 18 18 pu_rosdac_tx 17 17 pu_rxadc_tx 16 16 rxadc_clk_en_tx 15 15 pu_lodist_body_bias_tx 14 14 pu_vco_ldo_tx 13 13 pu_vco_tx 12 12 pu_fbdv_tx 11 11 pu_fbdv_buf_tx 10 10 lotpm_hfp_clk_en_tx 9 9 lotpm_lfp_bypass_tx 8 8 lotpm_hfp_bypass_tx 7 7 adpll_clk_en_tx 6 6 pu_adpll_adc_tx 5 5 pu_adpll_sfreg_tx 4 4 pu_dtc_tx 3 3 pu_rxbuf_tx 2 2 pu_txbuf_tx 1 1 lodist_tx_en_tx 0 0 pucr_rx Power up in RX state 0x114 pa_seri_cap_en_rx 24 24 rx_bypass_en_rx 23 23 pu_pa_rx 22 22 pu_lna_rx 21 21 pu_rmx_rx 20 20 pu_rbb_rx 19 19 pu_rbb_pkdet_rx 18 18 pu_rosdac_rx 17 17 pu_rxadc_rx 16 16 rxadc_clk_en_rx 15 15 pu_lodist_body_bias_rx 14 14 pu_vco_ldo_rx 13 13 pu_vco_rx 12 12 pu_fbdv_rx 11 11 pu_fbdv_buf_rx 10 10 lotpm_hfp_clk_en_rx 9 9 lotpm_lfp_bypass_rx 8 8 lotpm_hfp_bypass_rx 7 7 adpll_clk_en_rx 6 6 pu_adpll_adc_rx 5 5 pu_adpll_sfreg_rx 4 4 pu_dtc_rx 3 3 pu_rxbuf_rx 2 2 pu_txbuf_rx 1 1 lodist_tx_en_rx 0 0 pucr_hw Hardware read back of power up signals 0x118 rst_fbdv_hw 27 27 rst_lotpm_hfp_hw 26 26 rst_adpll_hw 25 25 pa_seri_cap_en_hw 24 24 rx_bypass_en_hw 23 23 pu_pa_hw 22 22 pu_lna_hw 21 21 pu_rmx_hw 20 20 pu_rbb_hw 19 19 pu_rbb_pkdet_hw 18 18 pu_rosdac_hw 17 17 pu_rxadc_hw 16 16 rxadc_clk_en_hw 15 15 pu_lodist_body_bias_hw 14 14 pu_vco_ldo_hw 13 13 pu_vco_hw 12 12 pu_fbdv_hw 11 11 pu_fbdv_buf_hw 10 10 lotpm_hfp_clk_en_hw 9 9 lotpm_lfp_bypass_hw 8 8 lotpm_hfp_bypass_hw 7 7 adpll_clk_en_hw 6 6 pu_adpll_adc_hw 5 5 pu_adpll_sfreg_hw 4 4 pu_dtc_hw 3 3 pu_rxbuf_hw 2 2 pu_txbuf_hw 1 1 lodist_tx_en_hw 0 0 non_reg_readback non_reg_readback. 0x11C ppu_lna_hw 16 16 ppu_rbb_hw 15 15 ppu_lodist_body_bias_hw 13 13 ppu_vco_ldo_hw 12 12 ppu_vco_hw 11 11 pud_vco_hw 10 10 ppu_fbdv_hw 9 9 ppu_adpll_sfreg_hw 8 8 ppu_rxbuf_hw 7 7 ppu_txbuf_hw 6 6 ppu_testbuf_hw 5 5 trx_gain_bw Register control of TX/RX gain 0x120 pa_inbuf_unit 20 22 pa_ref_dac 12 16 rbb_bw 8 8 gc_rbb2 5 7 gc_rbb1 3 4 gc_lna 0 2 trx_gain_bw_hw Hardware read back of TX/RX gain 0x124 pa_inbuf_unit_hw 20 22 pa_ref_dac_hw 12 16 rbb_bw_hw 8 8 gc_rbb2_hw 5 7 gc_rbb1_hw 3 4 gc_lna_hw 0 2 dctest_actest DC Test register 0 0x128 ten_mbg 31 31 ten_dll 28 28 ten_lodist 27 27 ten_pa_0 26 26 ten_pa_1 25 25 ten_rrf0 24 24 ten_rrf1 23 23 ten_rxadc 22 22 ten_vco 21 21 ten_adpll_adc 20 20 ten_rbb_actest 19 19 ten_rbb 18 18 ten_dtc 17 17 atest_out_en 6 7 dc_tp_out_en 4 5 dtest LO Bias Mode registers 0x12C dtest_en_dtc_in 29 29 dtest_en_dtc_out 28 28 dtest_en_fref 27 27 dtest_en_mod4 26 26 dtest_en_adpll_adc 25 25 dtest_en_rxadc_i 24 24 dtest_en_rxadc_q 23 23 dtest_pulldown 0 0 adpll_test adpll_test. 0x130 adpll_test_start 25 25 adpll_test_en 24 24 adpll_test_start_sel 20 21 adpll_test_data_sel 16 18 adpll_test_out 0 15 rf_ext_pa rf_ext_pa. 0x134 rf_ext_pa_rx 20 24 rf_ext_pa_lorx 15 19 rf_ext_pa_tx 10 14 rf_ext_pa_lotx 5 9 rf_ext_pa_sb 0 4 cip_ldo15 cip_ldo15. 0x200 vg11_sel 0 1 pa PA register 0x204 pa_force_short_open 30 30 pa_hp_en 29 29 pa_lp_en 28 28 pa_ldo_bm 24 26 pa_vdd11_sel 20 22 pa_para_cs 12 15 pa_seri_cs_hw 8 11 pa_seri_cs_rx 4 7 pa_seri_cs_tx 0 3 lna_mx LNA mixer register 0x208 lna_bm_hw 28 31 lna_bm_hg 24 27 lna_bm_lg 20 23 lna_cap_lg 18 19 lna_cap_match 15 17 lna_lg_gsel 12 14 lna_load_csw 8 11 lna_vdd13_sel 6 7 lna_rfb_match 3 5 rmx_bm 0 2 rbb_rosdac rbb_rosdac. 0x20C rosdac_i 24 29 rosdac_q 16 21 rosdac_i_hw 8 13 rosdac_q_hw 0 5 rbb_cap_1 rbb_cap_1. 0x210 rbb_cap1_fc_i 24 29 rbb_cap1_fc_q 16 21 rbb_cap2_fc_i 8 13 rbb_cap2_fc_q 0 5 rbb_cap_2 rbb_cap_2. 0x214 rbb_cap1_fc_i_hw 24 29 rbb_cap1_fc_q_hw 16 21 rbb_cap2_fc_i_hw 8 13 rbb_cap2_fc_q_hw 0 5 rbb_cap_3 rbb_cap_3. 0x218 rbb_cap1_fc_i_bw0 24 29 rbb_cap1_fc_q_bw0 16 21 rbb_cap2_fc_i_bw0 8 13 rbb_cap2_fc_q_bw0 0 5 rbb_cap4 rbb_cap4. 0x21C rbb_cap1_fc_i_bw1 24 29 rbb_cap1_fc_q_bw1 16 21 rbb_cap2_fc_i_bw1 8 13 rbb_cap2_fc_q_bw1 0 5 rbb_rx rbb_rx. 0x220 rbb_rx1 28 30 rbb_rx2 24 26 rbb_rx1_hw 20 22 rbb_rx2_hw 16 18 rbb_rx1_bw0 12 14 rbb_rx2_bw0 8 10 rbb_rx1_bw1 4 6 rbb_rx2_bw1 0 2 rbb rbb. 0x224 rbb_bm_op 28 29 rbb_vcm 24 25 rbb_deq 20 21 rbb_lpf_en 19 19 rosdac_range 16 17 rbb_pkdet_vth 12 15 rbb_pkdet_en 10 10 rbb_pkdet_en_hw 9 9 rbb_pkdet_en_ctrl_hw 8 8 rbb_pkdet_out_rstn 6 6 rbb_pkdet_out_rstn_hw 5 5 rbb_pkdet_out_rstn_ctrl_hw 4 4 pkdet_out_raw 1 1 pkdet_out_latch 0 0 rxadc rxadc. 0x228 rxadc_dly_ctrl 24 25 rxadc_glitch_remove 20 20 rxadc_clk_div_sel 16 16 rxadc_clk_inv 12 12 rxadc_clk_sync_inv 8 8 rxadc_vref_sel 4 5 rxadc_oscal_en 0 0 rxadc_readback rxadc_readback. 0x22C rxadc_dout_i 16 24 rxadc_dout_q 0 8 rf_adc_osdata rf_adc_osdata. 0x230 rxadc_os_i 16 24 rxadc_os_q 0 8 testbuf testbuf. 0x234 pu_testbuf 24 24 testbuf_vcm 20 21 testbuf_bm 16 18 testbuf_boost 12 12 testbuf_op_cc 8 11 testbuf_rfb 4 4 testbuf_rin 0 0 vco vco. 0x238 vco_acal_ud 31 31 vco_idac_hw 24 29 vco_idac 16 21 vco_ldo_bypass 15 15 vco_ldo_vsel 13 14 vco_idac_boost 12 12 vco_vbias 8 9 vco_acal_vref 4 6 vco_modcap_sel 2 3 vco_short_idac_filter 1 1 vco_short_vbias_filter 0 0 lodist lodist. 0x23C lodist_75dc_sel 16 16 lodist_nwell_bias 12 13 lodist_rwell_bias 8 9 lodist_rxbuf_supply_boost 6 6 lodist_rxbuf_supply_mode 4 5 lodist_txbuf_supply_mode 0 1 fbdv fbdv. 0x240 dco_dither_clk_polarity 29 29 lotpm_fmash_clk_polarity 28 28 rst_mmdiv 24 24 fbdv_stg_sel 20 20 fbdv_sample_clk_sel 16 17 fbdv_fb_clk_sel 12 12 fbdv_dco_dither_clk_sel 8 8 fbdv_adpll_clk_sel 4 4 fbdv_tpm_clk_sel 0 2 kcal1 kcal1. 0x244 kcal_ratio 20 29 kcal_cnt_start 16 16 kcal_div 0 15 kcal2 kcal2. 0x248 kcal_ratio_hw 20 29 kcal_cnt_rdy 16 16 kcal_cnt_op 0 15 adpll_slope_gen adpll_slope_gen. 0x24C adpll_slope_gen_pulse_width_enhance 6 6 adpll_slope_gen_dc_corr 4 5 adpll_slope_gen_r_sel 0 2 adpll_adc adpll_adc. 0x250 adpll_adc_clk_en 29 29 adpll_adc_clk_inv 28 28 adpll_adc_clk_div_sel 24 24 adpll_adc_clk_sync_inv 16 16 adpll_adc_oscal_en 12 12 adpll_adc_vref_coarse 8 9 adpll_adc_vref_fine 4 5 adpll_adc_data_sign_sel 2 2 adpll_adc_vth_en 1 1 adpll_adc_vth_bias_mode 0 0 adpll_dtc adpll_dtc. 0x254 adpll_dtc_inv_vth_sel 8 9 adpll_dtc_r_sel 4 6 adpll_dtc_bypass 0 0 lo_fc_config1 lo_fc_config1. 0x258 lo_fcw 0 24 lo_fcw_config2 lo_fcw_config2. 0x25C lo_fcw_hw 0 24 lo_fcw3 lo_fcw3. 0x260 tx_freq_mod_hp 16 25 tx_freq_mod_lp 0 11 lotpm lotpm. 0x264 lotpm_hfp_mash1_sel 16 16 lotpm_hfp_polarity 12 12 lotpm_hfp_delay_fref 8 9 lotpm_hfp_delay_fmash 4 7 lotpm_lfp_delay_sel 0 1 adpll1 adpll1. 0x268 adpll_force_inc_fcal_en 26 26 adpll_lo_unlock_intrpt_clear_sel 25 25 adpll_sfreg_sel 24 24 adpll_lo_open 23 23 adpll_mom_search_en_ext 22 22 adpll_freqerr_det_start_ext 21 21 adpll_mom_update_en_ext 20 20 adpll_vctrl_det_en_ext 19 19 adpll_vctrl_det_start_ext 18 18 adpll_abnormal_dealed 15 15 adpll_lock_fail_en 14 14 adpll_fsm_en 12 12 adpll_lo_fsm_ext 11 11 adpll_lo_lock_directly 10 10 adpll_fcal_start_ext 9 9 adpll_fcal_done_ext 8 8 adpll_loop_lock_ext 7 7 adpll_rst_spd_det_ext 6 6 adpll_rst_coarse_det_ext 5 5 adpll_momhold_lmsenb_ext 4 4 adpll_timeout_cnt_sel 3 3 adpll_timeout_cnt1_sel 2 2 adpll_lo_lock_sel 1 1 adpll_lo_unlock_intrpt_clear 0 0 adpll_lf_reg adpll_lf_reg. 0x26C adpll_lf_ctrl_hw 28 28 adpll_lf_alpha_base 27 27 adpll_lf_alpha_exp 24 26 adpll_lf_alpha_fast 20 21 adpll_lf_beta_base 17 18 adpll_lf_beta_exp 14 16 adpll_lf_beta_fast 13 13 adpll_lf_f_p3 10 11 adpll_lf_avg_en 9 9 adpll_lf_lsb_ext 2 8 adpll_lf_vctrl_range_ext 0 1 adpll_lf_tx adpll_lf_tx. 0x270 adpll_lf_alpha_base_tx 27 27 adpll_lf_alpha_exp_tx 24 26 adpll_lf_alpha_fast_tx 20 21 adpll_lf_beta_base_tx 17 18 adpll_lf_beta_exp_tx 14 16 adpll_lf_beta_fast_tx 13 13 adpll_lf_f_p3_tx 10 11 adpll_lf_rx adpll_lf_rx. 0x274 adpll_lf_alpha_base_rx 27 27 adpll_lf_alpha_exp_rx 24 26 adpll_lf_alpha_fast_rx 20 21 adpll_lf_beta_base_rx 17 18 adpll_lf_beta_exp_rx 14 16 adpll_lf_beta_fast_rx 13 13 adpll_lf_f_p3_rx 10 11 adpll_lf_hw adpll_lf_hw. 0x278 adpll_lf_alpha_base_hw 27 27 adpll_lf_alpha_exp_hw 24 26 adpll_lf_alpha_fast_hw 20 21 adpll_lf_beta_base_hw 17 18 adpll_lf_beta_exp_hw 14 16 adpll_lf_beta_fast_hw 13 13 adpll_lf_f_p3_hw 10 11 adpll_vctrl adpll_vctrl. 0x27C adpll_vctrl_range_sel_ext_en 27 27 adpll_vctrl_lock_win_sel 26 26 adpll_vctrl_moni_win_sel 25 25 adpll_vctrl_det_cons_en 24 24 adpll_mom_update_period 20 21 adpll_force_mom_hold 16 16 adpll_dco_mash_bypass 15 15 adpll_capcode_bypass 14 14 sdm_order 12 12 sdm_dither 8 9 sdm_bypass 4 4 sdmout_dly_sel 0 1 adpll_lms adpll_lms. 0x280 adpll_fref_div2_en 31 31 adpll_lms_ext_value_en 29 29 adpll_lms_ext_value 20 28 adpll_sdm_dither_en 19 19 adpll_sdm_dither_en_ctrl_hw 18 18 adpll_lms_step 16 17 adpll_sdm_dither_prbs_en 15 15 adpll_pha_dem_en 14 14 adpll_pha_dither_en 13 13 adpll_lms_step_enlarge 12 12 adpll_pha_prbs_sel 10 11 adpll_lms_q_delay 8 9 adpll_pha_cancel_en 4 4 adpll_pha_cancel_delay 0 1 adpll_spd adpll_spd. 0x284 adpll_spd_in_range_delay_1 30 31 adpll_coarsepha_dly_sel 29 29 adpll_force_coarse_path_on 28 28 adpll_spd_lms_sstp_win_sel 27 27 adpll_spd_outrange_dly_sel_ext 25 26 adpll_coarse_path_offtime_sel 24 24 adpll_coarse_phaerr_en 23 23 adpll_force_lf_fast_mode_hw 22 22 adpll_force_lf_fast_mode 21 21 adpll_force_lf_fast_mode_ctrl_hw 20 20 adpll_coarse_gain 18 19 adpll_spd_gain 16 17 adpll_coarse_in_range_cons 14 15 adpll_spd_threshold 12 13 adpll_coarse_path_turnoff 10 11 adpll_spd_in_range_cons 8 9 adpll_spd_out_range_delay 4 4 adpll_spd_in_range_delay 0 1 fcal fcal. 0x288 fcal_mom_ini_ext 16 23 fcal_mode 6 7 fcal_clk_period 4 5 fcal_mom_toggle_cnt 3 3 fcal_coarse_pha_threshold 1 2 fcal_div_ratio_adj_en 0 0 adpll_polarity adpll_polarity. 0x28C adpll_lp_polarity 20 20 adpll_fcal_polarity 16 16 adpll_lms_polarity 12 12 adpll_lp_mom_polarity 8 8 adpll_output adpll_output. 0x290 adpll_freqerr_det_done 21 21 adpll_freqerr_ou 20 20 adpll_freqerr_sign 19 19 adpll_vctrl_det_done 18 18 adpll_capcode_ud 17 17 adpll_mom_update_total_ou 15 16 adpll_capcode_out_range 14 14 adpll_fcal_done_fsm 13 13 adpll_spd_lock_fsm 12 12 adpll_spd_unlock_fsm 11 11 adpll_mom_update_ou_fsm 10 10 adpll_mom_update_fail_fsm 9 9 adpll_vctrl_out_range_fsm 8 8 adpll_spd_unlock_sign 7 7 adpll_fsm_state 3 6 adpll_lo_lock 1 1 adpll_unlock_intrpt 0 0 adpll_reserved adpll_reserved. 0x294 adpll_resv0 16 31 adpll_resv1 0 15 rf_reserved rf_reserved. 0x298 rf_resv0 16 31 rf_resv1 0 15 rf_reserved_2 rf_reserved_2. 0x29C rf_resv 0 31 rbb_gain_ctrl0 rbb_gain_ctrl0. 0x300 gain_ctrl0_g_rbb1 28 29 gain_ctrl0_g_rbb2 24 26 gain_ctrl0_rosdac_i_bw1 18 23 gain_ctrl0_rosdac_q_bw1 12 17 gain_ctrl0_rosdac_i_bw0 6 11 gain_ctrl0_rosdac_q_bw0 0 5 rbb_gain_ctrl1 rbb_gain_ctrl1. 0x304 gain_ctrl1_g_rbb1 28 29 gain_ctrl1_g_rbb2 24 26 gain_ctrl1_rosdac_i_bw1 18 23 gain_ctrl1_rosdac_q_bw1 12 17 gain_ctrl1_rosdac_i_bw0 6 11 gain_ctrl1_rosdac_q_bw0 0 5 rbb_gain_ctrl2 rbb_gain_ctrl2. 0x308 gain_ctrl2_g_rbb1 28 29 gain_ctrl2_g_rbb2 24 26 gain_ctrl2_rosdac_i_bw1 18 23 gain_ctrl2_rosdac_q_bw1 12 17 gain_ctrl2_rosdac_i_bw0 6 11 gain_ctrl2_rosdac_q_bw0 0 5 rbb_gain_ctrl3 rbb_gain_ctrl3. 0x30C gain_ctrl3_g_rbb1 28 29 gain_ctrl3_g_rbb2 24 26 gain_ctrl3_rosdac_i_bw1 18 23 gain_ctrl3_rosdac_q_bw1 12 17 gain_ctrl3_rosdac_i_bw0 6 11 gain_ctrl3_rosdac_q_bw0 0 5 rbb_gain_ctrl4 rbb_gain_ctrl4. 0x310 gain_ctrl4_g_rbb1 28 29 gain_ctrl4_g_rbb2 24 26 gain_ctrl4_rosdac_i_bw1 18 23 gain_ctrl4_rosdac_q_bw1 12 17 gain_ctrl4_rosdac_i_bw0 6 11 gain_ctrl4_rosdac_q_bw0 0 5 rbb_gain_ctrl5 rbb_gain_ctrl5. 0x314 gain_ctrl5_g_rbb1 28 29 gain_ctrl5_g_rbb2 24 26 gain_ctrl5_rosdac_i_bw1 18 23 gain_ctrl5_rosdac_q_bw1 12 17 gain_ctrl5_rosdac_i_bw0 6 11 gain_ctrl5_rosdac_q_bw0 0 5 rbb_gain_ctrl6 rbb_gain_ctrl6. 0x318 gain_ctrl6_g_rbb1 28 29 gain_ctrl6_g_rbb2 24 26 gain_ctrl6_rosdac_i_bw1 18 23 gain_ctrl6_rosdac_q_bw1 12 17 gain_ctrl6_rosdac_i_bw0 6 11 gain_ctrl6_rosdac_q_bw0 0 5 rbb_gain_ctrl7 rbb_gain_ctrl7. 0x31C gain_ctrl7_g_rbb1 28 29 gain_ctrl7_g_rbb2 24 26 gain_ctrl7_rosdac_i_bw1 18 23 gain_ctrl7_rosdac_q_bw1 12 17 gain_ctrl7_rosdac_i_bw0 6 11 gain_ctrl7_rosdac_q_bw0 0 5 rbb_gain_ctrl8 rbb_gain_ctrl8. 0x320 gain_ctrl8_g_rbb1 28 29 gain_ctrl8_g_rbb2 24 26 gain_ctrl8_rosdac_i_bw1 18 23 gain_ctrl8_rosdac_q_bw1 12 17 gain_ctrl8_rosdac_i_bw0 6 11 gain_ctrl8_rosdac_q_bw0 0 5 rbb_gain_ctrl9 rbb_gain_ctrl9. 0x324 gain_ctrl9_g_rbb1 28 29 gain_ctrl9_g_rbb2 24 26 gain_ctrl9_rosdac_i_bw1 18 23 gain_ctrl9_rosdac_q_bw1 12 17 gain_ctrl9_rosdac_i_bw0 6 11 gain_ctrl9_rosdac_q_bw0 0 5 rbb_gain_ctrl10 rbb_gain_ctrl10. 0x328 gain_ctrl10_g_rbb1 28 29 gain_ctrl10_g_rbb2 24 26 gain_ctrl10_rosdac_i_bw1 18 23 gain_ctrl10_rosdac_q_bw1 12 17 gain_ctrl10_rosdac_i_bw0 6 11 gain_ctrl10_rosdac_q_bw0 0 5 rbb_gain_ctrl11 rbb_gain_ctrl11. 0x32C gain_ctrl11_g_rbb1 28 29 gain_ctrl11_g_rbb2 24 26 gain_ctrl11_rosdac_i_bw1 18 23 gain_ctrl11_rosdac_q_bw1 12 17 gain_ctrl11_rosdac_i_bw0 6 11 gain_ctrl11_rosdac_q_bw0 0 5 rbb_gain_ctrl12 rbb_gain_ctrl12. 0x330 gain_ctrl12_g_rbb1 28 29 gain_ctrl12_g_rbb2 24 26 gain_ctrl12_rosdac_i_bw1 18 23 gain_ctrl12_rosdac_q_bw1 12 17 gain_ctrl12_rosdac_i_bw0 6 11 gain_ctrl12_rosdac_q_bw0 0 5 rbb_gain_ctrl13 rbb_gain_ctrl13. 0x334 gain_ctrl13_g_rbb1 28 29 gain_ctrl13_g_rbb2 24 26 gain_ctrl13_rosdac_i_bw1 18 23 gain_ctrl13_rosdac_q_bw1 12 17 gain_ctrl13_rosdac_i_bw0 6 11 gain_ctrl13_rosdac_q_bw0 0 5 rbb_gain_ctrl14 rbb_gain_ctrl14. 0x338 gain_ctrl14_g_rbb1 28 29 gain_ctrl14_g_rbb2 24 26 gain_ctrl14_rosdac_i_bw1 18 23 gain_ctrl14_rosdac_q_bw1 12 17 gain_ctrl14_rosdac_i_bw0 6 11 gain_ctrl14_rosdac_q_bw0 0 5 rbb_gain_ctrl15 rbb_gain_ctrl15. 0x33C gain_ctrl15_g_rbb1 28 29 gain_ctrl15_g_rbb2 24 26 gain_ctrl15_rosdac_i_bw1 18 23 gain_ctrl15_rosdac_q_bw1 12 17 gain_ctrl15_rosdac_i_bw0 6 11 gain_ctrl15_rosdac_q_bw0 0 5 acal_config acal_config. 0x400 vco_idac_hh 24 29 vco_idac_hl 16 21 vco_idac_lh 8 13 vco_idac_ll 0 5 lo_config_2402 lo_config_2402. 0x404 adpll_sdm_dither_en_2402 12 12 kcal_ratio_2402 0 9 lo_config_2404 lo_config_2404. 0x408 adpll_sdm_dither_en_2404 12 12 kcal_ratio_2404 0 9 lo_config_2406 lo_config_2406. 0x40C adpll_sdm_dither_en_2406 12 12 kcal_ratio_2406 0 9 lo_config_2408 lo_config_2408. 0x410 adpll_sdm_dither_en_2408 12 12 kcal_ratio_2408 0 9 lo_config_2410 lo_config_2410. 0x414 adpll_sdm_dither_en_2410 12 12 kcal_ratio_2410 0 9 lo_config_2412 lo_config_2412. 0x418 adpll_sdm_dither_en_2412 12 12 kcal_ratio_2412 0 9 lo_config_2414 lo_config_2414. 0x41C adpll_sdm_dither_en_2414 12 12 kcal_ratio_2414 0 9 lo_config_2416 lo_config_2416. 0x420 adpll_sdm_dither_en_2416 12 12 kcal_ratio_2416 0 9 lo_config_2418 lo_config_2418. 0x424 adpll_sdm_dither_en_2418 12 12 kcal_ratio_2418 0 9 lo_config_2420 lo_config_2420. 0x428 adpll_sdm_dither_en_2420 12 12 kcal_ratio_2420 0 9 lo_config_2422 lo_config_2422. 0x42C adpll_sdm_dither_en_2422 12 12 kcal_ratio_2422 0 9 lo_config_2424 lo_config_2424. 0x430 adpll_sdm_dither_en_2424 12 12 kcal_ratio_2424 0 9 lo_config_2426 lo_config_2426. 0x434 adpll_sdm_dither_en_2426 12 12 kcal_ratio_2426 0 9 lo_config_2428 lo_config_2428. 0x438 adpll_sdm_dither_en_2428 12 12 kcal_ratio_2428 0 9 lo_config_2430 lo_config_2430. 0x43C adpll_sdm_dither_en_2430 12 12 kcal_ratio_2430 0 9 lo_config_2432 lo_config_2432. 0x440 adpll_sdm_dither_en_2432 12 12 kcal_ratio_2432 0 9 lo_config_2434 lo_config_2434. 0x444 adpll_sdm_dither_en_2434 12 12 kcal_ratio_2434 0 9 lo_config_2436 lo_config_2436. 0x448 adpll_sdm_dither_en_2436 12 12 kcal_ratio_2436 0 9 lo_config_2438 lo_config_2438. 0x44C adpll_sdm_dither_en_2438 12 12 kcal_ratio_2438 0 9 lo_config_2440 lo_config_2440. 0x450 adpll_sdm_dither_en_2440 12 12 kcal_ratio_2440 0 9 lo_config_2442 lo_config_2442. 0x454 adpll_sdm_dither_en_2442 12 12 kcal_ratio_2442 0 9 lo_config_2444 lo_config_2444. 0x458 adpll_sdm_dither_en_2444 12 12 kcal_ratio_2444 0 9 lo_config_2446 lo_config_2446. 0x45C adpll_sdm_dither_en_2446 12 12 kcal_ratio_2446 0 9 lo_config_2448 lo_config_2448. 0x460 adpll_sdm_dither_en_2448 12 12 kcal_ratio_2448 0 9 lo_config_2450 lo_config_2450. 0x464 adpll_sdm_dither_en_2450 12 12 kcal_ratio_2450 0 9 lo_config_2452 lo_config_2452. 0x468 adpll_sdm_dither_en_2452 12 12 kcal_ratio_2452 0 9 lo_config_2454 lo_config_2454. 0x46C adpll_sdm_dither_en_2454 12 12 kcal_ratio_2454 0 9 lo_config_2456 lo_config_2456. 0x470 adpll_sdm_dither_en_2456 12 12 kcal_ratio_2456 0 9 lo_config_2458 lo_config_2458. 0x474 adpll_sdm_dither_en_2458 12 12 kcal_ratio_2458 0 9 lo_config_2460 lo_config_2460. 0x478 adpll_sdm_dither_en_2460 12 12 kcal_ratio_2460 0 9 lo_config_2462 lo_config_2462. 0x47C adpll_sdm_dither_en_2462 12 12 kcal_ratio_2462 0 9 lo_config_2464 lo_config_2464. 0x480 adpll_sdm_dither_en_2464 12 12 kcal_ratio_2464 0 9 lo_config_2466 lo_config_2466. 0x484 adpll_sdm_dither_en_2466 12 12 kcal_ratio_2466 0 9 lo_config_2468 lo_config_2468. 0x488 adpll_sdm_dither_en_2468 12 12 kcal_ratio_2468 0 9 lo_config_2470 lo_config_2470. 0x48C adpll_sdm_dither_en_2470 12 12 kcal_ratio_2470 0 9 lo_config_2472 lo_config_2472. 0x490 adpll_sdm_dither_en_2472 12 12 kcal_ratio_2472 0 9 lo_config_2474 lo_config_2474. 0x494 adpll_sdm_dither_en_2474 12 12 kcal_ratio_2474 0 9 lo_config_2476 lo_config_2476. 0x498 adpll_sdm_dither_en_2476 12 12 kcal_ratio_2476 0 9 lo_config_2478 lo_config_2478. 0x49C adpll_sdm_dither_en_2478 12 12 kcal_ratio_2478 0 9 lo_config_2480 lo_config_2480. 0x4A0 adpll_sdm_dither_en_2480 12 12 kcal_ratio_2480 0 9 lo_config_2405 lo_config_2405. 0x4A4 adpll_sdm_dither_en_2405 12 12 kcal_ratio_2405 0 9 lo_config_2415 lo_config_2415. 0x4A8 adpll_sdm_dither_en_2415 12 12 kcal_ratio_2415 0 9 lo_config_2425 lo_config_2425. 0x4AC adpll_sdm_dither_en_2425 12 12 kcal_ratio_2425 0 9 lo_config_2435 lo_config_2435. 0x4B0 adpll_sdm_dither_en_2435 12 12 kcal_ratio_2435 0 9 lo_config_2445 lo_config_2445. 0x4B4 adpll_sdm_dither_en_2445 12 12 kcal_ratio_2445 0 9 lo_config_2455 lo_config_2455. 0x4B8 adpll_sdm_dither_en_2455 12 12 kcal_ratio_2455 0 9 lo_config_2465 lo_config_2465. 0x4BC adpll_sdm_dither_en_2465 12 12 kcal_ratio_2465 0 9 lo_config_2475 lo_config_2475. 0x4C0 adpll_sdm_dither_en_2475 12 12 kcal_ratio_2475 0 9 dg_testbus_0 dg_testbus_0. 0x500 rf_testbus_read 0 31 dg_testbus_1 dg_testbus_1. 0x504 rf_testbus_sel 0 3 dg_ppud_0 dg_ppud_0. 0x508 ppud_manaual_en 30 30 ppud_cnt1 25 29 ppud_cnt2 16 24 rf_top rf_top. 0x50C rf_tx_en_src 31 31 rf_tx_en_4s 30 30 rf_rx_en_src 29 29 rf_rx_en_4s 28 28 rf_rx_mode_4s_en 26 26 rf_rx_mode_4s 24 25 rf_rx_mode_hw 22 23 rf_mac_lo_time_offset 16 21 rfckg_afifo_tx_inv 2 2 rfckg_afifo_rxadc_inv 1 1 rfckg_afifo_adpll_inv 0 0 rf_fsm rf_fsm. 0x510 rf_fsm_afifo_dly_time 26 31 rf_fsm_tx_afifo_4s_en 25 25 rf_fsm_tx_afifo_4s 24 24 rf_fsm_rx_afifo_4s_en 23 23 rf_fsm_rx_afifo_4s 22 22 rf_fsm_en 21 21 rf_fsm_st_4s_en 20 20 rf_fsm_st_4s 16 18 rf_fsm_state 12 14 rf_fsm_lo_time 0 11 rf_singen_0 rf_singen_0. 0x514 singen_en 31 31 singen_clkdiv_n 29 30 singen_unsign_en 28 28 singen_inc_step0 16 25 singen_inc_step1 0 9 rf_singen_1 rf_singen_1. 0x518 singen_mode_i 28 31 singen_clkdiv_i 16 25 singen_mode_q 12 15 singen_clkdiv_q 0 9 rf_singen_2 rf_singen_2. 0x51C singen_start_addr0_i 22 31 singen_start_addr1_i 12 21 singen_gain_i 0 10 rf_singen_3 rf_singen_3. 0x520 singen_start_addr0_q 22 31 singen_start_addr1_q 12 21 singen_gain_q 0 10 rf_singen_4 rf_singen_4. 0x524 singen_fix_en_i 28 28 singen_fix_i 16 27 singen_fix_en_q 12 12 singen_fix_q 0 11 rf_sram_ctrl0 rf_sram_ctrl0. 0x528 rf_sram_done_cnt 16 31 rf_sram_mode 4 5 rf_sram_sts_clr 3 3 rf_sram_loop_en 2 2 rf_sram_en 1 1 rf_sram_done 0 0 rf_sram_ctrl1 rf_sram_ctrl1. 0x52C rf_sram_addr_start 16 31 rf_sram_addr_end 0 15 rf_sram_ctrl2 rf_sram_ctrl2. 0x530 rf_sram_sts 0 31 rf_test_mode rf_test_mode. 0x534 rf_test_mode_en 30 30 dacout_4s_sram_en 29 29 dacout_4s_en 28 28 dacout_4s 16 27 dacout_hw 0 11 rf_rx_pulse_filter rf_rx_pulse_filter. 0x538 pf_en_i 21 21 pf_en_q 20 20 pf_th1 10 18 pf_th2 0 8 gpip General purpose DAC/ADC/ACOMP interface control gpip 0x40002000 0x20 read-write 0x0 0x1000 registers gpadc_config gpadc_config. 0x0 rsvd_31_24 24 31 gpadc_fifo_thl 22 23 gpadc_fifo_data_count 16 21 gpadc_fifo_rdy_mask 15 15 gpadc_fifo_underrun_mask 14 14 gpadc_fifo_overrun_mask 13 13 gpadc_rdy_mask 12 12 gpadc_fifo_underrun_clr 10 10 gpadc_fifo_overrun_clr 9 9 gpadc_rdy_clr 8 8 gpadc_fifo_rdy 7 7 gpadc_fifo_underrun 6 6 gpadc_fifo_overrun 5 5 gpadc_rdy 4 4 gpadc_fifo_full 3 3 gpadc_fifo_ne 2 2 gpadc_fifo_clr 1 1 gpadc_dma_en 0 0 gpadc_dma_rdata gpadc_dma_rdata. 0x4 rsvd_31_26 26 31 gpadc_dma_rdata 0 25 gpdac_config gpdac_config. 0x40 rsvd_31_24 24 31 gpdac_ch_b_sel 20 23 gpdac_ch_a_sel 16 19 gpdac_mode 8 10 dsm_mode 4 5 gpdac_en2 1 1 gpdac_en 0 0 gpdac_dma_config gpdac_dma_config. 0x44 gpdac_dma_format 4 5 gpdac_dma_tx_en 0 0 gpdac_dma_wdata gpdac_dma_wdata. 0x48 gpdac_dma_wdata 0 31 gpdac_tx_fifo_status gpdac_tx_fifo_status. 0x4C TxFifoWrPtr 8 9 TxFifoRdPtr 4 6 tx_cs 2 3 tx_fifo_full 1 1 tx_fifo_empty 0 0 sec_dbg sec_dbg. sec_dbg 0x40003000 0x20 read-write 0x0 0x1000 registers sd_chip_id_low sd_chip_id_low. 0x0 sd_chip_id_low 0 31 sd_chip_id_high sd_chip_id_high. 0x4 sd_chip_id_high 0 31 sd_wifi_mac_low sd_wifi_mac_low. 0x8 sd_wifi_mac_low 0 31 sd_wifi_mac_high sd_wifi_mac_high. 0xC sd_wifi_mac_high 0 31 sd_dbg_pwd_low sd_dbg_pwd_low. 0x10 sd_dbg_pwd_low 0 31 sd_dbg_pwd_high sd_dbg_pwd_high. 0x14 sd_dbg_pwd_high 0 31 sd_status sd_status. 0x18 sd_dbg_ena 28 31 sd_dbg_mode 24 27 sd_dbg_pwd_cnt 4 23 sd_dbg_cci_clk_sel 3 3 sd_dbg_cci_read_en 2 2 sd_dbg_pwd_trig 1 1 sd_dbg_pwd_busy 0 0 sd_dbg_reserved sd_dbg_reserved. 0x1C sd_dbg_reserved 0 31 sec_eng sec_eng. sec_eng 0x40004000 0x20 read-write 0x0 0x1000 registers se_sha_0_ctrl se_sha_0_ctrl. 0x0 se_sha_0_msg_len 16 31 se_sha_0_link_mode 15 15 se_sha_0_int_mask 11 11 se_sha_0_int_set_1t 10 10 se_sha_0_int_clr_1t 9 9 se_sha_0_int 8 8 se_sha_0_hash_sel 6 6 se_sha_0_en 5 5 se_sha_0_mode 2 4 se_sha_0_trig_1t 1 1 se_sha_0_busy 0 0 se_sha_0_msa se_sha_0_msa. 0x4 se_sha_0_msa 0 31 se_sha_0_status se_sha_0_status. 0x8 se_sha_0_status 0 31 se_sha_0_endian se_sha_0_endian. 0xC se_sha_0_dout_endian 0 0 se_sha_0_hash_l_0 se_sha_0_hash_l_0. 0x10 se_sha_0_hash_l_0 0 31 se_sha_0_hash_l_1 se_sha_0_hash_l_1. 0x14 se_sha_0_hash_l_1 0 31 se_sha_0_hash_l_2 se_sha_0_hash_l_2. 0x18 se_sha_0_hash_l_2 0 31 se_sha_0_hash_l_3 se_sha_0_hash_l_3. 0x1C se_sha_0_hash_l_3 0 31 se_sha_0_hash_l_4 se_sha_0_hash_l_4. 0x20 se_sha_0_hash_l_4 0 31 se_sha_0_hash_l_5 se_sha_0_hash_l_5. 0x24 se_sha_0_hash_l_5 0 31 se_sha_0_hash_l_6 se_sha_0_hash_l_6. 0x28 se_sha_0_hash_l_6 0 31 se_sha_0_hash_l_7 se_sha_0_hash_l_7. 0x2C se_sha_0_hash_l_7 0 31 se_sha_0_hash_h_0 se_sha_0_hash_h_0. 0x30 se_sha_0_hash_h_0 0 31 se_sha_0_hash_h_1 se_sha_0_hash_h_1. 0x34 se_sha_0_hash_h_1 0 31 se_sha_0_hash_h_2 se_sha_0_hash_h_2. 0x38 se_sha_0_hash_h_2 0 31 se_sha_0_hash_h_3 se_sha_0_hash_h_3. 0x3C se_sha_0_hash_h_3 0 31 se_sha_0_hash_h_4 se_sha_0_hash_h_4. 0x40 se_sha_0_hash_h_4 0 31 se_sha_0_hash_h_5 se_sha_0_hash_h_5. 0x44 se_sha_0_hash_h_5 0 31 se_sha_0_hash_h_6 se_sha_0_hash_h_6. 0x48 se_sha_0_hash_h_6 0 31 se_sha_0_hash_h_7 se_sha_0_hash_h_7. 0x4C se_sha_0_hash_h_7 0 31 se_sha_0_link se_sha_0_link. 0x50 se_sha_0_lca 0 31 se_sha_0_ctrl_prot se_sha_0_ctrl_prot. 0xFC se_sha_id1_en 2 2 se_sha_id0_en 1 1 se_sha_prot_en 0 0 se_aes_0_ctrl se_aes_0_ctrl. 0x100 se_aes_0_msg_len 16 31 se_aes_0_link_mode 15 15 se_aes_0_iv_sel 14 14 se_aes_0_block_mode 12 13 se_aes_0_int_mask 11 11 se_aes_0_int_set_1t 10 10 se_aes_0_int_clr_1t 9 9 se_aes_0_int 8 8 se_aes_0_hw_key_en 7 7 se_aes_0_dec_key_sel 6 6 se_aes_0_dec_en 5 5 se_aes_0_mode 3 4 se_aes_0_en 2 2 se_aes_0_trig_1t 1 1 se_aes_0_busy 0 0 se_aes_0_msa se_aes_0_msa. 0x104 se_aes_0_msa 0 31 se_aes_0_mda se_aes_0_mda. 0x108 se_aes_0_mda 0 31 se_aes_0_status se_aes_0_status. 0x10C se_aes_0_status 0 31 se_aes_0_iv_0 se_aes_0_iv_0. 0x110 se_aes_0_iv_0 0 31 se_aes_0_iv_1 se_aes_0_iv_1. 0x114 se_aes_0_iv_1 0 31 se_aes_0_iv_2 se_aes_0_iv_2. 0x118 se_aes_0_iv_2 0 31 se_aes_0_iv_3 se_aes_0_iv_3. 0x11C se_aes_0_iv_3 0 31 se_aes_0_key_0 se_aes_0_key_0. 0x120 se_aes_0_key_0 0 31 se_aes_0_key_1 se_aes_0_key_1. 0x124 se_aes_0_key_1 0 31 se_aes_0_key_2 se_aes_0_key_2. 0x128 se_aes_0_key_2 0 31 se_aes_0_key_3 se_aes_0_key_3. 0x12C se_aes_0_key_3 0 31 se_aes_0_key_4 se_aes_0_key_4. 0x130 se_aes_0_key_4 0 31 se_aes_0_key_5 se_aes_0_key_5. 0x134 se_aes_0_key_5 0 31 se_aes_0_key_6 se_aes_0_key_6. 0x138 se_aes_0_key_6 0 31 se_aes_0_key_7 se_aes_0_key_7. 0x13C se_aes_0_key_7 0 31 se_aes_0_key_sel_0 se_aes_0_key_sel_0. 0x140 se_aes_0_key_sel_0 0 1 se_aes_0_key_sel_1 se_aes_0_key_sel_1. 0x144 se_aes_0_key_sel_1 0 1 se_aes_0_endian se_aes_0_endian. 0x148 se_aes_0_ctr_len 30 31 se_aes_0_iv_endian 3 3 se_aes_0_key_endian 2 2 se_aes_0_din_endian 1 1 se_aes_0_dout_endian 0 0 se_aes_0_sboot se_aes_0_sboot. 0x14C se_aes_0_sboot_key_sel 0 0 se_aes_0_link se_aes_0_link. 0x150 se_aes_0_lca 0 31 se_aes_0_ctrl_prot se_aes_0_ctrl_prot. 0x1FC se_aes_id1_en 2 2 se_aes_id0_en 1 1 se_aes_prot_en 0 0 se_trng_0_ctrl_0 se_trng_0_ctrl_0. 0x200 se_trng_0_manual_en 15 15 se_trng_0_manual_reseed 14 14 se_trng_0_manual_fun_sel 13 13 se_trng_0_int_mask 11 11 se_trng_0_int_set_1t 10 10 se_trng_0_int_clr_1t 9 9 se_trng_0_int 8 8 se_trng_0_ht_error 4 4 se_trng_0_dout_clr_1t 3 3 se_trng_0_en 2 2 se_trng_0_trig_1t 1 1 se_trng_0_busy 0 0 se_trng_0_status se_trng_0_status. 0x204 se_trng_0_status 0 31 se_trng_0_dout_0 se_trng_0_dout_0. 0x208 se_trng_0_dout_0 0 31 se_trng_0_dout_1 se_trng_0_dout_1. 0x20C se_trng_0_dout_1 0 31 se_trng_0_dout_2 se_trng_0_dout_2. 0x210 se_trng_0_dout_2 0 31 se_trng_0_dout_3 se_trng_0_dout_3. 0x214 se_trng_0_dout_3 0 31 se_trng_0_dout_4 se_trng_0_dout_4. 0x218 se_trng_0_dout_4 0 31 se_trng_0_dout_5 se_trng_0_dout_5. 0x21C se_trng_0_dout_5 0 31 se_trng_0_dout_6 se_trng_0_dout_6. 0x220 se_trng_0_dout_6 0 31 se_trng_0_dout_7 se_trng_0_dout_7. 0x224 se_trng_0_dout_7 0 31 se_trng_0_test se_trng_0_test. 0x228 se_trng_0_ht_alarm_n 4 11 se_trng_0_ht_dis 3 3 se_trng_0_cp_bypass 2 2 se_trng_0_cp_test_en 1 1 se_trng_0_test_en 0 0 se_trng_0_ctrl_1 se_trng_0_ctrl_1. 0x22C se_trng_0_reseed_n_lsb 0 31 se_trng_0_ctrl_2 se_trng_0_ctrl_2. 0x230 se_trng_0_reseed_n_msb 0 15 se_trng_0_ctrl_3 se_trng_0_ctrl_3. 0x234 se_trng_0_rosc_en 31 31 se_trng_0_ht_od_en 26 26 se_trng_0_ht_apt_c 16 25 se_trng_0_ht_rct_c 8 15 se_trng_0_cp_ratio 0 7 se_trng_0_test_out_0 se_trng_0_test_out_0. 0x240 se_trng_0_test_out_0 0 31 se_trng_0_test_out_1 se_trng_0_test_out_1. 0x244 se_trng_0_test_out_1 0 31 se_trng_0_test_out_2 se_trng_0_test_out_2. 0x248 se_trng_0_test_out_2 0 31 se_trng_0_test_out_3 se_trng_0_test_out_3. 0x24C se_trng_0_test_out_3 0 31 se_trng_0_ctrl_prot se_trng_0_ctrl_prot. 0x2FC se_trng_id1_en 2 2 se_trng_id0_en 1 1 se_trng_prot_en 0 0 se_pka_0_ctrl_0 se_pka_0_ctrl_0. 0x300 se_pka_0_status 16 31 se_pka_0_status_clr_1t 15 15 se_pka_0_ram_clr_md 13 13 se_pka_0_endian 12 12 se_pka_0_int_mask 11 11 se_pka_0_int_set 10 10 se_pka_0_int_clr_1t 9 9 se_pka_0_int 8 8 se_pka_0_prot_md 4 7 se_pka_0_en 3 3 se_pka_0_busy 2 2 se_pka_0_done_clr_1t 1 1 se_pka_0_done 0 0 se_pka_0_seed se_pka_0_seed. 0x30C se_pka_0_seed 0 31 se_pka_0_ctrl_1 se_pka_0_ctrl_1. 0x310 se_pka_0_hbypass 3 3 se_pka_0_hburst 0 2 se_pka_0_rw se_pka_0_rw. 0x340 se_pka_0_rw_burst se_pka_0_rw_burst. 0x360 se_pka_0_ctrl_prot se_pka_0_ctrl_prot. 0x3FC se_pka_id1_en 2 2 se_pka_id0_en 1 1 se_pka_prot_en 0 0 se_cdet_0_ctrl_0 se_cdet_0_ctrl_0. 0x400 se_cdet_0_g_loop_min 24 31 se_cdet_0_g_loop_max 16 23 se_cdet_0_status 2 15 se_cdet_0_error 1 1 se_cdet_0_en 0 0 se_cdet_0_ctrl_1 se_cdet_0_ctrl_1. 0x404 se_cdet_0_g_slp_n 16 23 se_cdet_0_t_dly_n 8 15 se_cdet_0_t_loop_n 0 7 se_cdet_0_ctrl_prot se_cdet_0_ctrl_prot. 0x4FC se_cdet_id1_en 2 2 se_cdet_id0_en 1 1 se_cdet_prot_en 0 0 se_gmac_0_ctrl_0 se_gmac_0_ctrl_0. 0x500 se_gmac_0_x_endian 14 14 se_gmac_0_h_endian 13 13 se_gmac_0_t_endian 12 12 se_gmac_0_int_mask 11 11 se_gmac_0_int_set_1t 10 10 se_gmac_0_int_clr_1t 9 9 se_gmac_0_int 8 8 se_gmac_0_en 2 2 se_gmac_0_trig_1t 1 1 se_gmac_0_busy 0 0 se_gmac_0_lca se_gmac_0_lca. 0x504 se_gmac_0_lca 0 31 se_gmac_0_status se_gmac_0_status. 0x508 se_gmac_0_status 0 31 se_gmac_0_ctrl_prot se_gmac_0_ctrl_prot. 0x5FC se_gmac_id1_en 2 2 se_gmac_id0_en 1 1 se_gmac_prot_en 0 0 se_ctrl_prot_rd se_ctrl_prot_rd. 0xF00 se_dbg_dis 31 31 se_gmac_id1_en_rd 22 22 se_gmac_id0_en_rd 21 21 se_gmac_prot_en_rd 20 20 se_cdet_id1_en_rd 18 18 se_cdet_id0_en_rd 17 17 se_cdet_prot_en_rd 16 16 se_pka_id1_en_rd 14 14 se_pka_id0_en_rd 13 13 se_pka_prot_en_rd 12 12 se_trng_id1_en_rd 10 10 se_trng_id0_en_rd 9 9 se_trng_prot_en_rd 8 8 se_aes_id1_en_rd 6 6 se_aes_id0_en_rd 5 5 se_aes_prot_en_rd 4 4 se_sha_id1_en_rd 2 2 se_sha_id0_en_rd 1 1 se_sha_prot_en_rd 0 0 se_ctrl_reserved_0 se_ctrl_reserved_0. 0xF04 se_ctrl_reserved_0 0 31 se_ctrl_reserved_1 se_ctrl_reserved_1. 0xF08 se_ctrl_reserved_1 0 31 se_ctrl_reserved_2 se_ctrl_reserved_2. 0xF0C se_ctrl_reserved_2 0 31 tzc_sec tzc_sec. tzc_sec 0x40005000 0x20 read-write 0x0 0x1000 registers tzc_rom_ctrl tzc_rom_ctrl. 0x40 tzc_sboot_done 28 31 tzc_rom1_r1_lock 27 27 tzc_rom1_r0_lock 26 26 tzc_rom0_r1_lock 25 25 tzc_rom0_r0_lock 24 24 tzc_rom1_r1_en 19 19 tzc_rom1_r0_en 18 18 tzc_rom0_r1_en 17 17 tzc_rom0_r0_en 16 16 tzc_rom1_r1_id1_en 11 11 tzc_rom1_r0_id1_en 10 10 tzc_rom0_r1_id1_en 9 9 tzc_rom0_r0_id1_en 8 8 tzc_rom1_r1_id0_en 3 3 tzc_rom1_r0_id0_en 2 2 tzc_rom0_r1_id0_en 1 1 tzc_rom0_r0_id0_en 0 0 tzc_rom0_r0 tzc_rom0_r0. 0x44 tzc_rom0_r0_start 16 31 tzc_rom0_r0_end 0 15 tzc_rom0_r1 tzc_rom0_r1. 0x48 tzc_rom0_r1_start 16 31 tzc_rom0_r1_end 0 15 tzc_rom1_r0 tzc_rom1_r0. 0x4C tzc_rom1_r0_start 16 31 tzc_rom1_r0_end 0 15 tzc_rom1_r1 tzc_rom1_r1. 0x50 tzc_rom1_r1_start 16 31 tzc_rom1_r1_end 0 15 tzc_nsec tzc_nsec. tzc_nsec 0x40006000 0x20 read-write 0x0 0x1000 registers tzc_rom_ctrl tzc_rom_ctrl. 0x40 tzc_sboot_done 28 31 tzc_rom1_r1_lock 27 27 tzc_rom1_r0_lock 26 26 tzc_rom0_r1_lock 25 25 tzc_rom0_r0_lock 24 24 tzc_rom1_r1_en 19 19 tzc_rom1_r0_en 18 18 tzc_rom0_r1_en 17 17 tzc_rom0_r0_en 16 16 tzc_rom1_r1_id1_en 11 11 tzc_rom1_r0_id1_en 10 10 tzc_rom0_r1_id1_en 9 9 tzc_rom0_r0_id1_en 8 8 tzc_rom1_r1_id0_en 3 3 tzc_rom1_r0_id0_en 2 2 tzc_rom0_r1_id0_en 1 1 tzc_rom0_r0_id0_en 0 0 tzc_rom0_r0 tzc_rom0_r0. 0x44 tzc_rom0_r0_start 16 31 tzc_rom0_r0_end 0 15 tzc_rom0_r1 tzc_rom0_r1. 0x48 tzc_rom0_r1_start 16 31 tzc_rom0_r1_end 0 15 tzc_rom1_r0 tzc_rom1_r0. 0x4C tzc_rom1_r0_start 16 31 tzc_rom1_r0_end 0 15 tzc_rom1_r1 tzc_rom1_r1. 0x50 tzc_rom1_r1_start 16 31 tzc_rom1_r1_end 0 15 ef_data_0 ef_data_0. ef_data_0 0x40007000 0x20 read-write 0x0 0x1000 registers ef_cfg_0 ef_cfg_0. 0x0 ef_dbg_mode 28 31 ef_dbg_jtag_0_dis 26 27 ef_dbg_jtag_1_dis 24 25 ef_efuse_dbg_dis 23 23 ef_se_dbg_dis 22 22 ef_cpu_rst_dbg_dis 21 21 ef_cpu1_dis 20 20 ef_sf_dis 19 19 ef_cam_dis 18 18 ef_0_key_enc_en 17 17 ef_wifi_dis 16 16 ef_ble_dis 15 15 ef_sdu_dis 14 14 ef_sf_key_0_sel 12 13 ef_boot_sel 8 11 ef_cpu0_enc_en 7 7 ef_cpu1_enc_en 6 6 ef_sboot_en 4 5 ef_sboot_sign_mode 2 3 ef_sf_aes_mode 0 1 ef_dbg_pwd_low ef_dbg_pwd_low. 0x4 ef_dbg_pwd_low 0 31 ef_dbg_pwd_high ef_dbg_pwd_high. 0x8 ef_dbg_pwd_high 0 31 ef_ana_trim_0 ef_ana_trim_0. 0xC ef_ana_trim_0 0 31 ef_sw_usage_0 ef_sw_usage_0. 0x10 ef_sw_usage_0 0 31 ef_wifi_mac_low ef_wifi_mac_low. 0x14 ef_wifi_mac_low 0 31 ef_wifi_mac_high ef_wifi_mac_high. 0x18 ef_wifi_mac_high 0 31 ef_key_slot_0_w0 ef_key_slot_0_w0. 0x1C ef_key_slot_0_w0 0 31 ef_key_slot_0_w1 ef_key_slot_0_w1. 0x20 ef_key_slot_0_w1 0 31 ef_key_slot_0_w2 ef_key_slot_0_w2. 0x24 ef_key_slot_0_w2 0 31 ef_key_slot_0_w3 ef_key_slot_0_w3. 0x28 ef_key_slot_0_w3 0 31 ef_key_slot_1_w0 ef_key_slot_1_w0. 0x2C ef_key_slot_1_w0 0 31 ef_key_slot_1_w1 ef_key_slot_1_w1. 0x30 ef_key_slot_1_w1 0 31 ef_key_slot_1_w2 ef_key_slot_1_w2. 0x34 ef_key_slot_1_w2 0 31 ef_key_slot_1_w3 ef_key_slot_1_w3. 0x38 ef_key_slot_1_w3 0 31 ef_key_slot_2_w0 ef_key_slot_2_w0. 0x3C ef_key_slot_2_w0 0 31 ef_key_slot_2_w1 ef_key_slot_2_w1. 0x40 ef_key_slot_2_w1 0 31 ef_key_slot_2_w2 ef_key_slot_2_w2. 0x44 ef_key_slot_2_w2 0 31 ef_key_slot_2_w3 ef_key_slot_2_w3. 0x48 ef_key_slot_2_w3 0 31 ef_key_slot_3_w0 ef_key_slot_3_w0. 0x4C ef_key_slot_3_w0 0 31 ef_key_slot_3_w1 ef_key_slot_3_w1. 0x50 ef_key_slot_3_w1 0 31 ef_key_slot_3_w2 ef_key_slot_3_w2. 0x54 ef_key_slot_3_w2 0 31 ef_key_slot_3_w3 ef_key_slot_3_w3. 0x58 ef_key_slot_3_w3 0 31 ef_key_slot_4_w0 ef_key_slot_4_w0. 0x5C ef_key_slot_4_w0 0 31 ef_key_slot_4_w1 ef_key_slot_4_w1. 0x60 ef_key_slot_4_w1 0 31 ef_key_slot_4_w2 ef_key_slot_4_w2. 0x64 ef_key_slot_4_w2 0 31 ef_key_slot_4_w3 ef_key_slot_4_w3. 0x68 ef_key_slot_4_w3 0 31 ef_key_slot_5_w0 ef_key_slot_5_w0. 0x6C ef_key_slot_5_w0 0 31 ef_key_slot_5_w1 ef_key_slot_5_w1. 0x70 ef_key_slot_5_w1 0 31 ef_key_slot_5_w2 ef_key_slot_5_w2. 0x74 ef_key_slot_5_w2 0 31 ef_key_slot_5_w3 ef_key_slot_5_w3. 0x78 ef_key_slot_5_w3 0 31 ef_data_0_lock ef_data_0_lock. 0x7C rd_lock_key_slot_5 31 31 rd_lock_key_slot_4 30 30 rd_lock_key_slot_3 29 29 rd_lock_key_slot_2 28 28 rd_lock_key_slot_1 27 27 rd_lock_key_slot_0 26 26 rd_lock_dbg_pwd 25 25 wr_lock_key_slot_5_h 24 24 wr_lock_key_slot_4_h 23 23 wr_lock_key_slot_3 22 22 wr_lock_key_slot_2 21 21 wr_lock_key_slot_1 20 20 wr_lock_key_slot_0 19 19 wr_lock_wifi_mac 18 18 wr_lock_sw_usage_0 17 17 wr_lock_dbg_pwd 16 16 wr_lock_boot_mode 15 15 wr_lock_key_slot_5_l 14 14 wr_lock_key_slot_4_l 13 13 ef_ana_trim_1 0 12 ef_data_1 ef_data_1. ef_data_1 0x40007000 0x20 read-write 0x0 0x1000 registers reg_key_slot_6_w0 reg_key_slot_6_w0. 0x80 reg_key_slot_6_w0 0 31 reg_key_slot_6_w1 reg_key_slot_6_w1. 0x84 reg_key_slot_6_w1 0 31 reg_key_slot_6_w2 reg_key_slot_6_w2. 0x88 reg_key_slot_6_w2 0 31 reg_key_slot_6_w3 reg_key_slot_6_w3. 0x8C reg_key_slot_6_w3 0 31 reg_key_slot_7_w0 reg_key_slot_7_w0. 0x90 reg_key_slot_7_w0 0 31 reg_key_slot_7_w1 reg_key_slot_7_w1. 0x94 reg_key_slot_7_w1 0 31 reg_key_slot_7_w2 reg_key_slot_7_w2. 0x98 reg_key_slot_7_w2 0 31 reg_key_slot_7_w3 reg_key_slot_7_w3. 0x9C reg_key_slot_7_w3 0 31 reg_key_slot_8_w0 reg_key_slot_8_w0. 0xA0 reg_key_slot_8_w0 0 31 reg_key_slot_8_w1 reg_key_slot_8_w1. 0xA4 reg_key_slot_8_w1 0 31 reg_key_slot_8_w2 reg_key_slot_8_w2. 0xA8 reg_key_slot_8_w2 0 31 reg_key_slot_8_w3 reg_key_slot_8_w3. 0xAC reg_key_slot_8_w3 0 31 reg_key_slot_9_w0 reg_key_slot_9_w0. 0xB0 reg_key_slot_9_w0 0 31 reg_key_slot_9_w1 reg_key_slot_9_w1. 0xB4 reg_key_slot_9_w1 0 31 reg_key_slot_9_w2 reg_key_slot_9_w2. 0xB8 reg_key_slot_9_w2 0 31 reg_key_slot_9_w3 reg_key_slot_9_w3. 0xBC reg_key_slot_9_w3 0 31 reg_key_slot_10_w0 reg_key_slot_10_w0. 0xC0 reg_key_slot_10_w1 reg_key_slot_10_w1. 0xC4 reg_key_slot_10_w2 reg_key_slot_10_w2. 0xC8 reg_key_slot_10_w3 reg_key_slot_10_w3. 0xCC reg_key_slot_11_w0 reg_key_slot_11_w0. 0xD0 reg_key_slot_11_w1 reg_key_slot_11_w1. 0xD4 reg_key_slot_11_w2 reg_key_slot_11_w2. 0xD8 reg_key_slot_11_w3 reg_key_slot_11_w3. 0xDC reg_data_1_lock reg_data_1_lock. 0xE0 rd_lock_key_slot_9 29 29 rd_lock_key_slot_8 28 28 rd_lock_key_slot_7 27 27 rd_lock_key_slot_6 26 26 RESERVED_25_16 16 25 wr_lock_key_slot_9 13 13 wr_lock_key_slot_8 12 12 wr_lock_key_slot_7 11 11 wr_lock_key_slot_6 10 10 RESERVED_9_0 0 9 ef_ctrl eFuse memory control ef_ctrl 0x40007000 0x20 read-write 0x0 0x1000 registers ef_if_ctrl_0 ef_if_ctrl_0. 0x800 ef_if_prot_code_cyc 24 31 ef_if_0_int_set 22 22 ef_if_0_int_clr 21 21 ef_if_0_int 20 20 ef_if_cyc_modify_lock 19 19 ef_if_auto_rd_en 18 18 ef_clk_sahb_data_gate 17 17 ef_if_por_dig 16 16 ef_if_prot_code_ctrl 8 15 ef_clk_sahb_data_sel 7 7 ef_if_0_cyc_modify 6 6 ef_if_0_manual_en 5 5 ef_if_0_trig 4 4 ef_if_0_rw 3 3 ef_if_0_busy 2 2 ef_if_0_autoload_done 1 1 ef_if_0_autoload_p1_done 0 0 ef_if_cyc_0 ef_if_cyc_0. 0x804 ef_if_cyc_pd_cs_s 24 31 ef_if_cyc_cs 18 23 ef_if_cyc_rd_adr 12 17 ef_if_cyc_rd_dat 6 11 ef_if_cyc_rd_dmy 0 5 ef_if_cyc_1 ef_if_cyc_1. 0x808 ef_if_cyc_pd_cs_h 26 31 ef_if_cyc_ps_cs 20 25 ef_if_cyc_wr_adr 14 19 ef_if_cyc_pp 6 13 ef_if_cyc_pi 0 5 ef_if_0_manual ef_if_0_manual. 0x80C ef_if_prot_code_manual 24 31 ef_if_0_q 16 23 ef_if_csb 15 15 ef_if_load 14 14 ef_if_pgenb 13 13 ef_if_strobe 12 12 ef_if_ps 11 11 ef_if_pd 10 10 ef_if_a 0 9 ef_if_0_status ef_if_0_status. 0x810 ef_if_0_status 0 31 ef_if_cfg_0 ef_if_cfg_0. 0x814 ef_if_dbg_mode 28 31 ef_if_dbg_jtag_0_dis 26 27 ef_if_dbg_jtag_1_dis 24 25 ef_if_efuse_dbg_dis 23 23 ef_if_se_dbg_dis 22 22 ef_if_cpu_rst_dbg_dis 21 21 ef_if_cpu1_dis 20 20 ef_if_sf_dis 19 19 ef_if_cam_dis 18 18 ef_if_0_key_enc_en 17 17 ef_if_wifi_dis 16 16 ef_if_ble_dis 15 15 ef_if_sdu_dis 14 14 ef_if_sf_key_0_sel 12 13 ef_if_boot_sel 8 11 ef_if_cpu0_enc_en 7 7 ef_if_cpu1_enc_en 6 6 ef_if_sboot_en 4 5 ef_if_sboot_sign_mode 2 3 ef_if_sf_aes_mode 0 1 ef_sw_cfg_0 ef_sw_cfg_0. 0x818 ef_sw_dbg_mode 28 31 ef_sw_dbg_jtag_0_dis 26 27 ef_sw_dbg_jtag_1_dis 24 25 ef_sw_efuse_dbg_dis 23 23 ef_sw_se_dbg_dis 22 22 ef_sw_cpu_rst_dbg_dis 21 21 ef_sw_cpu1_dis 20 20 ef_sw_sf_dis 19 19 ef_sw_cam_dis 18 18 ef_sw_0_key_enc_en 17 17 ef_sw_wifi_dis 16 16 ef_sw_ble_dis 15 15 ef_sw_sdu_dis 14 14 ef_sw_sf_key_0_sel 12 13 ef_sw_cpu0_enc_en 7 7 ef_sw_cpu1_enc_en 6 6 ef_sw_sboot_en 4 5 ef_sw_sboot_sign_mode 2 3 ef_sw_sf_aes_mode 0 1 ef_reserved ef_reserved. 0x81C ef_reserved 0 31 ef_if_ana_trim_0 ef_if_ana_trim_0. 0x820 ef_if_ana_trim_0 0 31 ef_if_sw_usage_0 ef_if_sw_usage_0. 0x824 ef_if_sw_usage_0 0 31 ef_crc_ctrl_0 ef_crc_ctrl_0. 0xA00 ef_crc_slp_n 16 31 ef_crc_lock 11 11 ef_crc_int_set 10 10 ef_crc_int_clr 9 9 ef_crc_int 8 8 ef_crc_din_endian 7 7 ef_crc_dout_endian 6 6 ef_crc_dout_inv_en 5 5 ef_crc_error 4 4 ef_crc_mode 3 3 ef_crc_en 2 2 ef_crc_trig 1 1 ef_crc_busy 0 0 ef_crc_ctrl_1 ef_crc_ctrl_1. 0xA04 ef_crc_data_0_en 0 31 ef_crc_ctrl_2 ef_crc_ctrl_2. 0xA08 ef_crc_data_1_en 0 31 ef_crc_ctrl_3 ef_crc_ctrl_3. 0xA0C ef_crc_iv 0 31 ef_crc_ctrl_4 ef_crc_ctrl_4. 0xA10 ef_crc_golden 0 31 ef_crc_ctrl_5 ef_crc_ctrl_5. 0xA14 ef_crc_dout 0 31 cci cci. cci 0x40008000 0x20 read-write 0x0 0x1000 registers cci_cfg cci_cfg. 0x0 reg_mcci_clk_inv 9 9 reg_scci_clk_inv 8 8 cfg_cci1_pre_read 7 7 reg_div_m_cci_sclk 5 6 reg_m_cci_sclk_en 4 4 cci_mas_hw_mode 3 3 cci_mas_sel_cci2 2 2 cci_slv_sel_cci2 1 1 cci_en 0 0 cci_addr cci_addr. 0x4 apb_cci_addr 0 31 cci_wdata cci_wdata. 0x8 apb_cci_wdata 0 31 cci_rdata cci_rdata. 0xC apb_cci_rdata 0 31 cci_ctl cci_ctl. 0x10 ahb_state 2 3 cci_read_flag 1 1 cci_write_flag 0 0 l1c L1 Cache control l1c 0x40009000 0x20 read-write 0x0 0x1000 registers l1c_config l1c_config. 0x0 reserved_31_30 30 31 l1c_flush_done 29 29 l1c_flush_en 28 28 wrap_dis 26 26 early_resp_dis 25 25 l1c_bmx_busy_option_dis 24 24 l1c_bmx_timeout_en 20 23 l1c_bmx_arb_mode 16 17 l1c_bmx_err_en 15 15 l1c_bypass 14 14 irom_2t_access 12 12 l1c_way_dis 8 11 l1c_wa_en 6 6 l1c_wb_en 5 5 l1c_wt_en 4 4 l1c_invalid_done 3 3 l1c_invalid_en 2 2 l1c_cnt_en 1 1 l1c_cacheable 0 0 hit_cnt_lsb hit_cnt_lsb. 0x4 hit_cnt_lsb 0 31 hit_cnt_msb hit_cnt_msb. 0x8 hit_cnt_msb 0 31 miss_cnt miss_cnt. 0xC miss_cnt 0 31 l1c_misc l1c_misc. 0x10 l1c_fsm 28 30 l1c_bmx_err_addr_en l1c_bmx_err_addr_en. 0x200 l1c_hsel_option 16 19 l1c_bmx_err_tz 5 5 l1c_bmx_err_dec 4 4 l1c_bmx_err_addr_dis 0 0 l1c_bmx_err_addr l1c_bmx_err_addr. 0x204 l1c_bmx_err_addr 0 31 irom1_misr_dataout_0 irom1_misr_dataout_0. 0x208 irom1_misr_dataout_0 0 31 irom1_misr_dataout_1 irom1_misr_dataout_1. 0x20C irom1_misr_dataout_1 0 31 cpu_clk_gate cpu_clk_gate. 0x210 force_e21_clock_on_2 2 2 force_e21_clock_on_1 1 1 force_e21_clock_on_0 0 0 uart uart. uart 0x4000A000 0x20 read-write 0x0 0x1000 registers utx_config utx_config. 0x0 cr_utx_len 16 31 cr_utx_bit_cnt_b 13 15 cr_utx_bit_cnt_p 11 12 cr_utx_bit_cnt_d 8 10 cr_utx_ir_inv 7 7 cr_utx_ir_en 6 6 cr_utx_prt_sel 5 5 cr_utx_prt_en 4 4 cr_utx_lin_en 3 3 cr_utx_frm_en 2 2 cr_utx_cts_en 1 1 cr_utx_en 0 0 urx_config urx_config. 0x4 cr_urx_len 16 31 cr_urx_deg_cnt 12 15 cr_urx_deg_en 11 11 cr_urx_bit_cnt_d 8 10 cr_urx_ir_inv 7 7 cr_urx_ir_en 6 6 cr_urx_prt_sel 5 5 cr_urx_prt_en 4 4 cr_urx_lin_en 3 3 cr_urx_abr_en 1 1 cr_urx_en 0 0 uart_bit_prd uart_bit_prd. 0x8 cr_urx_bit_prd 16 31 cr_utx_bit_prd 0 15 data_config data_config. 0xC cr_uart_bit_inv 0 0 utx_ir_position utx_ir_position. 0x10 cr_utx_ir_pos_p 16 31 cr_utx_ir_pos_s 0 15 urx_ir_position urx_ir_position. 0x14 cr_urx_ir_pos_s 0 15 urx_rto_timer urx_rto_timer. 0x18 cr_urx_rto_value 0 7 uart_sw_mode uart_sw_mode. 0x1C cr_urx_rts_sw_val 3 3 cr_urx_rts_sw_mode 2 2 cr_utx_txd_sw_val 1 1 cr_utx_txd_sw_mode 0 0 uart_int_sts UART interrupt status 0x20 urx_lse_int 8 8 urx_fer_int 7 7 utx_fer_int 6 6 urx_pce_int 5 5 urx_rto_int 4 4 urx_fifo_int 3 3 utx_fifo_int 2 2 urx_end_int 1 1 utx_end_int 0 0 uart_int_mask UART interrupt mask 0x24 cr_urx_lse_mask 8 8 cr_urx_fer_mask 7 7 cr_utx_fer_mask 6 6 cr_urx_pce_mask 5 5 cr_urx_rto_mask 4 4 cr_urx_fifo_mask 3 3 cr_utx_fifo_mask 2 2 cr_urx_end_mask 1 1 cr_utx_end_mask 0 0 uart_int_clear UART interrupt clear 0x28 cr_urx_lse_clr 8 8 rsvd_7 7 7 rsvd_6 6 6 cr_urx_pce_clr 5 5 cr_urx_rto_clr 4 4 rsvd_3 3 3 rsvd_2 2 2 cr_urx_end_clr 1 1 cr_utx_end_clr 0 0 uart_int_en UART interrupt enable 0x2C cr_urx_lse_en 8 8 cr_urx_fer_en 7 7 cr_utx_fer_en 6 6 cr_urx_pce_en 5 5 cr_urx_rto_en 4 4 cr_urx_fifo_en 3 3 cr_utx_fifo_en 2 2 cr_urx_end_en 1 1 cr_utx_end_en 0 0 uart_status uart_status. 0x30 sts_urx_bus_busy 1 1 sts_utx_bus_busy 0 0 sts_urx_abr_prd sts_urx_abr_prd. 0x34 sts_urx_abr_prd_0x55 16 31 sts_urx_abr_prd_start 0 15 uart_fifo_config_0 uart_fifo_config_0. 0x80 rx_fifo_underflow 7 7 rx_fifo_overflow 6 6 tx_fifo_underflow 5 5 tx_fifo_overflow 4 4 rx_fifo_clr 3 3 tx_fifo_clr 2 2 uart_dma_rx_en 1 1 uart_dma_tx_en 0 0 uart_fifo_config_1 uart_fifo_config_1. 0x84 rx_fifo_th 24 30 tx_fifo_th 16 22 rx_fifo_cnt 8 15 tx_fifo_cnt 0 7 uart_fifo_wdata uart_fifo_wdata. 0x88 uart_fifo_wdata 0 7 uart_fifo_rdata uart_fifo_rdata. 0x8C uart_fifo_rdata 0 7 spi spi. spi 0x4000A200 0x20 read-write 0x0 0x1000 registers spi_config spi_config. 0x0 cr_spi_deg_cnt 12 15 cr_spi_deg_en 11 11 cr_spi_m_cont_en 9 9 cr_spi_rxd_ignr_en 8 8 cr_spi_byte_inv 7 7 cr_spi_bit_inv 6 6 cr_spi_sclk_ph 5 5 cr_spi_sclk_pol 4 4 cr_spi_frame_size 2 3 cr_spi_s_en 1 1 cr_spi_m_en 0 0 spi_int_sts spi_int_sts. 0x4 cr_spi_fer_en 29 29 cr_spi_txu_en 28 28 cr_spi_sto_en 27 27 cr_spi_rxf_en 26 26 cr_spi_txf_en 25 25 cr_spi_end_en 24 24 rsvd_21 21 21 cr_spi_txu_clr 20 20 cr_spi_sto_clr 19 19 rsvd_18 18 18 rsvd_17 17 17 cr_spi_end_clr 16 16 cr_spi_fer_mask 13 13 cr_spi_txu_mask 12 12 cr_spi_sto_mask 11 11 cr_spi_rxf_mask 10 10 cr_spi_txf_mask 9 9 cr_spi_end_mask 8 8 spi_fer_int 5 5 spi_txu_int 4 4 spi_sto_int 3 3 spi_rxf_int 2 2 spi_txf_int 1 1 spi_end_int 0 0 spi_bus_busy spi_bus_busy. 0x8 sts_spi_bus_busy 0 0 spi_prd_0 spi_prd_0. 0x10 cr_spi_prd_d_ph_1 24 31 cr_spi_prd_d_ph_0 16 23 cr_spi_prd_p 8 15 cr_spi_prd_s 0 7 spi_prd_1 spi_prd_1. 0x14 cr_spi_prd_i 0 7 spi_rxd_ignr spi_rxd_ignr. 0x18 cr_spi_rxd_ignr_s 16 20 cr_spi_rxd_ignr_p 0 4 spi_sto_value spi_sto_value. 0x1C cr_spi_sto_value 0 11 spi_fifo_config_0 spi_fifo_config_0. 0x80 rx_fifo_underflow 7 7 rx_fifo_overflow 6 6 tx_fifo_underflow 5 5 tx_fifo_overflow 4 4 rx_fifo_clr 3 3 tx_fifo_clr 2 2 spi_dma_rx_en 1 1 spi_dma_tx_en 0 0 spi_fifo_config_1 spi_fifo_config_1. 0x84 rx_fifo_th 24 25 tx_fifo_th 16 17 rx_fifo_cnt 8 10 tx_fifo_cnt 0 2 spi_fifo_wdata spi_fifo_wdata. 0x88 spi_fifo_wdata 0 31 spi_fifo_rdata spi_fifo_rdata. 0x8C spi_fifo_rdata 0 31 i2c i2c. i2c 0x4000A300 0x20 read-write 0x0 0x1000 registers i2c_config i2c_config. 0x0 cr_i2c_deg_cnt 28 31 cr_i2c_pkt_len 16 23 cr_i2c_slv_addr 8 14 cr_i2c_sub_addr_bc 5 6 cr_i2c_sub_addr_en 4 4 cr_i2c_scl_sync_en 3 3 cr_i2c_deg_en 2 2 cr_i2c_pkt_dir 1 1 cr_i2c_m_en 0 0 i2c_int_sts i2c_int_sts. 0x4 cr_i2c_fer_en 29 29 cr_i2c_arb_en 28 28 cr_i2c_nak_en 27 27 cr_i2c_rxf_en 26 26 cr_i2c_txf_en 25 25 cr_i2c_end_en 24 24 rsvd_21 21 21 cr_i2c_arb_clr 20 20 cr_i2c_nak_clr 19 19 rsvd_18 18 18 rsvd_17 17 17 cr_i2c_end_clr 16 16 cr_i2c_fer_mask 13 13 cr_i2c_arb_mask 12 12 cr_i2c_nak_mask 11 11 cr_i2c_rxf_mask 10 10 cr_i2c_txf_mask 9 9 cr_i2c_end_mask 8 8 i2c_fer_int 5 5 i2c_arb_int 4 4 i2c_nak_int 3 3 i2c_rxf_int 2 2 i2c_txf_int 1 1 i2c_end_int 0 0 i2c_sub_addr i2c_sub_addr. 0x8 cr_i2c_sub_addr_b3 24 31 cr_i2c_sub_addr_b2 16 23 cr_i2c_sub_addr_b1 8 15 cr_i2c_sub_addr_b0 0 7 i2c_bus_busy i2c_bus_busy. 0xC cr_i2c_bus_busy_clr 1 1 sts_i2c_bus_busy 0 0 i2c_prd_start i2c_prd_start. 0x10 cr_i2c_prd_s_ph_3 24 31 cr_i2c_prd_s_ph_2 16 23 cr_i2c_prd_s_ph_1 8 15 cr_i2c_prd_s_ph_0 0 7 i2c_prd_stop i2c_prd_stop. 0x14 cr_i2c_prd_p_ph_3 24 31 cr_i2c_prd_p_ph_2 16 23 cr_i2c_prd_p_ph_1 8 15 cr_i2c_prd_p_ph_0 0 7 i2c_prd_data i2c_prd_data. 0x18 cr_i2c_prd_d_ph_3 24 31 cr_i2c_prd_d_ph_2 16 23 cr_i2c_prd_d_ph_1 8 15 cr_i2c_prd_d_ph_0 0 7 i2c_fifo_config_0 i2c_fifo_config_0. 0x80 rx_fifo_underflow 7 7 rx_fifo_overflow 6 6 tx_fifo_underflow 5 5 tx_fifo_overflow 4 4 rx_fifo_clr 3 3 tx_fifo_clr 2 2 i2c_dma_rx_en 1 1 i2c_dma_tx_en 0 0 i2c_fifo_config_1 i2c_fifo_config_1. 0x84 rx_fifo_th 24 24 tx_fifo_th 16 16 rx_fifo_cnt 8 9 tx_fifo_cnt 0 1 i2c_fifo_wdata i2c_fifo_wdata. 0x88 i2c_fifo_wdata 0 31 i2c_fifo_rdata i2c_fifo_rdata. 0x8C i2c_fifo_rdata 0 31 pwm pwm. pwm 0x4000A400 0x20 read-write 0x0 0x1000 registers pwm_int_config pwm_int_config. 0x0 pwm_int_clear 8 13 pwm_interrupt_sts 0 5 pwm0_clkdiv pwm0_clkdiv. 0x20 pwm_clk_div 0 15 pwm0_thre1 pwm0_thre1. 0x24 pwm_thre1 0 15 pwm0_thre2 pwm0_thre2. 0x28 pwm_thre2 0 15 pwm0_period pwm0_period. 0x2C pwm_period 0 15 pwm0_config pwm0_config. 0x30 pwm_sts_top 7 7 pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm0_interrupt pwm0_interrupt. 0x34 pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm1_clkdiv pwm1_clkdiv. 0x40 pwm_clk_div 0 15 pwm1_thre1 pwm1_thre1. 0x44 pwm_thre1 0 15 pwm1_thre2 pwm1_thre2. 0x48 pwm_thre2 0 15 pwm1_period pwm1_period. 0x4C pwm_period 0 15 pwm1_config pwm1_config. 0x50 pwm_sts_top 7 7 pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm1_interrupt pwm1_interrupt. 0x54 pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm2_clkdiv pwm2_clkdiv. 0x60 pwm_clk_div 0 15 pwm2_thre1 pwm2_thre1. 0x64 pwm_thre1 0 15 pwm2_thre2 pwm2_thre2. 0x68 pwm_thre2 0 15 pwm2_period pwm2_period. 0x6C pwm_period 0 15 pwm2_config pwm2_config. 0x70 pwm_sts_top 7 7 pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm2_interrupt pwm2_interrupt. 0x74 pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm3_clkdiv pwm3_clkdiv. 0x80 pwm_clk_div 0 15 pwm3_thre1 pwm3_thre1. 0x84 pwm_thre1 0 15 pwm3_thre2 pwm3_thre2. 0x88 pwm_thre2 0 15 pwm3_period pwm3_period. 0x8C pwm_period 0 15 pwm3_config pwm3_config. 0x90 pwm_sts_top 7 7 pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm3_interrupt pwm3_interrupt. 0x94 pwm_int_enable 16 16 pwm_int_period_cnt 0 15 pwm4_clkdiv pwm4_clkdiv. 0xA0 pwm_clk_div 0 15 pwm4_thre1 pwm4_thre1. 0xA4 pwm_thre1 0 15 pwm4_thre2 pwm4_thre2. 0xA8 pwm_thre2 0 15 pwm4_period pwm4_period. 0xAC pwm_period 0 15 pwm4_config pwm4_config. 0xB0 pwm_sts_top 7 7 pwm_stop_en 6 6 pwm_sw_mode 5 5 pwm_sw_force_val 4 4 pwm_stop_mode 3 3 pwm_out_inv 2 2 reg_clk_sel 0 1 pwm4_interrupt pwm4_interrupt. 0xB4 pwm_int_enable 16 16 pwm_int_period_cnt 0 15 timer timer. timer 0x4000A500 0x20 read-write 0x0 0x1000 registers TCCR TCCR. 0x0 cs_wdt 8 9 RESERVED_7 7 7 cs_2 5 6 RESERVED_4 4 4 cs_1 2 3 TMR2_0 TMR2_0. 0x10 tmr 0 31 TMR2_1 TMR2_1. 0x14 tmr 0 31 TMR2_2 TMR2_2. 0x18 tmr 0 31 TMR3_0 TMR3_0. 0x1C tmr 0 31 TMR3_1 TMR3_1. 0x20 tmr 0 31 TMR3_2 TMR3_2. 0x24 tmr 0 31 TCR2 TCR2. 0x2C tcr 0 31 TCR3 TCR3. 0x30 tcr 0 31 TMSR2 TMSR2. 0x38 tmsr_2 2 2 tmsr_1 1 1 tmsr_0 0 0 TMSR3 TMSR3. 0x3C tmsr_2 2 2 tmsr_1 1 1 tmsr_0 0 0 TIER2 TIER2. 0x44 tier_2 2 2 tier_1 1 1 tier_0 0 0 TIER3 TIER3. 0x48 tier_2 2 2 tier_1 1 1 tier_0 0 0 TPLVR2 TPLVR2. 0x50 tplvr 0 31 TPLVR3 TPLVR3. 0x54 tplvr 0 31 TPLCR2 TPLCR2. 0x5C tplcr 0 1 TPLCR3 TPLCR3. 0x60 tplcr 0 1 WMER WMER. 0x64 wrie 1 1 we 0 0 WMR WMR. 0x68 wmr 0 15 WVR WVR. 0x6C wvr 0 15 WSR WSR. 0x70 wts 0 0 TICR2 TICR2. 0x78 tclr_2 2 2 tclr_1 1 1 tclr_0 0 0 TICR3 TICR3. 0x7C tclr_2 2 2 tclr_1 1 1 tclr_0 0 0 WICR WICR. 0x80 wiclr 0 0 TCER TCER. 0x84 timer3_en 2 2 timer2_en 1 1 TCMR TCMR. 0x88 timer3_mode 2 2 timer2_mode 1 1 TILR2 TILR2. 0x90 tilr_2 2 2 tilr_1 1 1 tilr_0 0 0 TILR3 TILR3. 0x94 tilr_2 2 2 tilr_1 1 1 tilr_0 0 0 WCR WCR. 0x98 wcr 0 0 WFAR WFAR. 0x9C wfar 0 15 WSAR WSAR. 0xA0 wsar 0 15 TCVWR2 TCVWR2. 0xA8 tcvwr 0 31 TCVWR3 TCVWR3. 0xAC tcvwr 0 31 TCVSYN2 TCVSYN2. 0xB4 tcvsyn2 0 31 TCVSYN3 TCVSYN3. 0xB8 tcvsyn3 0 31 TCDR TCDR. 0xBC wcdr 24 31 tcdr3 16 23 tcdr2 8 15 ir ir. ir 0x4000A600 0x20 read-write 0x0 0x1000 registers irtx_config irtx_config. 0x0 cr_irtx_data_num 12 17 cr_irtx_tail_hl_inv 11 11 cr_irtx_tail_en 10 10 cr_irtx_head_hl_inv 9 9 cr_irtx_head_en 8 8 cr_irtx_logic1_hl_inv 6 6 cr_irtx_logic0_hl_inv 5 5 cr_irtx_data_en 4 4 cr_irtx_swm_en 3 3 cr_irtx_mod_en 2 2 cr_irtx_out_inv 1 1 cr_irtx_en 0 0 irtx_int_sts irtx_int_sts. 0x4 cr_irtx_end_en 24 24 cr_irtx_end_clr 16 16 cr_irtx_end_mask 8 8 irtx_end_int 0 0 irtx_data_word0 irtx_data_word0. 0x8 cr_irtx_data_word0 0 31 irtx_data_word1 irtx_data_word1. 0xC cr_irtx_data_word1 0 31 irtx_pulse_width irtx_pulse_width. 0x10 cr_irtx_mod_ph1_w 24 31 cr_irtx_mod_ph0_w 16 23 cr_irtx_pw_unit 0 11 irtx_pw irtx_pw. 0x14 cr_irtx_tail_ph1_w 28 31 cr_irtx_tail_ph0_w 24 27 cr_irtx_head_ph1_w 20 23 cr_irtx_head_ph0_w 16 19 cr_irtx_logic1_ph1_w 12 15 cr_irtx_logic1_ph0_w 8 11 cr_irtx_logic0_ph1_w 4 7 cr_irtx_logic0_ph0_w 0 3 irtx_swm_pw_0 irtx_swm_pw_0. 0x40 cr_irtx_swm_pw_0 0 31 irtx_swm_pw_1 irtx_swm_pw_1. 0x44 cr_irtx_swm_pw_1 0 31 irtx_swm_pw_2 irtx_swm_pw_2. 0x48 cr_irtx_swm_pw_2 0 31 irtx_swm_pw_3 irtx_swm_pw_3. 0x4C cr_irtx_swm_pw_3 0 31 irtx_swm_pw_4 irtx_swm_pw_4. 0x50 cr_irtx_swm_pw_4 0 31 irtx_swm_pw_5 irtx_swm_pw_5. 0x54 cr_irtx_swm_pw_5 0 31 irtx_swm_pw_6 irtx_swm_pw_6. 0x58 cr_irtx_swm_pw_6 0 31 irtx_swm_pw_7 irtx_swm_pw_7. 0x5C cr_irtx_swm_pw_7 0 31 irrx_config irrx_config. 0x80 cr_irrx_deg_cnt 8 11 cr_irrx_deg_en 4 4 cr_irrx_mode 2 3 cr_irrx_in_inv 1 1 cr_irrx_en 0 0 irrx_int_sts irrx_int_sts. 0x84 cr_irrx_end_en 24 24 cr_irrx_end_clr 16 16 cr_irrx_end_mask 8 8 irrx_end_int 0 0 irrx_pw_config irrx_pw_config. 0x88 cr_irrx_end_th 16 31 cr_irrx_data_th 0 15 irrx_data_count irrx_data_count. 0x90 sts_irrx_data_cnt 0 6 irrx_data_word0 irrx_data_word0. 0x94 sts_irrx_data_word0 0 31 irrx_data_word1 irrx_data_word1. 0x98 sts_irrx_data_word1 0 31 irrx_swm_fifo_config_0 irrx_swm_fifo_config_0. 0xC0 rx_fifo_cnt 4 10 rx_fifo_underflow 3 3 rx_fifo_overflow 2 2 rx_fifo_clr 0 0 irrx_swm_fifo_rdata irrx_swm_fifo_rdata. 0xC4 rx_fifo_rdata 0 15 cks cks. cks 0x4000A700 0x20 read-write 0x0 0x1000 registers cks_config cks_config. 0x0 cr_cks_byte_swap 1 1 cr_cks_clr 0 0 data_in data_in. 0x4 data_in 0 7 cks_out cks_out. 0x8 cks_out 0 15 qdec Quadrature decoder control qdec 0x4000A800 0x20 read-write 0x0 0x1000 registers qdec_ctrl qdec_ctrl. 0x0 input_swap 31 31 rpt_mode 30 30 spl_mode 29 29 led_period 20 28 rpt_period 12 19 spl_period 8 11 deg_cnt 4 7 deg_en 3 3 led_pol 2 2 led_en 1 1 qdec_en 0 0 qdec_value qdec_value. 0x4 spl_val 28 29 acc2_val 16 19 acc1_val 0 10 qdec_int_en qdec_int_en. 0x10 overflow_en 3 3 dbl_rdy_en 2 2 spl_rdy_en 1 1 rpt_rdy_en 0 0 qdec_int_sts qdec_int_sts. 0x14 overflow_sts 3 3 dbl_rdy_sts 2 2 spl_rdy_sts 1 1 rpt_rdy_sts 0 0 qdec_int_clr qdec_int_clr. 0x18 overflow_clr 3 3 dbl_rdy_clr 2 2 spl_rdy_clr 1 1 rpt_rdy_clr 0 0 kys Key Scan kys 0x4000AB00 0x20 read-write 0x0 0x1000 registers ks_ctrl ks_ctrl. 0x0 col_num 20 24 row_num 16 18 rc_ext 8 9 deg_cnt 4 7 deg_en 3 3 ghost_en 2 2 ks_en 0 0 ks_int_en ks_int_en. 0x10 ks_int_en 0 0 ks_int_sts ks_int_sts. 0x14 keycode_valid 0 3 keycode_clr keycode_clr. 0x18 keycode_clr 0 3 keycode_value keycode_value. 0x1C keycode3 24 31 keycode2 16 23 keycode1 8 15 keycode0 0 7 i2s i2s. i2s 0x4000AA00 0x20 read-write 0x0 0x1000 registers i2s_config i2s_config. 0x0 cr_ofs_en 25 25 cr_ofs_cnt 20 24 cr_mono_rx_ch 19 19 cr_endian 18 18 cr_i2s_mode 16 17 cr_data_size 14 15 cr_frame_size 12 13 cr_fs_3ch_mode 8 8 cr_fs_4ch_mode 7 7 cr_fs_1t_mode 6 6 cr_mute_mode 5 5 cr_mono_mode 4 4 cr_i2s_rxd_en 3 3 cr_i2s_txd_en 2 2 cr_i2s_s_en 1 1 cr_i2s_m_en 0 0 i2s_int_sts i2s_int_sts. 0x4 cr_i2s_fer_en 26 26 cr_i2s_rxf_en 25 25 cr_i2s_txf_en 24 24 cr_i2s_fer_mask 10 10 cr_i2s_rxf_mask 9 9 cr_i2s_txf_mask 8 8 i2s_fer_int 2 2 i2s_rxf_int 1 1 i2s_txf_int 0 0 i2s_bclk_config i2s_bclk_config. 0x10 cr_bclk_div_h 16 27 cr_bclk_div_l 0 11 i2s_fifo_config_0 i2s_fifo_config_0. 0x80 cr_fifo_24b_lj 10 10 cr_fifo_lr_exchg 9 9 cr_fifo_lr_merge 8 8 rx_fifo_underflow 7 7 rx_fifo_overflow 6 6 tx_fifo_underflow 5 5 tx_fifo_overflow 4 4 rx_fifo_clr 3 3 tx_fifo_clr 2 2 i2s_dma_rx_en 1 1 i2s_dma_tx_en 0 0 i2s_fifo_config_1 i2s_fifo_config_1. 0x84 rx_fifo_th 24 27 tx_fifo_th 16 19 rx_fifo_cnt 8 12 tx_fifo_cnt 0 4 i2s_fifo_wdata i2s_fifo_wdata. 0x88 i2s_fifo_wdata 0 31 i2s_fifo_rdata i2s_fifo_rdata. 0x8C i2s_fifo_rdata 0 31 i2s_io_config i2s_io_config. 0xFC cr_deg_en 7 7 cr_deg_cnt 4 6 cr_i2s_bclk_inv 3 3 cr_i2s_fs_inv 2 2 cr_i2s_rxd_inv 1 1 cr_i2s_txd_inv 0 0 cam Camera cam 0x4000AD00 0x20 read-write 0x0 0x1000 registers dvp2axi_configue dvp2axi_configue. 0x0 reg_dvp_wait_cycle 24 31 reg_dvp_pix_clk_cg 20 20 reg_interlv_mode 16 16 reg_subsample_even 15 15 reg_subsample_en 14 14 reg_drop_even 13 13 reg_drop_en 12 12 reg_hw_mode_fwrap 11 11 reg_dvp_mode 8 10 reg_hburst 4 5 reg_line_vld_pol 3 3 reg_fram_vld_pol 2 2 reg_sw_mode 1 1 reg_dvp_enable 0 0 dvp2ahb_addr_start_0 dvp2ahb_addr_start_0. 0x4 reg_addr_start_0 0 31 dvp2ahb_mem_bcnt_0 dvp2ahb_mem_bcnt_0. 0x8 reg_mem_burst_cnt_0 0 31 dvp2ahb_frame_bcnt_0 dvp2ahb_frame_bcnt_0. 0xC reg_frame_burst_cnt_0 0 31 dvp2ahb_addr_start_1 dvp2ahb_addr_start_1. 0x10 reg_addr_start_1 0 31 dvp2ahb_mem_bcnt_1 dvp2ahb_mem_bcnt_1. 0x14 reg_mem_burst_cnt_1 0 31 dvp2ahb_frame_bcnt_1 dvp2ahb_frame_bcnt_1. 0x18 reg_frame_burst_cnt_1 0 31 dvp_status_and_error dvp_status_and_error. 0x1C st_bus_flsh 31 31 st_bus_wait 30 30 st_bus_func 29 29 st_bus_idle 28 28 frame_valid_cnt_1 24 27 frame_valid_cnt_0 20 23 st_dvp_idle 19 19 ahb_idle_1 17 17 ahb_idle_0 16 16 sts_vcnt_int 9 9 sts_hcnt_int 8 8 sts_fifo_int_1 7 7 sts_fifo_int_0 6 6 sts_frame_int_1 5 5 sts_frame_int_0 4 4 sts_mem_int_1 3 3 sts_mem_int_0 2 2 sts_normal_int_1 1 1 sts_normal_int_0 0 0 dvp_frame_fifo_pop dvp_frame_fifo_pop. 0x20 reg_int_fifo_clr_1 19 19 reg_int_frame_clr_1 18 18 reg_int_mem_clr_1 17 17 reg_int_normal_clr_1 16 16 reg_int_vcnt_clr_0 9 9 reg_int_hcnt_clr_0 8 8 reg_int_fifo_clr_0 7 7 reg_int_frame_clr_0 6 6 reg_int_mem_clr_0 5 5 reg_int_normal_clr_0 4 4 rfifo_pop_1 1 1 rfifo_pop_0 0 0 snsr_control snsr_control. 0x24 reg_cam_pwdn 1 1 reg_cam_rst 0 0 int_control int_control. 0x28 reg_frame_cnt_trgr_int 28 31 reg_int_vcnt_en 6 6 reg_int_hcnt_en 5 5 reg_int_fifo_en 4 4 reg_int_frame_en 3 3 reg_int_mem_en 2 2 reg_int_normal_1_en 1 1 reg_int_normal_0_en 0 0 hsync_control hsync_control. 0x30 reg_hsync_act_start 16 31 reg_hsync_act_end 0 15 vsync_control vsync_control. 0x34 reg_vsync_act_start 16 31 reg_vsync_act_end 0 15 frame_size_control frame_size_control. 0x38 reg_total_vcnt 16 31 reg_total_hcnt 0 15 frame_start_addr0_0 frame_start_addr0_0. 0x40 frame_start_addr_0_0 0 31 frame_byte_cnt0_0 frame_byte_cnt0_0. 0x44 frame_byte_cnt_0_0 0 31 frame_start_addr0_1 frame_start_addr0_1. 0x48 frame_start_addr_0_1 0 31 frame_byte_cnt0_1 frame_byte_cnt0_1. 0x4C frame_byte_cnt_0_1 0 31 frame_start_addr0_2 frame_start_addr0_2. 0x50 frame_start_addr_0_2 0 31 frame_byte_cnt0_2 frame_byte_cnt0_2. 0x54 frame_byte_cnt_0_2 0 31 frame_start_addr0_3 frame_start_addr0_3. 0x58 frame_start_addr_0_3 0 31 frame_byte_cnt0_3 frame_byte_cnt0_3. 0x5C frame_byte_cnt_0_3 0 31 frame_start_addr0_4 frame_start_addr0_4. 0x60 frame_start_addr_0_4 0 31 frame_byte_cnt0_4 frame_byte_cnt0_4. 0x64 frame_byte_cnt_0_4 0 31 frame_start_addr0_5 frame_start_addr0_5. 0x68 frame_start_addr_0_5 0 31 frame_byte_cnt0_5 frame_byte_cnt0_5. 0x6C frame_byte_cnt_0_5 0 31 frame_start_addr0_6 frame_start_addr0_6. 0x70 frame_start_addr_0_6 0 31 frame_byte_cnt0_6 frame_byte_cnt0_6. 0x74 frame_byte_cnt_0_6 0 31 frame_start_addr0_7 frame_start_addr0_7. 0x78 frame_start_addr_0_7 0 31 frame_byte_cnt0_7 frame_byte_cnt0_7. 0x7C frame_byte_cnt_0_7 0 31 frame_start_addr1_0 frame_start_addr1_0. 0x80 frame_start_addr_1_0 0 31 frame_byte_cnt1_0 frame_byte_cnt1_0. 0x84 frame_byte_cnt_1_0 0 31 frame_start_addr1_1 frame_start_addr1_1. 0x88 frame_start_addr_1_1 0 31 frame_byte_cnt1_1 frame_byte_cnt1_1. 0x8C frame_byte_cnt_1_1 0 31 frame_start_addr1_2 frame_start_addr1_2. 0x90 frame_start_addr_1_2 0 31 frame_byte_cnt1_2 frame_byte_cnt1_2. 0x94 frame_byte_cnt_1_2 0 31 frame_start_addr1_3 frame_start_addr1_3. 0x98 frame_start_addr_1_3 0 31 frame_byte_cnt1_3 frame_byte_cnt1_3. 0x9C frame_byte_cnt_1_3 0 31 frame_start_addr1_4 frame_start_addr1_4. 0xA0 frame_start_addr_1_4 0 31 frame_byte_cnt1_4 frame_byte_cnt1_4. 0xA4 frame_byte_cnt_1_4 0 31 frame_start_addr1_5 frame_start_addr1_5. 0xA8 frame_start_addr_1_5 0 31 frame_byte_cnt1_5 frame_byte_cnt1_5. 0xAC frame_byte_cnt_1_5 0 31 frame_start_addr1_6 frame_start_addr1_6. 0xB0 frame_start_addr_1_6 0 31 frame_byte_cnt1_6 frame_byte_cnt1_6. 0xB4 frame_byte_cnt_1_6 0 31 frame_start_addr1_7 frame_start_addr1_7. 0xB8 frame_start_addr_1_7 0 31 frame_byte_cnt1_7 frame_byte_cnt1_7. 0xBC frame_byte_cnt_1_7 0 31 dvp_debug dvp_debug. 0xFF0 reg_dvp_dbg_sel 1 3 reg_dvp_dbg_en 0 0 dvp_dummy_reg dvp_dummy_reg. 0xFFC RESERVED_31_0 0 31 mjpeg mjpeg. mjpeg 0x4000AE00 0x20 read-write 0x0 0x1000 registers mjpeg_control_1 mjpeg_control_1. 0x0 reg_v0_order 30 31 reg_y1_order 28 29 reg_u0_order 26 27 reg_y0_order 24 25 reg_q_mode 16 22 reg_yuv_mode 12 13 reg_h_bust 8 9 reg_reflect_dmy 6 6 reg_last_hf_hblk_dmy 5 5 reg_last_hf_wblk_dmy 4 4 reg_wr_over_stop 3 3 reg_order_u_even 2 2 reg_mjpeg_bit_order 1 1 reg_mjpeg_enable 0 0 mjpeg_control_2 mjpeg_control_2. 0x4 reg_mjpeg_wait_cycle 16 31 reg_uv_dvp2ahb_fsel 15 15 reg_uv_dvp2ahb_lsel 14 14 reg_yy_dvp2ahb_fsel 13 13 reg_yy_dvp2ahb_lsel 12 12 reg_mjpeg_sw_run 9 9 reg_mjpeg_sw_mode 8 8 reg_sw_frame 0 4 mjpeg_yy_frame_addr mjpeg_yy_frame_addr. 0x8 reg_yy_addr_start 0 31 mjpeg_uv_frame_addr mjpeg_uv_frame_addr. 0xC reg_uv_addr_start 0 31 mjpeg_yuv_mem mjpeg_yuv_mem. 0x10 reg_uv_mem_hblk 16 28 reg_yy_mem_hblk 0 12 jpeg_frame_addr jpeg_frame_addr. 0x14 reg_w_addr_start 0 31 jpeg_store_memory jpeg_store_memory. 0x18 reg_w_burst_cnt 0 31 mjpeg_control_3 mjpeg_control_3. 0x1C sts_swap_int 30 30 reg_int_swap_en 29 29 frame_valid_cnt 24 28 sts_idle_int 22 22 reg_int_idle_en 21 21 reg_frame_cnt_trgr_int 16 20 ahb_idle 14 14 mjpeg_manf 13 13 mjpeg_mans 12 12 mjpeg_flsh 11 11 mjpeg_wait 10 10 mjpeg_func 9 9 mjpeg_idle 8 8 sts_frame_int 7 7 sts_mem_int 6 6 sts_cam_int 5 5 sts_normal_int 4 4 reg_int_frame_en 3 3 reg_int_mem_en 2 2 reg_int_cam_en 1 1 reg_int_normal_en 0 0 mjpeg_frame_fifo_pop mjpeg_frame_fifo_pop. 0x20 reg_int_swap_clr 13 13 reg_int_idle_clr 12 12 reg_int_frame_clr 11 11 reg_int_mem_clr 10 10 reg_int_cam_clr 9 9 reg_int_normal_clr 8 8 reg_w_swap_clr 1 1 rfifo_pop 0 0 mjpeg_frame_size mjpeg_frame_size. 0x24 reg_frame_hblk 16 27 reg_frame_wblk 0 11 mjpeg_header_byte mjpeg_header_byte. 0x28 reg_tail_exp 16 16 reg_head_byte 0 11 mjpeg_swap_mode mjpeg_swap_mode. 0x30 sts_swap_fend 12 12 sts_swap_fstart 11 11 sts_read_swap_idx 10 10 sts_swap1_full 9 9 sts_swap0_full 8 8 reg_w_swap_mode 0 0 mjpeg_swap_bit_cnt mjpeg_swap_bit_cnt. 0x34 frame_swap_end_bit_cnt 0 31 mjpeg_paket_ctrl mjpeg_paket_ctrl. 0x38 reg_pket_body_byte 16 31 reg_jend_to_pend 1 1 reg_pket_en 0 0 mjpeg_paket_head_tail mjpeg_paket_head_tail. 0x3C reg_pket_tail_byte 16 27 reg_pket_head_byte 0 11 mjpeg_Y_frame_read_status_1 mjpeg_Y_frame_read_status_1. 0x40 yy_frm_hblk_r 16 28 yy_mem_hblk_r 0 12 mjpeg_Y_frame_read_status_2 mjpeg_Y_frame_read_status_2. 0x44 yy_frm_cnt_r 24 31 yy_mem_rnd_r 16 23 yy_wblk_r 0 12 mjpeg_Y_frame_write_status mjpeg_Y_frame_write_status. 0x48 yy_frm_cnt_w 24 31 yy_mem_rnd_w 16 23 yy_mem_hblk_w 0 12 mjpeg_UV_frame_read_status_1 mjpeg_UV_frame_read_status_1. 0x4C uv_frm_hblk_r 16 28 uv_mem_hblk_r 0 12 mjpeg_UV_frame_read_status_2 mjpeg_UV_frame_read_status_2. 0x50 uv_frm_cnt_r 24 31 uv_mem_rnd_r 16 23 uv_wblk_r 0 12 mjpeg_UV_frame_write_status mjpeg_UV_frame_write_status. 0x54 uv_frm_cnt_w 24 31 uv_mem_rnd_w 16 23 uv_mem_hblk_w 0 12 mjpeg_start_addr0 mjpeg_start_addr0. 0x80 frame_start_addr_0 0 31 mjpeg_bit_cnt0 mjpeg_bit_cnt0. 0x84 frame_bit_cnt_0 0 31 mjpeg_start_addr1 mjpeg_start_addr1. 0x88 frame_start_addr_1 0 31 mjpeg_bit_cnt1 mjpeg_bit_cnt1. 0x8C frame_bit_cnt_1 0 31 mjpeg_start_addr2 mjpeg_start_addr2. 0x90 frame_start_addr_2 0 31 mjpeg_bit_cnt2 mjpeg_bit_cnt2. 0x94 frame_bit_cnt_2 0 31 mjpeg_start_addr3 mjpeg_start_addr3. 0x98 frame_start_addr_3 0 31 mjpeg_bit_cnt3 mjpeg_bit_cnt3. 0x9C frame_bit_cnt_3 0 31 mjpeg_start_addr4 mjpeg_start_addr4. 0xA0 frame_start_addr_4 0 31 mjpeg_bit_cnt4 mjpeg_bit_cnt4. 0xA4 frame_bit_cnt_4 0 31 mjpeg_start_addr5 mjpeg_start_addr5. 0xA8 frame_start_addr_5 0 31 mjpeg_bit_cnt5 mjpeg_bit_cnt5. 0xAC frame_bit_cnt_5 0 31 mjpeg_start_addr6 mjpeg_start_addr6. 0xB0 frame_start_addr_6 0 31 mjpeg_bit_cnt6 mjpeg_bit_cnt6. 0xB4 frame_bit_cnt_6 0 31 mjpeg_start_addr7 mjpeg_start_addr7. 0xB8 frame_start_addr_7 0 31 mjpeg_bit_cnt7 mjpeg_bit_cnt7. 0xBC frame_bit_cnt_7 0 31 mjpeg_start_addr_8 mjpeg_start_addr_8. 0xC0 frame_start_addr_8 0 31 mjpeg_bit_cnt_8 mjpeg_bit_cnt_8. 0xC4 frame_bit_cnt_8 0 31 mjpeg_start_addr_9 mjpeg_start_addr_9. 0xC8 frame_start_addr_9 0 31 mjpeg_bit_cnt_9 mjpeg_bit_cnt_9. 0xCC frame_bit_cnt_9 0 31 mjpeg_start_addr_a mjpeg_start_addr_a. 0xD0 frame_start_addr_a 0 31 mjpeg_bit_cnt_a mjpeg_bit_cnt_a. 0xD4 frame_bit_cnt_a 0 31 mjpeg_start_addr_b mjpeg_start_addr_b. 0xD8 frame_start_addr_b 0 31 mjpeg_bit_cnt_b mjpeg_bit_cnt_b. 0xDC frame_bit_cnt_b 0 31 mjpeg_start_addr_c mjpeg_start_addr_c. 0xE0 frame_start_addr_c 0 31 mjpeg_bit_cnt_c mjpeg_bit_cnt_c. 0xE4 frame_bit_cnt_c 0 31 mjpeg_start_addr_d mjpeg_start_addr_d. 0xE8 frame_start_addr_d 0 31 mjpeg_bit_cnt_d mjpeg_bit_cnt_d. 0xEC frame_bit_cnt_d 0 31 mjpeg_start_addr_e mjpeg_start_addr_e. 0xF0 frame_start_addr_e 0 31 mjpeg_bit_cnt_e mjpeg_bit_cnt_e. 0xF4 frame_bit_cnt_e 0 31 mjpeg_start_addr_f mjpeg_start_addr_f. 0xF8 frame_start_addr_f 0 31 mjpeg_bit_cnt_f mjpeg_bit_cnt_f. 0xFC frame_bit_cnt_f 0 31 mjpeg_q_mode0 mjpeg_q_mode0. 0x100 frame_q_mode_0 0 6 mjpeg_q_mode1 mjpeg_q_mode1. 0x104 frame_q_mode_1 0 6 mjpeg_q_mode2 mjpeg_q_mode2. 0x108 frame_q_mode_2 0 6 mjpeg_q_mode3 mjpeg_q_mode3. 0x10C frame_q_mode_3 0 6 mjpeg_q_mode4 mjpeg_q_mode4. 0x110 frame_q_mode_4 0 6 mjpeg_q_mode5 mjpeg_q_mode5. 0x114 frame_q_mode_5 0 6 mjpeg_q_mode6 mjpeg_q_mode6. 0x118 frame_q_mode_6 0 6 mjpeg_q_mode7 mjpeg_q_mode7. 0x11C frame_q_mode_7 0 6 mjpeg_q_mode_8 mjpeg_q_mode_8. 0x120 frame_q_mode_8 0 6 mjpeg_q_mode_9 mjpeg_q_mode_9. 0x124 frame_q_mode_9 0 6 mjpeg_q_mode_a mjpeg_q_mode_a. 0x128 frame_q_mode_a 0 6 mjpeg_q_mode_b mjpeg_q_mode_b. 0x12C frame_q_mode_b 0 6 mjpeg_q_mode_c mjpeg_q_mode_c. 0x130 frame_q_mode_c 0 6 mjpeg_q_mode_d mjpeg_q_mode_d. 0x134 frame_q_mode_d 0 6 mjpeg_q_mode_e mjpeg_q_mode_e. 0x138 frame_q_mode_e 0 6 mjpeg_q_mode_f mjpeg_q_mode_f. 0x13C frame_q_mode_f 0 6 mjpeg_debug mjpeg_debug. 0x1F0 reg_mjpeg_dbg_sel 4 7 reg_mjpeg_dbg_en 0 0 mjpeg_dummy_reg mjpeg_dummy_reg. 0x1FC mjpeg_dummy_reg 0 31 sf_ctrl sf_ctrl. sf_ctrl 0x4000B000 0x20 read-write 0x0 0x1000 registers sf_ctrl_0 sf_ctrl_0. 0x0 sf_id 24 31 sf_aes_iv_endian 23 23 sf_aes_key_endian 22 22 sf_aes_ctr_plus_en 21 21 sf_aes_dout_endian 20 20 sf_aes_dly_mode 19 19 sf_if_int_set 18 18 sf_if_int_clr 17 17 sf_if_int 16 16 sf_if_read_dly_en 11 11 sf_if_read_dly_n 8 10 sf_clk_sahb_sram_sel 5 5 sf_clk_out_inv_sel 4 4 sf_clk_out_gate_en 3 3 sf_clk_sf_rx_inv_sel 2 2 sf_ctrl_1 sf_ctrl_1. 0x4 sf_ahb2sram_en 31 31 sf_ahb2sif_en 30 30 sf_if_en 29 29 sf_if_fn_sel 28 28 sf_ahb2sif_stop 27 27 sf_ahb2sif_stopped 26 26 sf_if_reg_wp 25 25 sf_if_reg_hold 24 24 sf_if_0_ack_lat 20 22 sf_if_sr_int_set 18 18 sf_if_sr_int_en 17 17 sf_if_sr_int 16 16 sf_if_sr_pat 8 15 sf_if_sr_pat_mask 0 7 sf_if_sahb_0 sf_if_sahb_0. 0x8 sf_if_0_qpi_mode_en 31 31 sf_if_0_spi_mode 28 30 sf_if_0_cmd_en 27 27 sf_if_0_adr_en 26 26 sf_if_0_dmy_en 25 25 sf_if_0_dat_en 24 24 sf_if_0_dat_rw 23 23 sf_if_0_cmd_byte 20 22 sf_if_0_adr_byte 17 19 sf_if_0_dmy_byte 12 16 sf_if_0_dat_byte 2 11 sf_if_0_trig 1 1 sf_if_busy 0 0 sf_if_sahb_1 sf_if_sahb_1. 0xC sf_if_0_cmd_buf_0 0 31 sf_if_sahb_2 sf_if_sahb_2. 0x10 sf_if_0_cmd_buf_1 0 31 sf_if_iahb_0 sf_if_iahb_0. 0x14 sf_if_1_qpi_mode_en 31 31 sf_if_1_spi_mode 28 30 sf_if_1_cmd_en 27 27 sf_if_1_adr_en 26 26 sf_if_1_dmy_en 25 25 sf_if_1_dat_en 24 24 sf_if_1_dat_rw 23 23 sf_if_1_cmd_byte 20 22 sf_if_1_adr_byte 17 19 sf_if_1_dmy_byte 12 16 sf_if_iahb_1 sf_if_iahb_1. 0x18 sf_if_1_cmd_buf_0 0 31 sf_if_iahb_2 sf_if_iahb_2. 0x1C sf_if_1_cmd_buf_1 0 31 sf_if_status_0 sf_if_status_0. 0x20 sf_if_status_0 0 31 sf_if_status_1 sf_if_status_1. 0x24 sf_if_status_1 0 31 sf_aes sf_aes. 0x28 sf_aes_status 5 31 sf_aes_pref_busy 4 4 sf_aes_pref_trig 3 3 sf_aes_mode 1 2 sf_aes_en 0 0 sf_ahb2sif_status sf_ahb2sif_status. 0x2C sf_ahb2sif_status 0 31 sf_if_io_dly_0 sf_if_io_dly_0. 0x30 sf_dqs_do_dly_sel 30 31 sf_dqs_di_dly_sel 28 29 sf_dqs_oe_dly_sel 26 27 sf_clk_out_dly_sel 8 9 sf_cs2_dly_sel 2 3 sf_cs_dly_sel 0 1 sf_if_io_dly_1 sf_if_io_dly_1. 0x34 sf_io_0_do_dly_sel 16 17 sf_io_0_di_dly_sel 8 9 sf_io_0_oe_dly_sel 0 1 sf_if_io_dly_2 sf_if_io_dly_2. 0x38 sf_io_1_do_dly_sel 16 17 sf_io_1_di_dly_sel 8 9 sf_io_1_oe_dly_sel 0 1 sf_if_io_dly_3 sf_if_io_dly_3. 0x3C sf_io_2_do_dly_sel 16 17 sf_io_2_di_dly_sel 8 9 sf_io_2_oe_dly_sel 0 1 sf_if_io_dly_4 sf_if_io_dly_4. 0x40 sf_io_3_do_dly_sel 16 17 sf_io_3_di_dly_sel 8 9 sf_io_3_oe_dly_sel 0 1 sf_reserved sf_reserved. 0x44 sf_reserved 0 31 sf2_if_io_dly_0 sf2_if_io_dly_0. 0x48 sf2_dqs_do_dly_sel 30 31 sf2_dqs_di_dly_sel 28 29 sf2_dqs_oe_dly_sel 26 27 sf2_clk_out_dly_sel 8 9 sf2_cs2_dly_sel 2 3 sf2_cs_dly_sel 0 1 sf2_if_io_dly_1 sf2_if_io_dly_1. 0x4C sf2_io_0_do_dly_sel 16 17 sf2_io_0_di_dly_sel 8 9 sf2_io_0_oe_dly_sel 0 1 sf2_if_io_dly_2 sf2_if_io_dly_2. 0x50 sf2_io_1_do_dly_sel 16 17 sf2_io_1_di_dly_sel 8 9 sf2_io_1_oe_dly_sel 0 1 sf2_if_io_dly_3 sf2_if_io_dly_3. 0x54 sf2_io_2_do_dly_sel 16 17 sf2_io_2_di_dly_sel 8 9 sf2_io_2_oe_dly_sel 0 1 sf2_if_io_dly_4 sf2_if_io_dly_4. 0x58 sf2_io_3_do_dly_sel 16 17 sf2_io_3_di_dly_sel 8 9 sf2_io_3_oe_dly_sel 0 1 sf3_if_io_dly_0 sf3_if_io_dly_0. 0x5C sf3_dqs_do_dly_sel 30 31 sf3_dqs_di_dly_sel 28 29 sf3_dqs_oe_dly_sel 26 27 sf3_clk_out_dly_sel 8 9 sf3_cs2_dly_sel 2 3 sf3_cs_dly_sel 0 1 sf3_if_io_dly_1 sf3_if_io_dly_1. 0x60 sf3_io_0_do_dly_sel 16 17 sf3_io_0_di_dly_sel 8 9 sf3_io_0_oe_dly_sel 0 1 sf3_if_io_dly_2 sf3_if_io_dly_2. 0x64 sf3_io_1_do_dly_sel 16 17 sf3_io_1_di_dly_sel 8 9 sf3_io_1_oe_dly_sel 0 1 sf3_if_io_dly_3 sf3_if_io_dly_3. 0x68 sf3_io_2_do_dly_sel 16 17 sf3_io_2_di_dly_sel 8 9 sf3_io_2_oe_dly_sel 0 1 sf3_if_io_dly_4 sf3_if_io_dly_4. 0x6C sf3_io_3_do_dly_sel 16 17 sf3_io_3_di_dly_sel 8 9 sf3_io_3_oe_dly_sel 0 1 sf_ctrl_2 sf_ctrl_2. 0x70 sf_if_0_bk_sel 31 31 sf_if_bk2_en 30 30 sf_if_bk2_mode 29 29 sf_if_bk_swap 28 28 sf_if_dqs_en 5 5 sf_if_dtr_en 4 4 sf_if_pad_sel_lock 3 3 sf_if_pad_sel 0 1 sf_ctrl_3 sf_ctrl_3. 0x74 sf_if_1_ack_lat 29 31 sf_cmds_wrap_q 11 11 sf_cmds_wrap_mode 10 10 sf_cmds_wrap_q_ini 9 9 sf_cmds_bt_en 8 8 sf_cmds_bt_dly 5 7 sf_cmds_en 4 4 sf_cmds_wrap_len 0 3 sf_if_iahb_3 sf_if_iahb_3. 0x78 sf_if_2_qpi_mode_en 31 31 sf_if_2_spi_mode 28 30 sf_if_2_cmd_en 27 27 sf_if_2_adr_en 26 26 sf_if_2_dmy_en 25 25 sf_if_2_dat_en 24 24 sf_if_2_dat_rw 23 23 sf_if_2_cmd_byte 20 22 sf_if_2_adr_byte 17 19 sf_if_2_dmy_byte 12 16 sf_if_iahb_4 sf_if_iahb_4. 0x7C sf_if_2_cmd_buf_0 0 31 sf_if_iahb_5 sf_if_iahb_5. 0x80 sf_if_2_cmd_buf_1 0 31 sf_if_iahb_6 sf_if_iahb_6. 0x84 sf_if_3_qpi_mode_en 31 31 sf_if_3_spi_mode 28 30 sf_if_3_cmd_en 27 27 sf_if_3_adr_en 26 26 sf_if_3_cmd_byte 20 22 sf_if_3_adr_byte 17 19 sf_if_iahb_7 sf_if_iahb_7. 0x88 sf_if_3_cmd_buf_0 0 31 sf_if_iahb_8 sf_if_iahb_8. 0x8C sf_if_3_cmd_buf_1 0 31 sf_if_iahb_9 sf_if_iahb_9. 0x90 sf_if_4_qpi_mode_en 31 31 sf_if_4_spi_mode 28 30 sf_if_4_cmd_en 27 27 sf_if_4_adr_en 26 26 sf_if_4_dmy_en 25 25 sf_if_4_dat_en 24 24 sf_if_4_dat_rw 23 23 sf_if_4_cmd_byte 20 22 sf_if_4_adr_byte 17 19 sf_if_4_dmy_byte 12 16 sf_if_iahb_10 sf_if_iahb_10. 0x94 sf_if_4_cmd_buf_0 0 31 sf_if_iahb_11 sf_if_iahb_11. 0x98 sf_if_4_cmd_buf_1 0 31 sf_if_iahb_12 sf_if_iahb_12. 0x9C sf2_if_read_dly_src 12 12 sf2_if_read_dly_en 11 11 sf2_if_read_dly_n 8 10 sf3_clk_out_inv_sel 5 5 sf2_clk_out_inv_sel 4 4 sf2_clk_sf_rx_inv_src 3 3 sf2_clk_sf_rx_inv_sel 2 2 sf_ctrl_prot_en_rd sf_ctrl_prot_en_rd. 0x100 sf_dbg_dis 31 31 sf_if_0_trig_wr_lock 30 30 sf_ctrl_id1_en_rd 2 2 sf_ctrl_id0_en_rd 1 1 sf_ctrl_prot_en_rd 0 0 sf_ctrl_prot_en sf_ctrl_prot_en. 0x104 sf_ctrl_id1_en 2 2 sf_ctrl_id0_en 1 1 sf_ctrl_prot_en 0 0 sf_aes_key_r0_0 sf_aes_key_r0_0. 0x200 sf_aes_key_r0_0 0 31 sf_aes_key_r0_1 sf_aes_key_r0_1. 0x204 sf_aes_key_r0_1 0 31 sf_aes_key_r0_2 sf_aes_key_r0_2. 0x208 sf_aes_key_r0_2 0 31 sf_aes_key_r0_3 sf_aes_key_r0_3. 0x20C sf_aes_key_r0_3 0 31 sf_aes_key_r0_4 sf_aes_key_r0_4. 0x210 sf_aes_key_r0_4 0 31 sf_aes_key_r0_5 sf_aes_key_r0_5. 0x214 sf_aes_key_r0_5 0 31 sf_aes_key_r0_6 sf_aes_key_r0_6. 0x218 sf_aes_key_r0_6 0 31 sf_aes_key_r0_7 sf_aes_key_r0_7. 0x21C sf_aes_key_r0_7 0 31 sf_aes_iv_r0_w0 sf_aes_iv_r0_w0. 0x220 sf_aes_iv_r0_w0 0 31 sf_aes_iv_r0_w1 sf_aes_iv_r0_w1. 0x224 sf_aes_iv_r0_w1 0 31 sf_aes_iv_r0_w2 sf_aes_iv_r0_w2. 0x228 sf_aes_iv_r0_w2 0 31 sf_aes_iv_r0_w3 sf_aes_iv_r0_w3. 0x22C sf_aes_iv_r0_w3 0 31 sf_aes_cfg_r0 sf_aes_cfg_r0. 0x230 sf_aes_region_r0_lock 31 31 sf_aes_region_r0_en 30 30 sf_aes_region_r0_hw_key_en 29 29 sf_aes_region_r0_start 14 27 sf_aes_region_r0_end 0 13 sf_aes_key_r1_0 sf_aes_key_r1_0. 0x300 sf_aes_key_r1_0 0 31 sf_aes_key_r1_1 sf_aes_key_r1_1. 0x304 sf_aes_key_r1_1 0 31 sf_aes_key_r1_2 sf_aes_key_r1_2. 0x308 sf_aes_key_r1_2 0 31 sf_aes_key_r1_3 sf_aes_key_r1_3. 0x30C sf_aes_key_r1_3 0 31 sf_aes_key_r1_4 sf_aes_key_r1_4. 0x310 sf_aes_key_r1_4 0 31 sf_aes_key_r1_5 sf_aes_key_r1_5. 0x314 sf_aes_key_r1_5 0 31 sf_aes_key_r1_6 sf_aes_key_r1_6. 0x318 sf_aes_key_r1_6 0 31 sf_aes_key_r1_7 sf_aes_key_r1_7. 0x31C sf_aes_key_r1_7 0 31 sf_aes_iv_r1_w0 sf_aes_iv_r1_w0. 0x320 sf_aes_iv_r1_w0 0 31 sf_aes_iv_r1_w1 sf_aes_iv_r1_w1. 0x324 sf_aes_iv_r1_w1 0 31 sf_aes_iv_r1_w2 sf_aes_iv_r1_w2. 0x328 sf_aes_iv_r1_w2 0 31 sf_aes_iv_r1_w3 sf_aes_iv_r1_w3. 0x32C sf_aes_iv_r1_w3 0 31 sf_aes_r1 sf_aes_r1. 0x330 sf_aes_r1_lock 31 31 sf_aes_r1_en 30 30 sf_aes_r1_hw_key_en 29 29 sf_aes_r1_start 14 27 sf_aes_r1_end 0 13 sf_aes_key_r2_0 sf_aes_key_r2_0. 0x400 sf_aes_key_r2_0 0 31 sf_aes_key_r2_1 sf_aes_key_r2_1. 0x404 sf_aes_key_r2_1 0 31 sf_aes_key_r2_2 sf_aes_key_r2_2. 0x408 sf_aes_key_r2_2 0 31 sf_aes_key_r2_3 sf_aes_key_r2_3. 0x40C sf_aes_key_r2_3 0 31 sf_aes_key_r2_4 sf_aes_key_r2_4. 0x410 sf_aes_key_r2_4 0 31 sf_aes_key_r2_5 sf_aes_key_r2_5. 0x414 sf_aes_key_r2_5 0 31 sf_aes_key_r2_6 sf_aes_key_r2_6. 0x418 sf_aes_key_r2_6 0 31 sf_aes_key_r2_7 sf_aes_key_r2_7. 0x41C sf_aes_key_r2_7 0 31 sf_aes_iv_r2_w0 sf_aes_iv_r2_w0. 0x420 sf_aes_iv_r2_w0 0 31 sf_aes_iv_r2_w1 sf_aes_iv_r2_w1. 0x424 sf_aes_iv_r2_w1 0 31 sf_aes_iv_r2_w2 sf_aes_iv_r2_w2. 0x428 sf_aes_iv_r2_w2 0 31 sf_aes_iv_r2_w3 sf_aes_iv_r2_w3. 0x42C sf_aes_iv_r2_w3 0 31 sf_aes_r2 sf_aes_r2. 0x430 sf_aes_r2_lock 31 31 sf_aes_r2_en 30 30 sf_aes_r2_hw_key_en 29 29 sf_aes_r2_start 14 27 sf_aes_r2_end 0 13 sf_id0_offset sf_id0_offset. 0x434 sf_id0_offset 0 23 sf_id1_offset sf_id1_offset. 0x438 sf_id1_offset 0 23 sf_bk2_id0_offset sf_bk2_id0_offset. 0x43C sf_bk2_id0_offset 0 23 sf_bk2_id1_offset sf_bk2_id1_offset. 0x440 sf_bk2_id1_offset 0 23 dma dma. dma 0x40007000 0x20 read-write 0x0 0x1000 registers DMA_IntStatus DMA_IntStatus. 0x0 IntStatus 0 7 DMA_IntTCStatus DMA_IntTCStatus. 0x4 IntTCStatus 0 7 DMA_IntTCClear DMA_IntTCClear. 0x8 IntTCClear 0 7 DMA_IntErrorStatus DMA_IntErrorStatus. 0xC IntErrorStatus 0 7 DMA_IntErrClr DMA_IntErrClr. 0x10 IntErrClr 0 7 DMA_RawIntTCStatus DMA_RawIntTCStatus. 0x14 RawIntTCStatus 0 7 DMA_RawIntErrorStatus DMA_RawIntErrorStatus. 0x18 RawIntErrorStatus 0 7 DMA_EnbldChns DMA_EnbldChns. 0x1C EnabledChannels 0 7 DMA_SoftBReq DMA_SoftBReq. 0x20 SoftBReq 0 31 DMA_SoftSReq DMA_SoftSReq. 0x24 SoftSReq 0 31 DMA_SoftLBReq DMA_SoftLBReq. 0x28 SoftLBReq 0 31 DMA_SoftLSReq DMA_SoftLSReq. 0x2C SoftLSReq 0 31 DMA_Top_Config DMA_Top_Config. 0x30 M 1 1 E 0 0 DMA_Sync DMA_Sync. 0x34 DMA_Sync 0 31 DMA_C0SrcAddr DMA_C0SrcAddr. 0x100 SrcAddr 0 31 DMA_C0DstAddr DMA_C0DstAddr. 0x104 DstAddr 0 31 DMA_C0LLI DMA_C0LLI. 0x108 LLI 0 31 DMA_C0Control DMA_C0Control. 0x10C I 31 31 Prot 28 30 DI 27 27 SI 26 26 SLargerD 25 25 fix_cnt 23 24 DWidth 21 22 SWidth 18 19 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C0Config DMA_C0Config. 0x110 LLICounter 20 29 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C1SrcAddr DMA_C1SrcAddr. 0x200 SrcAddr 0 31 DMA_C1DstAddr DMA_C1DstAddr. 0x204 DstAddr 0 31 DMA_C1LLI DMA_C1LLI. 0x208 LLI 2 31 DMA_C1Control DMA_C1Control. 0x20C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C1Config DMA_C1Config. 0x210 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C2SrcAddr DMA_C2SrcAddr. 0x300 SrcAddr 0 31 DMA_C2DstAddr DMA_C2DstAddr. 0x304 DstAddr 0 31 DMA_C2LLI DMA_C2LLI. 0x308 LLI 2 31 DMA_C2Control DMA_C2Control. 0x30C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C2Config DMA_C2Config. 0x310 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C3SrcAddr DMA_C3SrcAddr. 0x400 SrcAddr 0 31 DMA_C3DstAddr DMA_C3DstAddr. 0x404 DstAddr 0 31 DMA_C3LLI DMA_C3LLI. 0x408 LLI 2 31 DMA_C3Control DMA_C3Control. 0x40C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C3Config DMA_C3Config. 0x410 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C4SrcAddr DMA_C4SrcAddr. 0x500 SrcAddr 0 31 DMA_C4DstAddr DMA_C4DstAddr. 0x504 DstAddr 0 31 DMA_C4LLI DMA_C4LLI. 0x508 LLI 2 31 DMA_C4Control DMA_C4Control. 0x50C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C4Config DMA_C4Config. 0x510 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C5SrcAddr DMA_C5SrcAddr. 0x600 SrcAddr 0 31 DMA_C5DstAddr DMA_C5DstAddr. 0x604 DstAddr 0 31 DMA_C5LLI DMA_C5LLI. 0x608 LLI 2 31 DMA_C5Control DMA_C5Control. 0x60C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C5Config DMA_C5Config. 0x610 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C6SrcAddr DMA_C6SrcAddr. 0x700 SrcAddr 0 31 DMA_C6DstAddr DMA_C6DstAddr. 0x704 DstAddr 0 31 DMA_C6LLI DMA_C6LLI. 0x708 LLI 2 31 DMA_C6Control DMA_C6Control. 0x70C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C6Config DMA_C6Config. 0x710 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 DMA_C7SrcAddr DMA_C7SrcAddr. 0x800 SrcAddr 0 31 DMA_C7DstAddr DMA_C7DstAddr. 0x804 DstAddr 0 31 DMA_C7LLI DMA_C7LLI. 0x808 LLI 2 31 DMA_C7Control DMA_C7Control. 0x80C I 31 31 Prot 28 30 DI 27 27 SI 26 26 fix_cnt 23 24 DWidth 21 23 SWidth 18 20 dst_add_mode 17 17 DBSize 15 16 dst_min_mode 14 14 SBSize 12 13 TransferSize 0 11 DMA_C7Config DMA_C7Config. 0x810 H 18 18 A 17 17 L 16 16 ITC 15 15 IE 14 14 FlowCntrl 11 13 DstPeripheral 6 10 SrcPeripheral 1 5 E 0 0 emac Ethernet MAC emac 0x4000D000 0x20 read-write 0x0 0x1000 registers MODE MODE. 0x0 rsvd_23_18 18 23 RMII_EN 17 17 RECSMALL 16 16 PAD 15 15 HUGEN 14 14 CRCEN 13 13 rsvd_12_11 11 12 FULLD 10 10 rsvd_9_7 7 9 IFG 6 6 PRO 5 5 rsvd_4 4 4 BRO 3 3 NOPRE 2 2 TXEN 1 1 RXEN 0 0 INT_SOURCE INT_SOURCE. 0x4 RXC 6 6 TXC 5 5 BUSY 4 4 RXE 3 3 RXB 2 2 TXE 1 1 TXB 0 0 INT_MASK INT_MASK. 0x8 RXC_M 6 6 TXC_M 5 5 BUSY_M 4 4 RXE_M 3 3 RXB_M 2 2 TXE_M 1 1 TXB_M 0 0 IPGT IPGT. 0xC IPGT 0 6 PACKETLEN PACKETLEN. 0x18 MINFL 16 31 MAXFL 0 15 COLLCONFIG COLLCONFIG. 0x1C MAXRET 16 19 COLLVALID 0 5 TX_BD_NUM TX_BD_NUM. 0x20 RXBDPTR 24 30 TXBDPTR 16 22 TXBDNUM 0 7 MIIMODE MIIMODE. 0x28 MIINOPRE 8 8 CLKDIV 0 7 MIICOMMAND MIICOMMAND. 0x2C WCTRLDATA 2 2 RSTAT 1 1 SCANSTAT 0 0 MIIADDRESS MIIADDRESS. 0x30 RGAD 8 12 FIAD 0 4 MIITX_DATA MIITX_DATA. 0x34 CTRLDATA 0 15 MIIRX_DATA MIIRX_DATA. 0x38 PRSD 0 15 MIISTATUS MIISTATUS. 0x3C MIIM_BUSY 1 1 MIIM_LINKFAIL 0 0 MAC_ADDR0 MAC_ADDR0. 0x40 MAC_B2 24 31 MAC_B3 16 23 MAC_B4 8 15 MAC_B5 0 7 MAC_ADDR1 MAC_ADDR1. 0x44 MAC_B0 8 15 MAC_B1 0 7 HASH0_ADDR HASH0_ADDR. 0x48 HASH0 0 31 HASH1_ADDR HASH1_ADDR. 0x4C HASH1 0 31 TXCTRL TXCTRL. 0x50 TXPAUSERQ 16 16 TXPAUSETV 0 15 usb usb. usb 0x4000D800 0x20 read-write 0x0 0x1000 registers usb_config usb_config. 0x0 sts_usb_ep0_sw_rdy 28 28 cr_usb_ep0_sw_rdy 27 27 cr_usb_ep0_sw_nack_out 26 26 cr_usb_ep0_sw_nack_in 25 25 cr_usb_ep0_sw_stall 24 24 cr_usb_ep0_sw_size 16 23 cr_usb_ep0_sw_addr 9 15 cr_usb_ep0_sw_ctrl 8 8 cr_usb_rom_dct_en 4 4 cr_usb_en 0 0 usb_lpm_config usb_lpm_config. 0x4 sts_lpm 31 31 sts_lpm_attr 20 30 cr_lpm_resp 2 3 cr_lpm_resp_upd 1 1 cr_lpm_en 0 0 usb_resume_config usb_resume_config. 0x8 cr_res_force 31 31 cr_res_trig 12 12 cr_res_width 0 10 usb_setup_data_0 usb_setup_data_0. 0x10 sts_setup_data_b3 24 31 sts_setup_data_b2 16 23 sts_setup_data_b1 8 15 sts_setup_data_b0 0 7 usb_setup_data_1 usb_setup_data_1. 0x14 sts_setup_data_b7 24 31 sts_setup_data_b6 16 23 sts_setup_data_b5 8 15 sts_setup_data_b4 0 7 usb_frame_no usb_frame_no. 0x18 sts_ep_no 16 19 sts_pid 12 15 sts_frame_no 0 10 usb_error usb_error. 0x1C crc16_err 6 6 crc5_err 5 5 pid_cks_err 4 4 pid_seq_err 3 3 ivld_ep_err 2 2 xfer_to_err 1 1 utmi_rx_err 0 0 usb_int_en USB interrupt enable 0x20 cr_usb_err_en 31 31 cr_sof_3ms_en 30 30 cr_lpm_pkt_en 29 29 cr_lpm_wkup_en 28 28 rsvd_27_24 24 27 cr_ep7_done_en 23 23 cr_ep7_cmd_en 22 22 cr_ep6_done_en 21 21 cr_ep6_cmd_en 20 20 cr_ep5_done_en 19 19 cr_ep5_cmd_en 18 18 cr_ep4_done_en 17 17 cr_ep4_cmd_en 16 16 cr_ep3_done_en 15 15 cr_ep3_cmd_en 14 14 cr_ep2_done_en 13 13 cr_ep2_cmd_en 12 12 cr_ep1_done_en 11 11 cr_ep1_cmd_en 10 10 cr_ep0_out_done_en 9 9 cr_ep0_out_cmd_en 8 8 cr_ep0_in_done_en 7 7 cr_ep0_in_cmd_en 6 6 cr_ep0_setup_done_en 5 5 cr_ep0_setup_cmd_en 4 4 cr_get_dct_cmd_en 3 3 cr_vbus_tgl_en 2 2 cr_usb_reset_en 1 1 cr_sof_en 0 0 usb_int_sts USB interrupt status 0x24 usb_err_int 31 31 sof_3ms_int 30 30 lpm_pkt_int 29 29 lpm_wkup_int 28 28 rsvd_27_24 24 27 ep7_done_int 23 23 ep7_cmd_int 22 22 ep6_done_int 21 21 ep6_cmd_int 20 20 ep5_done_int 19 19 ep5_cmd_int 18 18 ep4_done_int 17 17 ep4_cmd_int 16 16 ep3_done_int 15 15 ep3_cmd_int 14 14 ep2_done_int 13 13 ep2_cmd_int 12 12 ep1_done_int 11 11 ep1_cmd_int 10 10 ep0_out_done_int 9 9 ep0_out_cmd_int 8 8 ep0_in_done_int 7 7 ep0_in_cmd_int 6 6 ep0_setup_done_int 5 5 ep0_setup_cmd_int 4 4 get_dct_cmd_int 3 3 vbus_tgl_int 2 2 usb_reset_int 1 1 sof_int 0 0 usb_int_mask USB interrupt mask 0x28 cr_usb_err_mask 31 31 cr_sof_3ms_mask 30 30 cr_lpm_pkt_mask 29 29 cr_lpm_wkup_mask 28 28 rsvd_27_24 24 27 cr_ep7_done_mask 23 23 cr_ep7_cmd_mask 22 22 cr_ep6_done_mask 21 21 cr_ep6_cmd_mask 20 20 cr_ep5_done_mask 19 19 cr_ep5_cmd_mask 18 18 cr_ep4_done_mask 17 17 cr_ep4_cmd_mask 16 16 cr_ep3_done_mask 15 15 cr_ep3_cmd_mask 14 14 cr_ep2_done_mask 13 13 cr_ep2_cmd_mask 12 12 cr_ep1_done_mask 11 11 cr_ep1_cmd_mask 10 10 cr_ep0_out_done_mask 9 9 cr_ep0_out_cmd_mask 8 8 cr_ep0_in_done_mask 7 7 cr_ep0_in_cmd_mask 6 6 cr_ep0_setup_done_mask 5 5 cr_ep0_setup_cmd_mask 4 4 cr_get_dct_cmd_mask 3 3 cr_vbus_tgl_mask 2 2 cr_usb_reset_mask 1 1 cr_sof_mask 0 0 usb_int_clear USB interrupt clear 0x2C cr_usb_err_clr 31 31 cr_sof_3ms_clr 30 30 cr_lpm_pkt_clr 29 29 cr_lpm_wkup_clr 28 28 rsvd_27_24 24 27 cr_ep7_done_clr 23 23 cr_ep7_cmd_clr 22 22 cr_ep6_done_clr 21 21 cr_ep6_cmd_clr 20 20 cr_ep5_done_clr 19 19 cr_ep5_cmd_clr 18 18 cr_ep4_done_clr 17 17 cr_ep4_cmd_clr 16 16 cr_ep3_done_clr 15 15 cr_ep3_cmd_clr 14 14 cr_ep2_done_clr 13 13 cr_ep2_cmd_clr 12 12 cr_ep1_done_clr 11 11 cr_ep1_cmd_clr 10 10 cr_ep0_out_done_clr 9 9 cr_ep0_out_cmd_clr 8 8 cr_ep0_in_done_clr 7 7 cr_ep0_in_cmd_clr 6 6 cr_ep0_setup_done_clr 5 5 cr_ep0_setup_cmd_clr 4 4 cr_get_dct_cmd_clr 3 3 cr_vbus_tgl_clr 2 2 cr_usb_reset_clr 1 1 cr_sof_clr 0 0 ep1_config ep1_config. 0x40 sts_ep1_rdy 19 19 cr_ep1_rdy 18 18 cr_ep1_nack 17 17 cr_ep1_stall 16 16 cr_ep1_type 13 15 cr_ep1_dir 11 12 cr_ep1_size 0 10 ep2_config ep2_config. 0x44 sts_ep2_rdy 19 19 cr_ep2_rdy 18 18 cr_ep2_nack 17 17 cr_ep2_stall 16 16 cr_ep2_type 13 15 cr_ep2_dir 11 12 cr_ep2_size 0 10 ep3_config ep3_config. 0x48 sts_ep3_rdy 19 19 cr_ep3_rdy 18 18 cr_ep3_nack 17 17 cr_ep3_stall 16 16 cr_ep3_type 13 15 cr_ep3_dir 11 12 cr_ep3_size 0 10 ep4_config ep4_config. 0x4C sts_ep4_rdy 19 19 cr_ep4_rdy 18 18 cr_ep4_nack 17 17 cr_ep4_stall 16 16 cr_ep4_type 13 15 cr_ep4_dir 11 12 cr_ep4_size 0 10 ep5_config ep5_config. 0x50 sts_ep5_rdy 19 19 cr_ep5_rdy 18 18 cr_ep5_nack 17 17 cr_ep5_stall 16 16 cr_ep5_type 13 15 cr_ep5_dir 11 12 cr_ep5_size 0 10 ep6_config ep6_config. 0x54 sts_ep6_rdy 19 19 cr_ep6_rdy 18 18 cr_ep6_nack 17 17 cr_ep6_stall 16 16 cr_ep6_type 13 15 cr_ep6_dir 11 12 cr_ep6_size 0 10 ep7_config ep7_config. 0x58 sts_ep7_rdy 19 19 cr_ep7_rdy 18 18 cr_ep7_nack 17 17 cr_ep7_stall 16 16 cr_ep7_type 13 15 cr_ep7_dir 11 12 cr_ep7_size 0 10 ep0_fifo_config ep0_fifo_config. 0x100 ep0_rx_fifo_underflow 7 7 ep0_rx_fifo_overflow 6 6 ep0_tx_fifo_underflow 5 5 ep0_tx_fifo_overflow 4 4 ep0_rx_fifo_clr 3 3 ep0_tx_fifo_clr 2 2 ep0_dma_rx_en 1 1 ep0_dma_tx_en 0 0 ep0_fifo_status ep0_fifo_status. 0x104 ep0_rx_fifo_full 31 31 ep0_rx_fifo_empty 30 30 ep0_rx_fifo_cnt 16 22 ep0_tx_fifo_full 15 15 ep0_tx_fifo_empty 14 14 ep0_tx_fifo_cnt 0 6 ep0_tx_fifo_wdata ep0_tx_fifo_wdata. 0x108 ep0_tx_fifo_wdata 0 7 ep0_rx_fifo_rdata ep0_rx_fifo_rdata. 0x10C ep0_rx_fifo_rdata 0 7 ep1_fifo_config ep1_fifo_config. 0x110 ep1_rx_fifo_underflow 7 7 ep1_rx_fifo_overflow 6 6 ep1_tx_fifo_underflow 5 5 ep1_tx_fifo_overflow 4 4 ep1_rx_fifo_clr 3 3 ep1_tx_fifo_clr 2 2 ep1_dma_rx_en 1 1 ep1_dma_tx_en 0 0 ep1_fifo_status ep1_fifo_status. 0x114 ep1_rx_fifo_full 31 31 ep1_rx_fifo_empty 30 30 ep1_rx_fifo_cnt 16 22 ep1_tx_fifo_full 15 15 ep1_tx_fifo_empty 14 14 ep1_tx_fifo_cnt 0 6 ep1_tx_fifo_wdata ep1_tx_fifo_wdata. 0x118 ep1_tx_fifo_wdata 0 7 ep1_rx_fifo_rdata ep1_rx_fifo_rdata. 0x11C ep1_rx_fifo_rdata 0 7 ep2_fifo_config ep2_fifo_config. 0x120 ep2_rx_fifo_underflow 7 7 ep2_rx_fifo_overflow 6 6 ep2_tx_fifo_underflow 5 5 ep2_tx_fifo_overflow 4 4 ep2_rx_fifo_clr 3 3 ep2_tx_fifo_clr 2 2 ep2_dma_rx_en 1 1 ep2_dma_tx_en 0 0 ep2_fifo_status ep2_fifo_status. 0x124 ep2_rx_fifo_full 31 31 ep2_rx_fifo_empty 30 30 ep2_rx_fifo_cnt 16 22 ep2_tx_fifo_full 15 15 ep2_tx_fifo_empty 14 14 ep2_tx_fifo_cnt 0 6 ep2_tx_fifo_wdata ep2_tx_fifo_wdata. 0x128 ep2_tx_fifo_wdata 0 7 ep2_rx_fifo_rdata ep2_rx_fifo_rdata. 0x12C ep2_rx_fifo_rdata 0 7 ep3_fifo_config ep3_fifo_config. 0x130 ep3_rx_fifo_underflow 7 7 ep3_rx_fifo_overflow 6 6 ep3_tx_fifo_underflow 5 5 ep3_tx_fifo_overflow 4 4 ep3_rx_fifo_clr 3 3 ep3_tx_fifo_clr 2 2 ep3_dma_rx_en 1 1 ep3_dma_tx_en 0 0 ep3_fifo_status ep3_fifo_status. 0x134 ep3_rx_fifo_full 31 31 ep3_rx_fifo_empty 30 30 ep3_rx_fifo_cnt 16 22 ep3_tx_fifo_full 15 15 ep3_tx_fifo_empty 14 14 ep3_tx_fifo_cnt 0 6 ep3_tx_fifo_wdata ep3_tx_fifo_wdata. 0x138 ep3_tx_fifo_wdata 0 7 ep3_rx_fifo_rdata ep3_rx_fifo_rdata. 0x13C ep3_rx_fifo_rdata 0 7 ep4_fifo_config ep4_fifo_config. 0x140 ep4_rx_fifo_underflow 7 7 ep4_rx_fifo_overflow 6 6 ep4_tx_fifo_underflow 5 5 ep4_tx_fifo_overflow 4 4 ep4_rx_fifo_clr 3 3 ep4_tx_fifo_clr 2 2 ep4_dma_rx_en 1 1 ep4_dma_tx_en 0 0 ep4_fifo_status ep4_fifo_status. 0x144 ep4_rx_fifo_full 31 31 ep4_rx_fifo_empty 30 30 ep4_rx_fifo_cnt 16 22 ep4_tx_fifo_full 15 15 ep4_tx_fifo_empty 14 14 ep4_tx_fifo_cnt 0 6 ep4_tx_fifo_wdata ep4_tx_fifo_wdata. 0x148 ep4_tx_fifo_wdata 0 7 ep4_rx_fifo_rdata ep4_rx_fifo_rdata. 0x14C ep4_rx_fifo_rdata 0 7 ep5_fifo_config ep5_fifo_config. 0x150 ep5_rx_fifo_underflow 7 7 ep5_rx_fifo_overflow 6 6 ep5_tx_fifo_underflow 5 5 ep5_tx_fifo_overflow 4 4 ep5_rx_fifo_clr 3 3 ep5_tx_fifo_clr 2 2 ep5_dma_rx_en 1 1 ep5_dma_tx_en 0 0 ep5_fifo_status ep5_fifo_status. 0x154 ep5_rx_fifo_full 31 31 ep5_rx_fifo_empty 30 30 ep5_rx_fifo_cnt 16 22 ep5_tx_fifo_full 15 15 ep5_tx_fifo_empty 14 14 ep5_tx_fifo_cnt 0 6 ep5_tx_fifo_wdata ep5_tx_fifo_wdata. 0x158 ep5_tx_fifo_wdata 0 7 ep5_rx_fifo_rdata ep5_rx_fifo_rdata. 0x15C ep5_rx_fifo_rdata 0 7 ep6_fifo_config ep6_fifo_config. 0x160 ep6_rx_fifo_underflow 7 7 ep6_rx_fifo_overflow 6 6 ep6_tx_fifo_underflow 5 5 ep6_tx_fifo_overflow 4 4 ep6_rx_fifo_clr 3 3 ep6_tx_fifo_clr 2 2 ep6_dma_rx_en 1 1 ep6_dma_tx_en 0 0 ep6_fifo_status ep6_fifo_status. 0x164 ep6_rx_fifo_full 31 31 ep6_rx_fifo_empty 30 30 ep6_rx_fifo_cnt 16 22 ep6_tx_fifo_full 15 15 ep6_tx_fifo_empty 14 14 ep6_tx_fifo_cnt 0 6 ep6_tx_fifo_wdata ep6_tx_fifo_wdata. 0x168 ep6_tx_fifo_wdata 0 7 ep6_rx_fifo_rdata ep6_rx_fifo_rdata. 0x16C ep6_rx_fifo_rdata 0 7 ep7_fifo_config ep7_fifo_config. 0x170 ep7_rx_fifo_underflow 7 7 ep7_rx_fifo_overflow 6 6 ep7_tx_fifo_underflow 5 5 ep7_tx_fifo_overflow 4 4 ep7_rx_fifo_clr 3 3 ep7_tx_fifo_clr 2 2 ep7_dma_rx_en 1 1 ep7_dma_tx_en 0 0 ep7_fifo_status ep7_fifo_status. 0x174 ep7_rx_fifo_full 31 31 ep7_rx_fifo_empty 30 30 ep7_rx_fifo_cnt 16 22 ep7_tx_fifo_full 15 15 ep7_tx_fifo_empty 14 14 ep7_tx_fifo_cnt 0 6 ep7_tx_fifo_wdata ep7_tx_fifo_wdata. 0x178 ep7_tx_fifo_wdata 0 7 ep7_rx_fifo_rdata ep7_rx_fifo_rdata. 0x17C ep7_rx_fifo_rdata 0 7 rsvd_0 rsvd_0. 0x1F0 rsvd_0 0 31 rsvd_1 rsvd_1. 0x1F4 rsvd_1 0 31 xcvr_if_config xcvr_if_config. 0x1FC sts_vbus_det 31 31 cr_xcvr_om_rx_dn 11 11 cr_xcvr_om_rx_dp 10 10 cr_xcvr_om_rx_d 9 9 cr_xcvr_om_rx_sel 8 8 cr_xcvr_force_rx_dn 7 7 cr_xcvr_force_rx_dp 6 6 cr_xcvr_force_rx_d 5 5 cr_xcvr_force_rx_en 4 4 cr_xcvr_force_tx_dn 3 3 cr_xcvr_force_tx_dp 2 2 cr_xcvr_force_tx_oe 1 1 cr_xcvr_force_tx_en 0 0 pds Sleep control (Power Down Sleep) pds 0x4000E000 0x20 read-write 0x0 0x1000 registers PDS_CTL PDS_CTL. 0x0 cr_pds_ctrl_pll 30 31 cr_pds_ctrl_rf 28 29 cr_pds_ldo_vol 24 27 cr_pds_force_ram_clk_en 23 23 cr_pds_pd_ldo11 22 22 cr_np_wfi_mask 21 21 cr_pds_ram_lp_with_clk_en 19 19 cr_pds_ldo_vsel_en 18 18 cr_pds_rc32m_off_dis 17 17 cr_pds_rst_soc_en 16 16 cr_pds_soc_enb_force_on 15 15 cr_pds_pd_xtal 14 14 cr_pds_pwr_off 13 13 cr_pds_wait_xtal_rdy 12 12 cr_pds_iso_en 11 11 cr_sw_pu_flash 10 10 cr_pds_mem_stby 9 9 cr_pds_gate_clk 8 8 cr_pds_ctrl_pu_flash 7 7 cr_pds_ctrl_gpio_ie_pu_pd 6 6 cr_pds_pd_bg_sys 5 5 cr_pds_pd_dcdc18 4 4 cr_wifi_pds_save_state 3 3 cr_xtal_force_off 2 2 cr_sleep_forever 1 1 pds_start_ps 0 0 PDS_TIME1 PDS_TIME1. 0x4 cr_sleep_duration 0 31 PDS_INT PDS_INT. 0xC ro_pds_wakeup_event 24 31 cr_pds_wakeup_src_en 16 23 cr_pds_int_clr 15 15 cr_pds_pll_done_int_mask 11 11 cr_pds_rf_done_int_mask 10 10 cr_pds_wake_int_mask 8 8 pds_clr_reset_event 7 7 pds_reset_event 4 6 ro_pds_pll_done_int 3 3 ro_pds_rf_done_int 2 2 ro_pds_wake_int 0 0 PDS_CTL2 PDS_CTL2. 0x10 cr_pds_force_usb_gate_clk 19 19 cr_pds_force_bz_gate_clk 18 18 cr_pds_force_np_gate_clk 16 16 cr_pds_force_usb_mem_stby 15 15 cr_pds_force_bz_mem_stby 14 14 cr_pds_force_np_mem_stby 12 12 cr_pds_force_usb_pds_rst 11 11 cr_pds_force_bz_pds_rst 10 10 cr_pds_force_np_pds_rst 8 8 cr_pds_force_usb_iso_en 7 7 cr_pds_force_bz_iso_en 6 6 cr_pds_force_np_iso_en 4 4 cr_pds_force_usb_pwr_off 3 3 cr_pds_force_bz_pwr_off 2 2 cr_pds_force_np_pwr_off 0 0 PDS_CTL3 PDS_CTL3. 0x14 cr_pds_misc_iso_en 30 30 cr_pds_usb_iso_en 29 29 cr_pds_ble_iso_en 28 28 cr_pds_bz_iso_en 27 27 cr_pds_np_iso_en 24 24 cr_pds_force_ble_gate_clk 14 14 cr_pds_force_misc_gate_clk 13 13 cr_pds_force_ble_mem_stby 11 11 cr_pds_force_misc_mem_stby 10 10 cr_pds_force_ble_pds_rst 8 8 cr_pds_force_misc_pds_rst 7 7 cr_pds_force_ble_iso_en 5 5 cr_pds_force_ble_pwr_off 2 2 cr_pds_force_misc_pwr_off 1 1 PDS_CTL4 PDS_CTL4. 0x18 cr_pds_misc_dig_pwr_off 31 31 cr_pds_misc_ana_pwr_off 30 30 cr_pds_misc_gate_clk 27 27 cr_pds_misc_mem_stby 26 26 cr_pds_misc_reset 25 25 cr_pds_misc_pwr_off 24 24 cr_pds_usb_gate_clk 23 23 cr_pds_usb_mem_stby 22 22 cr_pds_usb_reset 21 21 cr_pds_usb_pwr_off 20 20 cr_pds_ble_gate_clk 19 19 cr_pds_ble_mem_stby 18 18 cr_pds_ble_reset 17 17 cr_pds_ble_pwr_off 16 16 cr_pds_bz_gate_clk 15 15 cr_pds_bz_mem_stby 14 14 cr_pds_bz_reset 13 13 cr_pds_bz_pwr_off 12 12 cr_pds_np_gate_clk 3 3 cr_pds_np_mem_stby 2 2 cr_pds_np_reset 1 1 cr_pds_np_pwr_off 0 0 pds_stat pds_stat. 0x1C ro_pds_pll_state 16 17 ro_pds_rf_state 8 11 ro_pds_state 0 3 pds_ram1 pds_ram1. 0x20 cr_pds_ram_pgen 8 11 cr_pds_ram_ret2n 4 7 cr_pds_ram_ret1n 0 3 pds_gpio_set_pu_pd pds_gpio_set_pu_pd. 0x30 cr_pds_gpio_28_23_pu 24 29 cr_pds_gpio_28_23_pd 16 21 cr_pds_gpio_22_17_pu 8 13 cr_pds_gpio_22_17_pd 0 5 pds_gpio_int pds_gpio_int. 0x40 pds_gpio_int_select 8 10 pds_gpio_int_mode 4 6 pds_gpio_int_clr 2 2 pds_gpio_int_stat 1 1 pds_gpio_int_mask 0 0 rc32m_ctrl0 rc32m_ctrl0. 0x300 rc32m_code_fr_ext 22 29 rc32m_pd 21 21 rc32m_cal_en 20 20 rc32m_ext_code_en 19 19 rc32m_refclk_half 18 18 rc32m_allow_cal 17 17 rc32m_dig_code_fr_cal 6 13 rc32m_cal_precharge 5 5 rc32m_cal_div 3 4 rc32m_cal_inprogress 2 2 rc32m_rdy 1 1 rc32m_cal_done 0 0 rc32m_ctrl1 rc32m_ctrl1. 0x304 rc32m_reserved 24 31 rc32m_clk_force_on 4 4 rc32m_clk_inv 3 3 rc32m_clk_soft_rst 2 2 rc32m_soft_rst 1 1 rc32m_test_en 0 0 pu_rst_clkpll pu_rst_clkpll. 0x400 pu_clkpll 10 10 pu_clkpll_sfreg 9 9 clkpll_pu_cp 8 8 clkpll_pu_pfd 7 7 clkpll_pu_clamp_op 6 6 clkpll_pu_fbdv 5 5 clkpll_pu_postdiv 4 4 clkpll_reset_refdiv 3 3 clkpll_reset_fbdv 2 2 clkpll_reset_postdiv 1 1 clkpll_sdm_reset 0 0 clkpll_top_ctrl clkpll_top_ctrl. 0x404 clkpll_resv 24 25 clkpll_vg11_sel 20 21 clkpll_refclk_sel 16 16 clkpll_xtal_rc32m_sel 12 12 clkpll_refdiv_ratio 8 11 clkpll_postdiv 0 6 clkpll_cp clkpll_cp. 0x408 clkpll_cp_opamp_en 10 10 clkpll_cp_startup_en 9 9 clkpll_int_frac_sw 8 8 clkpll_icp_1u 6 7 clkpll_icp_5u 4 5 clkpll_sel_cp_bias 0 0 clkpll_rz clkpll_rz. 0x40C clkpll_rz 16 18 clkpll_cz 14 15 clkpll_c3 12 13 clkpll_r4_short 8 8 clkpll_r4 4 5 clkpll_c4_en 0 0 clkpll_fbdv clkpll_fbdv. 0x410 clkpll_sel_fb_clk 2 3 clkpll_sel_sample_clk 0 1 clkpll_vco clkpll_vco. 0x414 clkpll_shrtr 3 3 clkpll_vco_speed 0 2 clkpll_sdm clkpll_sdm. 0x418 clkpll_sdm_bypass 29 29 clkpll_sdm_flag 28 28 clkpll_dither_sel 24 25 clkpll_sdmin 0 23 clkpll_output_en clkpll_output_en. 0x41C clkpll_en_div2_480m 9 9 clkpll_en_32m 8 8 clkpll_en_48m 7 7 clkpll_en_80m 6 6 clkpll_en_96m 5 5 clkpll_en_120m 4 4 clkpll_en_160m 3 3 clkpll_en_192m 2 2 clkpll_en_240m 1 1 clkpll_en_480m 0 0 clkpll_test_enable clkpll_test_enable. 0x420 clkpll_dc_tp_out_en 8 8 ten_clkpll 7 7 ten_clkpll_sfreg 6 6 dten_clkpll_fin 5 5 dten_clkpll_fref 4 4 dten_clkpll_fsdm 3 3 dten_clk32M 2 2 dten_clk96M 1 1 dten_clkpll_postdiv_clk 0 0 HBN HBN. HBN 0x4000F000 0x20 read-write 0x0 0x1000 registers HBN_CTL HBN_CTL. 0x0 hbn_state 28 31 sram_slp 27 27 sram_slp_option 26 26 pwr_on_option 25 25 rtc_dly_option 24 24 pu_dcdc18_aon 23 23 hbn_ldo11_aon_vout_sel 19 22 hbn_ldo11_rt_vout_sel 15 18 hbn_dis_pwr_off_ldo11_rt 14 14 hbn_dis_pwr_off_ldo11 13 13 sw_rst 12 12 pwrdn_hbn_rtc 11 11 pwrdn_hbn_core 9 9 trap_mode 8 8 hbn_mode 7 7 rtc_ctl 0 6 HBN_TIME_L HBN_TIME_L. 0x4 hbn_time_l 0 31 HBN_TIME_H HBN_TIME_H. 0x8 hbn_time_h 0 7 RTC_TIME_L RTC_TIME_L. 0xC rtc_time_latch_l 0 31 RTC_TIME_H RTC_TIME_H. 0x10 rtc_time_latch 31 31 rtc_time_latch_h 0 7 HBN_IRQ_MODE HBN_IRQ_MODE. 0x14 pin_wakeup_en 27 27 pin_wakeup_sel 24 26 irq_acomp1_en 22 23 irq_acomp0_en 20 21 irq_bor_en 18 18 reg_en_hw_pu_pd 16 16 reg_aon_pad_ie_smt 8 12 hbn_pin_wakeup_mask 3 7 hbn_pin_wakeup_mode 0 2 HBN_IRQ_STAT HBN_IRQ_STAT. 0x18 irq_stat 0 31 HBN_IRQ_CLR HBN_IRQ_CLR. 0x1C irq_clr 0 31 HBN_PIR_CFG HBN_PIR_CFG. 0x20 gpadc_nosync 9 9 gpadc_cgen 8 8 pir_en 7 7 pir_dis 4 5 pir_lpf_sel 2 2 pir_hpf_sel 0 1 HBN_PIR_VTH HBN_PIR_VTH. 0x24 pir_vth 0 13 HBN_PIR_INTERVAL HBN_PIR_INTERVAL. 0x28 pir_interval 0 11 HBN_MISC HBN_MISC. 0x2C hbn_flash_pulldown_aon 24 29 hbn_flash_pullup_aon 16 21 r_bor_out 3 3 pu_bor 2 2 bor_vth 1 1 bor_sel 0 0 HBN_GLB HBN_GLB. 0x30 sw_ldo11_aon_vout_sel 28 31 sw_ldo11_rt_vout_sel 24 27 sw_ldo11soc_vout_sel_aon 16 19 hbn_clear_reset_event 13 13 hbn_reset_event 8 12 ldo11_rt_iload_sel 6 7 hbn_pu_rc32k 5 5 hbn_f32k_sel 3 4 hbn_uart_clk_sel 2 2 hbn_root_clk_sel 0 1 HBN_SRAM HBN_SRAM. 0x34 retram_slp 7 7 retram_ret 6 6 retram_emaw 3 4 retram_ema 0 2 HBN_RSV0 HBN_RSV0. 0x100 HBN_RSV0 0 31 HBN_RSV1 HBN_RSV1. 0x104 HBN_RSV1 0 31 HBN_RSV2 HBN_RSV2. 0x108 HBN_RSV2 0 31 HBN_RSV3 HBN_RSV3. 0x10C HBN_RSV3 0 31 rc32k_ctrl0 rc32k_ctrl0. 0x200 rc32k_code_fr_ext 22 31 rc32k_cal_en 20 20 rc32k_ext_code_en 19 19 rc32k_allow_cal 18 18 rc32k_vref_dly 16 17 rc32k_dig_code_fr_cal 6 15 rc32k_cal_precharge 5 5 rc32k_cal_div 3 4 rc32k_cal_inprogress 2 2 rc32k_rdy 1 1 rc32k_cal_done 0 0 xtal32k xtal32k. 0x204 pu_xtal32k 19 19 pu_xtal32k_buf 18 18 xtal32k_ac_cap_short 17 17 xtal32k_capbank 11 16 xtal32k_inv_stre 9 10 xtal32k_otf_short 8 8 xtal32k_outbuf_stre 7 7 xtal32k_reg 5 6 xtal32k_amp_ctrl 3 4 xtal32k_ext_sel 2 2 xtal32k_lowv_en 1 1 xtal32k_hiz_en 0 0 AON AON. AON 0x4000F000 0x20 read-write 0x0 0x1000 registers aon aon. 0x800 sw_pu_ldo11_rt 22 22 ldo11_rt_pulldown_sel 21 21 ldo11_rt_pulldown 20 20 pu_aon_dc_tbuf 12 12 aon_resv 0 7 aon_common aon_common. 0x804 ten_cip_misc_aon 20 20 ten_mbg_aon 19 19 dten_xtal_aon 18 18 ten_xtal_aon 17 17 ten_ldo15rf_aon 16 16 ten_bg_sys_aon 12 12 ten_dcdc18_1_aon 11 11 ten_dcdc18_0_aon 10 10 ten_ldo11soc_aon 9 9 ten_vddcore_aon 8 8 ten_xtal32k 6 6 dten_xtal32k 5 5 ten_aon 4 4 tmux_aon 0 2 aon_misc aon_misc. 0x808 sw_bz_en_aon 1 1 sw_soc_en_aon 0 0 bg_sys_top bg_sys_top. 0x810 bg_sys_start_ctrl_aon 12 12 pu_bg_sys_aon 8 8 pmip_resv 0 7 dcdc18_top_0 dcdc18_top_0. 0x814 dcdc18_rdy_aon 31 31 dcdc18_sstart_time_aon 28 29 dcdc18_osc_inhibit_t2_aon 27 27 dcdc18_slow_osc_aon 26 26 dcdc18_stop_osc_aon 25 25 dcdc18_slope_curr_sel_aon 20 24 dcdc18_osc_freq_trim_aon 16 19 dcdc18_osc_2m_mode_aon 12 12 dcdc18_vpfm_aon 8 11 dcdc18_vout_sel_aon 1 5 dcdc18_top_1 dcdc18_top_1. 0x818 dcdc18_pulldown_aon 29 29 dcdc18_en_antiring_aon 28 28 dcdc18_cfb_sel_aon 24 27 dcdc18_chf_sel_aon 20 23 dcdc18_rc_sel_aon 16 19 dcdc18_nonoverlap_td_aon 8 12 dcdc18_zvs_td_opt_aon 4 6 dcdc18_cs_delay_aon 1 3 dcdc18_force_cs_zvs_aon 0 0 ldo11soc_and_dctest ldo11soc_and_dctest. 0x81C pmip_dc_tp_out_en_aon 31 31 pu_vddcore_misc_aon 30 30 ldo11soc_power_good_aon 29 29 ldo11soc_rdy_aon 28 28 ldo11soc_cc_aon 24 25 ldo11soc_vth_sel_aon 12 13 ldo11soc_pulldown_sel_aon 11 11 ldo11soc_pulldown_aon 10 10 ldo11soc_sstart_delay_aon 8 9 ldo11soc_sstart_sel_aon 4 4 pu_ldo11soc_aon 0 0 psw_irrcv psw_irrcv. 0x820 pu_ir_psw_aon 0 0 rf_top_aon rf_top_aon. 0x880 ldo15rf_bypass_aon 28 28 ldo15rf_cc_aon 24 25 ldo15rf_vout_sel_aon 16 18 ldo15rf_pulldown_sel_aon 13 13 ldo15rf_pulldown_aon 12 12 ldo15rf_sstart_delay_aon 9 10 ldo15rf_sstart_sel_aon 8 8 pu_xtal_aon 5 5 pu_xtal_buf_aon 4 4 pu_sfreg_aon 2 2 pu_ldo15rf_aon 1 1 pu_mbg_aon 0 0 xtal_cfg xtal_cfg. 0x884 xtal_rdy_sel_aon 30 31 xtal_gm_boost_aon 28 29 xtal_capcode_in_aon 22 27 xtal_capcode_out_aon 16 21 xtal_amp_ctrl_aon 14 15 xtal_sleep_aon 13 13 xtal_fast_startup_aon 12 12 xtal_buf_hp_aon 8 11 xtal_buf_en_aon 4 7 xtal_ext_sel_aon 3 3 xtal_capcode_extra_aon 2 2 xtal_bk_aon 0 1 tsen tsen. 0x888 xtal_rdy_int_sel_aon 30 31 xtal_inn_cfg_en_aon 29 29 xtal_rdy 28 28 tsen_refcode_rfcal 16 27 tsen_refcode_corner 0 11 acomp0_ctrl acomp0_ctrl. 0x900 acomp0_muxen 26 26 acomp0_pos_sel 22 25 acomp0_neg_sel 18 21 acomp0_level_sel 12 17 acomp0_bias_prog 10 11 acomp0_hyst_selp 7 9 acomp0_hyst_seln 4 6 acomp0_en 0 0 acomp1_ctrl acomp1_ctrl. 0x904 acomp1_muxen 26 26 acomp1_pos_sel 22 25 acomp1_neg_sel 18 21 acomp1_level_sel 12 17 acomp1_bias_prog 10 11 acomp1_hyst_selp 7 9 acomp1_hyst_seln 4 6 acomp1_en 0 0 acomp_ctrl acomp_ctrl. 0x908 acomp_reserved 24 31 acomp0_out_raw 19 19 acomp1_out_raw 17 17 acomp0_test_sel 12 13 acomp1_test_sel 10 11 acomp0_test_en 9 9 acomp1_test_en 8 8 acomp0_rstn_ana 1 1 acomp1_rstn_ana 0 0 gpadc_reg_cmd gpadc_reg_cmd. 0x90C gpadc_sen_test_en 30 30 gpadc_sen_sel 28 29 gpadc_chip_sen_pu 27 27 gpadc_micboost_32db_en 23 23 gpadc_mic_pga2_gain 21 22 gpadc_mic1_diff 20 20 gpadc_mic2_diff 19 19 gpadc_dwa_en 18 18 gpadc_byp_micboost 16 16 gpadc_micpga_en 15 15 gpadc_micbias_en 14 14 gpadc_neg_gnd 13 13 gpadc_pos_sel 8 12 gpadc_neg_sel 3 7 gpadc_soft_rst 2 2 gpadc_conv_start 1 1 gpadc_global_en 0 0 gpadc_reg_config1 gpadc_reg_config1. 0x910 gpadc_v18_sel 29 30 gpadc_v11_sel 27 28 gpadc_dither_en 26 26 gpadc_scan_en 25 25 gpadc_scan_length 21 24 gpadc_clk_div_ratio 18 20 gpadc_clk_ana_inv 17 17 gpadc_lowv_det_en 10 10 gpadc_vcm_hyst_sel 9 9 gpadc_vcm_sel_en 8 8 gpadc_res_sel 2 4 gpadc_cont_conv_en 1 1 gpadc_cal_os_en 0 0 gpadc_reg_config2 gpadc_reg_config2. 0x914 gpadc_tsvbe_low 31 31 gpadc_dly_sel 28 30 gpadc_pga1_gain 25 27 gpadc_pga2_gain 22 24 gpadc_test_sel 19 21 gpadc_test_en 18 18 gpadc_bias_sel 17 17 gpadc_chop_mode 15 16 gpadc_pga_vcmi_en 14 14 gpadc_pga_en 13 13 gpadc_pga_os_cal 9 12 gpadc_pga_vcm 7 8 gpadc_ts_en 6 6 gpadc_tsext_sel 5 5 gpadc_vbat_en 4 4 gpadc_vref_sel 3 3 gpadc_diff_mode 2 2 gpadc_reg_scn_pos1 adc converation sequence 1 0x918 gpadc_scan_pos_5 25 29 gpadc_scan_pos_4 20 24 gpadc_scan_pos_3 15 19 gpadc_scan_pos_2 10 14 gpadc_scan_pos_1 5 9 gpadc_scan_pos_0 0 4 gpadc_reg_scn_pos2 adc converation sequence 2 0x91C gpadc_scan_pos_11 25 29 gpadc_scan_pos_10 20 24 gpadc_scan_pos_9 15 19 gpadc_scan_pos_8 10 14 gpadc_scan_pos_7 5 9 gpadc_scan_pos_6 0 4 gpadc_reg_scn_neg1 adc converation sequence 3 0x920 gpadc_scan_neg_5 25 29 gpadc_scan_neg_4 20 24 gpadc_scan_neg_3 15 19 gpadc_scan_neg_2 10 14 gpadc_scan_neg_1 5 9 gpadc_scan_neg_0 0 4 gpadc_reg_scn_neg2 adc converation sequence 4 0x924 gpadc_scan_neg_11 25 29 gpadc_scan_neg_10 20 24 gpadc_scan_neg_9 15 19 gpadc_scan_neg_8 10 14 gpadc_scan_neg_7 5 9 gpadc_scan_neg_6 0 4 gpadc_reg_status gpadc_reg_status. 0x928 gpadc_reserved 16 31 gpadc_data_rdy 0 0 gpadc_reg_isr gpadc_reg_isr. 0x92C gpadc_pos_satur_mask 9 9 gpadc_neg_satur_mask 8 8 gpadc_pos_satur_clr 5 5 gpadc_neg_satur_clr 4 4 gpadc_pos_satur 1 1 gpadc_neg_satur 0 0 gpadc_reg_result gpadc_reg_result. 0x930 gpadc_data_out 0 25 gpadc_reg_raw_result gpadc_reg_raw_result. 0x934 gpadc_raw_data 0 11 gpadc_reg_define gpadc_reg_define. 0x938 gpadc_os_cal_data 0 15 hbncore_resv0 hbncore_resv0. 0x93C hbncore_resv0_data 0 31 hbncore_resv1 hbncore_resv1. 0x940 hbncore_resv1_data 0 31