Bouffalo Lab bouffalolab BL808 1.0 Bouffalo BL808 chip 8 64 32 read-write 0x00000000 0xFFFFFFFF CODEC Codec miscellaneous control 0x30020000 0 0x1000 registers todo ?? 0 MJPEG Motion JPEG encoder 0x30021000 0 0x1000 registers todo ?? 0 H264 H.264 video codec control 0x30022000 0 0x1000 registers todo ?? 0 NPU Bouffalo Convolutional Neural Network 0x30024000 0 0x1000 registers todo ?? 0 MMGLB Multimedia Global controller 0x30007000 0 0x1000 registers todo ?? 0 PTA Packet Traffic Arbitration 0x24920000 0 0x1000 registers todo ?? 0 WIFI Wireless Fidelity control 0x24B00000 0 0x1000 registers todo ?? 0 > EMAC Ethernet Media Access Control 0x20070000 0 0x1000 registers mode Interface enables and configurations 0x00 interrupt_source Interrupt source register 0x04 0x00000000 0xffffffff read-write oneToClear control_receive Control frame received interrupt state 6 6 InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 control_transmit Control frame transmitted interrupt state 5 5 busy Lack of buffer interrupt state 4 4 receive_error Receive error interrupt state 3 3 frame_received Frame received interrupt state 2 2 transmit_error Transmit error interrupt state 1 1 buffer_transmitted Buffer transmitted interrupt state 0 0 interrupt_mask Interrupt mask register 0x08 0x00000000 0xffffffff read-write true control_receive Control frame received interrupt mask 6 6 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 control_transmit Control frame transmitted interrupt mask 5 5 busy Lack of buffer interrupt mask 4 4 receive_error Receive error interrupt mask 3 3 frame_received Frame received interrupt mask 2 2 transmit_error Transmit error interrupt mask 1 1 buffer_transmitted Buffer transmitted interrupt mask 0 0 backed_gap Back-to-back inter-packet gap register 0x0C non_backed_gap_1 Non back-to-back inter-packet gap register 1 0x10 non_backed_gap_2 Non back-to-back inter-packet gap register 2 0x14 frame_length Minimum and maximum ethernet frame length 0x18 collision Collision time window and maximum retries 0x1C transmit_buffer Transmit buffer descriptor 0x20 flow_control Control frame function register 0x24 mii_mode MII clock divider and premable enable 0x28 mii_command MII control data, read and scan state 0x2C mii_address Physical layer bus address 0x30 control_write Write data to MII physcial layer 0x34 control_read Read data from MII physcial layer 0x38 mii_state MII bus and link layer state 0x3C 2 0x04 mac_address[%s] Media Access Control address 0x40 2 0x04 hash[%s] Hash register 0x48 transmit_control Transmit control register 0x50 SDH Secure Digital host control 0x20060000 0 0x1000 registers todo ?? 0 AUDIO Audio codec controller 0x20055000 0 0x1000 registers todo ?? 0 USB Universal Serial Bus host 0x20072000 0 0x1000 registers capability Host Controller Capability Registers 0x000 operation Host Controller Operational Registers 0x010 PSRAM Pseudo Static Random Access Memory control 0x20052000 0 0x100 registers todo ?? 0 AON Always-On function control 0x2000F800 0 0x800 registers todo ?? 0 HBN Hibernate (Deep sleep) control 0x2000F000 0 0x800 registers control Miscellaneous control register 0x00 time_lo Low bits of hibernate time 0x04 time_hi High bits of hibernate time 0x08 rtc_time_lo Low bits of Real-Time Clock time 0x0C rtc_time_hi High bits of Real-Time Clock time 0x10 interrupt_mode Hibernate interrupt contol 0x14 interrupt_state Hibernate interrupt state 0x18 interrupt_clear Clear hibernate interrupt 0x1C global Global hibernate configuration 0x30 sram Static Random-Access Memory hibernate control 0x34 rc32k 32-kHz internal RC oscillator control 0x200 xtal32k External crystal oscillator control 0x204 rtc_control_0 Real-Time Clock control and reset register 0 0x208 rtc_control_1 Real-Time Clock control and reset register 1 0x20C PDS Power-Down Sleep control 0x2000E000 0 0x1000 registers touch_config ?? 0xA00 touch_channel ?? 0xA04 touch_process ?? 0xA08 touch_sleep ?? 0xA0C touch_delay ?? 0xA10 6 0x04 touch_force[%s] ?? 0xA14 3 0x04 touch_voltage[%s] ?? 0xA2C 12 0x04 touch_raw[%s] ?? 0xA38 touch_interrupt_0 ?? 0xACC touch_interrupt_1 ?? 0xAD0 2 0x65000 DMA%s Direct Memory Access 0x2000C000 0 0x1000 registers todo ?? 0 FLASH Quad Serial Flash control 0x2000B000 0 0x100 registers todo ?? 0 LZ4D Hardware LZ4 Decompressor 0x2000AD00 0 0x100 registers config Decompressor peripheral configuration 0x00 0x00000000 0xffffffff enable Enable peripheral decompression 0 0 suspend Suspend peripheral decompression 1 1 source_start Writes source address before decompression 0x10 0x00000000 0xffffffff start Start address 0 25 base Address base 26 31 source_end Reads the end address of source after decompression 0x14 0x00000000 0xffffffff read-only end End of address 0 25 destination_start Writes destination address before decompression 0x18 0x00000000 0xffffffff start Start address 0 25 base Address base 26 31 destination_end Reads the end address of destination after decompression 0x1C 0x00000000 0xffffffff read-only end End of address 0 25 interrupt_enable Interrupt enable register 0x20 0x00000003 0xffffffff true done Decompliation finished 0 0 InterruptEnable enable Enable interrupt 1 disable Disable interrupt 0 error Error occurred while decompliation 1 1 interrupt_state Interrupt state register 0x24 0x00000000 0xffffffff read-only done Decompliation finished 0 0 InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 error Error occurred while decompliation 1 1 PDM Pulse Density Modulation 0x2000AC00 0 0x100 registers todo ?? 0 I2S Inter-IC Sound controller 0x2000AB00 0 0x100 registers config Function configuration register 0x00 interrupt_state Interrupt enables, masks and states 0x04 base_clock Base clock divider 0x10 0x00010001 0xffffffff divide_high Higher half of base clock dividing factor 16 27 read-write divide_low Lower half of base clock dividing factor 0 11 read-write fifo_config_0 FIFO configuration register 0 0x80 0x00000000 0xffffffff left_justified 10 10 swap_left_right 9 9 merge_left_right 8 8 receive_underflow Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`. 7 7 read-only true HasUnderflow not_underflow No FIFO buffer underflow 0 underflow Has FIFO buffer underflow 1 receive_overflow Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`. 6 6 read-only true HasOverflow not_overflow No FIFO buffer overflow 0 overflow Has FIFO buffer overflow 1 transmit_underflow Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`. 5 5 read-only true transmit_overflow Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`. 4 4 read-only true receive_clear Clears receive FIFO overflow and underflow flags 3 3 write-only true FlagClear clear Write 1 to clear fifo flags 0x1 transmit_clear Clears transmit FIFO overflow and underflow flags 2 2 write-only true receive_dma Enable signal of receive DMA interface 1 1 true DmaEnable enable Enable DMA interface 0x1 disable Disable DMA interface 0x0 transmit_dma Enable signal of transmit DMA interface 0 0 true fifo_config_1 FIFO configuration register 1 0x84 0x00000010 0xffffffff receive_threshold Receive FIFO threshold\n\n DMA request will not be asserted if `receive_available` is less than this value 24 27 transmit_threshold Transmit FIFO threshold\n\n DMA request will not be asserted if `transmit_available` is less than this value 16 19 receive_count Count of available data in receive FIFO 8 12 read-only transmit_count Count of available data in transmit FIFO 0 4 read-only data_write FIFO write data register 0x88 0x00000000 0xffffffff write-only value Write data to FIFO 0 7 data_read FIFO read data register 0x8C 0x00000000 0xffffffff read-only value Read data from FIFO 0 7 ISO11898 ISO 11898 communication protocol 0x2000AA00 0 0x100 registers todo ?? 0 IPC Inter-processor Channel 0x2000A800 0 0x100 registers todo ?? 0 IR Infrared Remote module 0x2000A600 0 0x100 registers transmit_config ?? 0x00 transmit_interrupt ?? 0x04 2 0x04 transmit_data[%s] ?? 0x08 transmit_width ?? 0x10 receive_config ?? 0x80 receive_interrupt ?? 0x84 receive_width ?? 0x88 receive_bit_count ?? 0x90 2 0x04 receive_data[%s] ?? 0x94 TIMER Timer control 0x2000A500 0 0x1000 registers todo ?? 0 PWM Pulse-Width Modulation module 0x2000A400 0 0x100 registers config_0 Configuration register 0 0x00 config_1 Configuration register 1 0x04 period Cycle duration in clock source cycles 0x08 dead_time ?? 0x0C 4 0x04 channel_threshold[%s] ?? 0x10 interrupt_state Interrut state register 0x20 interrupt_mask Interrut mask register 0x24 interrupt_clear Clear interrupt register 0x28 interrupt_enable Interrupt enable register 0x2C 2 0x600 I2C[%s] Inter-Integrated Circuit bus 0x2000A300 0 0x100 registers config Function configuration register 0x00 0x0000000a 0xffffffff deglitch_cycle De-glitch function cycle count 28 31 packet_length Byte count for each packet 16 23 slave_address I2C transaction slave address 8 14 sub_address_length Byte count for I2C sub-address 5 6 true one Sub-addresses include 1 byte 0 two Sub-addresses include 2 bytes 1 three Sub-addresses include 3 bytes 2 four Sub-addresses include 4 bytes 3 sub_address_enable Enable sub-address fields 4 4 true enable Enable sub-address fields 1 disable Disable sub-address fields 0 clock_synchronize Enable I2C clock synchronization\n\n Enable this bit to support multi-master and clock-stretching. It should not be turned-off normally. 3 3 true enable Enable clock synchronization 1 disable Disable clock synchronization 0 deglitch_enable Enable de-glitch function on all input pins 2 2 true enable Enable de-glitch function on inputs 1 disable Disable de-glitch function on inputs 0 transfer_direction Packet transfer direction 1 1 true write Write from master side 0 read Read from master side 1 master_enable Enable signal of I2C master function\n\n Asserting this bit will trigger the transaction, and should be de-asserted after finish. 0 0 true enable Enable I2C master function 1 disable Disable I2C master function 0 interrupt Interrupt enables, states and masks 0x04 0x3f003f00 0xffffffff true fifo_error_enable Transmit or receive FIFO error interrupt enable 29 29 InterruptEnable enable Enable interrupt 1 disable Disable interrupt 0 arbitrate_lost_enable Arbitration lost interrupt enable 28 28 not_acknowledged_enable Not-acknowledged response interrupt enable 27 27 receive_fifo_ready_enable Receive FIFO ready interrupt enable 26 26 transmit_fifo_ready_enable Transmit FIFO ready interrupt enable 25 25 transfer_end_enable Transfer ended interrupt enable 24 24 arbitrate_lost_clear Write 1 to clear arbitration lost 20 20 write-only InterruptClear clear Write 1 to clear interrupt state 0x1 not_acknowledged_clear Write 1 to clear not-acknowledged response 19 19 write-only transfer_end_clear Write 1 to clear transfer ended 16 16 write-only fifo_error_mask Transmit or receive FIFO error interrupt mask 13 13 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 arbitrate_lost_mask Arbitration lost interrupt mask 12 12 not_acknowledged_mask Not-acknowledged response interrupt mask 11 11 receive_fifo_ready_mask Receive FIFO ready interrupt mask 10 10 transmit_fifo_ready_mask Transmit FIFO ready interrupt mask 9 9 transfer_end_mask Transfer ended interrupt mask 8 8 fifo_error_state Transmit or receive FIFO error interrupt state\n\n Auto cleared when FIFO overflow or underflow error flag is cleared. 5 5 read-only InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 arbitrate_lost_state Arbitration lost interrupt state 4 4 read-only not_acknowledged_state Not-acknowledged response interrupt state 3 3 read-only receive_fifo_ready_state Receive FIFO ready interrupt state\n\n Auto cleared when data is popped from receive FIFO. 2 2 read-only transmit_fifo_ready_state Transmit FIFO ready interrupt state\n\n Auto cleared when data is pushed into transmit FIFO. 1 1 read-only transfer_end_state Transfer ended interrupt state 0 0 read-only sub_address Register address of slave device 0x08 0x00000000 0xffffffff 4 8 byte[%s] I2C sub-address byte %s 0 7 read-write bus_busy Bus busy state indicator 0x0C 0x00000000 0xffffffff true force_clear Force clear I2C bus busy state\n\n Not for normal use; only use when I2C bus hangs 1 1 write-only clear Write 1 to force clear busy flag 0x1 busy Indicator to I2C bus busy signal 0 0 read-only busy Bus is busy 1 idle Bus is not busy 0 period_start Duration of start phase 0x10 0x0f0f0f0f 0xffffffff 4 8 phase[%s] Length of start condition phase %s 0 7 read-write period_stop Duration of stop phase 0x14 0x0f0f0f0f 0xffffffff 4 8 phase[%s] Length of stop condition phase %s 0 7 read-write period_data Duration of data phase 0x18 0x0f0f0f0f 0xffffffff 4 8 phase[%s] Length of data condition phase %s 0 7 read-write fifo_config_0 FIFO configuration register 0 0x80 0x00000000 0xffffffff true receive_underflow Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`. 7 7 read-only HasUnderflow not_underflow No FIFO buffer underflow 0 underflow Has FIFO buffer underflow 1 receive_overflow Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`. 6 6 read-only HasOverflow not_overflow No FIFO buffer overflow 0 overflow Has FIFO buffer overflow 1 transmit_underflow Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`. 5 5 read-only transmit_overflow Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`. 4 4 read-only receive_clear Clears receive FIFO overflow and underflow flags 3 3 write-only FlagClear clear Write 1 to clear fifo flags 0x1 transmit_clear Clears transmit FIFO overflow and underflow flags 2 2 write-only receive_dma Enable signal of receive DMA interface 1 1 DmaEnable enable Enable DMA interface 0x1 disable Disable DMA interface 0x0 transmit_dma Enable signal of transmit DMA interface 0 0 fifo_config_1 FIFO configuration register 1 0x84 0x00000002 0xffffffff receive_threshold Receive FIFO threshold\n\n DMA request will not be asserted if `receive_available` is less than this value 24 24 transmit_threshold Transmit FIFO threshold\n\n DMA request will not be asserted if `transmit_available` is less than this value 16 16 receive_count Count of available data in receive FIFO 8 9 read-only transmit_count Count of available data in transmit FIFO 0 1 read-only data_write FIFO write data register 0x88 0x00000000 0xffffffff write-only value Write data to FIFO 0 7 data_read FIFO read data register 0x8C 0x00000000 0xffffffff read-only value Read data from FIFO 0 7 1 0x100 SPI[%s] Serial Peripheral Interface 0x2000A200 0 0x100 registers config Function configuration register 0x00 interrupt_state Interrupt enables, masks and states 0x04 bus_busy Bus busy state indicator 0x08 period_control Duration of control signals 0x10 period_interval Interval bitween frames 0x14 ignore_index Receive ignore index configuration 0x18 timeout Slave mode transmit timeout values 0x1c fifo_config_0 FIFO configuration register 0 0x80 fifo_config_1 FIFO configuration register 1 0x84 data_write FIFO write data register 0x88 data_read FIFO read data register 0x8C 2 0x100 UART[%s] Universal Asynchronous Receiver Transmitter 0x2000A000 read-write 0 0x100 registers transmit_config Transmit configuration register 0x00 0x00008f00 0xffffffff transfer_length Length of words per UART transmit transfer\n\n This field is ignored when `freerun` mode is enabled. 16 31 break_bits Number of break bits for LIN protocol 13 15 stop_bits Number of stop bits 11 12 true zero_p_five 0.5 stop bits 0 one 1 stop bit 1 one_p_five 1.5 stop bits 2 two 2 stop bits 3 word_length Bit count for each transmit data word 8 10 true five Each word includes 5 bits 4 six Each word includes 6 bits 5 seven Each word includes 7 bits 6 eight Each word includes 8 bits 7 ir_inverse Inverse transmit signal output in IR mode 7 7 true inverse Inverse transmit input in IR mode 1 no_inverse Don't inverse transmit input in IR mode 0 ir_transmit Enable IR transmit mode 6 6 true enable Enable IR transmit mode 1 disable Disable IR transmit mode 0 parity_mode Select transmit parity mode if enabled 5 5 true odd Odd parity if `parity_enable` is set 1 even Even parity if `parity_enable` is set 0 parity_enable Enable transmit parity check 4 4 true enable Enable transmit parity check 1 disable Disable transmit parity check 0 lin_transmit Local Interconnect Network protocol enable 3 3 true enable Enable Local Interconnect Network protocol 1 disable Disable Local Interconnect Network protocol 0 freerun Enable freerun mode 2 2 true enable Enable freerun mode 1 disable Disable freerun mode 0 cts Enable Clear-to-Send flow control signal 1 1 true enable Enable Clear-to-Send flow control signal 1 disable Disable Clear-to-Send flow control signal 0 function Enable transmit function 0 0 true enable Enable UART receive function signal 1 disable Disable UART receive function signal 0 receive_config Receive configuration register 0x04 0x00000700 0xffffffff transfer_length Length of words per UART receive transfer 16 31 deglitch_cycle De-glitch function cycle count 12 15 deglitch_enable Enable receive de-glitch function 11 11 true enable Enable de-glitch function upon receive 1 disable Disable de-glitch function upon receive 0 word_length Bit count for each receive data word 8 10 true five Each word includes 5 bits 4 six Each word includes 6 bits 5 seven Each word includes 7 bits 6 eight Each word includes 8 bits 7 ir_inverse Inverse receive signal output in IR mode 7 7 true inverse Inverse receive input in IR mode 1 no_inverse Don't inverse receive input in IR mode 0 ir_receive Enable IR receive mode 6 6 true enable Enable IR receive mode 1 disable Disable IR receive mode 0 parity_mode Select receive parity mode if enabled 5 5 true odd Odd parity if `parity_enable` is set 1 even Even parity if `parity_enable` is set 0 parity_enable Enable receive parity check 4 4 true enable Enable receive parity check 1 disable Disable receive parity check 0 lin_receive Local Interconnect Network protocol enable 3 3 true enable Enable Local Interconnect Network protocol 1 disable Disable Local Interconnect Network protocol 0 auto_baudrate Enable receive auto baudrate detection 1 1 true enable Enable auto baudrate upon receive 1 disable Disable auto baudrate upon receive 0 function Enable receive function 0 0 true enable Enable UART receive function signal 1 disable Disable UART receive function signal 0 bit_period Bit period control register 0x08 0x00ff00ff 0xffffffff receive Period of each receive bit\n\n This field relates to baudrate. 16 31 transmit Period of each transmit bit\n\n This field relates to baudrate. 0 15 data_config Data configuration register 0x0C 0x00000000 0xffffffff true bit_order Enable bit inverse in each data word 0 0 inverse Each byte is sent out MSB-first 1 no_inverse Each byte is sent out LSB-first 0 transmit_position IR-mode transmit position control 0x10 0x009f0070 0xffffffff stop Stop position of transmit IR pulse 16 31 start Start position of transmit IR pulse 0 15 receive_position IR-mode receive position control 0x14 0x0000006f 0xffffffff start Start position of received pulse recovered from IR signal 0 15 receive_timeout Receive Time-Out interrupt control 0x18 0x0000000f 0xffffffff value Timeout interrupt triggering value by bits received 0 7 signal_override Manual override of flow control signal 0x1C 0x00000000 0xffffffff true rts_value Value to override Request-to-Send signal if override is enabled 3 3 SignalAssert high Assert this signal 1 low Deassert this signal 0 rts_signal Enable manual override of Request-to-Send flow control signal 2 2 OverrideEnable enable Enable manual override of this signal 1 disable Disable manual override of this signal 0 transmit_value Value to override transmit signal if override is enabled 1 1 transmit_signal Enable manual override of transmit signal 0 0 interrupt_state Interrupt state register 0x20 0x00000004 0xffffffff read-only true auto_baudrate_five_five Receive auto baudrate detection finished using 0x55 occurred 11 11 InterruptState has_interrupt Has interrupt 1 no_interrupt No interrupt occurred 0 auto_baudrate_start_bit Receive auto baudrate detection finished using start bit occurred 10 10 receive_byte_count Receive byte count reached occurred 9 9 receive_sync_error Receive LIN mode synchronization field error occurred 8 8 receive_fifo_error Receive FIFO overflow or underflow occurred 7 7 transmit_fifo_error Transmit FIFO overflow or underflow occurred 6 6 receive_parity Receive parity check failure occurred 5 5 receive_timeout Receive timed-out interrupt occurred 4 4 receive_fifo_ready Receive FIFO ready signal raised 3 3 transmit_fifo_ready Transmit FIFO ready signal raised 2 2 receive_transfer Receive transfer finish signal raised 1 1 transmit_transfer Transmit transfer finish signal raised 0 0 interrupt_mask Interrupt mask register 0x24 0x00000fff 0xffffffff true auto_baudrate_five_five Receive auto baudrate detection finished using 0x55 occurred 11 11 InterruptMask mask Mask interrupt 1 unmask Unmask interrupt 0 auto_baudrate_start_bit Receive auto baudrate detection finished using start bit interrupt mask 10 10 receive_byte_count Receive byte count reached interrupt mask 9 9 receive_sync_error Receive LIN mode synchronization field error interrupt mask 8 8 receive_fifo_error Receive FIFO overflow or underflow interrupt mask 7 7 transmit_fifo_error Transmit FIFO overflow or underflow interrupt mask 6 6 receive_parity Receive parity check failure interrupt mask 5 5 receive_timeout Receive timed-out interrupt mask 4 4 receive_fifo_ready Receive FIFO ready signal interrupt mask 3 3 transmit_fifo_ready Transmit FIFO ready signal interrupt mask 2 2 receive_transfer Receive transfer finish signal interrupt mask 1 1 transmit_transfer Transmit transfer finish signal interrupt mask 0 0 interrupt_clear Clear interrupt register 0x28 0x00000000 0xffffffff write-only true auto_baudrate_five_five Write 1 to clear receive auto baudrate detection finished using 0x55 11 11 InterruptClear clear Write 1 to clear interrupt state 0x1 auto_baudrate_start_bit Write 1 to clear receive auto baudrate detection finished using start bit 10 10 receive_byte_count Write 1 to clear receive byte count reached 9 9 receive_sync_error Write 1 to clear receive LIN mode synchronization field error 8 8 receive_parity Write 1 to clear receive parity check failure 5 5 receive_timeout Write 1 to clear receive timed-out 4 4 receive_transfer Write 1 to clear receive transfer finish signal 1 1 transmit_transfer Write 1 to clear transmit transfer finish signal 0 0 interrupt_enable Interrupt enable register 0x2C 0x000000ff 0xffffffff true auto_baudrate_five_five Receive auto baudrate detection finished using 0x55 interrupt enable 11 11 InterruptEnable enable Enable interrupt 1 disable Disable interrupt 0 auto_baudrate_start_bit Receive auto baudrate detection finished using start bit interrupt enable 10 10 receive_byte_count Receive byte count reached interrupt enable 9 9 receive_sync_error Receive LIN mode synchronization field error interrupt enable 8 8 receive_fifo_error Receive FIFO overflow or underflow interrupt enable 7 7 transmit_fifo_error Transmit FIFO overflow or underflow interrupt enable 6 6 receive_parity Receive parity check failure interrupt enable 5 5 receive_timeout Receive timed-out interrupt enable 4 4 receive_fifo_ready Receive FIFO ready signal interrupt enable 3 3 transmit_fifo_ready Transmit FIFO ready signal interrupt enable 2 2 receive_transfer Receive transfer signal interrupt enable 1 1 transmit_transfer Transmit transfer signal interrupt enable 0 0 bus_state Bus state register 0x30 0x00000000 0xffffffff read-only receive_busy Indicates that UART receive bus is busy 1 1 BusBusy busy Bus is busy 1 idle Bus is not busy 0 transmit_busy Indicates that UART transmit bus is busy 0 0 auto_baudrate Auto baudrate detection register 0x34 0x00000000 0xffffffff read-only by_five_five Bit period of auto baudrate detection using codeword 0x55 16 31 by_start_bit Bit period of auto baudrate detection using start bit 0 15 fifo_config_0 FIFO configuration register 0 0x80 0x00000000 0xffffffff true receive_underflow Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`. 7 7 read-only HasUnderflow not_underflow No FIFO buffer underflow 0 underflow Has FIFO buffer underflow 1 receive_overflow Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`. 6 6 read-only HasOverflow not_overflow No FIFO buffer overflow 0 overflow Has FIFO buffer overflow 1 transmit_underflow Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`. 5 5 read-only transmit_overflow Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`. 4 4 read-only receive_clear Clears receive FIFO overflow and underflow flags 3 3 write-only FlagClear clear Write 1 to clear fifo flags 0x1 transmit_clear Clears transmit FIFO overflow and underflow flags 2 2 write-only receive_dma Enable signal of receive DMA interface 1 1 DmaEnable enable Enable DMA interface 0x1 disable Disable DMA interface 0x0 transmit_dma Enable signal of transmit DMA interface 0 0 fifo_config_1 FIFO configuration register 1 0x84 0x00000020 0xffffffff receive_threshold Receive FIFO threshold\n\n DMA request will not be asserted if `receive_available` is less than this value 24 28 transmit_threshold Transmit FIFO threshold\n\n DMA request will not be asserted if `transmit_available` is less than this value 16 20 receive_count Count of available data in receive FIFO 8 13 read-only transmit_count Count of available data in transmit FIFO 0 5 read-only data_write FIFO write data register 0x88 0x00000000 0xffffffff write-only value Write data to FIFO 0 7 data_read FIFO read data register 0x8C 0x00000000 0xffffffff read-only value Read data from FIFO 0 7 MISC Chip Miscellaneous control 0x20009000 0 0x1000 registers todo ?? 0 CCI Camera Control Interface 0x20008000 0 0x1000 registers todo ?? 0 EFUSE eFuse memory control 0x20056000 0 0x1000 registers todo ?? 0 SEC Secure Engine 0x20004000 0 0x1000 registers todo ?? 0 DEBUG Secure debug configuration 0x20003000 0 0x100 registers 2 0x04 identify[%s] Unique module identifier 0x00 read-only word Read identifier part in word 0 31 4 0x04 password[%s] Password of debug module 0x08 0x00000000 0xffffffff word Read or write password in word 0 31 control Module control register 0x18 0x00000000 0xffffffff password_busy ?? 0 0 read-only password_trigger ?? 1 1 password_count ?? 4 23 debug_mode ?? 24 27 read-only debug_enable Read if debug module is enabled 28 31 read-only AGC Automatic Gain Control 0x20002C00 0 0x1000 registers todo ?? 0 GPIP Generic DAC, ADC and ACOMP interface control 0x20002000 0 0x400 registers todo ?? 0 GLB Global configuration register 0x20000000 0 0x1000 registers chip_inform Chip information register 0x000 core_config_16 Core configuration register 16 0x050 core_config_17 Core configuration register 17 0x054 core_config_18 Core configuration register 18 0x058 core_config_19 Core configuration register 19 0x05C core_config_20 Core configuration register 20 0x060 core_config_21 Core configuration register 21 0x064 core_config_22 Core configuration register 22 0x068 core_config_23 Core configuration register 23 0x06C core_config_24 Core configuration register 24 0x070 core_config_25 Core configuration register 25 0x074 sys_config_0 System configuration register 0 0x090 sys_config_1 System configuration register 1 0x094 bus_config_0 Bus configuration register 0 0x0A0 emi_config Electromagnetic interference configuration 0x0E0 rtc_config Real-time clock configuration 0x0F0 adc_config Analog-to-digital convert configuration 0x110 dac_config_0 Digital-to-analog convert configuration 0 0x120 dac_config_1 Digital-to-analog convert configuration 1 0x124 dac_config_2 Digital-to-analog convert configuration 2 0x128 dac_config_3 Digital-to-analog convert configuration 3 0x12C dma_config_0 Direct memory access configuration 0 0x130 dma_config_1 Direct memory access configuration 1 0x134 dma_config_2 Direct memory access configuration 2 0x138 ir_config_0 Infrared configuration register 0 0x140 ir_config_1 Infrared configuration register 1 0x144 uart_config Universal Asynchronous Receiver/Transmitter configuration 0x150 clock_divide Peripheral clock divide factor 0 2 clock_enable Peripheral level clock gate enable 4 4 hibernate_clock_source Reads clock source from hibernate registers 7 7 read-only hibernate_clock_source_2 Reads clock source from hibernate registers 22 22 read-only uart2_mode Select interface mode for UART2 peripheral 25 31 true Uart2Mode uart Universal Asynchronous Receiver/Transmitter interface 0 iso11898 ISO 11898 communication protocol interface 1 uart_signal_0 Universal Asynchronous Receiver/Transmitter signal configuration 0 0x154 true 8 4 function_0[%s] Select peripheral function for UART signal %s 0 7 Function uart0_rts UART0 Request-to-Send flow control 0 uart0_cts UART0 Clear-to-Send flow control 1 uart0_txd UART0 transmit data 2 uart0_rxd UART0 receive data 3 uart1_rts UART1 Request-to-Send flow control 4 uart1_cts UART1 Clear-to-Send flow control 5 uart1_txd UART1 transmit data 6 uart1_rxd UART1 receive data 7 uart2_rts UART2 Request-to-Send flow control 8 uart2_cts UART2 Clear-to-Send flow control 9 uart2_txd UART2 transmit data 10 uart2_rxd UART2 receive data 11 uart_signal_1 Universal Asynchronous Receiver/Transmitter signal configuration 1 0x158 true 4 4 function_1[%s] Select peripheral function for UART signal %s (offset by 8) 0 7 flash_config Serial flash configuration 0x170 i2c_config Inter-Integrated Circuit bus configuration 0x180 i2s_config Inter-IC Sound configuration 0x190 spi_config Serial Peripheral Interface configuration 0x1B0 quad_config Quadrature decoder configuration 0x1C0 digit_clock_0 Digital clock configuration 0 0x250 digit_clock_1 Digital clock configuration 1 0x254 digit_clock_2 Digital clock configuration 2 0x258 radio_config Radio configuration register 0x260 debug_config_0 Debug configuration register 0 0x2E0 debug_config_1 Debug configuration register 1 0x2E4 debug_config_2 Debug configuration register 2 0x2E8 debug_config_3 Debug configuration register 3 0x2EC debug_config_4 Debug configuration register 4 0x2F0 test_mode Memory Built-in Self Test mode 0x300 test_done Memory Built-in Self Test done state 0x308 test_fail Memory Built-in Self Test fail state 0x310 audio_config_0 Audio configuration register 0 0x340 audio_config_1 Audio configuration register 1 0x344 emac_config Ethernet Media Access Control register 0x390 cam_config ?? 0x420 46 0x04 gpio_config[%s] Generic Purpose Input/Output config 0x8C4 pin_mode Pin input/output mode switch 30 31 PinMode input Digital input mode 0 output Digital output mode 1 alternate Alternate function mode 2 analog Analog mode 3 input_value Input value 28 28 output_clear Clear output value to 0 26 26 output_set Set output value to 1 25 25 output_value Output value 24 24 interrupt_mask Pin interrupt mask 22 22 interrupt_state Pin interrupt state 21 21 interrupt_clear Clear pin interrupt flag 20 20 interrupt_mode Select pin interrupt mode 16 19 alternate Pin alternate function switch 8 12 Alternate sdh Secure Digital host 0 spi0 Serial Peripheral Interface 0 1 flash Flash control 2 i2s Inter-IC Sound 3 pdm Pulse Density Modulation 4 i2c0 Inter-Integrated Circuit bus 0 5 i2c1 Inter-Integrated Circuit bus 1 6 uart Universal Asynchronous Receiver/Transmitter 7 emac Ethernet Media Access Control 8 cam ?? 9 analog ?? 10 gpio Generic Purpose Input/Output 11 pwm0 Pulse-Width Modulation module 0 16 pwm1 Pulse-Width Modulation module 1 17 spi1 Serial Peripheral Interface 1 18 i2c2 Inter-Integrated Circuit bus 2 19 i2c3 Inter-Integrated Circuit bus 3 20 mm_uart Multimedia subsystem Universal Asynchronous Receiver/Transmitter 21 dbi_b ?? 22 dbi_c ?? 23 dpi ?? 24 jtag_lp Low power core JTAG interface 25 jtag_m0 M0 core JTAG interface 26 jtag_d0 D0 core JTAG interface 27 clock_out Clock output 31 output_function Enable output signal 6 6 pull_down Enable internal pull-down 5 5 pull_up Enable internal pull-up 4 4 drive Drive strength 2 3 schmitt Enable schmitt trigger 1 1 input_function Enable input signal 0 0 2 0x04 gpio_input[%s] Read value from Generic Purpose Input/Output pins 0xAC4 2 0x04 gpio_output[%s] Write value to Generic Purpose Input/Output pins 0xAE4 2 0x04 gpio_set[%s] Set pin output value to high 0xAEC 2 0x04 gpio_clear[%s] Set pin output value to low 0xAF4