# Generated by Yosys 0.27+3 (git sha1 b58664d44, x86_64-conda-linux-gnu-cc 11.2.0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/root/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1678231239250/work=/usr/local/src/conda/yosys-0.27_4_gb58664d44 -fdebug-prefix-map=/home/eecs/joonho.whangbo/.conda-yosys=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)

.model Adder
.inputs clock reset io_a[0] io_a[1] io_b[0] io_b[1]
.outputs io_c[0] io_c[1]
.names $false
.names $true
1
.names $undef
.names io_b[1] io_a[1] $abc$112$new_n9_ $techmap$add$Adder.sv:12$2.$auto$alumacc.cc:485:replace_alu$81.Y[1]
001 1
010 1
100 1
111 1
.names io_b[0] io_a[0] $abc$112$new_n9_
11 1
.names io_b[0] io_a[0] $techmap$add$Adder.sv:12$2.$auto$alumacc.cc:485:replace_alu$81.X[0]
01 1
10 1
.latch $techmap$add$Adder.sv:12$2.$auto$alumacc.cc:485:replace_alu$81.X[0] io_c[0] re clock 2
.latch $techmap$add$Adder.sv:12$2.$auto$alumacc.cc:485:replace_alu$81.Y[1] io_c[1] re clock 2
.names $techmap$add$Adder.sv:12$2.$auto$alumacc.cc:485:replace_alu$81.X[0] $techmap$add$Adder.sv:12$2.$auto$alumacc.cc:485:replace_alu$81.Y[0]
1 1
.end