# Generated by Yosys 0.27+3 (git sha1 b58664d44, x86_64-conda-linux-gnu-cc 11.2.0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/root/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1678231239250/work=/usr/local/src/conda/yosys-0.27_4_gb58664d44 -fdebug-prefix-map=/home/eecs/joonho.whangbo/.conda-yosys=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)

.model Const
.inputs clock reset io_input[0] io_input[1] io_input[2] io_input[3] io_input[4] io_input[5] io_input[6] io_input[7]
.outputs io_outSum[0] io_outSum[1] io_outSum[2] io_outSum[3] io_outSum[4] io_outSum[5] io_outSum[6] io_outSum[7] io_outAnd[0] io_outAnd[1] io_outAnd[2] io_outAnd[3] io_outAnd[4] io_outAnd[5] io_outAnd[6] io_outAnd[7] io_outOr[0] io_outOr[1] io_outOr[2] io_outOr[3] io_outOr[4] io_outOr[5] io_outOr[6] io_outOr[7] io_outXor[0] io_outXor[1] io_outXor[2] io_outXor[3] io_outXor[4] io_outXor[5] io_outXor[6] io_outXor[7]
.names $false
.names $true
1
.names $undef
.names io_input[3] io_input[2] io_input[1] $0\io_outXor_REG[7:0][3]
011 1
100 1
101 1
110 1
.names io_input[5] io_input[4] $abc$316$new_n30_ $0\io_outXor_REG[7:0][5]
010 1
100 1
101 1
111 1
.names io_input[3] io_input[1] io_input[2] $abc$316$new_n30_
000 1
001 1
010 1
.names io_input[7] io_input[6] $abc$316$new_n32_ $0\io_outXor_REG[7:0][7]
000 1
001 1
011 1
110 1
.names io_input[5] $abc$316$new_n30_ io_input[4] $abc$316$new_n32_
000 1
010 1
011 1
.names io_input[2] io_input[1] _d_T[2]
01 1
10 1
.names io_input[4] $abc$316$new_n30_ _d_T[4]
00 1
11 1
.names io_input[6] $abc$316$new_n32_ _d_T[6]
00 1
11 1
.names io_input[0] io_input[1] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[1]
01 1
10 1
.names io_input[2] $abc$316$new_n38_ $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[2]
01 1
10 1
.names io_input[0] io_input[1] $abc$316$new_n38_
11 1
.names io_input[3] io_input[2] $abc$316$new_n38_ $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[3]
000 1
001 1
010 1
111 1
.names io_input[4] $abc$316$new_n41_ $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[4]
01 1
10 1
.names io_input[3] $abc$316$new_n38_ io_input[2] $abc$316$new_n41_
000 1
001 1
010 1
.names io_input[5] $abc$316$new_n41_ io_input[4] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[5]
010 1
100 1
101 1
111 1
.names io_input[6] $abc$316$new_n44_ $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[6]
00 1
11 1
.names $abc$316$new_n41_ io_input[4] io_input[5] $abc$316$new_n44_
100 1
.names io_input[7] io_input[6] $abc$316$new_n44_ $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[7]
010 1
100 1
101 1
111 1
.names io_input[1] _d_T[1]
0 1
.names io_input[0] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[0]
0 1
.names $0\io_outXor_REG[7:0][3] _d_T[3]
0 1
.names $0\io_outXor_REG[7:0][5] _d_T[5]
0 1
.names $0\io_outXor_REG[7:0][7] _d_T[7]
0 1
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[0] io_outSum[0] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[1] io_outSum[1] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[2] io_outSum[2] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[3] io_outSum[3] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[4] io_outSum[4] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[5] io_outSum[5] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[6] io_outSum[6] re clock 2
.latch $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[7] io_outSum[7] re clock 2
.latch io_input[0] io_outOr[0] re clock 2
.latch io_input[1] io_outXor[1] re clock 2
.latch _d_T[2] io_outOr[2] re clock 2
.latch $0\io_outXor_REG[7:0][3] io_outXor[3] re clock 2
.latch _d_T[4] io_outOr[4] re clock 2
.latch $0\io_outXor_REG[7:0][5] io_outXor[5] re clock 2
.latch _d_T[6] io_outOr[6] re clock 2
.latch $0\io_outXor_REG[7:0][7] io_outXor[7] re clock 2
.latch _d_T[1] io_outAnd[1] re clock 2
.latch _d_T[3] io_outAnd[3] re clock 2
.latch _d_T[5] io_outAnd[5] re clock 2
.latch _d_T[7] io_outAnd[7] re clock 2
.names io_input[0] $0\io_outXor_REG[7:0][0]
1 1
.names io_input[1] $0\io_outXor_REG[7:0][1]
1 1
.names _d_T[2] $0\io_outXor_REG[7:0][2]
1 1
.names _d_T[4] $0\io_outXor_REG[7:0][4]
1 1
.names _d_T[6] $0\io_outXor_REG[7:0][6]
1 1
.names io_input[1] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[1]
1 1
.names io_input[2] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[2]
1 1
.names io_input[6] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[6]
1 1
.names io_input[7] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[7]
1 1
.names $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.X[0] $techmap$add$Const.sv:18$3.$auto$alumacc.cc:485:replace_alu$92.Y[0]
1 1
.names io_input[0] _d_T[0]
1 1
.names $false io_outAnd[0]
1 1
.names $false io_outAnd[2]
1 1
.names $false io_outAnd[4]
1 1
.names $false io_outAnd[6]
1 1
.names $true io_outOr[1]
1 1
.names $true io_outOr[3]
1 1
.names $true io_outOr[5]
1 1
.names $true io_outOr[7]
1 1
.names io_outOr[0] io_outXor[0]
1 1
.names io_outOr[2] io_outXor[2]
1 1
.names io_outOr[4] io_outXor[4]
1 1
.names io_outOr[6] io_outXor[6]
1 1
.end