# Calyx compiler
calyx-base = /Users/rachitnigam/git/calyx
calyx-exe = $calyx-base/target/debug/calyx
rule calyx
  command = $calyx-exe -l $calyx-base -b $backend $args $in > $out

# RTL simulation
python = python3
json_dat = $python /Users/rachitnigam/git/calyx/fud2/rsrc/json-dat.py
rule hex-data
  command = $json_dat --from-json $in $out
rule json-data
  command = $json_dat --to-json $out $in
testbench = /Users/rachitnigam/git/calyx/fud2/rsrc/tb.sv
sim_data = tests/correctness/seq-mem-d4-add.futil.data
datadir = sim_data
build $datadir: hex-data $sim_data
rule sim-run
  command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out
cycle-limit = 500000000

# Verilator
verilator = verilator
cycle-limit = 500000000
rule verilator-compile
  command = $verilator $in $testbench --trace --binary --top-module TOP -fno-inline -Mdir $out-dir
rule cp
  command = cp $in $out

# build targets
build seq-mem-d4-add.sv: calyx tests/correctness/seq-mem-d4-add.futil
  backend = verilog
build verilator-out/VTOP: verilator-compile seq-mem-d4-add.sv
  out-dir = verilator-out
build seq-mem-d4-add.exe: cp verilator-out/VTOP
build sim.log: sim-run seq-mem-d4-add.exe $datadir
  bin = seq-mem-d4-add.exe
  args = +NOTRACE=1
build seq-mem-d4-add.json: json-data $datadir sim.log

default seq-mem-d4-add.json