module comb_mem_d1 #( parameter WIDTH = 32, parameter SIZE = 16, parameter IDX_SIZE = 4 ) ( input wire logic [IDX_SIZE-1:0] addr0, input wire logic [ WIDTH-1:0] write_data, input wire logic write_en, input wire logic clk, input wire logic reset, output logic [ WIDTH-1:0] read_data, output logic done ); logic [WIDTH-1:0] mem[SIZE-1:0]; /* verilator lint_off WIDTH */ assign read_data = mem[addr0]; always_ff @(posedge clk) begin if (reset) done <= '0; else if (write_en) done <= '1; else done <= '0; end always_ff @(posedge clk) begin if (!reset && write_en) mem[addr0] <= write_data; end // Check for out of bounds access `ifdef VERILATOR always_comb begin if (addr0 >= SIZE) $error( "comb_mem_d1: Out of bounds access\n", "addr0: %0d\n", addr0, "SIZE: %0d", SIZE ); end `endif endmodule module comb_mem_d2 #( parameter WIDTH = 32, parameter D0_SIZE = 16, parameter D1_SIZE = 16, parameter D0_IDX_SIZE = 4, parameter D1_IDX_SIZE = 4 ) ( input wire logic [D0_IDX_SIZE-1:0] addr0, input wire logic [D1_IDX_SIZE-1:0] addr1, input wire logic [ WIDTH-1:0] write_data, input wire logic write_en, input wire logic clk, input wire logic reset, output logic [ WIDTH-1:0] read_data, output logic done ); /* verilator lint_off WIDTH */ logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0]; assign read_data = mem[addr0][addr1]; always_ff @(posedge clk) begin if (reset) done <= '0; else if (write_en) done <= '1; else done <= '0; end always_ff @(posedge clk) begin if (!reset && write_en) mem[addr0][addr1] <= write_data; end // Check for out of bounds access `ifdef VERILATOR always_comb begin if (addr0 >= D0_SIZE) $error( "comb_mem_d2: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE ); if (addr1 >= D1_SIZE) $error( "comb_mem_d2: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE ); end `endif endmodule module comb_mem_d3 #( parameter WIDTH = 32, parameter D0_SIZE = 16, parameter D1_SIZE = 16, parameter D2_SIZE = 16, parameter D0_IDX_SIZE = 4, parameter D1_IDX_SIZE = 4, parameter D2_IDX_SIZE = 4 ) ( input wire logic [D0_IDX_SIZE-1:0] addr0, input wire logic [D1_IDX_SIZE-1:0] addr1, input wire logic [D2_IDX_SIZE-1:0] addr2, input wire logic [ WIDTH-1:0] write_data, input wire logic write_en, input wire logic clk, input wire logic reset, output logic [ WIDTH-1:0] read_data, output logic done ); /* verilator lint_off WIDTH */ logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0]; assign read_data = mem[addr0][addr1][addr2]; always_ff @(posedge clk) begin if (reset) done <= '0; else if (write_en) done <= '1; else done <= '0; end always_ff @(posedge clk) begin if (!reset && write_en) mem[addr0][addr1][addr2] <= write_data; end // Check for out of bounds access `ifdef VERILATOR always_comb begin if (addr0 >= D0_SIZE) $error( "comb_mem_d3: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE ); if (addr1 >= D1_SIZE) $error( "comb_mem_d3: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE ); if (addr2 >= D2_SIZE) $error( "comb_mem_d3: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE ); end `endif endmodule module comb_mem_d4 #( parameter WIDTH = 32, parameter D0_SIZE = 16, parameter D1_SIZE = 16, parameter D2_SIZE = 16, parameter D3_SIZE = 16, parameter D0_IDX_SIZE = 4, parameter D1_IDX_SIZE = 4, parameter D2_IDX_SIZE = 4, parameter D3_IDX_SIZE = 4 ) ( input wire logic [D0_IDX_SIZE-1:0] addr0, input wire logic [D1_IDX_SIZE-1:0] addr1, input wire logic [D2_IDX_SIZE-1:0] addr2, input wire logic [D3_IDX_SIZE-1:0] addr3, input wire logic [ WIDTH-1:0] write_data, input wire logic write_en, input wire logic clk, input wire logic reset, output logic [ WIDTH-1:0] read_data, output logic done ); /* verilator lint_off WIDTH */ logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0][D3_SIZE-1:0]; assign read_data = mem[addr0][addr1][addr2][addr3]; always_ff @(posedge clk) begin if (reset) done <= '0; else if (write_en) done <= '1; else done <= '0; end always_ff @(posedge clk) begin if (!reset && write_en) mem[addr0][addr1][addr2][addr3] <= write_data; end // Check for out of bounds access `ifdef VERILATOR always_comb begin if (addr0 >= D0_SIZE) $error( "comb_mem_d4: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE ); if (addr1 >= D1_SIZE) $error( "comb_mem_d4: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE ); if (addr2 >= D2_SIZE) $error( "comb_mem_d4: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE ); if (addr3 >= D3_SIZE) $error( "comb_mem_d4: Out of bounds access\n", "addr3: %0d\n", addr3, "D3_SIZE: %0d", D3_SIZE ); end `endif endmodule