CC2652 1.1 CC2652 CM4 r1p0 little true true 3 false 8 32 32 read-write 0xFFFFFFFF AUX_ADI4 0x400CB000 0 0x200 registers Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic) MUX0 0x0 8 Internal. Only to be used through TI provided API. RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 ADCCOMPB_IN [6:6] Internal. Only to be used through TI provided API. 1 6 VDDR_1P8V 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. RESERVED4 [5:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 4 COMPA_REF [3:0] Internal. Only to be used through TI provided API. 4 0 ADCVREFP 8 Internal. Only to be used through TI provided API. VDDS 4 Internal. Only to be used through TI provided API. VSS 2 Internal. Only to be used through TI provided API. DCOUPL 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. 0x0 MUX1 0x1 8 Internal. Only to be used through TI provided API. COMPA_IN [7:0] Internal. Only to be used through TI provided API. 8 0 AUXIO19 128 Internal. Only to be used through TI provided API. AUXIO20 64 Internal. Only to be used through TI provided API. AUXIO21 32 Internal. Only to be used through TI provided API. AUXIO22 16 Internal. Only to be used through TI provided API. AUXIO23 8 Internal. Only to be used through TI provided API. AUXIO24 4 Internal. Only to be used through TI provided API. AUXIO25 2 Internal. Only to be used through TI provided API. AUXIO26 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. 0x0 MUX2 0x2 8 Internal. Only to be used through TI provided API. ADCCOMPB_IN [7:3] Internal. Only to be used through TI provided API. 5 3 VDDS 16 Internal. Only to be used through TI provided API. VSS 8 Internal. Only to be used through TI provided API. DCOUPL 4 Internal. Only to be used through TI provided API. ATEST1 2 Internal. Only to be used through TI provided API. ATEST0 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. DAC_VREF_SEL [2:0] Internal. Only to be used through TI provided API. 3 0 VDDS 4 Internal. Only to be used through TI provided API. ADCREF 2 Internal. Only to be used through TI provided API. DCOUPL 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. 0x0 MUX3 0x3 8 Internal. Only to be used through TI provided API. ADCCOMPB_IN [7:0] Internal. Only to be used through TI provided API. 8 0 AUXIO19 128 Internal. Only to be used through TI provided API. AUXIO20 64 Internal. Only to be used through TI provided API. AUXIO21 32 Internal. Only to be used through TI provided API. AUXIO22 16 Internal. Only to be used through TI provided API. AUXIO23 8 Internal. Only to be used through TI provided API. AUXIO24 4 Internal. Only to be used through TI provided API. AUXIO25 2 Internal. Only to be used through TI provided API. AUXIO26 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. 0x0 ISRC 0x4 8 Current Source Strength and trim control for current source. Only to be used through TI provided API. TRIM [7:2] Adjust current from current source. Output currents may be combined to get desired total current. 6 2 11P75U 32 11.75 uA 4P5U 16 4.5 uA 2P0U 8 2.0 uA 1P0U 4 1.0 uA 0P5U 2 0.5 uA 0P25U 1 0.25 uA NC 0 No current connected RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 EN [0:0] Current source enable 1 0 0x0 COMP 0x5 8 Comparator Control COMPA and COMPB comparators. Only to be used through TI provided API. COMPA_REF_RES_EN [7:7] Enables 400kohm resistance from COMPA reference node to ground. Used with COMPA_REF_CURR_EN to generate voltage reference for cap-sense. 1 7 COMPA_REF_CURR_EN [6:6] Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for cap-sense. 1 6 LPM_BIAS_WIDTH_TRIM [5:3] Internal. Only to be used through TI provided API. 3 3 COMPB_EN [2:2] COMPB enable 1 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 COMPA_EN [0:0] COMPA enable 1 0 0x0 MUX4 0x7 8 Internal. Only to be used through TI provided API. COMPA_REF [7:0] Internal. Only to be used through TI provided API. 8 0 AUXIO19 128 Internal. Only to be used through TI provided API. AUXIO20 64 Internal. Only to be used through TI provided API. AUXIO21 32 Internal. Only to be used through TI provided API. AUXIO22 16 Internal. Only to be used through TI provided API. AUXIO23 8 Internal. Only to be used through TI provided API. AUXIO24 4 Internal. Only to be used through TI provided API. AUXIO25 2 Internal. Only to be used through TI provided API. AUXIO26 1 Internal. Only to be used through TI provided API. NC 0 Internal. Only to be used through TI provided API. 0x0 ADC0 0x8 8 ADC Control 0 ADC Sample Control. Only to be used through TI provided API. SMPL_MODE [7:7] ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode The ADC does a sample-and-hold before conversion. In synchronous mode the sampling starts when the ADC clock detects a rising edge on the trigger signal. Jitter/uncertainty will be inferred in the detection if the trigger signal originates from a domain that is asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the the duration of sampling. Conversion starts immediately after sampling ends. In asynchronous mode the sampling is continuous when enabled. Sampling ends and conversion starts immediately with the rising edge of the trigger signal. Sampling restarts when the conversion has finished. Asynchronous mode is useful when it is important to avoid jitter in the sampling instant of an externally driven signal 1 7 SMPL_CYCLE_EXP [6:3] Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. 4 3 10P9_MS 15 65536x 6 MHz clock periods = 10.9ms 5P46_MS 14 32768x 6 MHz clock periods = 5.46ms 2P73_MS 13 16384x 6 MHz clock periods = 2.73ms 1P37_MS 12 8192x 6 MHz clock periods = 1.37ms 682_US 11 4096x 6 MHz clock periods = 682us 341_US 10 2048x 6 MHz clock periods = 341us 170_US 9 1024x 6 MHz clock periods = 170us 85P3_US 8 512x 6 MHz clock periods = 85.3us 42P6_US 7 256x 6 MHz clock periods = 42.6us 21P3_US 6 128x 6 MHz clock periods = 21.3us 10P6_US 5 64x 6 MHz clock periods = 10.6us 5P3_US 4 32x 6 MHz clock periods = 5.3us 2P7_US 3 16x 6 MHz clock periods = 2.7us RESERVED2 [2:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 2 RESET_N [1:1] Reset ADC digital subchip, active low. ADC must be reset every time it is reconfigured. 0: Reset 1: Normal operation 1 1 EN [0:0] ADC Enable 0: Disable 1: Enable 1 0 0x0 ADC1 0x9 8 ADC Control 1 ADC Comparator Control. Only to be used through TI provided API. RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 SCALE_DIS [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 ADCREF0 0xa 8 ADC Reference 0 Control reference used by the ADC. Only to be used through TI provided API. SPARE7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 REF_ON_IDLE [6:6] Enable ADCREF in IDLE state. 0: Disabled in IDLE state 1: Enabled in IDLE state Keep ADCREF enabled when ADC0.SMPL_MODE = 0. Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than 0x6 (21.3us sampling time). 1 6 IOMUX [5:5] Internal. Only to be used through TI provided API. 1 5 EXT [4:4] Internal. Only to be used through TI provided API. 1 4 SRC [3:3] ADC reference source: 0: Fixed reference = 4.3V 1: Relative reference = VDDS 1 3 RESERVED1 [2:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 1 EN [0:0] ADC reference module enable: 0: ADC reference module powered down 1: ADC reference module enabled 1 0 0x0 ADCREF1 0xb 8 ADC Reference 1 Control reference used by the ADC. Only to be used through TI provided API. RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 VTRIM [5:0] Trim output voltage of ADC fixed reference (64 steps, 2's complement). Applies only for ADCREF0.SRC = 0. Examples: 0x00 - nominal voltage 1.43V 0x01 - nominal + 0.4% 1.435V 0x3F - nominal - 0.4% 1.425V 0x1F - maximum voltage 1.6V 0x20 - minimum voltage 1.3V 6 0 0x0 LPMBIAS 0xe 8 Internal. Only to be used through TI provided API. SPARE6 [7:6] Internal. Only to be used through TI provided API. 2 6 LPM_TRIM_IOUT [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 STAT 0xf 8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SPARE0 [7:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 0 0x0 AON_BATMON 0x40095000 0 0x400 registers Always On (AON) Battery And Temperature MONitor (BATMON) residing in the AON domain Note: This module only supports 32 bit Read/Write access from MCU. CTL 0x0 32 Internal. Only to be used through TI provided API. RESERVED2 [31:2] Internal. Only to be used through TI provided API. 30 2 CALC_EN [1:1] Internal. Only to be used through TI provided API. 1 1 MEAS_EN [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 MEASCFG 0x4 32 Internal. Only to be used through TI provided API. RESERVED2 [31:2] Internal. Only to be used through TI provided API. 30 2 PER [1:0] Internal. Only to be used through TI provided API. 2 0 32CYC 3 Internal. Only to be used through TI provided API. 16CYC 2 Internal. Only to be used through TI provided API. 8CYC 1 Internal. Only to be used through TI provided API. CONT 0 Internal. Only to be used through TI provided API. 0x0 TEMPP0 0xc 32 Internal. Only to be used through TI provided API. RESERVED8 [31:8] Internal. Only to be used through TI provided API. 24 8 CFG [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 TEMPP1 0x10 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Internal. Only to be used through TI provided API. 26 6 CFG [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 TEMPP2 0x14 32 Internal. Only to be used through TI provided API. RESERVED5 [31:5] Internal. Only to be used through TI provided API. 27 5 CFG [4:0] Internal. Only to be used through TI provided API. 5 0 0x0 BATMONP0 0x18 32 Internal. Only to be used through TI provided API. RESERVED6 [31:7] Internal. Only to be used through TI provided API. 25 7 CFG [6:0] Internal. Only to be used through TI provided API. 7 0 0x0 BATMONP1 0x1c 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Internal. Only to be used through TI provided API. 26 6 CFG [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 IOSTRP0 0x20 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Internal. Only to be used through TI provided API. 26 6 CFG2 [5:4] Internal. Only to be used through TI provided API. 2 4 CFG1 [3:0] Internal. Only to be used through TI provided API. 4 0 0x28 FLASHPUMPP0 0x24 32 Internal. Only to be used through TI provided API. RESERVED9 [31:10] Internal. Only to be used through TI provided API. 22 10 DIS_NOISE_FILTER [9:9] Internal. Only to be used through TI provided API. 1 9 FALLB [8:8] Internal. Only to be used through TI provided API. 1 8 HIGHLIM [7:6] Internal. Only to be used through TI provided API. 2 6 LOWLIM [5:5] Internal. Only to be used through TI provided API. 1 5 OVR [4:4] Internal. Only to be used through TI provided API. 1 4 CFG [3:0] Internal. Only to be used through TI provided API. 4 0 0x0 BAT 0x28 32 Last Measured Battery Voltage This register may be read while BATUPD.STAT = 1 RESERVED11 [31:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 21 11 INT [10:8] Integer part: 0x0: 0V + fractional part ... 0x3: 3V + fractional part 0x4: 4V + fractional part 3 8 FRAC [7:0] Fractional part, standard binary fractional encoding. 0x00: .0V ... 0x20: 1/8 = .125V 0x40: 1/4 = .25V 0x80: 1/2 = .5V ... 0xA0: 1/2 + 1/8 = .625V ... 0xFF: Max 8 0 0x0 BATUPD 0x2c 32 Battery Update Indicates BAT Updates RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] 0: No update since last clear 1: New battery voltage is present. Write 1 to clear the status. 1 0 0x0 TEMP 0x30 32 Temperature Last Measured Temperature in Degrees Celsius This register may be read while TEMPUPD.STAT = 1. RESERVED17 [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 INT [16:8] Integer part (signed) of temperature value. Total value = INTEGER + FRACTIONAL 2's complement encoding 0x100: Min value 0x1D8: -40C 0x1FF: -1C 0x00: 0C 0x1B: 27C 0x55: 85C 0xFF: Max value 9 8 RESERVED0 [7:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 0 0x0 TEMPUPD 0x34 32 Temperature Update Indicates TEMP Updates RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] 0: No update since last clear 1: New temperature is present. Write 1 to clear the status. 1 0 0x0 EVENTMASK 0x48 32 Event Mask RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 TEMP_UPDATE_MASK [5:5] 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON 1 5 BATT_UPDATE_MASK [4:4] 1: EVENT.BATT_UPDATE contributes to combined event from BATMON 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON 1 4 TEMP_BELOW_LL_MASK [3:3] 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON 1 3 TEMP_OVER_UL_MASK [2:2] 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON 1 2 BATT_BELOW_LL_MASK [1:1] 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON 1 1 BATT_OVER_UL_MASK [0:0] 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON 1 0 0x0 EVENT 0x4c 32 Event RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 TEMP_UPDATE [5:5] Alias to TEMPUPD.STAT 1 5 BATT_UPDATE [4:4] Alias to BATUPD.STAT 1 4 TEMP_BELOW_LL [3:3] Read: 1: Temperature level is below the lower limit set by TEMPLL. 0: Temperature level is not below the lower limit set by TEMPLL. Write: 1: Clears the flag 0: No change in the flag 1 3 TEMP_OVER_UL [2:2] Read: 1: Temperature level is above the upper limit set by TEMPUL. 0: Temperature level is not above the upper limit set by TEMPUL. Write: 1: Clears the flag 0: No change in the flag 1 2 BATT_BELOW_LL [1:1] Read: 1: Battery level is below the lower limit set by BATTLL. 0: Battery level is not below the lower limit set by BATTLL. Write: 1: Clears the flag 0: No change in the flag 1 1 BATT_OVER_UL [0:0] Read: 1: Battery level is above the upper limit set by BATTUL. 0: Battery level is not above the upper limit set by BATTUL. Write: 1: Clears the flag 0: No change in the flag 1 0 0x0 BATTUL 0x50 32 Battery Upper Limit RESERVED11 [31:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 21 11 INT [10:8] Integer part: 0x0: 0V + fractional part ... 0x3: 3V + fractional part 0x4: 4V + fractional part 3 8 FRAC [7:0] Fractional part, standard binary fractional encoding. 0x00: .0V ... 0x20: 1/8 = .125V 0x40: 1/4 = .25V 0x80: 1/2 = .5V ... 0xA0: 1/2 + 1/8 = .625V ... 0xFF: Max 8 0 0x7FF BATTLL 0x54 32 Battery Lower Limit RESERVED11 [31:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 21 11 INT [10:8] Integer part: 0x0: 0V + fractional part ... 0x3: 3V + fractional part 0x4: 4V + fractional part 3 8 FRAC [7:0] Fractional part, standard binary fractional encoding. 0x00: .0V ... 0x20: 1/8 = .125V 0x40: 1/4 = .25V 0x80: 1/2 = .5V ... 0xA0: 1/2 + 1/8 = .625V ... 0xFF: Max 8 0 0x0 TEMPUL 0x58 32 Temperature Upper Limit RESERVED17 [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 INT [16:8] Integer part (signed) of temperature upper limit. Total value = INTEGER + FRACTIONAL 2's complement encoding 0x100: Min value 0x1D8: -40C 0x1FF: -1C 0x00: 0C 0x1B: 27C 0x55: 85C 0xFF: Max value 9 8 FRAC [7:6] Fractional part of temperature upper limit. Total value = INTEGER + FRACTIONAL The encoding is an extension of the 2's complement encoding. 00: 0.0C 01: 0.25C 10: 0.5C 11: 0.75C For example: 000000001,00 = ( 1+0,00) = 1,00 000000000,11 = ( 0+0,75) = 0,75 000000000,10 = ( 0+0,50) = 0,50 000000000,01 = ( 0+0,25) = 0,25 000000000,00 = ( 0+0,00) = 0,00 111111111,11 = (-1+0,75) = -0,25 111111111,10 = (-1+0,50) = -0,50 111111111,01 = (-1+0,25) = -0,75 111111111,00 = (-1+0,00) = -1,00 111111110,11 = (-2+0,75) = -1,25 2 6 RESERVED0 [5:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 0 0xFFC0 TEMPLL 0x5c 32 Temperature Lower Limit RESERVED17 [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 INT [16:8] Integer part (signed) of temperature lower limit. Total value = INTEGER + FRACTIONAL 2's complement encoding 0x100: Min value 0x1D8: -40C 0x1FF: -1C 0x00: 0C 0x1B: 27C 0x55: 85C 0xFF: Max value 9 8 FRAC [7:6] Fractional part of temperature lower limit. Total value = INTEGER + FRACTIONAL The encoding is an extension of the 2's complement encoding. 00: 0.0C 01: 0.25C 10: 0.5C 11: 0.75C For example: 000000001,00 = ( 1+0,00) = 1,00 000000000,11 = ( 0+0,75) = 0,75 000000000,10 = ( 0+0,50) = 0,50 000000000,01 = ( 0+0,25) = 0,25 000000000,00 = ( 0+0,00) = 0,00 111111111,11 = (-1+0,75) = -0,25 111111111,10 = (-1+0,50) = -0,50 111111111,01 = (-1+0,25) = -0,75 111111111,00 = (-1+0,00) = -1,00 111111110,11 = (-2+0,75) = -1,25 2 6 RESERVED0 [5:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 0 0x10000 AON_EVENT 0x40093000 0 0x400 registers This module configures the event fabric located in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU MCUWUSEL 0x0 32 Wake-up Selector For MCU This register contains pointers to 4 of 8 events (events 0 to 3) which are routed to AON_PMCTRL as wakeup sources for MCU. AON_PMCTRL will start a wakeup sequence for the MCU domain when either of the 8 selected events are asserted. A wakeup sequence will guarantee that the MCU power switches are turned on, LDO resources are available and SCLK_HF is available and selected as clock source for MCU. Note: It is required to setup a wakeup event in AON_EVENT before MCU is requesting powerdown ( PRCM requests uLDO, see conditions in PRCM:VDCTL.ULDO ). RESERVED30 [31:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 30 WU3_EV [29:24] MCU Wakeup Source #3 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 24 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] RESERVED22 [23:22] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 22 WU2_EV [21:16] MCU Wakeup Source #2 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 16 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] RESERVED14 [15:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 14 WU1_EV [13:8] MCU Wakeup Source #1 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 8 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 WU0_EV [5:0] MCU Wakeup Source #0 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 0 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] 0x3F3F3F3F MCUWUSEL1 0x4 32 Wake-up Selector For MCU This register contains pointers to 4 of 8 events (events 4 to 7) which are routed to AON_PMCTRL as wakeup sources for MCU. AON_PMCTRL will start a wakeup sequence for the MCU domain when either of the 8 selected events are asserted. A wakeup sequence will guarantee that the MCU power switches are turned on, LDO resources are available and SCLK_HF is available and selected as clock source for MCU. Note: It is required to setup a wakeup event in AON_EVENT before MCU is requesting powerdown ( PRCM requests uLDO, see conditions in PRCM:VDCTL.ULDO ). RESERVED30 [31:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 30 WU7_EV [29:24] MCU Wakeup Source #7 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 24 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] RESERVED22 [23:22] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 22 WU6_EV [21:16] MCU Wakeup Source #6 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 16 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] RESERVED14 [15:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 14 WU5_EV [13:8] MCU Wakeup Source #5 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 8 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 WU4_EV [5:0] MCU Wakeup Source #4 AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down. Note: 6 0 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_MCU_WU 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_MCU_WU in [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] 0x3F3F3F3F EVTOMCUSEL 0x8 32 Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT RESERVED22 [31:22] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 10 22 AON_PROG2_EV [21:16] Event selector for AON_PROG2 event. AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. 6 16 NONE 63 No event, always low AUX_COMPB_ASYNC_N 56 Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX AUX_COMPB_ASYNC 55 Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX BATMON_VOLT 54 BATMON voltage update event BATMON_TEMP 53 BATMON temperature update event AUX_TIMER1_EV 52 AUX Timer 1 Event AUX_TIMER0_EV 51 AUX Timer 0 Event AUX_TDC_DONE 50 TDC completed or timed out AUX_ADC_DONE 49 ADC conversion completed AUX_COMPB 48 Comparator B triggered AUX_COMPA 47 Comparator A triggered AUX_SWEV2 46 AUX Software triggered event #2. Triggered by AUX_EVCTL:SWEVSET.SWEV2 AUX_SWEV1 45 AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 AUX_SWEV0 44 AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 JTAG 43 JTAG generated event RTC_UPD 42 RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) RTC_COMB_DLY 41 RTC combined delayed event RTC_CH2_DLY 40 RTC channel 2 - delayed event RTC_CH1_DLY 39 RTC channel 1 - delayed event RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_AON_PROG2 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_AON_PROG2 in [MCU_IOC:IOCFGx.IOEV_AON_PROG2_EN] RESERVED14 [15:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 14 AON_PROG1_EV [13:8] Event selector for AON_PROG1 event. AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. 6 8 NONE 63 0 AUX_COMPB_ASYNC_N 56 0 AUX_COMPB_ASYNC 55 0 BATMON_VOLT 54 0 BATMON_TEMP 53 0 AUX_TIMER1_EV 52 0 AUX_TIMER0_EV 51 0 AUX_TDC_DONE 50 0 AUX_ADC_DONE 49 0 AUX_COMPB 48 0 AUX_COMPA 47 0 AUX_SWEV2 46 0 AUX_SWEV1 45 0 AUX_SWEV0 44 0 JTAG 43 0 RTC_UPD 42 0 RTC_COMB_DLY 41 0 RTC_CH2_DLY 40 0 RTC_CH1_DLY 39 0 RTC_CH0_DLY 38 RTC channel 0 - delayed event RTC_CH2 37 RTC channel 2 event RTC_CH1 36 RTC channel 1 event RTC_CH0 35 RTC channel 0 event PAD 32 Edge detect on any PAD BATMON_COMBINED 9 Combined event from BATMON BATMON_TEMP_LL 8 BATMON event: Temperature level below lower limit BATMON_TEMP_UL 7 BATMON event: Temperature level above upper limit BATMON_BATT_LL 6 BATMON event: Battery level below lower limit BATMON_BATT_UL 5 BATMON event: Battery level above upper limit AUX_TIMER2_EV3 4 Event 3 from AUX TImer2 AUX_TIMER2_EV2 3 Event 2 from AUX TImer2 AUX_TIMER2_EV1 2 Event 1 from AUX TImer2 AUX_TIMER2_EV0 1 Event 0 from AUX TImer2 IOEV_AON_PROG1 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_AON_PROG1 in [MCU_IOC:IOCFGx.IOEV_AON_PROG1_EN] RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 AON_PROG0_EV [5:0] Event selector for AON_PROG0 event. AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. 6 0 NONE 63 0 AUX_COMPB_ASYNC_N 56 0 AUX_COMPB_ASYNC 55 0 BATMON_VOLT 54 0 BATMON_TEMP 53 0 AUX_TIMER1_EV 52 0 AUX_TIMER0_EV 51 0 AUX_TDC_DONE 50 0 AUX_ADC_DONE 49 0 AUX_COMPB 48 0 AUX_COMPA 47 0 AUX_SWEV2 46 0 AUX_SWEV1 45 0 AUX_SWEV0 44 0 JTAG 43 0 RTC_UPD 42 0 RTC_COMB_DLY 41 0 RTC_CH2_DLY 40 0 RTC_CH1_DLY 39 0 RTC_CH0_DLY 38 0 RTC_CH2 37 0 RTC_CH1 36 0 RTC_CH0 35 0 PAD 32 0 BATMON_COMBINED 9 0 BATMON_TEMP_LL 8 0 BATMON_TEMP_UL 7 0 BATMON_BATT_LL 6 0 BATMON_BATT_UL 5 0 AUX_TIMER2_EV3 4 0 AUX_TIMER2_EV2 3 0 AUX_TIMER2_EV1 2 0 AUX_TIMER2_EV0 1 0 IOEV_AON_PROG0 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_AON_PROG0 in [MCU_IOC:IOCFGx.IOEV_AON_PROG0_EN] 0x2B2B2B RTCSEL 0xc 32 RTC Capture Event Selector For AON_RTC This register contains a pointer to select an AON event for RTC capture. Please refer to AON_RTC:CH1CAPT RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 RTC_CH1_CAPT_EV [5:0] AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer to AON_RTC:CH1CAPT 6 0 NONE 63 0 AUX_COMPB_ASYNC_N 56 0 AUX_COMPB_ASYNC 55 0 BATMON_VOLT 54 0 BATMON_TEMP 53 0 AUX_TIMER1_EV 52 0 AUX_TIMER0_EV 51 0 AUX_TDC_DONE 50 0 AUX_ADC_DONE 49 0 AUX_COMPB 48 0 AUX_COMPA 47 0 AUX_SWEV2 46 0 AUX_SWEV1 45 0 AUX_SWEV0 44 0 JTAG 43 0 RTC_UPD 42 0 RTC_COMB_DLY 41 0 RTC_CH2_DLY 40 0 RTC_CH1_DLY 39 0 RTC_CH0_DLY 38 0 RTC_CH2 37 0 RTC_CH1 36 0 RTC_CH0 35 0 PAD 32 0 BATMON_COMBINED 9 0 BATMON_TEMP_LL 8 0 BATMON_TEMP_UL 7 0 BATMON_BATT_LL 6 0 BATMON_BATT_UL 5 0 AUX_TIMER2_EV3 4 0 AUX_TIMER2_EV2 3 0 AUX_TIMER2_EV1 2 0 AUX_TIMER2_EV0 1 0 IOEV_RTC 0 Edge detect IO event from the DIO(s) which have enabled contribution to IOEV_RTC in [MCU_IOC:IOCFGx.IOEV_RTC_EN] 0x3F AON_IOC 0x40094000 0 0x400 registers Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain. Note: This module only supports 32 bit Read/Write access from MCU. IOSTRMIN 0x0 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 GRAY_CODE [2:0] Internal. Only to be used through TI provided API. 3 0 0x3 IOSTRMED 0x4 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 GRAY_CODE [2:0] Internal. Only to be used through TI provided API. 3 0 0x6 IOSTRMAX 0x8 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 GRAY_CODE [2:0] Internal. Only to be used through TI provided API. 3 0 0x5 CLK32KCTL 0x10 32 SCLK_LF External Output Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 OE_N [0:0] 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for example IOC:IOCFG0.PORT_ID) set to AON_CLK32K. 1: Output enable not active 1 0 0x1 TCKCTL 0x14 32 TCK IO Pin Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] 0: Input driver for TCK disabled. 1: Input driver for TCK enabled. 1 0 0x1 AON_PMCTL 0x40090000 0 0x1000 registers This component control the Power Management controller residing in the AON domain. Note: This module is only supporting 32 bit Read Write access from MCU AUXSCECLK 0x4 32 AUX SCE Clock Management This register contains bitfields that are relevant for setting up the clock to the AUX domain. RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 PD_SRC [8:8] Selects the clock source for the AUX domain when AUX is in powerdown mode. Note: Switching the clock source is guaranteed to be glitch-free 1 8 SCLK_LF 1 LF clock (SCLK_LF ) NO_CLOCK 0 No clock RESERVED3 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 SRC [0:0] Selects the clock source for the AUX domain when AUX is in active mode. Note: Switching the clock source is guaranteed to be glitch-free 1 0 SCLK_MF 1 MF Clock (SCLK_MF) SCLK_HFDIV2 0 HF Clock divided by 2 (SCLK_HFDIV2) 0x0 RAMCFG 0x8 32 RAM Configuration This register contains power management related configuration for the SRAM in the MCU and AUX domain. RESERVED18 [31:18] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14 18 AUX_SRAM_PWR_OFF [17:17] Internal. Only to be used through TI provided API. 1 17 AUX_SRAM_RET_EN [16:16] Internal. Only to be used through TI provided API. 1 16 RESERVED4 [15:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 4 BUS_SRAM_RET_EN [3:0] MCU SRAM is partitioned into 5 banks . This register controls which of the banks that has retention during MCU Bus domain power off 4 0 RET_FULL 15 Retention on for all banks SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 RET_LEVEL3 7 Retention on for SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3 RET_LEVEL2 3 Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2 RET_LEVEL1 1 Retention on for SRAM:BANK0 and SRAM:BANK1 RET_NONE 0 Retention is disabled 0x1000F PWRCTL 0x10 32 Power Management Control This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 DCDC_ACTIVE [2:2] Select to use DCDC regulator for VDDR in active mode 0: Use GLDO for regulation of VDDR in active mode. 1: Use DCDC for regulation of VDDR in active mode. DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active mode 1 2 EXT_REG_MODE [1:1] Status of source for VDDRsupply: 0: DCDC or GLDO are generating VDDR 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR 1 1 DCDC_EN [0:0] Select to use DCDC regulator during recharge of VDDR 0: Use GLDO for recharge of VDDR 1: Use DCDC for recharge of VDDR Note: This bitfield should be set to the same as DCDC_ACTIVE 1 0 0x0 PWRSTAT 0x14 32 AON Power and Reset Status This register is used to monitor various power management related signals in AON. All other signals than JTAG_PD_ON, AUX_BUS_RESET_DONE, and AUX_RESET_DONE are for test, calibration and debug purpose only. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 JTAG_PD_ON [2:2] Indicates JTAG power state: 0: JTAG is powered off 1: JTAG is powered on 1 2 AUX_BUS_RESET_DONE [1:1] Indicates Reset Done from AUX Bus: 0: AUX Bus is being reset 1: AUX Bus reset is released 1 1 AUX_RESET_DONE [0:0] Indicates Reset Done from AUX: 0: AUX is being reset 1: AUX reset is released 1 0 0x3C00003 SHUTDOWN 0x18 32 Shutdown Control This register contains bitfields required for entering shutdown mode RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] Shutdown control. 0: Do not write 0 to this bit. 1: Immediately start the process to enter shutdown mode 1 0 0x0 RECHARGECFG 0x1c 32 Recharge Controller Configuration This register sets all relevant parameters for controlling the recharge algorithm. MODE [31:30] Selects recharge algorithm for VDDR when the system is running on the uLDO 2 30 COMPARATOR 3 External recharge comparator. Note that the clock to the recharge comparator must be enabled, [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], before selecting this recharge algorithm. ADAPTIVE 2 Adaptive timer STATIC 1 Static timer OFF 0 Recharge disabled RESERVED24 [29:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 24 C2 [23:20] Internal. Only to be used through TI provided API. 4 20 C1 [19:16] Internal. Only to be used through TI provided API. 4 16 MAX_PER_M [15:11] Internal. Only to be used through TI provided API. 5 11 MAX_PER_E [10:8] Internal. Only to be used through TI provided API. 3 8 PER_M [7:3] Internal. Only to be used through TI provided API. 5 3 PER_E [2:0] Internal. Only to be used through TI provided API. 3 0 0xC0000000 RECHARGESTAT 0x20 32 Recharge Controller Status This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug. RESERVED20 [31:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 20 VDDR_SMPLS [19:16] The last 4 VDDR samples. For each bit: 0: VDDR was below VDDR_OK threshold when recharge started 1: VDDR was above VDDR_OK threshold when recharge started The register is updated prior to every recharge period with a shift left, and bit 0 is updated with the last VDDR sample. 4 16 MAX_USED_PER [15:0] Shows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started. This register can be used as an indication of the leakage current during standby. This bitfield is cleared to 0 when writing this register. 16 0 0x0 OSCCFG 0x24 32 Oscillator Configuration This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PER_M [7:3] Internal. Only to be used through TI provided API. 5 3 PER_E [2:0] Internal. Only to be used through TI provided API. 3 0 0x0 RESETCTL 0x28 32 Reset Management This register contains bitfields related to system reset such as reset source and reset request and control of brown out resets. SYSRESET [31:31] Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again. 0: No effect 1: Generate system reset. Appears as SYSRESET in RESET_SRC 1 31 RESERVED26 [30:26] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 26 BOOT_DET_1_CLR [25:25] Internal. Only to be used through TI provided API. 1 25 BOOT_DET_0_CLR [24:24] Internal. Only to be used through TI provided API. 1 24 RESERVED18 [23:18] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 18 BOOT_DET_1_SET [17:17] Internal. Only to be used through TI provided API. 1 17 BOOT_DET_0_SET [16:16] Internal. Only to be used through TI provided API. 1 16 WU_FROM_SD [15:15] A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low) Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources. 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 1: A wakeup has occurred from SHUTDOWN Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. 1 15 GPIO_WU_FROM_SD [14:14] A wakeup from SHUTDOWN on an IO event has occurred Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources. 0: The wakeup did not occur from SHUTDOWN on an IO event 1: A wakeup from SHUTDOWN occurred from an IO event The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well. Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. 1 14 BOOT_DET_1 [13:13] Internal. Only to be used through TI provided API. 1 13 BOOT_DET_0 [12:12] Internal. Only to be used through TI provided API. 1 12 RESERVED9 [11:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 9 VDDS_LOSS_EN [8:8] Controls reset generation in case VDDS is lost 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out detect of VDDS generates system reset 1 8 VDDR_LOSS_EN [7:7] Controls reset generation in case VDDR is lost 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out detect of VDDR generates system reset 1 7 VDD_LOSS_EN [6:6] Controls reset generation in case VDD is lost 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect of VDD generates system reset 1 6 CLK_LOSS_EN [5:5] Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 0: Clock loss is ignored 1: Clock loss generates system reset Note: Clock loss reset generation must be disabled when changing clock source for SCLK_LF. Failure to do so may result in a spurious system reset. Clock loss reset generation is controlled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 1 5 MCU_WARM_RESET [4:4] Internal. Only to be used through TI provided API. 1 4 RESET_SRC [3:1] Shows the root cause of the last system reset. More than the reported reset source can have been active during the last system reset but only the root cause is reported. The capture feature is not rearmed until all off the possible reset sources have been released and the result has been copied to AON_PMCTL. During the copy and rearm process it is one 2MHz period in which and eventual new system reset will be reported as Power on reset regardless of the root cause. 3 1 WARMRESET 7 Software reset via PRCM warm reset request SYSRESET 6 Software reset via SYSRESET or hardware power management timeout detection. Note: The hardware power management timeout circuit is always enabled. CLK_LOSS 5 SCLK_LF, SCLK_MF or SCLK_HF clock loss detect VDDR_LOSS 4 Brown out detect on VDDR VDDS_LOSS 2 Brown out detect on VDDS PIN_RESET 1 Reset pin PWR_ON 0 Power on reset RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x1C0 SLEEPCTL 0x2c 32 Sleep Control This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 IO_PAD_SLEEP_DIS [0:0] Controls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set). 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations are latched. Inputs are transparent if pad is configured as input before IO_PAD_SLEEP_DIS is set to 1 1: I/O pad sleep mode is disabled Application software must reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. 1 0 0x0 JTAGCFG 0x34 32 JTAG Configuration This register contains control for configuration of the JTAG domain. This includes permissions for each TAP. RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 JTAG_PD_FORCE_ON [8:8] Controls JTAG Power domain power state: 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be powered off unless a debugger is attached) 1: JTAG Power Domain is forced on, independent of debug subsystem. Note: The reset value causes JTAG Power domain to be powered on by default. Software must clear this bit to turn off the JTAG Power domain 1 8 RESERVED0 [7:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 0 0x100 JTAGUSERCODE 0x3c 32 JTAG USERCODE Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem. USER_CODE [31:0] 32-bit JTAG USERCODE register feeding main JTAG TAP Note: This field can be locked by LOCKCFG.LOCK 32 0 0xB99A02F AON_RTC 0x40092000 0 0x400 registers This component control the Real Time Clock residing in AON Note: This module is only supporting 32 bit ReadWrite access. CTL 0x0 32 Control This register contains various bitfields for configuration of RTC RTL Name = CONFIG RESERVED19 [31:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 13 19 COMB_EV_MASK [18:16] Eventmask selecting which delayed events that form the combined event. 3 16 CH2 4 Use Channel 2 delayed event in combined event CH1 2 Use Channel 1 delayed event in combined event CH0 1 Use Channel 0 delayed event in combined event NONE 0 No event is selected for combined event. RESERVED12 [15:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 12 EV_DELAY [11:8] Number of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed 4 8 D144 13 Delay by 144 clock cycles D128 12 Delay by 128 clock cycles D112 11 Delay by 112 clock cycles D96 10 Delay by 96 clock cycles D80 9 Delay by 80 clock cycles D64 8 Delay by 64 clock cycles D48 7 Delay by 48 clock cycles D32 6 Delay by 32 clock cycles D16 5 Delay by 16 clock cycles D8 4 Delay by 8 clock cycles D4 3 Delay by 4 clock cycles D2 2 Delay by 2 clock cycles D1 1 Delay by 1 clock cycles D0 0 No delay on delayed event RESET [7:7] RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when reset takes effect 1 7 RESERVED3 [6:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 3 RTC_4KHZ_EN [2:2] RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) 1 2 RTC_UPD_EN [1:1] RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2 0: RTC_UPD signal is forced to 0 1: RTC_UPD signal is toggling @16 kHz 1 1 EN [0:0] Enable RTC counter 0: Halted (frozen) 1: Running 1 0 0x0 EVFLAGS 0x4 32 Event Flags, RTC Status This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to the corresponding bitfield. RESERVED17 [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 CH2 [16:16] Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value. An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any time between next RTC value and 1 second in the past Writing 1 clears this flag. AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 CH1 [8:8] Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value. - CHCTL.CH1_CAPT_EN = 1 and capture occurs. An event will be scheduled to occur as soon as possible when writing to CH1CMP provided that the channel is enabled, in compare mode and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 CH0 [0:0] Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value. An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. 1 0 0x0 SEC 0x8 32 Second Counter Value, Integer Part VALUE [31:0] Unsigned integer representing Real Time Clock in seconds. When reading this register the content of SUBSEC.VALUE is simultaneously latched. A consistent reading of the combined Real Time Clock can be obtained by first reading this register, then reading SUBSEC register. 32 0 0x0 SUBSEC 0xc 32 Second Counter Value, Fractional Part VALUE [31:0] Unsigned integer representing Real Time Clock in fractions of a second (VALUE/2^32 seconds) at the time when SEC register was read. Examples : - 0x0000_0000 = 0.0 sec - 0x4000_0000 = 0.25 sec - 0x8000_0000 = 0.5 sec - 0xC000_0000 = 0.75 sec 32 0 0x0 SUBSECINC 0x10 32 Subseconds Increment Value added to SUBSEC.VALUE on every SCLK_LFclock cycle. RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 VALUEINC [23:0] This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. The compensation value can be found as 2^38 / freq, where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow. The default value corresponds to incrementing by precisely 1/32768 of a second. NOTE: This register is read only. Modification of the register value must be done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and AUX_SYSIF:RTCSUBSECINCCTL 24 0 0x800000 CHCTL 0x14 32 Channel Configuration RESERVED19 [31:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 13 19 CH2_CONT_EN [18:18] Set to enable continuous operation of Channel 2 1 18 RESERVED17 [17:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 17 CH2_EN [16:16] RTC Channel 2 Enable 0: Disable RTC Channel 2 1: Enable RTC Channel 2 1 16 RESERVED10 [15:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 10 CH1_CAPT_EN [9:9] Set Channel 1 mode 0: Compare mode (default) 1: Capture mode 1 9 CH1_EN [8:8] RTC Channel 1 Enable 0: Disable RTC Channel 1 1: Enable RTC Channel 1 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 CH0_EN [0:0] RTC Channel 0 Enable 0: Disable RTC Channel 0 1: Enable RTC Channel 0 1 0 0x0 CH0CMP 0x18 32 Channel 0 Compare Value VALUE [31:0] RTC Channel 0 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization. 32 0 0x0 CH1CMP 0x1c 32 Channel 1 Compare Value VALUE [31:0] RTC Channel 1 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization. 32 0 0x0 CH2CMP 0x20 32 Channel 2 Compare Value VALUE [31:0] RTC Channel 2 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization. 32 0 0x0 CH2CMPINC 0x24 32 Channel 2 Compare Value Auto-increment This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the [AUX_EVCTL.EVSTAT0.AON_RTC] event. VALUE [31:0] If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every channel 2 compare event. 32 0 0x0 CH1CAPT 0x28 32 Channel 1 Capture Value If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL. SEC [31:16] Value of SEC.VALUE bits 15:0 at capture time. 16 16 SUBSEC [15:0] Value of SUBSEC.VALUE bits 31:16 at capture time. 16 0 0x0 SYNC 0x2c 32 AON Synchronization This register is used for synchronizing between MCU and entire AON domain. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 WBUSY [0:0] This register will always return 0,- however it will not return the value until there are no outstanding write requests between MCU and AON Note: Writing to this register prior to reading will force a wait until next SCLK_MF edge. This is recommended for syncing read registers from AON when waking up from sleep Failure to do so may result in reading AON values from prior to going to sleep 1 0 0x0 TIME 0x30 32 Current Counter Value SEC_L [31:16] Returns the lower halfword of SEC register. 16 16 SUBSEC_H [15:0] Returns the upper halfword of SUBSEC register. 16 0 0x0 SYNCLF 0x34 32 Synchronization to SCLK_LF This register is used for synchronizing MCU to positive or negative edge of SCLK_LF. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 PHASE [0:0] This bit will always return the SCLK_LF phase. The return will delayed until a positive or negative edge of SCLK_LF is seen. 0: Falling edge of SCLK_LF 1: Rising edge of SCLK_LF 1 0 0x0 AUX_AIODIO0 0x400CC000 0 0x1000 registers AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio. IOMODE 0x0 32 Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 IO7 [15:14] Selects mode for AUXIO[8i+7]. 2 14 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer. When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7]. When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7]. IO6 [13:12] Selects mode for AUXIO[8i+6]. 2 12 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer. When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6]. When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6]. IO5 [11:10] Selects mode for AUXIO[8i+5]. 2 10 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer. When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5]. When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5]. IO4 [9:8] Selects mode for AUXIO[8i+4]. 2 8 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer. When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4]. When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4]. IO3 [7:6] Selects mode for AUXIO[8i+3]. 2 6 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer. When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3]. When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3]. IO2 [5:4] Select mode for AUXIO[8i+2]. 2 4 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer. When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2]. When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2]. IO1 [3:2] Select mode for AUXIO[8i+1]. 2 2 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer. When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1]. When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1]. IO0 [1:0] Select mode for AUXIO[8i+0]. 2 0 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer. When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0]. When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0]. 0x0 GPIODIE 0x4 32 General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. 8 0 0x0 IOPOE 0x8 32 Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*]. Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT. 8 0 0x0 GPIODOUT 0xc 32 General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]. 8 0 0x0 GPIODIN 0x10 32 General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. 8 0 0x0 GPIODOUTSET 0x14 32 General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTCLR 0x18 32 General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTTGL 0x1c 32 General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. 8 0 0x0 IO0PSEL 0x20 32 Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO1PSEL 0x24 32 Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO2PSEL 0x28 32 Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO3PSEL 0x2c 32 Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO4PSEL 0x30 32 Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO5PSEL 0x34 32 Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO6PSEL 0x38 32 Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO7PSEL 0x3c 32 Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IOMODEL 0x40 32 Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO3 [7:6] See IOMODE.IO3. 2 6 IO2 [5:4] See IOMODE.IO2. 2 4 IO1 [3:2] See IOMODE.IO1. 2 2 IO0 [1:0] See IOMODE.IO0. 2 0 0x0 IOMODEH 0x44 32 Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7 [7:6] See IOMODE.IO7. 2 6 IO6 [5:4] See IOMODE.IO6. 2 4 IO5 [3:2] See IOMODE.IO5. 2 2 IO4 [1:0] See IOMODE.IO4. 2 0 0x0 AUX_AIODIO1 0x400CD000 0 0x1000 registers AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio. IOMODE 0x0 32 Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 IO7 [15:14] Selects mode for AUXIO[8i+7]. 2 14 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer. When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7]. When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7]. IO6 [13:12] Selects mode for AUXIO[8i+6]. 2 12 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer. When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6]. When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6]. IO5 [11:10] Selects mode for AUXIO[8i+5]. 2 10 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer. When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5]. When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5]. IO4 [9:8] Selects mode for AUXIO[8i+4]. 2 8 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer. When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4]. When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4]. IO3 [7:6] Selects mode for AUXIO[8i+3]. 2 6 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer. When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3]. When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3]. IO2 [5:4] Select mode for AUXIO[8i+2]. 2 4 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer. When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2]. When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2]. IO1 [3:2] Select mode for AUXIO[8i+1]. 2 2 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer. When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1]. When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1]. IO0 [1:0] Select mode for AUXIO[8i+0]. 2 0 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer. When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0]. When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0]. 0x0 GPIODIE 0x4 32 General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. 8 0 0x0 IOPOE 0x8 32 Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*]. Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT. 8 0 0x0 GPIODOUT 0xc 32 General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]. 8 0 0x0 GPIODIN 0x10 32 General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. 8 0 0x0 GPIODOUTSET 0x14 32 General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTCLR 0x18 32 General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTTGL 0x1c 32 General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. 8 0 0x0 IO0PSEL 0x20 32 Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO1PSEL 0x24 32 Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO2PSEL 0x28 32 Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO3PSEL 0x2c 32 Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO4PSEL 0x30 32 Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO5PSEL 0x34 32 Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO6PSEL 0x38 32 Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO7PSEL 0x3c 32 Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IOMODEL 0x40 32 Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO3 [7:6] See IOMODE.IO3. 2 6 IO2 [5:4] See IOMODE.IO2. 2 4 IO1 [3:2] See IOMODE.IO1. 2 2 IO0 [1:0] See IOMODE.IO0. 2 0 0x0 IOMODEH 0x44 32 Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7 [7:6] See IOMODE.IO7. 2 6 IO6 [5:4] See IOMODE.IO6. 2 4 IO5 [3:2] See IOMODE.IO5. 2 2 IO4 [1:0] See IOMODE.IO4. 2 0 0x0 AUX_AIODIO2 0x400CE000 0 0x1000 registers AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio. IOMODE 0x0 32 Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 IO7 [15:14] Selects mode for AUXIO[8i+7]. 2 14 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer. When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7]. When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7]. IO6 [13:12] Selects mode for AUXIO[8i+6]. 2 12 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer. When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6]. When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6]. IO5 [11:10] Selects mode for AUXIO[8i+5]. 2 10 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer. When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5]. When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5]. IO4 [9:8] Selects mode for AUXIO[8i+4]. 2 8 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer. When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4]. When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4]. IO3 [7:6] Selects mode for AUXIO[8i+3]. 2 6 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer. When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3]. When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3]. IO2 [5:4] Select mode for AUXIO[8i+2]. 2 4 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer. When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2]. When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2]. IO1 [3:2] Select mode for AUXIO[8i+1]. 2 2 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer. When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1]. When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1]. IO0 [1:0] Select mode for AUXIO[8i+0]. 2 0 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer. When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0]. When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0]. 0x0 GPIODIE 0x4 32 General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. 8 0 0x0 IOPOE 0x8 32 Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*]. Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT. 8 0 0x0 GPIODOUT 0xc 32 General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]. 8 0 0x0 GPIODIN 0x10 32 General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. 8 0 0x0 GPIODOUTSET 0x14 32 General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTCLR 0x18 32 General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTTGL 0x1c 32 General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. 8 0 0x0 IO0PSEL 0x20 32 Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO1PSEL 0x24 32 Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO2PSEL 0x28 32 Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO3PSEL 0x2c 32 Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO4PSEL 0x30 32 Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO5PSEL 0x34 32 Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO6PSEL 0x38 32 Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO7PSEL 0x3c 32 Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IOMODEL 0x40 32 Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO3 [7:6] See IOMODE.IO3. 2 6 IO2 [5:4] See IOMODE.IO2. 2 4 IO1 [3:2] See IOMODE.IO1. 2 2 IO0 [1:0] See IOMODE.IO0. 2 0 0x0 IOMODEH 0x44 32 Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7 [7:6] See IOMODE.IO7. 2 6 IO6 [5:4] See IOMODE.IO6. 2 4 IO5 [3:2] See IOMODE.IO5. 2 2 IO4 [1:0] See IOMODE.IO4. 2 0 0x0 AUX_AIODIO3 0x400CF000 0 0x1000 registers AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio. IOMODE 0x0 32 Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 IO7 [15:14] Selects mode for AUXIO[8i+7]. 2 14 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer. When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7]. When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7]. IO6 [13:12] Selects mode for AUXIO[8i+6]. 2 12 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer. When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6]. When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6]. IO5 [11:10] Selects mode for AUXIO[8i+5]. 2 10 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer. When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5]. When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5]. IO4 [9:8] Selects mode for AUXIO[8i+4]. 2 8 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer. When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4]. When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4]. IO3 [7:6] Selects mode for AUXIO[8i+3]. 2 6 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer. When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3]. When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3]. IO2 [5:4] Select mode for AUXIO[8i+2]. 2 4 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer. When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2]. When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2]. IO1 [3:2] Select mode for AUXIO[8i+1]. 2 2 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer. When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1]. When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1]. IO0 [1:0] Select mode for AUXIO[8i+0]. 2 0 OPEN_SOURCE 3 Open-Source Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. OPEN_DRAIN 2 Open-Drain Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. IN 1 Input Mode: When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer. When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input. OUT 0 Output Mode: When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0]. When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0]. 0x0 GPIODIE 0x4 32 General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. 8 0 0x0 IOPOE 0x8 32 Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*]. Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT. 8 0 0x0 GPIODOUT 0xc 32 General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]. 8 0 0x0 GPIODIN 0x10 32 General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. 8 0 0x0 GPIODOUTSET 0x14 32 General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTCLR 0x18 32 General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. 8 0 0x0 GPIODOUTTGL 0x1c 32 General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7_0 [7:0] Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. 8 0 0x0 IO0PSEL 0x20 32 Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO1PSEL 0x24 32 Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO2PSEL 0x28 32 Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO3PSEL 0x2c 32 Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO4PSEL 0x30 32 Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO5PSEL 0x34 32 Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO6PSEL 0x38 32 Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IO7PSEL 0x3c 32 Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set. 3 0 AUX_TIMER2_PULSE 7 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. AUX_TIMER2_EV3 6 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. AUX_TIMER2_EV2 5 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. AUX_TIMER2_EV1 4 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. AUX_TIMER2_EV0 3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. AUX_SPIM_MOSI 2 Peripheral output mux selects AUX_SPIM MOSI. AUX_SPIM_SCLK 1 Peripheral output mux selects AUX_SPIM SCLK. AUX_EV_OBS 0 Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 0x0 IOMODEL 0x40 32 Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO3 [7:6] See IOMODE.IO3. 2 6 IO2 [5:4] See IOMODE.IO2. 2 4 IO1 [3:2] See IOMODE.IO1. 2 2 IO0 [1:0] See IOMODE.IO0. 2 0 0x0 IOMODEH 0x44 32 Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 IO7 [7:6] See IOMODE.IO7. 2 6 IO6 [5:4] See IOMODE.IO6. 2 4 IO5 [3:2] See IOMODE.IO5. 2 2 IO4 [1:0] See IOMODE.IO4. 2 0 0x0 AUX_ANAIF 0x400C9000 0 0x1000 registers AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets AUX_SCE, UDMA0, and system CPU: -Trigger ADC sample and conversion process. - Write ADC samples to FIFO. - Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information. - Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes. To use: - ADC : AUX_SCE must request active operational mode with AON_PMCTL:AUXSCECLK.SRC set to SCLK_HFDIV2. There are no requirements for system CPU. - ISRC : AUX_SCE must request active operational mode. There are no requirements for system CPU. - DAC : AUX_SCE must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to SCE_RATE as long as DAC state machine generates the sample clock. System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information. ADCCTL 0x10 32 ADC Control Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion. RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 START_POL [14:14] Select active polarity for START_SRC event. 1 14 FALL 1 Set ADC trigger on falling edge of event source. RISE 0 Set ADC trigger on rising edge of event source. START_SRC [13:8] Select ADC trigger event source from the asynchronous AUX event bus. Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 8 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 RESERVED2 [7:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 2 CMD [1:0] ADC interface command. Non-enumerated values are not supported. The written value is returned when read. 2 0 FLUSH 3 Flush ADC FIFO. You must set CMD to EN or DIS after flush. System CPU must wait two clock cycles before it sets CMD to EN or DIS. EN 1 Enable ADC interface. DIS 0 Disable ADC interface. 0x3F00 ADCFIFOSTAT 0x14 32 ADC FIFO Status FIFO can hold up to four ADC samples. RESERVED5 [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 OVERFLOW [4:4] FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO write pointer is static. It is not possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. 1 4 UNDERFLOW [3:3] FIFO underflow flag. 0: FIFO has not underflowed. 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO read pointer is static. Read returns the previous sample that was read. Flush FIFO to clear the flag. 1 3 FULL [2:2] FIFO full flag. 0: FIFO is not full, there is less than 4 samples in the FIFO. 1: FIFO is full, there are 4 samples in the FIFO. When the flag is set, it is not possible to add more samples to the ADC FIFO. An attempt to add samples sets the OVERFLOW flag. 1 2 ALMOST_FULL [1:1] FIFO almost full flag. 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL flag is also asserted in the latter case. 1: There are 3 samples in the FIFO, there is room for one more sample. 1 1 EMPTY [0:0] FIFO empty flag. 0: FIFO contains one or more samples. 1: FIFO is empty. When the flag is set, read returns the previous sample that was read and sets the UNDERFLOW flag. 1 0 0x1 ADCFIFO 0x18 32 ADC FIFO RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 DATA [11:0] FIFO data. Read: Get oldest ADC sample from FIFO. Write: Write dummy sample to FIFO. This is useful for code development when you do not have real ADC samples. 12 0 0x0 ADCTRIG 0x1c 32 ADC Trigger RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 START [0:0] Manual ADC trigger. 0: No effect. 1: Single ADC trigger. To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to avoid conflict with event-driven ADC trigger. 1 0 0x0 ISRCCTL 0x20 32 Current Source Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 RESET_N [0:0] ISRC reset control. 0: ISRC drives 0 uA. 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. 1 0 0x1 DACCTL 0x30 32 DAC Control This register controls the analog part of the DAC. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 DAC_EN [5:5] DAC module enable. 0: Disable DAC. 1: Enable DAC. The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA. The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode. The System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active and Idle TI-RTOS power modes. 1 5 DAC_BUFFER_EN [4:4] DAC buffer enable. DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption. 0: Disable DAC buffer. 1: Enable DAC buffer. Enable buffer when DAC_VOUT_SEL equals COMPA_IN. Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. 1 4 DAC_PRECHARGE_EN [3:3] DAC precharge enable. Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V. DAC output voltage range: 0: 0 V to 1.28 V. 1: 1.28 V to 2.56 V. Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. Enable precharge 1 us before you enable the DAC and the buffer. 1 3 DAC_VOUT_SEL [2:0] DAC output connection. An analog node must only have one driver. Other drivers for the following analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*]. 3 0 COMPA_IN 4 Connect to COMPA_IN analog node. Required setting to drive external load selected in ADI_4_AUX:MUX1.COMPA_IN. COMPA_REF 2 Connect to COMPA_REF analog node. It is not possible to drive external loads connected to COMPA_REF I/O mux with this setting. COMPB_REF 1 Connect to COMPB_REF analog node. Required setting to use Comparator B. NC 0 Connect to nothing It is recommended to use NC as intermediate step when you change DAC_VOUT_SEL. 0x0 LPMBIASCTL 0x34 32 Low Power Mode Bias Control The low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] Module enable. 0: Disable low power mode bias module. 1: Enable low power mode bias module. Set EN to 1 15 us before you enable the DAC or Comparator A. 1 0 0x0 DACSMPLCTL 0x38 32 DAC Sample Control The DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. In the setup phase the sample-and-hold capacitor charges to the programmed voltage. The hold phase maintains the voltage with minimal power. DACSMPLCFG0 and DACSMPLCFG1 configure the DAC sample clock waveform. RESERVED7 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] DAC sample clock enable. 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 when the current sample clock period completes. 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample clock. 1 0 0x0 DACSMPLCFG0 0x3c 32 DAC Sample Configuration 0 RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 CLKDIV [5:0] Clock division. AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency. 0: Divide by 1. 1: Divide by 2. ... 63: Divide by 64. 6 0 0x0 DACSMPLCFG1 0x40 32 DAC Sample Configuration 1 The sample clock period equals (high time + low time) * base period. DACSMPLCFG0.CLKDIV determines the base period. Timing requirements (DAC Buffer On / DAC Buffer Off): - (high time + low time) * base period > (4 us / 1 us) - (high time * base period) > (2 us / 0.5 us) - (low time * base period) > (2 us / 0.5 us) - (low time * base period + HOLD_INTERVAL * sample clock period) < 32 us If AUX_SYSIF:OPMODEREQ.REQ equals PDLP, you must set: - H_PER = L_PER = HOLD_INTERVAL = 0. RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 H_PER [14:14] High time. The sample clock period is high for this many base periods. 0: 2 periods 1: 4 periods 1 14 L_PER [13:12] Low time. The sample clock period is low for this many base periods. 0: 1 period 1: 2 periods 2: 3 periods 3: 4 periods 2 12 SETUP_CNT [11:8] Setup count. Number of active sample clock periods during the setup phase. 0: 1 sample clock period 1: 2 sample clock periods ... 15 : 16 sample clock periods 4 8 HOLD_INTERVAL [7:0] Hold interval. Number of inactive sample clock periods between each active sample clock period during hold phase. The sample clock is low when inactive. The range is 0 to 255. 8 0 0x0 DACVALUE 0x44 32 DAC Value RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 VALUE [7:0] DAC value. Digital data word for the DAC. Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable the DAC. 8 0 0x0 DACSTAT 0x48 32 DAC Status RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 SETUP_ACTIVE [1:1] DAC setup phase status. 0: Sample clock is disabled or setup phase is complete. 1: Setup phase in progress. 1 1 HOLD_ACTIVE [0:0] DAC hold phase status. 0: Sample clock is disabled or DAC is not in hold phase. 1: Hold phase in progress. 1 0 0x0 AUX_EVCTL 0x400C5000 0 0x1000 registers AUX Event Controller (AUX_EVCTL) assembles events originating from: - AUX submodules, including ADC and comparators. - AUXIO. - EVENT. - AON_PMCTL. - AON_RTC. - AON_BATMON. into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized. The subscribers to the synchronous event bus are AUX_TIMER01, AUX_SCE and AUX_EVCTL. The subscribers to the asynchronous event bus are AUX_TIMER2, AUX_ANAIF, AUX_TDC and AUX_SYSIF. AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT, as well as to AUX_SCE. AUX_SCE can poll event status registers and combine certain instructions like WEV0, WEV1 with one or two configurable events. The latter saves power when execution must stall until a condition is met. EVSTAT0 0x0 32 Event Status 0 Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_TIMER2. - AUX_ANAIF. - AUX_TDC. - AUX_SYSIF. - AUX_AIODIOn. - EVOBSCFG. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUXIO15 [15:15] AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. 1 15 AUXIO14 [14:14] AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. 1 14 AUXIO13 [13:13] AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. 1 13 AUXIO12 [12:12] AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. 1 12 AUXIO11 [11:11] AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. 1 11 AUXIO10 [10:10] AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. 1 10 AUXIO9 [9:9] AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. 1 9 AUXIO8 [8:8] AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. 1 8 AUXIO7 [7:7] AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. 1 7 AUXIO6 [6:6] AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. 1 6 AUXIO5 [5:5] AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. 1 5 AUXIO4 [4:4] AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. 1 4 AUXIO3 [3:3] AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. 1 3 AUXIO2 [2:2] AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. 1 2 AUXIO1 [1:1] AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. 1 1 AUXIO0 [0:0] AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. 1 0 0x0 EVSTAT1 0x4 32 Event Status 1 Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_TIMER2. - AUX_ANAIF. - AUX_TDC. - AUX_SYSIF. - AUX_AIODIOn. - EVOBSCFG. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUXIO31 [15:15] AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. 1 15 AUXIO30 [14:14] AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. 1 14 AUXIO29 [13:13] AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. 1 13 AUXIO28 [12:12] AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. 1 12 AUXIO27 [11:11] AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. 1 11 AUXIO26 [10:10] AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. 1 10 AUXIO25 [9:9] AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. 1 9 AUXIO24 [8:8] AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. 1 8 AUXIO23 [7:7] AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. 1 7 AUXIO22 [6:6] AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. 1 6 AUXIO21 [5:5] AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. 1 5 AUXIO20 [4:4] AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. 1 4 AUXIO19 [3:3] AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. 1 3 AUXIO18 [2:2] AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. 1 2 AUXIO17 [1:1] AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. 1 1 AUXIO16 [0:0] AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. 1 0 0x0 EVSTAT2 0x8 32 Event Status 2 Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_TIMER2. - AUX_ANAIF. - AUX_TDC. - AUX_SYSIF. - AUX_AIODIOn. - EVOBSCFG. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUX_COMPB [15:15] Comparator B output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the synchronization rate for this event. 1 15 AUX_COMPA [14:14] Comparator A output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the synchronization rate for this event. 1 14 MCU_OBSMUX1 [13:13] Observation input 1 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL1. 1 13 MCU_OBSMUX0 [12:12] Observation input 0 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC. 1 12 MCU_EV [11:11] Event from EVENT configured by EVENT:AUXSEL0. 1 11 ACLK_REF [10:10] TDC reference clock. It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ. 1 10 VDDR_RECHARGE [9:9] Event is high during VDDR recharge. 1 9 MCU_ACTIVE [8:8] Event is high while system(MCU, AUX, or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state). Event is not high during VDDR recharge. 1 8 PWR_DWN [7:7] Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO power supply). 1 7 SCLK_LF [6:6] SCLK_LF clock 1 6 AON_BATMON_TEMP_UPD [5:5] Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP. 1 5 AON_BATMON_BAT_UPD [4:4] Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT. 1 4 AON_RTC_4KHZ [3:3] AON_RTC:SUBSEC.VALUE bit 19. AON_RTC:CTL.RTC_4KHZ_EN enables this event. 1 3 AON_RTC_CH2_DLY [2:2] AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. 1 2 AON_RTC_CH2 [1:1] AON_RTC:EVFLAGS.CH2. 1 1 MANUAL_EV [0:0] Programmable event. See MANUAL for description. 1 0 0x0 EVSTAT3 0xc 32 Event Status 3 Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_TIMER2. - AUX_ANAIF. - AUX_TDC . - AUX_SYSIF. - AUX_AIODIOn. - EVOBSCFG. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUX_TIMER2_CLKSWITCH_RDY [15:15] AUX_SYSIF:TIMER2CLKSWITCH.RDY 1 15 AUX_DAC_HOLD_ACTIVE [14:14] AUX_ANAIF:DACSTAT.HOLD_ACTIVE 1 14 AUX_SMPH_AUTOTAKE_DONE [13:13] See AUX_SMPH:AUTOTAKE.SMPH_ID for description. 1 13 AUX_ADC_FIFO_NOT_EMPTY [12:12] AUX_ANAIF:ADCFIFOSTAT.EMPTY negated 1 12 AUX_ADC_FIFO_ALMOST_FULL [11:11] AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL 1 11 AUX_ADC_IRQ [10:10] The logical function for this event is configurable. When DMACTL.EN = 1 : Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW When DMACTL.EN = 0 : Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW Bit 7 in UDMA0:DONEMASK must be 0. 1 10 AUX_ADC_DONE [9:9] AUX_ANAIF ADC conversion done event. Event is synchronized at AUX bus rate. 1 9 AUX_ISRC_RESET_N [8:8] AUX_ANAIF:ISRCCTL.RESET_N 1 8 AUX_TDC_DONE [7:7] AUX_TDC:STAT.DONE 1 7 AUX_TIMER0_EV [6:6] AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. 1 6 AUX_TIMER1_EV [5:5] AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. 1 5 AUX_TIMER2_PULSE [4:4] AUX_TIMER2 pulse event. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event. 1 4 AUX_TIMER2_EV3 [3:3] AUX_TIMER2 event output 3. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event. 1 3 AUX_TIMER2_EV2 [2:2] AUX_TIMER2 event output 2. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event. 1 2 AUX_TIMER2_EV1 [1:1] AUX_TIMER2 event output 1. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event. 1 1 AUX_TIMER2_EV0 [0:0] AUX_TIMER2 event output 0. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event. 1 0 0x0 SCEWEVCFG0 0x10 32 Sensor Controller Engine Wait Event Configuration 0 Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS. This bit can be used by AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions. When COMB_EV_EN = 0: AUX_SCE:WUSTAT.EV_SIGNALS (7) = EV0_SEL event When COMB_EV_EN = 1: AUX_SCE:WUSTAT.EV_SIGNALS (7) = ( EV0_SEL event ) OR ( SCEWEVCFG1.EV1_SEL event ) Bit fields SCEWEVCFG1.EV0_POL and SCEWEVCFG1.EV1_POL control the polarity of selected events. Event combination is useful when there is a need to wait for a certain condition with timeout. RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 COMB_EV_EN [6:6] Event combination control: 0: Disable event combination. 1: Enable event combination. 1 6 EV0_SEL [5:0] Select the event source from the synchronous event bus to be used in event equation. 6 0 AUX_TIMER2_CLKSWITCH_RDY 63 EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY AUX_DAC_HOLD_ACTIVE 62 EVSTAT3.AUX_DAC_HOLD_ACTIVE AUX_SMPH_AUTOTAKE_DONE 61 EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 EVSTAT2.AUX_COMPB AUX_COMPA 46 EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 EVSTAT2.MCU_OBSMUX0 MCU_EV 43 EVSTAT2.MCU_EV ACLK_REF 42 EVSTAT2.ACLK_REF VDDR_RECHARGE 41 EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 EVSTAT2.MCU_ACTIVE PWR_DWN 39 EVSTAT2.PWR_DWN SCLK_LF 38 EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 EVSTAT2.AON_RTC_CH2 AUX_PROG_DLY_IDLE 32 Programmable delay event as described in PROGDLY AUXIO31 31 EVSTAT1.AUXIO31 AUXIO30 30 EVSTAT1.AUXIO30 AUXIO29 29 EVSTAT1.AUXIO29 AUXIO28 28 EVSTAT1.AUXIO28 AUXIO27 27 EVSTAT1.AUXIO27 AUXIO26 26 EVSTAT1.AUXIO26 AUXIO25 25 EVSTAT1.AUXIO25 AUXIO24 24 EVSTAT1.AUXIO24 AUXIO23 23 EVSTAT1.AUXIO23 AUXIO22 22 EVSTAT1.AUXIO22 AUXIO21 21 EVSTAT1.AUXIO21 AUXIO20 20 EVSTAT1.AUXIO20 AUXIO19 19 EVSTAT1.AUXIO19 AUXIO18 18 EVSTAT1.AUXIO18 AUXIO17 17 EVSTAT1.AUXIO17 AUXIO16 16 EVSTAT1.AUXIO16 AUXIO15 15 EVSTAT0.AUXIO15 AUXIO14 14 EVSTAT0.AUXIO14 AUXIO13 13 EVSTAT0.AUXIO13 AUXIO12 12 EVSTAT0.AUXIO12 AUXIO11 11 EVSTAT0.AUXIO11 AUXIO10 10 EVSTAT0.AUXIO10 AUXIO9 9 EVSTAT0.AUXIO9 AUXIO8 8 EVSTAT0.AUXIO8 AUXIO7 7 EVSTAT0.AUXIO7 AUXIO6 6 EVSTAT0.AUXIO6 AUXIO5 5 EVSTAT0.AUXIO5 AUXIO4 4 EVSTAT0.AUXIO4 AUXIO3 3 EVSTAT0.AUXIO3 AUXIO2 2 EVSTAT0.AUXIO2 AUXIO1 1 EVSTAT0.AUXIO1 AUXIO0 0 EVSTAT0.AUXIO0 0x0 SCEWEVCFG1 0x14 32 Sensor Controller Engine Wait Event Configuration 1 See SCEWEVCFG0 for description. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EV0_POL [7:7] Polarity of SCEWEVCFG0.EV0_SEL event. When SCEWEVCFG0.COMB_EV_EN is 0: 0: Non-inverted. 1: Non-inverted. When SCEWEVCFG0.COMB_EV_EN is 1. 0: Non-inverted. 1: Inverted. 1 7 EV1_POL [6:6] Polarity of EV1_SEL event. When SCEWEVCFG0.COMB_EV_EN is 0: 0: Non-inverted. 1: Non-inverted. When SCEWEVCFG0.COMB_EV_EN is 1. 0: Non-inverted. 1: Inverted. 1 6 EV1_SEL [5:0] Select the event source from the synchronous event bus to be used in event equation. 6 0 AUX_TIMER2_CLKSWITCH_RDY 63 EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY AUX_DAC_HOLD_ACTIVE 62 EVSTAT3.AUX_DAC_HOLD_ACTIVE AUX_SMPH_AUTOTAKE_DONE 61 EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 EVSTAT2.AUX_COMPB AUX_COMPA 46 EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 EVSTAT2.MCU_OBSMUX0 MCU_EV 43 EVSTAT2.MCU_EV ACLK_REF 42 EVSTAT2.ACLK_REF VDDR_RECHARGE 41 EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 EVSTAT2.MCU_ACTIVE PWR_DWN 39 EVSTAT2.PWR_DWN SCLK_LF 38 EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 EVSTAT2.AON_RTC_CH2 AUX_PROG_DLY_IDLE 32 Programmable delay event as described in PROGDLY AUXIO31 31 EVSTAT1.AUXIO31 AUXIO30 30 EVSTAT1.AUXIO30 AUXIO29 29 EVSTAT1.AUXIO29 AUXIO28 28 EVSTAT1.AUXIO28 AUXIO27 27 EVSTAT1.AUXIO27 AUXIO26 26 EVSTAT1.AUXIO26 AUXIO25 25 EVSTAT1.AUXIO25 AUXIO24 24 EVSTAT1.AUXIO24 AUXIO23 23 EVSTAT1.AUXIO23 AUXIO22 22 EVSTAT1.AUXIO22 AUXIO21 21 EVSTAT1.AUXIO21 AUXIO20 20 EVSTAT1.AUXIO20 AUXIO19 19 EVSTAT1.AUXIO19 AUXIO18 18 EVSTAT1.AUXIO18 AUXIO17 17 EVSTAT1.AUXIO17 AUXIO16 16 EVSTAT1.AUXIO16 AUXIO15 15 EVSTAT0.AUXIO15 AUXIO14 14 EVSTAT0.AUXIO14 AUXIO13 13 EVSTAT0.AUXIO13 AUXIO12 12 EVSTAT0.AUXIO12 AUXIO11 11 EVSTAT0.AUXIO11 AUXIO10 10 EVSTAT0.AUXIO10 AUXIO9 9 EVSTAT0.AUXIO9 AUXIO8 8 EVSTAT0.AUXIO8 AUXIO7 7 EVSTAT0.AUXIO7 AUXIO6 6 EVSTAT0.AUXIO6 AUXIO5 5 EVSTAT0.AUXIO5 AUXIO4 4 EVSTAT0.AUXIO4 AUXIO3 3 EVSTAT0.AUXIO3 AUXIO2 2 EVSTAT0.AUXIO2 AUXIO1 1 EVSTAT0.AUXIO1 AUXIO0 0 EVSTAT0.AUXIO0 0x0 DMACTL 0x18 32 Direct Memory Access Control RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 REQ_MODE [2:2] UDMA0 Request mode 1 2 SINGLE 1 Single requests are generated on UDMA0 channel 7 when the condition configured in SEL is met. BURST 0 Burst requests are generated on UDMA0 channel 7 when the condition configured in SEL is met. EN [1:1] uDMA ADC interface enable. 0: Disable UDMA0 interface to ADC. 1: Enable UDMA0 interface to ADC. 1 1 SEL [0:0] Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data. 1 0 AUX_ADC_FIFO_ALMOST_FULL 1 UDMA0 trigger event will be generated when the ADC FIFO is almost full (3/4 full). AUX_ADC_FIFO_NOT_EMPTY 0 UDMA0 trigger event will be generated when there are samples in the ADC FIFO. 0x0 SWEVSET 0x20 32 Software Event Set Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR. Use of these event flags is software-defined. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SWEV2 [2:2] Software event flag 2. 0: No effect. 1: Set software event flag 2. 1 2 SWEV1 [1:1] Software event flag 1. 0: No effect. 1: Set software event flag 1. 1 1 SWEV0 [0:0] Software event flag 0. 0: No effect. 1: Set software event flag 0. 1 0 0x0 EVTOAONFLAGS 0x24 32 Events To AON Flags This register contains a collection of event flags routed to AON_EVENT. To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register. RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 AUX_TIMER1_EV [8:8] This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV. 1 8 AUX_TIMER0_EV [7:7] This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV. 1 7 AUX_TDC_DONE [6:6] This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE. 1 6 AUX_ADC_DONE [5:5] This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE. 1 5 AUX_COMPB [4:4] This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB. 1 4 AUX_COMPA [3:3] This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA. 1 3 SWEV2 [2:2] This event flag is set when software writes a 1 to SWEVSET.SWEV2. 1 2 SWEV1 [1:1] This event flag is set when software writes a 1 to SWEVSET.SWEV1. 1 1 SWEV0 [0:0] This event flag is set when software writes a 1 to SWEVSET.SWEV0. 1 0 0x0 EVTOAONPOL 0x28 32 Events To AON Polarity Event source polarity configuration for EVTOAONFLAGS. RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 AUX_TIMER1_EV [8:8] Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV. 1 8 LOW 1 Low level HIGH 0 High level AUX_TIMER0_EV [7:7] Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV. 1 7 LOW 1 Low level HIGH 0 High level AUX_TDC_DONE [6:6] Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE. 1 6 LOW 1 Low level HIGH 0 High level AUX_ADC_DONE [5:5] Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE. 1 5 LOW 1 Low level HIGH 0 High level AUX_COMPB [4:4] Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. 1 4 FALL 1 Falling edge RISE 0 Rising edge AUX_COMPA [3:3] Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. 1 3 FALL 1 Falling edge RISE 0 Rising edge RESERVED2 [2:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 0 0x0 EVTOAONFLAGSCLR 0x2c 32 Events To AON Clear Clear event flags in EVTOAONFLAGS. In order to clear a level sensitive event flag, the event must be deasserted. RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 AUX_TIMER1_EV [8:8] Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. Read value is 0. 1 8 AUX_TIMER0_EV [7:7] Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. Read value is 0. 1 7 AUX_TDC_DONE [6:6] Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. Read value is 0. 1 6 AUX_ADC_DONE [5:5] Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. Read value is 0. 1 5 AUX_COMPB [4:4] Write 1 to clear EVTOAONFLAGS.AUX_COMPB. Read value is 0. 1 4 AUX_COMPA [3:3] Write 1 to clear EVTOAONFLAGS.AUX_COMPA. Read value is 0. 1 3 SWEV2 [2:2] Write 1 to clear EVTOAONFLAGS.SWEV2. Read value is 0. 1 2 SWEV1 [1:1] Write 1 to clear EVTOAONFLAGS.SWEV1. Read value is 0. 1 1 SWEV0 [0:0] Write 1 to clear EVTOAONFLAGS.SWEV0. Read value is 0. 1 0 0x0 EVTOMCUFLAGS 0x30 32 Events to MCU Flags This register contains a collection of event flags routed to MCU domain. To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUX_TIMER2_PULSE [15:15] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE. 1 15 AUX_TIMER2_EV3 [14:14] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3. 1 14 AUX_TIMER2_EV2 [13:13] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2. 1 13 AUX_TIMER2_EV1 [12:12] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1. 1 12 AUX_TIMER2_EV0 [11:11] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0. 1 11 AUX_ADC_IRQ [10:10] This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ. 1 10 MCU_OBSMUX0 [9:9] This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0. 1 9 AUX_ADC_FIFO_ALMOST_FULL [8:8] This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. 1 8 AUX_ADC_DONE [7:7] This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE. 1 7 AUX_SMPH_AUTOTAKE_DONE [6:6] This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. 1 6 AUX_TIMER1_EV [5:5] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV. 1 5 AUX_TIMER0_EV [4:4] This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV. 1 4 AUX_TDC_DONE [3:3] This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE. 1 3 AUX_COMPB [2:2] This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB. 1 2 AUX_COMPA [1:1] This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA. 1 1 AUX_WU_EV [0:0] This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register. 1 0 0x0 EVTOMCUPOL 0x34 32 Event To MCU Polarity Event source polarity configuration for EVTOMCUFLAGS. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUX_TIMER2_PULSE [15:15] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE. 1 15 LOW 1 Low level HIGH 0 High level AUX_TIMER2_EV3 [14:14] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3. 1 14 LOW 1 Low level HIGH 0 High level AUX_TIMER2_EV2 [13:13] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2. 1 13 LOW 1 Low level HIGH 0 High level AUX_TIMER2_EV1 [12:12] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1. 1 12 LOW 1 Low level HIGH 0 High level AUX_TIMER2_EV0 [11:11] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0. 1 11 LOW 1 Low level HIGH 0 High level AUX_ADC_IRQ [10:10] Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ. 1 10 LOW 1 Low level HIGH 0 High level MCU_OBSMUX0 [9:9] Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0. 1 9 LOW 1 Low level HIGH 0 High level AUX_ADC_FIFO_ALMOST_FULL [8:8] Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. 1 8 LOW 1 Low level HIGH 0 High level AUX_ADC_DONE [7:7] Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE. 1 7 LOW 1 Low level HIGH 0 High level AUX_SMPH_AUTOTAKE_DONE [6:6] Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. 1 6 LOW 1 Low level HIGH 0 High level AUX_TIMER1_EV [5:5] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV. 1 5 LOW 1 Low level HIGH 0 High level AUX_TIMER0_EV [4:4] Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV. 1 4 LOW 1 Low level HIGH 0 High level AUX_TDC_DONE [3:3] Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE. 1 3 LOW 1 Low level HIGH 0 High level AUX_COMPB [2:2] Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB. 1 2 FALL 1 Falling edge RISE 0 Rising edge AUX_COMPA [1:1] Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA. 1 1 FALL 1 Falling edge RISE 0 Rising edge AUX_WU_EV [0:0] Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV. 1 0 LOW 1 Low level HIGH 0 High level 0x0 EVTOMCUFLAGSCLR 0x38 32 Events To MCU Flags Clear Clear event flags in EVTOMCUFLAGS. In order to clear a level sensitive event flag, the event must be deasserted. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUX_TIMER2_PULSE [15:15] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE. Read value is 0. 1 15 AUX_TIMER2_EV3 [14:14] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3. Read value is 0. 1 14 AUX_TIMER2_EV2 [13:13] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2. Read value is 0. 1 13 AUX_TIMER2_EV1 [12:12] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1. Read value is 0. 1 12 AUX_TIMER2_EV0 [11:11] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0. Read value is 0. 1 11 AUX_ADC_IRQ [10:10] Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. Read value is 0. 1 10 MCU_OBSMUX0 [9:9] Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. Read value is 0. 1 9 AUX_ADC_FIFO_ALMOST_FULL [8:8] Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. Read value is 0. 1 8 AUX_ADC_DONE [7:7] Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. Read value is 0. 1 7 AUX_SMPH_AUTOTAKE_DONE [6:6] Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. Read value is 0. 1 6 AUX_TIMER1_EV [5:5] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. Read value is 0. 1 5 AUX_TIMER0_EV [4:4] Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. Read value is 0. 1 4 AUX_TDC_DONE [3:3] Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. Read value is 0. 1 3 AUX_COMPB [2:2] Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. Read value is 0. 1 2 AUX_COMPA [1:1] Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. Read value is 0. 1 1 AUX_WU_EV [0:0] Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV. Read value is 0. 1 0 0x0 COMBEVTOMCUMASK 0x3c 32 Combined Event To MCU Mask Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU. The AUX_COMB event is high as long as one or more of the included event flags are set. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AUX_TIMER2_PULSE [15:15] EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 15 AUX_TIMER2_EV3 [14:14] EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 14 AUX_TIMER2_EV2 [13:13] EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 13 AUX_TIMER2_EV1 [12:12] EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 12 AUX_TIMER2_EV0 [11:11] EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 11 AUX_ADC_IRQ [10:10] EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 10 MCU_OBSMUX0 [9:9] EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 9 AUX_ADC_FIFO_ALMOST_FULL [8:8] EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 8 AUX_ADC_DONE [7:7] EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 7 AUX_SMPH_AUTOTAKE_DONE [6:6] EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 6 AUX_TIMER1_EV [5:5] EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 5 AUX_TIMER0_EV [4:4] EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 4 AUX_TDC_DONE [3:3] EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 3 AUX_COMPB [2:2] EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. 0: Exclude 1: Include. 1 2 AUX_COMPA [1:1] EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 1 AUX_WU_EV [0:0] EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include. 1 0 0x0 EVOBSCFG 0x40 32 Event Observation Configuration RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 EVOBS_SEL [5:0] Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn. 6 0 AUX_TIMER2_CLKSW_RDY 63 EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY AUX_DAC_HOLD_ACTIVE 62 EVSTAT3.AUX_DAC_HOLD_ACTIVE AUX_SMPH_AUTOTAKE_DONE 61 EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 EVSTAT2.AUX_COMPB AUX_COMPA 46 EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 EVSTAT2.MCU_OBSMUX0 MCU_EV 43 EVSTAT2.MCU_EV ACLK_REF 42 EVSTAT2.ACLK_REF VDDR_RECHARGE 41 EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 EVSTAT2.MCU_ACTIVE PWR_DWN 39 EVSTAT2.PWR_DWN SCLK_LF 38 EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 EVSTAT2.MANUAL_EV AUXIO31 31 EVSTAT1.AUXIO31 AUXIO30 30 EVSTAT1.AUXIO30 AUXIO29 29 EVSTAT1.AUXIO29 AUXIO28 28 EVSTAT1.AUXIO28 AUXIO27 27 EVSTAT1.AUXIO27 AUXIO26 26 EVSTAT1.AUXIO26 AUXIO25 25 EVSTAT1.AUXIO25 AUXIO24 24 EVSTAT1.AUXIO24 AUXIO23 23 EVSTAT1.AUXIO23 AUXIO22 22 EVSTAT1.AUXIO22 AUXIO21 21 EVSTAT1.AUXIO21 AUXIO20 20 EVSTAT1.AUXIO20 AUXIO19 19 EVSTAT1.AUXIO19 AUXIO18 18 EVSTAT1.AUXIO18 AUXIO17 17 EVSTAT1.AUXIO17 AUXIO16 16 EVSTAT1.AUXIO16 AUXIO15 15 EVSTAT0.AUXIO15 AUXIO14 14 EVSTAT0.AUXIO14 AUXIO13 13 EVSTAT0.AUXIO13 AUXIO12 12 EVSTAT0.AUXIO12 AUXIO11 11 EVSTAT0.AUXIO11 AUXIO10 10 EVSTAT0.AUXIO10 AUXIO9 9 EVSTAT0.AUXIO9 AUXIO8 8 EVSTAT0.AUXIO8 AUXIO7 7 EVSTAT0.AUXIO7 AUXIO6 6 EVSTAT0.AUXIO6 AUXIO5 5 EVSTAT0.AUXIO5 AUXIO4 4 EVSTAT0.AUXIO4 AUXIO3 3 EVSTAT0.AUXIO3 AUXIO2 2 EVSTAT0.AUXIO2 AUXIO1 1 EVSTAT0.AUXIO1 AUXIO0 0 EVSTAT0.AUXIO0 0x0 PROGDLY 0x44 32 Programmable Delay RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] VALUE decrements to 0 at a rate of 1 MHz. The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low. Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when AUX_SYSIF:OPMODEACK.ACK equals A or LP. Decrementation of VALUE halts when either is true: - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode. - AUX_SYSIF:TIMERHALT.PROGDLY is set. 16 0 0x0 MANUAL 0x48 32 Manual Programmable event. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EV [0:0] This bit field sets the value of EVSTAT2.MANUAL_EV. 1 0 0x0 EVSTAT0L 0x4c 32 Event Status 0 Low RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT0 event 7 down to 0. 8 0 0x0 EVSTAT0H 0x50 32 Event Status 0 High RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT0 event 15 down to 8. 8 0 0x0 EVSTAT1L 0x54 32 Event Status 1 Low RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT1 event 7 down to 0. 8 0 0x0 EVSTAT1H 0x58 32 Event Status 1 High RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT1 event 15 down to 8. 8 0 0x0 EVSTAT2L 0x5c 32 Event Status 2 Low RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT2 event 7 down to 0. 8 0 0x0 EVSTAT2H 0x60 32 Event Status 2 High RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT2 event 15 down to 8. 8 0 0x0 EVSTAT3L 0x64 32 Event Status 3 Low RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT3 event 7 down to 0. 8 0 0x0 EVSTAT3H 0x68 32 Event Status 3 High RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 ALIAS_EV [7:0] Alias of EVSTAT3 event 15 down to 8. 8 0 0x0 AUX_MAC 0x400C2000 0 0x1000 registers The AUX Multiply-Accumulate (AUX_MAC) peripheral enables AUX_SCE with power-efficient and flexible mathematical operations: - 2's complement signed and unsigned sequential multiplication (MUL) with optional accumulation of the result (MAC). - 16 or 32-bit 2's complement signed and unsigned addition of configurable term and accumulator (ADD). - Results of ADD, MUL and MAC operations are always stored in the accumulator (ACC). Software can easily: - Access arbitrary 16-bit slice of the 40-bit accumulator. - Find the number of leading zero or sign bits. - Perform shift operations on the accumulator. AUX_SCE must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to SCE_RATE to access and use AUX_MAC. System CPU must set AUX_SYSIF:PEROPRATE.MAC_OP_RATE to BUS_RATE to access and use AUX_MAC. This guarantees constant execution times for ADD, MUL, and MAC operations. The ADD operation requires a single peripheral clock cycle to finish. MUL and MAC operations require four peripheral clock periods to finish. An unfinished ADD, MUL, or MAC operation stalls register access to this peripheral. AUX_SCE becomes clock gated if it encounters a bus stall. Software can use this to reduce power consumption during back to back accesses. Only full word access is supported by the peripheral. An attempt to write a single byte will have no effect. OP0S 0x0 32 Signed Operand 0 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP0_VALUE [15:0] Signed operand 0. Operand for multiply, multiply-and-accumulate, or 32-bit add operations. 16 0 0x0 OP0U 0x4 32 Unsigned Operand 0 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP0_VALUE [15:0] Unsigned operand 0. Operand for multiply, multiply-and-accumulate, or 32-bit add operations. 16 0 0x0 OP1SMUL 0x8 32 Signed Operand 1 and Multiply RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Signed operand 1 and multiplication trigger. Write OP1_VALUE to set signed operand 1 and trigger the following operation: When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * OP0S.OP0_VALUE. When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * OP0U.OP0_VALUE. 16 0 0x0 OP1UMUL 0xc 32 Unsigned Operand 1 and Multiply RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Unsigned operand 1 and multiplication trigger. Write OP1_VALUE to set unsigned operand 1 and trigger the following operation: When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * OP0S.OP0_VALUE. When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * OP0U.OP0_VALUE. 16 0 0x0 OP1SMAC 0x10 32 Signed Operand 1 and Multiply-Accumulate RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Signed operand 1 and multiply-accumulation trigger. Write OP1_VALUE to set signed operand 1 and trigger the following operation: When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0S.OP0_VALUE ). When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0U.OP0_VALUE ). 16 0 0x0 OP1UMAC 0x14 32 Unsigned Operand 1 and Multiply-Accumulate RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Unsigned operand 1 and multiply-accumulation trigger. Write OP1_VALUE to set unsigned operand 1 and trigger the following operation: When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0S.OP0_VALUE ). When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0U.OP0_VALUE ). 16 0 0x0 OP1SADD16 0x18 32 Signed Operand 1 and 16-bit Addition RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Signed operand 1 and 16-bit addition trigger. Write OP1_VALUE to set signed operand 1 and trigger the following operation: ACC = ACC + OP1_VALUE. 16 0 0x0 OP1UADD16 0x1c 32 Unsigned Operand 1 and 16-bit Addition RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Unsigned operand 1 and 16-bit addition trigger. Write OP1_VALUE to set unsigned operand 1 and trigger the following operation: ACC = ACC + OP1_VALUE. 16 0 0x0 OP1SADD32 0x20 32 Signed Operand 1 and 32-bit Addition RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Upper half of signed 32-bit operand and addition trigger. Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the following operation: When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). 16 0 0x0 OP1UADD32 0x24 32 Unsigned Operand 1 and 32-bit Addition RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OP1_VALUE [15:0] Upper half of unsigned 32-bit operand and addition trigger. Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the following operation: When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). 16 0 0x0 CLZ 0x28 32 Count Leading Zero RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 VALUE [5:0] Number of leading zero bits in the accumulator: 0x00: 0 leading zeros. 0x01: 1 leading zero. ... 0x28: 40 leading zeros (accumulator value is 0). 6 0 0x28 CLS 0x2c 32 Count Leading Sign RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 VALUE [5:0] Number of leading sign bits in the accumulator. When MSB of accumulator is 0, VALUE is number of leading zeros, MSB included. When MSB of accumulator is 1, VALUE is number of leading ones, MSB included. VALUE range is 1 thru 40. 6 0 0x28 ACCSHIFT 0x30 32 Accumulator Shift Only one shift operation can be triggered per register write. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 LSL1 [2:2] Logic shift left by 1 bit. Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0. 1 2 LSR1 [1:1] Logic shift right by 1 bit. Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39. 1 1 ASR1 [0:0] Arithmetic shift right by 1 bit. Write 1 to shift the accumulator one bit to the right, previous sign bit inserted at bit 39. 1 0 0x0 ACCRESET 0x34 32 Accumulator Reset RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TRG [15:0] Write any value to this register to trigger a reset of all bits in the accumulator. 16 0 0x0 ACC15_0 0x38 32 Accumulator Bits 15:0 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 15:0. Write VALUE to initialize bits 15:0 of accumulator. 16 0 0x0 ACC16_1 0x3c 32 Accumulator Bits 16:1 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 16:1. 16 0 0x0 ACC17_2 0x40 32 Accumulator Bits 17:2 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 17:2. 16 0 0x0 ACC18_3 0x44 32 Accumulator Bits 18:3 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 18:3. 16 0 0x0 ACC19_4 0x48 32 Accumulator Bits 19:4 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 19:4. 16 0 0x0 ACC20_5 0x4c 32 Accumulator Bits 20:5 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 20:5. 16 0 0x0 ACC21_6 0x50 32 Accumulator Bits 21:6 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 21:6. 16 0 0x0 ACC22_7 0x54 32 Accumulator Bits 22:7 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 22:7. 16 0 0x0 ACC23_8 0x58 32 Accumulator Bits 23:8 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 23:8. 16 0 0x0 ACC24_9 0x5c 32 Accumulator Bits 24:9 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 24:9. 16 0 0x0 ACC25_10 0x60 32 Accumulator Bits 25:10 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 25:10. 16 0 0x0 ACC26_11 0x64 32 Accumulator Bits 26:11 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 26:11. 16 0 0x0 ACC27_12 0x68 32 Accumulator Bits 27:12 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 27:12. 16 0 0x0 ACC28_13 0x6c 32 Accumulator Bits 28:13 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 28:13. 16 0 0x0 ACC29_14 0x70 32 Accumulator Bits 29:14 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 29:14. 16 0 0x0 ACC30_15 0x74 32 Accumulator Bits 30:15 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 30:15. 16 0 0x0 ACC31_16 0x78 32 Accumulator Bits 31:16 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 31:16. Write VALUE to initialize bits 31:16 of accumulator. 16 0 0x0 ACC32_17 0x7c 32 Accumulator Bits 32:17 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 32:17. 16 0 0x0 ACC33_18 0x80 32 Accumulator Bits 33:18 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 33:18. 16 0 0x0 ACC34_19 0x84 32 Accumulator Bits 34:19 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 34:19. 16 0 0x0 ACC35_20 0x88 32 Accumulator Bits 35:20 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 35:20. 16 0 0x0 ACC36_21 0x8c 32 Accumulator Bits 36:21 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 36:21. 16 0 0x0 ACC37_22 0x90 32 Accumulator Bits 37:22 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 37:22. 16 0 0x0 ACC38_23 0x94 32 Accumulator Bits 38:23 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 38:23. 16 0 0x0 ACC39_24 0x98 32 Accumulator Bits 39:24 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Value of the accumulator, bits 39:24. 16 0 0x0 ACC39_32 0x9c 32 Accumulator Bits 39:32 RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 VALUE [7:0] Value of the accumulator, bits 39:32. Write VALUE to initialize bits 39:32 of accumulator. 8 0 0x0 AUX_SCE 0x400E1000 0 0x1000 registers AUX Sensor Control Engine (AUX_SCE) is a RISC-style microprocessor with separate fetch and execution cycles. It is optimized for low power and simple operations. AUX_SCE code and data segments are stored in AUX_RAM. AON_PMCTL:AUXSCECLK sets the operational frequency. CTL 0x0 32 Internal. Only to be used through TI provided API. FORCE_EV_LOW [31:24] Internal. Only to be used through TI provided API. 8 24 FORCE_EV_HIGH [23:16] Internal. Only to be used through TI provided API. 8 16 RESET_VECTOR [15:8] Internal. Only to be used through TI provided API. 8 8 RESERVED7 [7:7] Internal. Only to be used through TI provided API. 1 7 DBG_FREEZE_EN [6:6] Internal. Only to be used through TI provided API. 1 6 FORCE_WU_LOW [5:5] Internal. Only to be used through TI provided API. 1 5 FORCE_WU_HIGH [4:4] Internal. Only to be used through TI provided API. 1 4 RESTART [3:3] Internal. Only to be used through TI provided API. 1 3 SINGLE_STEP [2:2] Internal. Only to be used through TI provided API. 1 2 SUSPEND [1:1] Internal. Only to be used through TI provided API. 1 1 CLK_EN [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 FETCHSTAT 0x4 32 Internal. Only to be used through TI provided API. OPCODE [31:16] Internal. Only to be used through TI provided API. 16 16 PC [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 CPUSTAT 0x8 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 BUS_ERROR [11:11] Internal. Only to be used through TI provided API. 1 11 SLEEP [10:10] Internal. Only to be used through TI provided API. 1 10 WEV [9:9] Internal. Only to be used through TI provided API. 1 9 HALTED [8:8] Internal. Only to be used through TI provided API. 1 8 RESERVED4 [7:4] Internal. Only to be used through TI provided API. 4 4 V_FLAG [3:3] Internal. Only to be used through TI provided API. 1 3 C_FLAG [2:2] Internal. Only to be used through TI provided API. 1 2 N_FLAG [1:1] Internal. Only to be used through TI provided API. 1 1 Z_FLAG [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 WUSTAT 0xc 32 Internal. Only to be used through TI provided API. RESERVED20 [31:19] Internal. Only to be used through TI provided API. 13 19 EXC_VECTOR [18:16] Internal. Only to be used through TI provided API. 3 16 RESERVED9 [15:9] Internal. Only to be used through TI provided API. 7 9 WU_SIGNAL [8:8] Internal. Only to be used through TI provided API. 1 8 EV_SIGNALS [7:0] Internal. Only to be used through TI provided API. 8 0 SCEWEV_PROG 128 Internal. Only to be used through TI provided API. AUX_ADC_FIFO_NOT_EMPTY 64 Internal. Only to be used through TI provided API. AUX_TIMER1_EV_OR_IDLE 32 Internal. Only to be used through TI provided API. AUX_TIMER0_EV_OR_IDLE 16 Internal. Only to be used through TI provided API. AUX_TDC_DONE 8 Internal. Only to be used through TI provided API. AUX_COMPB 4 Internal. Only to be used through TI provided API. AUX_COMPA 2 Internal. Only to be used through TI provided API. AUX_PROG_DLY_IDLE 1 Internal. Only to be used through TI provided API. 0x0 REG1_0 0x10 32 Internal. Only to be used through TI provided API. REG1 [31:16] Internal. Only to be used through TI provided API. 16 16 REG0 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 REG3_2 0x14 32 Internal. Only to be used through TI provided API. REG3 [31:16] Internal. Only to be used through TI provided API. 16 16 REG2 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 REG5_4 0x18 32 Internal. Only to be used through TI provided API. REG5 [31:16] Internal. Only to be used through TI provided API. 16 16 REG4 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 REG7_6 0x1c 32 Internal. Only to be used through TI provided API. REG7 [31:16] Internal. Only to be used through TI provided API. 16 16 REG6 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 LOOPADDR 0x20 32 Internal. Only to be used through TI provided API. STOP [31:16] Internal. Only to be used through TI provided API. 16 16 START [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 LOOPCNT 0x24 32 Internal. Only to be used through TI provided API. RESERVED8 [31:8] Internal. Only to be used through TI provided API. 24 8 ITER_LEFT [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 AUX_SMPH 0x400C8000 0 0x1000 registers AUX Semaphore (AUX_SMPH) provides hardware means to share modules in AUX safely between CPUs based on resource ownership. AUX_SMPH operates at AUX bus rate. SMPH0 0x0 32 Semaphore 0 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH1 0x4 32 Semaphore 1 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH2 0x8 32 Semaphore 2 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH3 0xc 32 Semaphore 3 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH4 0x10 32 Semaphore 4 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH5 0x14 32 Semaphore 5 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH6 0x18 32 Semaphore 6 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 SMPH7 0x1c 32 Semaphore 7 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore. 1 0 0x1 AUTOTAKE 0x20 32 Auto Take Sticky Request for Single Semaphore. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SMPH_ID [2:0] Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until it is granted. When semaphore SMPH_ID is granted, event AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE becomes 1. The event becomes 0 when software releases the semaphore or writes a new value to SMPH_ID. To avoid corrupted semaphores: - Usage of this functionality must be restricted to one CPU core. - Software must wait until AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE is 1 before it writes a new value to SMPH_ID. 3 0 0x0 AUX_SPIM 0x400C1000 0 0x1000 registers The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication. It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete. Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus. AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers. AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency. AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission. SPIMCFG 0x0 32 SPI Master Configuration Write operation stalls until current transfer completes. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 DIV [7:2] SCLK divider. Peripheral clock frequency division gives the SCLK clock frequency. The division factor equals (2 * (DIV+1)): 0x00: Divide by 2. 0x01: Divide by 4. 0x02: Divide by 6. ... 0x3F: Divide by 128. 6 2 PHA [1:1] Phase of the MOSI and MISO data signals. 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) edges of SCLK. 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) edges of SCLK. 1 1 POL [0:0] Polarity of the SCLK signal. 0: SCLK is low when idle, first clock edge rises. 1: SCLK is high when idle, first clock edge falls. 1 0 0x0 MISOCFG 0x4 32 MISO Configuration Write operation stalls until current transfer completes. RESERVED5 [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 AUXIO [4:0] AUXIO to MISO mux. Select the AUXIO pin that connects to MISO. 5 0 0x0 MOSICTL 0x8 32 MOSI Control Write operation stalls until current transfer completes. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 VALUE [0:0] MOSI level control. 0: Set MOSI low. 1: Set MOSI high. 1 0 0x0 TX8 0xc 32 Transmit 8 Bit Write operation stalls until current transfer completes. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 DATA [7:0] 8 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. 8 0 0x0 TX16 0x10 32 Transmit 16 Bit Write operation stalls until current transfer completes. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DATA [15:0] 16 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. 16 0 0x0 RX8 0x14 32 Receive 8 Bit Read operation stalls until current transfer completes. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 DATA [7:0] Latest 8 bits received on MISO. 8 0 0x0 RX16 0x18 32 Receive 16 Bit Read operation stalls until current transfer completes. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DATA [15:0] Latest 16 bits received on MISO. 16 0 0x0 SCLKIDLE 0x1c 32 SCLK Idle Read operation stalls until SCLK is idle with no remaining clock edges. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Wait for SCLK idle. Read operation stalls until SCLK is idle with no remaining clock edges. Read then returns 1. AUX_SCE can use this to control CS deassertion. 1 0 0x1 DATAIDLE 0x20 32 Data Idle Read operation stalls until current transfer completes. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Wait for data idle. Read operation stalls until the SCLK period associated with LSB transmission completes. Read then returns 1. AUX_SCE can use this to control CS deassertion. 1 0 0x1 AUX_SYSIF 0x400C6000 0 0x1000 registers AUX System Interface (AUX_SYSIF) is responsible for: - system resource requests, such as power supply, clock and, wakeup requests. - configuration of AUX peripheral operational rates for AUX_SPIM, AUX_MAC, AUX_ANAIF DAC state machine and AUX_TIMER01. - configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3. - configuration of AUX_SCE wakeup vectors that trigger AUX_SCE execution from sleep. Peripheral operational rate for AUX modules mentioned above can either be: - SCE rate, which is configured in AON_PMCTL:AUXSCECLK. - AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active. AUX_SYSIF also interfaces AON_RTC and AON_BATMON to enable read access to data and sub-second increment control of AON_RTC. OPMODEREQ 0x0 32 Operational Mode Request AUX can operate in three operational modes. Each mode is associated with: - a SCE clock source or rate, given by AON_PMCTL:AUXSCECLK. This rate is termed SCE_RATE. - a system power supply state request. AUX can request powerdown (uLDO) or active (GLDO or DCDC) system power supply state. - a specific system response to an active AUX wakeup flag. The response is dependent on what operational mode is requested. uLDO power supply state offers limited current supply. AUX_SCE cannot use certain peripherals and functions such as AUX_DDI0_OSC, AUX_TDC and AUX_ANAIF ADC interface in this power supply state. Follow these rules: - It is not allowed to change a request until it has been acknowledged through OPMODEACK. - A change in mode request must happen stepwise along this sequence, the direction is irrelevant: PDA - A - LP - PDLP. Failure to follow these rules might result in unexpected behavior and must be avoided. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 REQ [1:0] AUX operational mode request. 2 0 PDLP 3 Powerdown operational mode with wakeup to lowpower mode, characterized by: - Powerdown system power supply state (uLDO) request. - AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE). - An active wakeup flag overrides the operational mode externally to lowpower (LP) as long as the flag is set. PDA 2 Powerdown operational mode with wakeup to active mode, characterized by: - Powerdown system power supply state (uLDO) request. - AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE). - An active wakeup flag overrides the operational mode externally to active (A) as long as the flag is set. LP 1 Lowpower operational mode, characterized by: - Powerdown system power supply state (uLDO) request. - SCE clock frequency (SCE_RATE) equals SCLK_MF. - An active wakeup flag does not change operational mode. A 0 Active operational mode, characterized by: - Active system power supply state (GLDO or DCDC) request. - AON_PMCTL:AUXSCECLK.SRC sets the SCE clock frequency (SCE_RATE). - An active wakeup flag does not change operational mode. 0x0 OPMODEACK 0x4 32 Operational Mode Acknowledgement AUX_SCE program must assume that the current operational mode is the one acknowledged. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 ACK [1:0] AUX operational mode acknowledgement. 2 0 PDLP 3 Powerdown operational mode with wakeup to lowpower mode is acknowledged. PDA 2 Powerdown operational mode with wakeup to active mode is acknowledged. LP 1 Lowpower operational mode is acknowledged. A 0 Active operational mode is acknowledged. 0x0 PROGWU0CFG 0x8 32 Programmable Wakeup 0 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU0 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 POL [7:7] Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU0. 1 7 LOW 1 The wakeup flag is set when WU_SRC is low or goes low. HIGH 0 The wakeup flag is set when WU_SRC is high or goes high. EN [6:6] Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. 1 6 WU_SRC [5:0] Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 0 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 0x0 PROGWU1CFG 0xc 32 Programmable Wakeup 1 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU1 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 POL [7:7] Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU1. 1 7 LOW 1 The wakeup flag is set when WU_SRC is low or goes low. HIGH 0 The wakeup flag is set when WU_SRC is high or goes high. EN [6:6] Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. 1 6 WU_SRC [5:0] Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 0 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 0x0 PROGWU2CFG 0x10 32 Programmable Wakeup 2 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU2 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 POL [7:7] Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU2. 1 7 LOW 1 The wakeup flag is set when WU_SRC is low or goes low. HIGH 0 The wakeup flag is set when WU_SRC is high or goes high. EN [6:6] Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. 1 6 WU_SRC [5:0] Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 0 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 0x0 PROGWU3CFG 0x14 32 Programmable Wakeup 3 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU3 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 POL [7:7] Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU3. 1 7 LOW 1 The wakeup flag is set when WU_SRC is low or goes low. HIGH 0 The wakeup flag is set when WU_SRC is high or goes high. EN [6:6] Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. 1 6 WU_SRC [5:0] Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 0 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 0x0 SWWUTRIG 0x18 32 Software Wakeup Triggers System CPU uses these wakeup flags to perform handshaking with AUX_SCE. The wakeup flags can change the operational mode of AUX and guarantees a non-zero SCE clock rate. AUX_SCE wakeup vectors are configured in VECCFGn. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 SW_WU3 [3:3] Software wakeup 3 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup. 1 3 SW_WU2 [2:2] Software wakeup 2 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup. 1 2 SW_WU1 [1:1] Software wakeup 1 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup. 1 1 SW_WU0 [0:0] Software wakeup 0 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup. 1 0 0x0 WUFLAGS 0x1c 32 Wakeup Flags This register holds the eight AUX wakeup flags. Each flag can cause AUX operational mode to change as given in OPMODEREQ. To clear flag n you must set bit n in WUFLAGSCLR until flag n is read as 0. You must clear bit n in WUFLAGSCLR before flag n can be set again. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SW_WU3 [7:7] Software wakeup 3 flag. 0: Software wakeup 3 not triggered. 1: Software wakeup 3 triggered. 1 7 SW_WU2 [6:6] Software wakeup 2 flag. 0: Software wakeup 2 not triggered. 1: Software wakeup 2 triggered. 1 6 SW_WU1 [5:5] Software wakeup 1 flag. 0: Software wakeup 1 not triggered. 1: Software wakeup 1 triggered. 1 5 SW_WU0 [4:4] Software wakeup 0 flag. 0: Software wakeup 0 not triggered. 1: Software wakeup 0 triggered. 1 4 PROG_WU3 [3:3] Programmable wakeup 3. 0: Programmable wakeup 3 not triggered. 1: Programmable wakeup 3 triggered. 1 3 PROG_WU2 [2:2] Programmable wakeup 2. 0: Programmable wakeup 2 not triggered. 1: Programmable wakeup 2 triggered. 1 2 PROG_WU1 [1:1] Programmable wakeup 1. 0: Programmable wakeup 1 not triggered. 1: Programmable wakeup 1 triggered. 1 1 PROG_WU0 [0:0] Programmable wakeup 0. 0: Programmable wakeup 0 not triggered. 1: Programmable wakeup 0 triggered. 1 0 0x0 WUFLAGSCLR 0x20 32 Wakeup Flags Clear This register clears AUX wakeup flags WUFLAGS. To clear programmable wakeup flags you must disable the AUX wakeup output first. After the programmable wakeup flags are cleared you must re-enable the AUX wakeup output. Write WUGATE to disable or enable the AUX wakeup output. This procedure is not required when you want to clear a software-triggered wakeup. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SW_WU3 [7:7] Clear software wakeup flag 3. 0: No effect. 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0. 1 7 SW_WU2 [6:6] Clear software wakeup flag 2. 0: No effect. 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0. 1 6 SW_WU1 [5:5] Clear software wakeup flag 1. 0: No effect. 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0. 1 5 SW_WU0 [4:4] Clear software wakeup flag 0. 0: No effect. 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0. 1 4 PROG_WU3 [3:3] Programmable wakeup flag 3. 0: No effect. 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN. 1 3 PROG_WU2 [2:2] Programmable wakeup flag 2. 0: No effect. 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN. 1 2 PROG_WU1 [1:1] Programmable wakeup flag 1. 0: No effect. 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN. 1 1 PROG_WU0 [0:0] Programmable wakeup flag 0. 0: No effect. 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN. 1 0 0xF WUGATE 0x24 32 Wakeup Gate You must disable the AUX wakeup output: - Before you clear a programmable wakeup flag. - Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC]. The AUX wakeup output must be re-enabled after clear operation or programmable wakeup configuration. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] Wakeup output enable. 0: Disable AUX wakeup output. 1: Enable AUX wakeup output. 1 0 0x0 VECCFG0 0x28 32 Vector Configuration 0 AUX_SCE wakeup vector 0 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 0. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG1 0x2c 32 Vector Configuration 1 AUX_SCE wakeup vector 1 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 1. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG2 0x30 32 Vector Configuration 2 AUX_SCE wakeup vector 2 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 2. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG3 0x34 32 Vector Configuration 3 AUX_SCE wakeup vector 3 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 3. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG4 0x38 32 Vector Configuration 4 AUX_SCE wakeup vector 4 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 4. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG5 0x3c 32 Vector Configuration 5 AUX_SCE wakeup vector 5 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 5. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG6 0x40 32 Vector Configuration 6 AUX_SCE wakeup vector 6 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 6. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 VECCFG7 0x44 32 Vector Configuration 7 AUX_SCE wakeup vector 7 configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 VEC_EV [3:0] Select trigger event for vector 7. Non-enumerated values are treated as NONE. 4 0 AON_RTC_CH2_DLY 9 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY SW_WU3 8 WUFLAGS.SW_WU3 SW_WU2 7 WUFLAGS.SW_WU2 SW_WU1 6 WUFLAGS.SW_WU1 SW_WU0 5 WUFLAGS.SW_WU0 PROG_WU3 4 WUFLAGS.PROG_WU3 PROG_WU2 3 WUFLAGS.PROG_WU2 PROG_WU1 2 WUFLAGS.PROG_WU1 PROG_WU0 1 WUFLAGS.PROG_WU0 NONE 0 Vector is disabled. 0x0 EVSYNCRATE 0x48 32 Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus. You must select SCE rate when AUX_SCE uses the event. You must select AUX bus rate when system CPU uses the event. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by two when MCU domain is active. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 AUX_COMPA_SYNC_RATE [2:2] Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event. 1 2 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate AUX_COMPB_SYNC_RATE [1:1] Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event. 1 1 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate AUX_TIMER2_SYNC_RATE [0:0] Select synchronization rate for: - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 1 0 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate 0x0 PEROPRATE 0x4c 32 Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate. You must select SCE rate when AUX_SCE uses such peripheral or an event produced by it. You must select AUX bus rate when system CPU uses such peripheral. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by 2 when MCU domain is active. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 ANAIF_DAC_OP_RATE [3:3] Select operational rate for AUX_ANAIF DAC sample clock state machine. 1 3 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate TIMER01_OP_RATE [2:2] Select operational rate for AUX_TIMER01. 1 2 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate SPIM_OP_RATE [1:1] Select operational rate for AUX_SPIM. 1 1 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate MAC_OP_RATE [0:0] Select operational rate for AUX_MAC. 1 0 BUS_RATE 1 AUX bus rate SCE_RATE 0 SCE rate 0x0 ADCCLKCTL 0x50 32 ADC Clock Control RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 ACK [1:1] Clock acknowledgement. 0: ADC clock is disabled. 1: ADC clock is enabled. 1 1 REQ [0:0] ADC clock request. 0: Disable ADC clock. 1: Enable ADC clock. Only modify REQ when equal to ACK. 1 0 0x0 TDCCLKCTL 0x54 32 TDC Counter Clock Control Controls if the AUX_TDC counter clock source is enabled. TDC counter clock source is configured in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 ACK [1:1] TDC counter clock acknowledgement. 0: TDC counter clock is disabled. 1: TDC counter clock is enabled. 1 1 REQ [0:0] TDC counter clock request. 0: Disable TDC counter clock. 1: Enable TDC counter clock. Only modify REQ when equal to ACK. 1 0 0x0 TDCREFCLKCTL 0x58 32 TDC Reference Clock Control Controls if the AUX_TDC reference clock source is enabled. This clock is compared against the AUX_TDC counter clock. TDC reference clock source is configured in DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 ACK [1:1] TDC reference clock acknowledgement. 0: TDC reference clock is disabled. 1: TDC reference clock is enabled. 1 1 REQ [0:0] TDC reference clock request. 0: Disable TDC reference clock. 1: Enable TDC reference clock. Only modify REQ when equal to ACK. 1 0 0x0 TIMER2CLKCTL 0x5c 32 AUX_TIMER2 Clock Control Access to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 SRC [2:0] Select clock source for AUX_TIMER2. Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1. It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0. A non-enumerated value is ignored. 3 0 SCLK_HFDIV2 4 SCLK_HF / 2 SCLK_MF 2 SCLK_MF SCLK_LF 1 SCLK_LF NONE 0 no clock 0x0 TIMER2CLKSTAT 0x60 32 AUX_TIMER2 Clock Status RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 STAT [2:0] AUX_TIMER2 clock source status. 3 0 SCLK_HFDIV2 4 SCLK_HF / 2 SCLK_MF 2 SCLK_MF SCLK_LF 1 SCLK_LF NONE 0 No clock 0x0 TIMER2CLKSWITCH 0x64 32 AUX_TIMER2 Clock Switch RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 RDY [0:0] Status of clock switcher. 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT. 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY. 1 0 0x1 TIMER2DBGCTL 0x68 32 AUX_TIMER2 Debug Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 DBG_FREEZE_EN [0:0] Debug freeze enable. 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. 1: Halt AUX_TIMER2 when the system CPU halts in debug mode. 1 0 0x0 CLKSHIFTDET 0x70 32 Clock Shift Detection A transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF: - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when MCU domain enters active state. - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles shorter when MCU domain exits active state. AUX_SCE detects if such events occurred to the SCE clock during the time period between a clear of STAT and a read of STAT. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Clock shift detection. Write: 0: Restart clock shift detection. 1: Do not use. Read: 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. 1: MCU domain entered or exited active state since you wrote 0 to STAT. 1 0 0x1 RECHARGETRIG 0x74 32 VDDR Recharge Trigger RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 TRIG [0:0] Recharge trigger. 0: No effect. 1: Request VDDR recharge. Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1. Follow this sequence when OPMODEREQ.REQ is LP: - Set TRIG. - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1. - Clear TRIG. - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0. Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: - Set TRIG. - Clear TRIG. 1 0 0x0 RECHARGEDET 0x78 32 VDDR Recharge Detection Some applications can be sensitive to power noise caused by recharge of VDDR. You can detect if VDDR recharge occurs. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 STAT [1:1] VDDR recharge detector status. 0: No recharge of VDDR has occurred since EN was set. 1: Recharge of VDDR has occurred since EN was set. 1 1 EN [0:0] VDDR recharge detector enable. 0: Disable recharge detection. STAT becomes zero. 1: Enable recharge detection. 1 0 0x0 RTCSUBSECINC0 0x7c 32 Real Time Counter Sub Second Increment 0 INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 INC15_0 [15:0] New value for bits 15:0 in AON_RTC:SUBSECINC. 16 0 0x0 RTCSUBSECINC1 0x80 32 Real Time Counter Sub Second Increment 1 INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 INC23_16 [7:0] New value for bits 23:16 in AON_RTC:SUBSECINC. 8 0 0x0 RTCSUBSECINCCTL 0x84 32 Real Time Counter Sub Second Increment Control RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 UPD_ACK [1:1] Update acknowledgement. 0: AON_RTC has not acknowledged UPD_REQ. 1: AON_RTC has acknowledged UPD_REQ. 1 1 UPD_REQ [0:0] Request AON_RTC to update AON_RTC:SUBSECINC. 0: Clear request to update. 1: Set request to update. Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is 1. 1 0 0x0 RTCSEC 0x88 32 Real Time Counter Second System CPU must not access this register. Instead, system CPU must access AON_RTC:SEC.VALUE directly. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SEC [15:0] Bits 15:0 in AON_RTC:SEC.VALUE. Follow this procedure to get the correct value: - Do two dummy reads of SEC. - Then read SEC until two consecutive reads are equal. 16 0 0x0 RTCSUBSEC 0x8c 32 Real Time Counter Sub-Second System CPU must not access this register. Instead, system CPU must access AON_RTC:SUBSEC.VALUE directly. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SUBSEC [15:0] Bits 31:16 in AON_RTC:SUBSEC.VALUE. Follow this procedure to get the correct value: - Do two dummy reads SUBSEC. - Then read SUBSEC until two consecutive reads are equal. 16 0 0x0 RTCEVCLR 0x90 32 AON_RTC Event Clear Request to clear events: - AON_RTC:EVFLAGS.CH2. - AON_RTC:EVFLAGS.CH2 delayed version. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 RTC_CH2_EV_CLR [0:0] Clear events from AON_RTC channel 2. 0: No effect. 1: Clear events from AON_RTC channel 2. Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0. 1 0 0x0 BATMONBAT 0x94 32 AON_BATMON Battery Voltage Value Read access to AON_BATMON:BAT. System CPU must not access this register. Instead, system CPU must access AON_BATMON:BAT directly. AON_BATMON:BAT updates during VDDR recharge or active operational mode. RESERVED11 [31:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 21 11 INT [10:8] See AON_BATMON:BAT.INT. Follow this procedure to get the correct value: - Do two dummy reads of INT. - Then read INT until two consecutive reads are equal. 3 8 FRAC [7:0] See AON_BATMON:BAT.FRAC. Follow this procedure to get the correct value: - Do two dummy reads of FRAC. - Then read FRAC until two consecutive reads are equal. 8 0 0x0 BATMONTEMP 0x9c 32 AON_BATMON Temperature Value Read access to AON_BATMON:TEMP. System CPU must not access this register. Instead, system CPU must access AON_BATMON:TEMP directly. AON_BATMON:TEMP updates during VDDR recharge or active operational mode. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SIGN [15:11] Sign extension of INT. Follow this procedure to get the correct value: - Do two dummy reads of SIGN. - Then read SIGN until two consecutive reads are equal. 5 11 INT [10:2] See AON_BATMON:TEMP.INT. Follow this procedure to get the correct value: - Do two dummy reads of INT. - Then read INT until two consecutive reads are equal. 9 2 FRAC [1:0] See AON_BATMON:TEMP.FRAC. Follow this procedure to get the correct value: - Do two dummy reads of FRAC. - Then read FRAC until two consecutive reads are equal. 2 0 0x0 TIMERHALT 0xa0 32 Timer Halt Debug register RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 PROGDLY [3:3] Halt programmable delay. 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation. 1 3 AUX_TIMER2 [2:2] Halt AUX_TIMER2. 0: AUX_TIMER2 operates as normal. 1: Halt AUX_TIMER2 operation. 1 2 AUX_TIMER1 [1:1] Halt AUX_TIMER01 Timer 1. 0: AUX_TIMER01 Timer 1 operates as normal. 1: Halt AUX_TIMER01 Timer 1 operation. 1 1 AUX_TIMER0 [0:0] Halt AUX_TIMER01 Timer 0. 0: AUX_TIMER01 Timer 0 operates as normal. 1: Halt AUX_TIMER01 Timer 0 operation. 1 0 0x0 TIMER2BRIDGE 0xb0 32 AUX_TIMER2 Bridge RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 BUSY [0:0] Status of bus transactions to AUX_TIMER2. 0: No unfinished bus transactions. 1: A bus transaction is ongoing. 1 0 0x0 SWPWRPROF 0xb4 32 Software Power Profiler RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 STAT [2:0] Software status bits that can be read by the power profiler. 3 0 0x0 AUX_TDC 0x400C4000 0 0x1000 registers AUX Time To Digital Converter (AUX_TDC) is used to measure the time between two events with high resolution. AUX_TDC consists of a state machine that operates at AUX bus rate and an asynchronous fast-counter which is clocked by the TDC clock. DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL configures TDC clock source. The fast-counter counts on both edges of the TDC clock to double the resolution. See the Technical Reference Manual for event timing requirements. CTL 0x0 32 Control RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CMD [1:0] TDC commands. 2 0 ABORT 3 Force TDC state machine back to IDLE state. Never write this command while AUX_TDC:STAT.STATE equals CLR_CNT or WAIT_CLR_CNT_DONE. RUN 2 Asynchronous counter start. The counter starts to count when the start event is high. To achieve precise edge-to-edge measurements you must ensure that the start event is low for at least 420 ns after you write this command. RUN_SYNC_START 1 Synchronous counter start. The counter looks for the opposite edge of the selected start event before it starts to count when the selected edge occurs. This guarantees an edge-triggered start and is recommended for frequency measurements. CLR_RESULT 0 Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. This is not needed as prerequisite for a measurement. Reliable clear is only guaranteed from IDLE state. 0x0 STAT 0x4 32 Status RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SAT [7:7] TDC measurement saturation flag. 0: Conversion has not saturated. 1: Conversion stopped due to saturation. This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD. 1 7 DONE [6:6] TDC measurement complete flag. 0: TDC measurement has not yet completed. 1: TDC measurement has completed. This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD. 1 6 STATE [5:0] TDC state machine status. 6 0 FORCE_STOP 46 Current state is TDC_FORCESTOP. You wrote ABORT to CTL.CMD to abort the TDC measurement. START_FALL 30 Current state is TDC_WAIT_STARTFALL. The fast-counter circuit waits for a falling edge on the start event. WAIT_CLR_CNT_DONE 22 Current state is TDC_STATE_WAIT_CLRCNT_DONE. The state machine waits for fast-counter circuit to finish reset. POR 15 Current state is TDC_STATE_POR. This is the reset state. GET_RESULT 14 Current state is TDC_STATE_GETRESULTS. The state machine copies the counter value from the fast-counter circuit. WAIT_STOP_CNTDWN 12 Current state is TDC_STATE_WAIT_STOPCNTDOWN. The fast-counter circuit looks for the stop condition. It will ignore a number of stop events configured in TRIGCNTLOAD.CNT. WAIT_STOP 8 Current state is TDC_STATE_WAIT_STOP. The state machine waits for the fast-counter circuit to stop. CLR_CNT 7 Current state is TDC_STATE_CLRCNT. The fast-counter circuit is reset. IDLE 6 Current state is TDC_STATE_IDLE. This is the default state after reset and abortion. State will change when you write CTL.CMD to either RUN_SYNC_START or RUN. WAIT_START_STOP_CNT_EN 4 Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment. WAIT_START 0 Current state is TDC_STATE_WAIT_START. The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment. 0x6 RESULT 0x8 32 Result Result of last TDC conversion. RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 VALUE [24:0] TDC conversion result. The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and falling edges are counted. If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it takes a non-zero time to stop the measurement. Hence, the maximum value of this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT to R24. 25 0 0x2 SATCFG 0xc 32 Saturation Configuration RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 LIMIT [3:0] Saturation limit. The flag STAT.SAT is set when the TDC counter saturates. Values not enumerated are not supported 4 0 R24 15 Result bit 24: TDC conversion saturates and stops when RESULT.VALUE[24] is set. R23 14 Result bit 23: TDC conversion saturates and stops when RESULT.VALUE[23] is set. R22 13 Result bit 22: TDC conversion saturates and stops when RESULT.VALUE[22] is set. R21 12 Result bit 21: TDC conversion saturates and stops when RESULT.VALUE[21] is set. R20 11 Result bit 20: TDC conversion saturates and stops when RESULT.VALUE[20] is set. R19 10 Result bit 19: TDC conversion saturates and stops when RESULT.VALUE[19] is set. R18 9 Result bit 18: TDC conversion saturates and stops when RESULT.VALUE[18] is set. R17 8 Result bit 17: TDC conversion saturates and stops when RESULT.VALUE[17] is set. R16 7 Result bit 16: TDC conversion saturates and stops when RESULT.VALUE[16] is set. R15 6 Result bit 15: TDC conversion saturates and stops when RESULT.VALUE[15] is set. R14 5 Result bit 14: TDC conversion saturates and stops when RESULT.VALUE[14] is set. R13 4 Result bit 13: TDC conversion saturates and stops when RESULT.VALUE[13] is set. R12 3 Result bit 12: TDC conversion saturates and stops when RESULT.VALUE[12] is set. 0xF TRIGSRC 0x10 32 Trigger Source Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements. RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 STOP_POL [14:14] Polarity of stop source. Change only while STAT.STATE is IDLE. 1 14 LOW 1 TDC conversion stops when low level is detected. HIGH 0 TDC conversion stops when high level is detected. STOP_SRC [13:8] Select stop source from the asynchronous AUX event bus. Change only while STAT.STATE is IDLE. 6 8 NO_EVENT 63 No event. AUX_TDC_PRE 62 Select TDC Prescaler event which is generated by configuration of PRECTL. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 START_POL [6:6] Polarity of start source. Change only while STAT.STATE is IDLE. 1 6 LOW 1 TDC conversion starts when low level is detected. HIGH 0 TDC conversion starts when high level is detected. START_SRC [5:0] Select start source from the asynchronous AUX event bus. Change only while STAT.STATE is IDLE. 6 0 NO_EVENT 63 No event. AUX_TDC_PRE 62 Select TDC Prescaler event which is generated by configuration of PRECTL. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 0x0 TRIGCNT 0x14 32 Trigger Counter Stop-counter control and status. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CNT [15:0] Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. Read CNT to get the remaining number of stop events to ignore during a TDC measurement. Write CNT to update the remaining number of stop events to ignore during a TDC measurement. The TDC measurement ignores updates of CNT if there are no more stop events left to ignore. When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the start of the measurement. 16 0 0x0 TRIGCNTLOAD 0x18 32 Trigger Counter Load Stop-counter load. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CNT [15:0] Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. To measure frequency of an event source: - Set start event equal to stop event. - Set CNT to number of periods to measure. Both 0 and 1 values measures a single event source period. To measure pulse width of an event source: - Set start event source equal to stop event source. - Select different polarity for start and stop event. - Set CNT to 0. To measure time from the start event to the Nth stop event when N > 1: - Select different start and stop event source. - Set CNT to (N-1). See the Technical Reference Manual for event timing requirements. When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start of the measurement. 16 0 0x0 TRIGCNTCFG 0x1c 32 Trigger Counter Configuration Stop-counter configuration. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] Enable stop-counter. 0: Disable stop-counter. 1: Enable stop-counter. Change only while STAT.STATE is IDLE. 1 0 0x0 PRECTL 0x20 32 Prescaler Control The prescaler can be used to count events that are faster than the AUX bus rate. It can be used to: - count pulses on a specified event from the asynchronous event bus. - prescale a specified event from the asynchronous event bus. To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE. It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX bus rate. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 RESET_N [7:7] Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler. 1 7 RATIO [6:6] Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler. 1 6 DIV64 1 Prescaler divides input by 64. AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input. DIV16 0 Prescaler divides input by 16. AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input. SRC [5:0] Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0. 6 0 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 0x3F PRECNTR 0x24 32 Prescaler Counter RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CNT [15:0] Prescaler counter value. Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value. The read value gets 1 LSB uncertainty if the event source level rises when you release the reset. The read value gets 1 LSB uncertainty if the event source level rises when you capture the prescaler counter. Please note the following: - The prescaler counter is reset to 2 by PRECTL.RESET_N. - The captured value is 2 when the number of rising edges on prescaler input is less than 3. Otherwise, captured value equals number of event pulses - 1. 16 0 0x0 AUX_TIMER01 0x400C7000 0 0x1000 registers AUX Timer 0 and AUX Timer 1 (AUX_TIMER01) are two 16-bit timers capable of generating one event each: - AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV. - AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV. The events are described in T0TARGET and T1TARGET. Subscribers to the AUX event bus can use these events to sequence and trigger actions. AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the peripheral clock frequency used by the prescaler, timer, and event logic to SCE or AUX bus rate. To use AUX_TIMER01: - AUX_SCE must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to SCE_RATE. - System CPU must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to BUS_RATE. - The timers must only subscribe to events updated at the peripheral clock frequency or lower. Unexpected execution behavior can result if software does not obey these rules. T0CFG 0x0 32 Timer 0 Configuration RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 TICK_SRC_POL [14:14] Tick source polarity for Timer 0. 1 14 FALL 1 Count on falling edges of TICK_SRC. RISE 0 Count on rising edges of TICK_SRC. TICK_SRC [13:8] Select Timer 0 tick source from the synchronous event bus. 6 8 AUX_TIMER2_CLKSW_RDY 63 AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY AUX_DAC_HOLD_ACTIVE 62 AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE NO_EVENT 54 No event. AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 PRE [7:4] Prescaler division ratio is 2^PRE: 0x0: Divide by 1. 0x1: Divide by 2. 0x2: Divide by 4. ... 0xF: Divide by 32,768. 4 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 MODE [1:1] Timer 0 mode. Configure source for Timer 0 prescaler. 1 1 TICK 1 Use event set by TICK_SRC as source for prescaler. CLK 0 Use clock as source for prescaler. Note that AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the clock frequency. RELOAD [0:0] Timer 0 reload mode. 1 0 CONT 1 Continuous mode. Timer 0 restarts when the counter value becomes equal to or greater than ( T0TARGET.VALUE - 1). MAN 0 Manual mode. Timer 0 stops and T0CTL.EN becomes 0 when the counter value becomes equal to or greater than T0TARGET.VALUE. 0x0 T0CTL 0x4 32 Timer 0 Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] Timer 0 enable. 0: Disable Timer 0. 1: Enable Timer 0. The counter restarts from 0 when you enable Timer 0. 1 0 0x0 T0TARGET 0x8 32 Timer 0 Target RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Timer 0 target value. Manual Reload Mode: - Timer 0 increments until the counter value becomes equal to or greater than VALUE. - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter value is equal to or greater than VALUE. Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 peripheral clock period. Continuous Reload Mode: - Timer 0 increments until the counter value becomes equal to or greater than ( VALUE - 1), then restarts from 0. - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter value is 0, except for when you enable the timer. Note: When VALUE is less than 2, Timer 0 counter value remains 0. AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you enable the timer. It is allowed to update the VALUE while the timer runs. 16 0 0x0 T0CNTR 0xc 32 Timer 0 Counter RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Timer 0 counter value. 16 0 0x0 T1CFG 0x10 32 Timer 1 Configuration RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 TICK_SRC_POL [14:14] Tick source polarity for Timer 1. 1 14 FALL 1 Count on falling edges of TICK_SRC. RISE 0 Count on rising edges of TICK_SRC. TICK_SRC [13:8] Select Timer 1 tick source from the synchronous event bus. 6 8 AUX_TIMER2_CLKSW_RDY 63 AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY AUX_DAC_HOLD_ACTIVE 62 AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV NO_EVENT 53 No event. AUX_TIMER2_PULSE 52 AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 PRE [7:4] Prescaler division ratio is 2^PRE: 0x0: Divide by 1. 0x1: Divide by 2. 0x2: Divide by 4. ... 0xF: Divide by 32,768. 4 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 MODE [1:1] Timer 1 mode. Configure source for Timer 1 prescaler. 1 1 TICK 1 Use event set by TICK_SRC as source for prescaler. CLK 0 Use clock as source for prescaler. Note that AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the clock frequency. RELOAD [0:0] Timer 1 reload mode. 1 0 CONT 1 Continuous mode. Timer 1 restarts when the counter value becomes equal to or greater than ( T1TARGET.VALUE - 1). MAN 0 Manual mode. Timer 1 stops and T1CTL.EN becomes 0 when the counter value becomes equal to or greater than T1TARGET.VALUE. 0x0 T1CTL 0x14 32 Timer 1 Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN [0:0] Timer 1 enable. 0: Disable Timer 1. 1: Enable Timer 1. The counter restarts from 0 when you enable Timer 1. 1 0 0x0 T1TARGET 0x18 32 Timer 1 Target Timer 1 counter target value RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Timer 1 target value. Manual Reload Mode: - Timer 1 increments until the counter value becomes equal to or greater than VALUE. - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter value is equal to or greater than VALUE. Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 peripheral clock period. Continuous Reload Mode: - Timer 1 increments until the counter value becomes equal to or greater than ( VALUE - 1), then restarts from 0. - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter value is 0, except for when you enable the timer. Note: When VALUE is less than 2, Timer 1 counter value remains 0. AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you enable the timer. It is allowed to update the VALUE while the timer runs. 16 0 0x0 T1CNTR 0x1c 32 Timer 1 Counter RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Timer 1 counter value. 16 0 0x0 AUX_TIMER2 0x400C3000 0 0x1000 registers AUX Timer2 (AUX_TIMER2) offers flexible: - generation of waveforms and events. - capture of signal period and duty cycle. - generation of single clock pulse. It consists of a: - 16-bit counter. - 4 capture compare channels. - 4 event outputs, which are mapped to AUX event bus, see EVCTL. Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer. CTL 0x0 32 Timer Control RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 CH3_RESET [6:6] Channel 3 reset. 0: No effect. 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. Read returns 0. 1 6 CH2_RESET [5:5] Channel 2 reset. 0: No effect. 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. Read returns 0. 1 5 CH1_RESET [4:4] Channel 1 reset. 0: No effect. 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. Read returns 0. 1 4 CH0_RESET [3:3] Channel 0 reset. 0: No effect. 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. Read returns 0. 1 3 TARGET_EN [2:2] Select counter target value. You must select TARGET to use shadow target functionality. 1 2 TARGET 1 TARGET.VALUE CNTR_MAX 0 65535 MODE [1:0] Timer mode control. The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or UPDWN_PER. When you write MODE all internally queued updates to [CHnCC.*] and TARGET clear. 2 0 UPDWN_PER 3 Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly. Period = (target value * 2) * timer clock period UP_PER 2 Count up periodically. The timer increments from 0 to target value, repeatedly. Period = (target value + 1) * timer clock period UP_ONCE 1 Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS. DIS 0 Disable timer. Updates to counter, channels, and events stop. 0x0 TARGET 0x4 32 Target User defined counter target. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] 16 bit user defined counter target value, which is used when selected by CTL.TARGET_EN. 16 0 0x0 SHDWTARGET 0x8 32 Shadow Target RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Target value for next counter period. The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy does not happen when you restart the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. 16 0 0x0 CNTR 0xc 32 Counter RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] 16 bit current counter value. 16 0 0x0 PRECFG 0x10 32 Clock Prescaler Configuration RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 CLKDIV [7:0] Clock division. CLKDIV determines the timer clock frequency for counter, synchronization, and timer event updates. The timer clock frequency is the clock selected by AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256. 8 0 0x0 EVCTL 0x14 32 Event Control Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected. An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time. The four events connect to the asynchronous AUX event bus: - Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. - Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. - Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. - Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EV3_SET [7:7] Set event 3. Write 1 to set event 3. 1 7 EV3_CLR [6:6] Clear event 3. Write 1 to clear event 3. 1 6 EV2_SET [5:5] Set event 2. Write 1 to set event 2. 1 5 EV2_CLR [4:4] Clear event 2. Write 1 to clear event 2. 1 4 EV1_SET [3:3] Set event 1. Write 1 to set event 1. 1 3 EV1_CLR [2:2] Clear event 1. Write 1 to clear event 1. 1 2 EV0_SET [1:1] Set event 0. Write 1 to set event 0. 1 1 EV0_CLR [0:0] Clear event 0. Write 1 to clear event 0. 1 0 0x0 PULSETRIG 0x18 32 Pulse Trigger RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 TRIG [0:0] Pulse trigger. Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. 1 0 0x0 CH0EVCFG 0x80 32 Channel 0 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EV3_GEN [7:7] Event 3 enable. 0: Channel 0 does not control event 3. 1: Channel 0 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 1 7 EV2_GEN [6:6] Event 2 enable. 0: Channel 0 does not control event 2. 1: Channel 0 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 1 6 EV1_GEN [5:5] Event 1 enable. 0: Channel 0 does not control event 1. 1: Channel 0 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 1 5 EV0_GEN [4:4] Event 0 enable. 0: Channel 0 does not control event 0. 1: Channel 0 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 1 4 CCACT [3:0] Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 4 0 PULSE_ON_CMP 15 Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH0CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods. TGL_ON_CMP 14 Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. SET_ON_CMP 13 Set on compare repeatedly. Channel function sequence: - Set enabled events when CH0CC.VALUE = CNTR.VALUE. CLR_ON_CMP 12 Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH0CC.VALUE = CNTR.VALUE. SET_ON_0_TGL_ON_CMP 11 Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH0CC.VALUE <= TARGET.VALUE: Duty cycle = CH0CC.VALUE / ( TARGET.VALUE + 1 ). When CH0CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP 10 Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH0CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH0CC.VALUE / TARGET.VALUE ). When CH0CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT 9 Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH0CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. PER_PULSE_WIDTH_MEAS 8 Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH0CCFG.CAPT_SRC relative to the signal edge given by CH0CCFG.EDGE. Set enabled events when CH0CC.VALUE contains signal period and CH0PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH0CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH0CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. PULSE_ON_CMP_DIS 7 Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. TGL_ON_CMP_DIS 6 Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_CMP_DIS 5 Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. CLR_ON_CMP_DIS 4 Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_0_TGL_ON_CMP_DIS 3 Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP_DIS 2 Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT_DIS 1 Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH0CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. DIS 0 Disable channel. 0x0 CH0CCFG 0x84 32 Channel 0 Capture Configuration RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 CAPT_SRC [6:1] Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH0EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function is: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH0EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 1 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 EDGE [0:0] Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH0EVCFG.CCACT. 1 0 RISING 1 Capture CNTR.VALUE at rising edge of CAPT_SRC. FALLING 0 Capture CNTR.VALUE at falling edge of CAPT_SRC. 0x0 CH0PCC 0x88 32 Channel 0 Pipeline Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH0CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. 16 0 0x0 CH0CC 0x8c 32 Channel 0 Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH0EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. 16 0 0x0 CH1EVCFG 0x90 32 Channel 1 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EV3_GEN [7:7] Event 3 enable. 0: Channel 1 does not control event 3. 1: Channel 1 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 1 7 EV2_GEN [6:6] Event 2 enable. 0: Channel 1 does not control event 2. 1: Channel 1 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 1 6 EV1_GEN [5:5] Event 1 enable. 0: Channel 1 does not control event 1. 1: Channel 1 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 1 5 EV0_GEN [4:4] Event 0 enable. 0: Channel 1 does not control event 0. 1: Channel 1 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 1 4 CCACT [3:0] Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 4 0 PULSE_ON_CMP 15 Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH1CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods. TGL_ON_CMP 14 Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. SET_ON_CMP 13 Set on compare repeatedly. Channel function sequence: - Set enabled events when CH1CC.VALUE = CNTR.VALUE. CLR_ON_CMP 12 Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH1CC.VALUE = CNTR.VALUE. SET_ON_0_TGL_ON_CMP 11 Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH1CC.VALUE <= TARGET.VALUE: Duty cycle = CH1CC.VALUE / ( TARGET.VALUE + 1 ). When CH1CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP 10 Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH1CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH1CC.VALUE / TARGET.VALUE ). When CH1CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH1CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT 9 Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH1CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH1CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. PER_PULSE_WIDTH_MEAS 8 Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH1CCFG.CAPT_SRC relative to the signal edge given by CH1CCFG.EDGE. Set enabled events when CH1CC.VALUE contains signal period and CH1PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH1CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH1CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. PULSE_ON_CMP_DIS 7 Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. TGL_ON_CMP_DIS 6 Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_CMP_DIS 5 Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. CLR_ON_CMP_DIS 4 Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_0_TGL_ON_CMP_DIS 3 Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP_DIS 2 Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH1CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT_DIS 1 Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH1CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH1CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. DIS 0 Disable channel. 0x0 CH1CCFG 0x94 32 Channel 1 Capture Configuration RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 CAPT_SRC [6:1] Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH1EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function is: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH1EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 1 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 EDGE [0:0] Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH1EVCFG.CCACT. 1 0 RISING 1 Capture CNTR.VALUE at rising edge of CAPT_SRC. FALLING 0 Capture CNTR.VALUE at falling edge of CAPT_SRC. 0x0 CH1PCC 0x98 32 Channel 1 Pipeline Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH1CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. 16 0 0x0 CH1CC 0x9c 32 Channel 1 Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH1EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. 16 0 0x0 CH2EVCFG 0xa0 32 Channel 2 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EV3_GEN [7:7] Event 3 enable. 0: Channel 2 does not control event 3. 1: Channel 2 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 1 7 EV2_GEN [6:6] Event 2 enable. 0: Channel 2 does not control event 2. 1: Channel 2 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 1 6 EV1_GEN [5:5] Event 1 enable. 0: Channel 2 does not control event 1. 1: Channel 2 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 1 5 EV0_GEN [4:4] Event 0 enable. 0: Channel 2 does not control event 0. 1: Channel 2 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 1 4 CCACT [3:0] Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 4 0 PULSE_ON_CMP 15 Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH2CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods. TGL_ON_CMP 14 Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. SET_ON_CMP 13 Set on compare repeatedly. Channel function sequence: - Set enabled events when CH2CC.VALUE = CNTR.VALUE. CLR_ON_CMP 12 Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH2CC.VALUE = CNTR.VALUE. SET_ON_0_TGL_ON_CMP 11 Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH2CC.VALUE <= TARGET.VALUE: Duty cycle = CH2CC.VALUE / ( TARGET.VALUE + 1 ). When CH2CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP 10 Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH2CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH2CC.VALUE / TARGET.VALUE ). When CH2CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH2CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT 9 Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH2CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH2CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. PER_PULSE_WIDTH_MEAS 8 Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH2CCFG.CAPT_SRC relative to the signal edge given by CH2CCFG.EDGE. Set enabled events when CH2CC.VALUE contains signal period and CH2PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH2CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH2CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. PULSE_ON_CMP_DIS 7 Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. TGL_ON_CMP_DIS 6 Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_CMP_DIS 5 Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. CLR_ON_CMP_DIS 4 Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_0_TGL_ON_CMP_DIS 3 Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP_DIS 2 Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH2CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT_DIS 1 Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH2CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set to SET_ON_CAPT with no event enable. - Configure CH2CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. DIS 0 Disable channel. 0x0 CH2CCFG 0xa4 32 Channel 2 Capture Configuration RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 CAPT_SRC [6:1] Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH2EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function is: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH2EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 1 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 EDGE [0:0] Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH2EVCFG.CCACT. 1 0 RISING 1 Capture CNTR.VALUE at rising edge of CAPT_SRC. FALLING 0 Capture CNTR.VALUE at falling edge of CAPT_SRC. 0x0 CH2PCC 0xa8 32 Channel 2 Pipeline Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH2CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. 16 0 0x0 CH2CC 0xac 32 Channel 2 Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH2EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. 16 0 0x0 CH3EVCFG 0xb0 32 Channel 3 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EV3_GEN [7:7] Event 3 enable. 0: Channel 3 does not control event 3. 1: Channel 3 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 1 7 EV2_GEN [6:6] Event 2 enable. 0: Channel 3 does not control event 2. 1: Channel 3 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 1 6 EV1_GEN [5:5] Event 1 enable. 0: Channel 3 does not control event 1. 1: Channel 3 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 1 5 EV0_GEN [4:4] Event 0 enable. 0: Channel 3 does not control event 0. 1: Channel 3 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 1 4 CCACT [3:0] Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 4 0 PULSE_ON_CMP 15 Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH3CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods. TGL_ON_CMP 14 Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. SET_ON_CMP 13 Set on compare repeatedly. Channel function sequence: - Set enabled events when CH3CC.VALUE = CNTR.VALUE. CLR_ON_CMP 12 Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH3CC.VALUE = CNTR.VALUE. SET_ON_0_TGL_ON_CMP 11 Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH3CC.VALUE <= TARGET.VALUE: Duty cycle = CH3CC.VALUE / ( TARGET.VALUE + 1 ). When CH3CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP 10 Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH3CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH3CC.VALUE / TARGET.VALUE ). When CH3CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT 9 Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH3CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. PER_PULSE_WIDTH_MEAS 8 Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH3CCFG.CAPT_SRC relative to the signal edge given by CH3CCFG.EDGE. Set enabled events when CH3CC.VALUE contains signal period and CH3PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH3CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH3CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. PULSE_ON_CMP_DIS 7 Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. TGL_ON_CMP_DIS 6 Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_CMP_DIS 5 Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. CLR_ON_CMP_DIS 4 Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. SET_ON_0_TGL_ON_CMP_DIS 3 Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0. CLR_ON_0_TGL_ON_CMP_DIS 2 Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0. SET_ON_CAPT_DIS 1 Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH3CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. DIS 0 Disable channel. 0x0 CH3CCFG 0xb4 32 Channel 3 Capture Configuration RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 CAPT_SRC [6:1] Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH3EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH3EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 6 1 NO_EVENT 63 No event. AUX_SMPH_AUTOTAKE_DONE 61 AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE AUX_ADC_FIFO_NOT_EMPTY 60 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY AUX_ADC_FIFO_ALMOST_FULL 59 AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_IRQ 58 AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ AUX_ADC_DONE 57 AUX_EVCTL:EVSTAT3.AUX_ADC_DONE AUX_ISRC_RESET_N 56 AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N AUX_TDC_DONE 55 AUX_EVCTL:EVSTAT3.AUX_TDC_DONE AUX_TIMER0_EV 54 AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV AUX_TIMER1_EV 53 AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV AUX_TIMER2_EV3 51 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 AUX_TIMER2_EV2 50 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 AUX_TIMER2_EV1 49 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 AUX_TIMER2_EV0 48 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 AUX_COMPB 47 AUX_EVCTL:EVSTAT2.AUX_COMPB AUX_COMPA 46 AUX_EVCTL:EVSTAT2.AUX_COMPA MCU_OBSMUX1 45 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 MCU_OBSMUX0 44 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 MCU_EV 43 AUX_EVCTL:EVSTAT2.MCU_EV ACLK_REF 42 AUX_EVCTL:EVSTAT2.ACLK_REF VDDR_RECHARGE 41 AUX_EVCTL:EVSTAT2.VDDR_RECHARGE MCU_ACTIVE 40 AUX_EVCTL:EVSTAT2.MCU_ACTIVE PWR_DWN 39 AUX_EVCTL:EVSTAT2.PWR_DWN SCLK_LF 38 AUX_EVCTL:EVSTAT2.SCLK_LF AON_BATMON_TEMP_UPD 37 AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD AON_BATMON_BAT_UPD 36 AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD AON_RTC_4KHZ 35 AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ AON_RTC_CH2_DLY 34 AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY AON_RTC_CH2 33 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 MANUAL_EV 32 AUX_EVCTL:EVSTAT2.MANUAL_EV AUXIO31 31 AUX_EVCTL:EVSTAT1.AUXIO31 AUXIO30 30 AUX_EVCTL:EVSTAT1.AUXIO30 AUXIO29 29 AUX_EVCTL:EVSTAT1.AUXIO29 AUXIO28 28 AUX_EVCTL:EVSTAT1.AUXIO28 AUXIO27 27 AUX_EVCTL:EVSTAT1.AUXIO27 AUXIO26 26 AUX_EVCTL:EVSTAT1.AUXIO26 AUXIO25 25 AUX_EVCTL:EVSTAT1.AUXIO25 AUXIO24 24 AUX_EVCTL:EVSTAT1.AUXIO24 AUXIO23 23 AUX_EVCTL:EVSTAT1.AUXIO23 AUXIO22 22 AUX_EVCTL:EVSTAT1.AUXIO22 AUXIO21 21 AUX_EVCTL:EVSTAT1.AUXIO21 AUXIO20 20 AUX_EVCTL:EVSTAT1.AUXIO20 AUXIO19 19 AUX_EVCTL:EVSTAT1.AUXIO19 AUXIO18 18 AUX_EVCTL:EVSTAT1.AUXIO18 AUXIO17 17 AUX_EVCTL:EVSTAT1.AUXIO17 AUXIO16 16 AUX_EVCTL:EVSTAT1.AUXIO16 AUXIO15 15 AUX_EVCTL:EVSTAT0.AUXIO15 AUXIO14 14 AUX_EVCTL:EVSTAT0.AUXIO14 AUXIO13 13 AUX_EVCTL:EVSTAT0.AUXIO13 AUXIO12 12 AUX_EVCTL:EVSTAT0.AUXIO12 AUXIO11 11 AUX_EVCTL:EVSTAT0.AUXIO11 AUXIO10 10 AUX_EVCTL:EVSTAT0.AUXIO10 AUXIO9 9 AUX_EVCTL:EVSTAT0.AUXIO9 AUXIO8 8 AUX_EVCTL:EVSTAT0.AUXIO8 AUXIO7 7 AUX_EVCTL:EVSTAT0.AUXIO7 AUXIO6 6 AUX_EVCTL:EVSTAT0.AUXIO6 AUXIO5 5 AUX_EVCTL:EVSTAT0.AUXIO5 AUXIO4 4 AUX_EVCTL:EVSTAT0.AUXIO4 AUXIO3 3 AUX_EVCTL:EVSTAT0.AUXIO3 AUXIO2 2 AUX_EVCTL:EVSTAT0.AUXIO2 AUXIO1 1 AUX_EVCTL:EVSTAT0.AUXIO1 AUXIO0 0 AUX_EVCTL:EVSTAT0.AUXIO0 EDGE [0:0] Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH3EVCFG.CCACT. 1 0 RISING 1 Capture CNTR.VALUE at rising edge of CAPT_SRC. FALLING 0 Capture CNTR.VALUE at falling edge of CAPT_SRC. 0x0 CH3PCC 0xb8 32 Channel 3 Pipeline Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH3CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. 16 0 0x0 CH3CC 0xbc 32 Channel 3 Capture Compare RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH3EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. 16 0 0x0 CCFG 0x50003000 0 0x2000 registers Customer configuration area (CCFG) RESERVED_0 0x0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0xFFFFFFFF EXT_LF_CLK 0x1fa8 32 Extern LF clock configuration DIO [31:24] Unsigned integer, selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO will be marked as reserved by the pin driver (TI-RTOS environment) and hence not selectable for other usage. 8 24 RTC_INCREMENT [23:0] Unsigned integer, defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) 24 0 0xFFFFFFFF MODE_CONF_1 0x1fac 32 Mode Configuration 1 RESERVED [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 ALT_DCDC_VMIN [23:20] Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Voltage = (28 + ALT_DCDC_VMIN) / 16. 0: 1.75V 1: 1.8125V ... 14: 2.625V 15: 2.6875V NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). 4 20 ALT_DCDC_DITHER_EN [19:19] Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 0: Dither disable 1: Dither enable 1 19 ALT_DCDC_IPEAK [18:16] Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external inductor! Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : 0: 31mA (min) ... 4: 47mA ... 7: 59mA (max) 3 16 DELTA_IBIAS_INIT [15:12] Signed delta value for IBIAS_INIT. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT 4 12 DELTA_IBIAS_OFFSET [11:8] Signed delta value for IBIAS_OFFSET. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET 4 8 XOSC_MAX_START [7:0] Unsigned value of maximum XOSC startup time (worst case) in units of 100us. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 8 0 0xFFFFFFFF SIZE_AND_DIS_FLAGS 0x1fb0 32 CCFG Size and Disable Flags SIZE_OF_CCFG [31:16] Total size of CCFG in bytes. 16 16 DISABLE_FLAGS [15:4] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 12 4 DIS_TCXO [3:3] Disable TCXO. 0: TCXO functionality enabled. 1: TCXO functionality disabled. Note: An external TCXO is required if DIS_TCXO = 0. 1 3 DIS_GPRAM [2:2] Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 0: GPRAM is enabled and hence CACHE disabled. 1: GPRAM is disabled and instead CACHE is enabled (default). Notes: - Disabling CACHE will reduce CPU execution speed (up to 60%). - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled. See: VIMS:CTL.MODE 1 2 DIS_ALT_DCDC_SETTING [1:1] Disable alternate DC/DC settings. 0: Enable alternate DC/DC settings. 1: Disable alternate DC/DC settings. See: MODE_CONF_1.ALT_DCDC_VMIN MODE_CONF_1.ALT_DCDC_DITHER_EN MODE_CONF_1.ALT_DCDC_IPEAK NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). 1 1 DIS_XOSC_OVR [0:0] Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START 1 0 0xFFFFFFFF MODE_CONF 0x1fb4 32 Mode Configuration 0 VDDR_TRIM_SLEEP_DELTA [31:28] Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. 0x8 (-8) : Delta = -7 ... 0xF (-1) : Delta = 0 0x0 (0) : Delta = +1 ... 0x7 (7) : Delta = +8 4 28 DCDC_RECHARGE [27:27] DC/DC during recharge in powerdown. 0: Use the DC/DC during recharge in powerdown. 1: Do not use the DC/DC during recharge in powerdown (default). NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). 1 27 DCDC_ACTIVE [26:26] DC/DC in active mode. 0: Use the DC/DC during active mode. 1: Do not use the DC/DC during active mode (default). NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). 1 26 VDDR_EXT_LOAD [25:25] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 1 25 VDDS_BOD_LEVEL [24:24] VDDS BOD level. 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum PA output power on CC13xx). 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). 1 24 SCLK_LF_OPTION [23:22] Select source for SCLK_LF. 2 22 RCOSC_LF 3 Low frequency RCOSC (default) XOSC_LF 2 32.768kHz low frequency XOSC EXTERNAL_LF 1 External low frequency clock on DIO defined by EXT_LF_CLK.DIO. The RTC tick speed AON_RTC:SUBSECINC is updated to EXT_LF_CLK.RTC_INCREMENT (done in the trimDevice() xxWare boot function). External clock must always be running when the chip is in standby for VDDR recharge timing. XOSC_HF_DLF 0 31.25kHz clock derived from 24MHz XOSC (dividing by 768 in HW). The RTC tick speed [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, corresponding to a 31.25kHz clock (done in the trimDevice() xxWare boot function). Standby power mode is not supported when using this clock source. VDDR_TRIM_SLEEP_TC [21:21] 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time standby mode is entered. This improves low-temperature RCOSC_LF frequency stability in standby mode. When temperature compensation is performed, the delta is calculates this way: Delta = max (delta, min(8, floor(62-temp)/8)) Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C. 1 21 RTC_COMP [20:20] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 1 20 XOSC_FREQ [19:18] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 2 18 24M 3 24 MHz XOSC_HF 48M 2 48 MHz XOSC_HF HPOSC 1 HPOSC XOSC_CAP_MOD [17:17] Enable modification (delta) to XOSC cap-array. Value specified in XOSC_CAPARRAY_DELTA. 0: Apply cap-array delta 1: Do not apply cap-array delta (default) 1 17 HF_COMP [16:16] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 1 16 XOSC_CAPARRAY_DELTA [15:8] Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. Enabled by XOSC_CAP_MOD. 8 8 VDDR_CAP [7:0] Unsigned 8-bit integer, representing the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby. NOTE! If using the following functions this field must be configured (used by TI RTOS): SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() 8 0 0xFFFFFFFF VOLT_LOAD_0 0x1fb8 32 Voltage Load 0 Enabled by MODE_CONF.VDDR_EXT_LOAD. VDDR_EXT_TP45 [31:24] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 24 VDDR_EXT_TP25 [23:16] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 16 VDDR_EXT_TP5 [15:8] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 8 VDDR_EXT_TM15 [7:0] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 0 0xFFFFFFFF VOLT_LOAD_1 0x1fbc 32 Voltage Load 1 Enabled by MODE_CONF.VDDR_EXT_LOAD. VDDR_EXT_TP125 [31:24] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 24 VDDR_EXT_TP105 [23:16] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 16 VDDR_EXT_TP85 [15:8] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 8 VDDR_EXT_TP65 [7:0] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 0 0xFFFFFFFF RTC_OFFSET 0x1fc0 32 Real Time Clock Offset Enabled by MODE_CONF.RTC_COMP. RTC_COMP_P0 [31:16] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 16 16 RTC_COMP_P1 [15:8] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 8 RTC_COMP_P2 [7:0] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 0 0xFFFFFFFF FREQ_OFFSET 0x1fc4 32 Frequency Offset HF_COMP_P0 [31:16] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 16 16 HF_COMP_P1 [15:8] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 8 HF_COMP_P2 [7:0] Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 8 0 0xFFFFFFFF IEEE_MAC_0 0x1fc8 32 IEEE MAC Address 0 ADDR [31:0] Bits[31:0] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. 32 0 0xFFFFFFFF IEEE_MAC_1 0x1fcc 32 IEEE MAC Address 1 ADDR [31:0] Bits[63:32] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. 32 0 0xFFFFFFFF IEEE_BLE_0 0x1fd0 32 IEEE BLE Address 0 ADDR [31:0] Bits[31:0] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. 32 0 0xFFFFFFFF IEEE_BLE_1 0x1fd4 32 IEEE BLE Address 1 ADDR [31:0] Bits[63:32] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. 32 0 0xFFFFFFFF BL_CONFIG 0x1fd8 32 Bootloader Configuration Configures the functionality of the ROM boot loader. If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image is present in flash. BOOTLOADER_ENABLE [31:24] Bootloader enable. Boot loader can be accessed if IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and conditions for boot loader backdoor are met). 0xC5: Boot loader is enabled. Any other value: Boot loader is disabled. 8 24 RESERVED [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 BL_LEVEL [16:16] Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field. 0: Active low. 1: Active high. 1 16 BL_PIN_NUMBER [15:8] DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field. 8 8 BL_ENABLE [7:0] Enables the boot loader backdoor. 0xC5: Boot loader backdoor is enabled. Any other value: Boot loader backdoor is disabled. NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader backdoor is enabled. 8 0 0xC5FFFFFF ERASE_CONF 0x1fdc 32 Erase Configuration RESERVED2 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 CHIP_ERASE_DIS_N [8:8] Chip erase. This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD. A successful chip erase operation will force the content of the flash main bank back to the state as it was when delivered by TI. 0: Disable. Any chip erase request detected during boot will be ignored. 1: Enable. Any chip erase request detected during boot will be performed by the boot FW. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 BANK_ERASE_DIS_N [0:0] Bank erase. This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE). A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration bits in CCFG. 0: Disable the boot loader bank erase function. 1: Enable the boot loader bank erase function. 1 0 0xFFFFFFFF CCFG_TI_OPTIONS 0x1fe0 32 TI Options RESERVED [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TI_FA_ENABLE [7:0] TI Failure Analysis. 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) option with the unlock code. All other values: Disable the functionality of unlocking the TI FA option with the unlock code. 8 0 0xFFFFFFC5 CCFG_TAP_DAP_0 0x1fe4 32 Test Access Points Enable 0 RESERVED [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 CPU_DAP_ENABLE [23:16] Enable CPU DAP. 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM boot FW. Any other value: Main CPU DAP access will remain disabled out of power-up/system-reset. 8 16 PWRPROF_TAP_ENABLE [15:8] Enable PWRPROF TAP. 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PWRPROF TAP access will remain disabled out of power-up/system-reset. 8 8 TEST_TAP_ENABLE [7:0] Enable Test TAP. 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: TEST TAP access will remain disabled out of power-up/system-reset. 8 0 0xFFC5C5C5 CCFG_TAP_DAP_1 0x1fe8 32 Test Access Points Enable 1 RESERVED [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 PBIST2_TAP_ENABLE [23:16] Enable PBIST2 TAP. 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST2 TAP access will remain disabled out of power-up/system-reset. 8 16 PBIST1_TAP_ENABLE [15:8] Enable PBIST1 TAP. 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST1 TAP access will remain disabled out of power-up/system-reset. 8 8 AON_TAP_ENABLE [7:0] Enable AON TAP 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: AON TAP access will remain disabled out of power-up/system-reset. 8 0 0xFFC5C5C5 IMAGE_VALID_CONF 0x1fec 32 Image Valid IMAGE_VALID [31:0] This field must have the address value of the start of the flash vector table in order to enable the boot FW in ROM to transfer control to a flash image. Any illegal vector table start address value will force the boot FW in ROM to transfer control to the serial boot loader in ROM. 32 0 0xFFFFFFFF CCFG_PROT_31_0 0x1ff0 32 Protect Sectors 0-31 Each bit write protects one 8KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. WRT_PROT_SEC_31 [31:31] 0: Sector protected 1 31 WRT_PROT_SEC_30 [30:30] 0: Sector protected 1 30 WRT_PROT_SEC_29 [29:29] 0: Sector protected 1 29 WRT_PROT_SEC_28 [28:28] 0: Sector protected 1 28 WRT_PROT_SEC_27 [27:27] 0: Sector protected 1 27 WRT_PROT_SEC_26 [26:26] 0: Sector protected 1 26 WRT_PROT_SEC_25 [25:25] 0: Sector protected 1 25 WRT_PROT_SEC_24 [24:24] 0: Sector protected 1 24 WRT_PROT_SEC_23 [23:23] 0: Sector protected 1 23 WRT_PROT_SEC_22 [22:22] 0: Sector protected 1 22 WRT_PROT_SEC_21 [21:21] 0: Sector protected 1 21 WRT_PROT_SEC_20 [20:20] 0: Sector protected 1 20 WRT_PROT_SEC_19 [19:19] 0: Sector protected 1 19 WRT_PROT_SEC_18 [18:18] 0: Sector protected 1 18 WRT_PROT_SEC_17 [17:17] 0: Sector protected 1 17 WRT_PROT_SEC_16 [16:16] 0: Sector protected 1 16 WRT_PROT_SEC_15 [15:15] 0: Sector protected 1 15 WRT_PROT_SEC_14 [14:14] 0: Sector protected 1 14 WRT_PROT_SEC_13 [13:13] 0: Sector protected 1 13 WRT_PROT_SEC_12 [12:12] 0: Sector protected 1 12 WRT_PROT_SEC_11 [11:11] 0: Sector protected 1 11 WRT_PROT_SEC_10 [10:10] 0: Sector protected 1 10 WRT_PROT_SEC_9 [9:9] 0: Sector protected 1 9 WRT_PROT_SEC_8 [8:8] 0: Sector protected 1 8 WRT_PROT_SEC_7 [7:7] 0: Sector protected 1 7 WRT_PROT_SEC_6 [6:6] 0: Sector protected 1 6 WRT_PROT_SEC_5 [5:5] 0: Sector protected 1 5 WRT_PROT_SEC_4 [4:4] 0: Sector protected 1 4 WRT_PROT_SEC_3 [3:3] 0: Sector protected 1 3 WRT_PROT_SEC_2 [2:2] 0: Sector protected 1 2 WRT_PROT_SEC_1 [1:1] 0: Sector protected 1 1 WRT_PROT_SEC_0 [0:0] 0: Sector protected 1 0 0xFFFFFFFF CCFG_PROT_63_32 0x1ff4 32 Protect Sectors 32-63 Each bit write protects one 8KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. WRT_PROT_SEC_63 [31:31] 0: Sector protected 1 31 WRT_PROT_SEC_62 [30:30] 0: Sector protected 1 30 WRT_PROT_SEC_61 [29:29] 0: Sector protected 1 29 WRT_PROT_SEC_60 [28:28] 0: Sector protected 1 28 WRT_PROT_SEC_59 [27:27] 0: Sector protected 1 27 WRT_PROT_SEC_58 [26:26] 0: Sector protected 1 26 WRT_PROT_SEC_57 [25:25] 0: Sector protected 1 25 WRT_PROT_SEC_56 [24:24] 0: Sector protected 1 24 WRT_PROT_SEC_55 [23:23] 0: Sector protected 1 23 WRT_PROT_SEC_54 [22:22] 0: Sector protected 1 22 WRT_PROT_SEC_53 [21:21] 0: Sector protected 1 21 WRT_PROT_SEC_52 [20:20] 0: Sector protected 1 20 WRT_PROT_SEC_51 [19:19] 0: Sector protected 1 19 WRT_PROT_SEC_50 [18:18] 0: Sector protected 1 18 WRT_PROT_SEC_49 [17:17] 0: Sector protected 1 17 WRT_PROT_SEC_48 [16:16] 0: Sector protected 1 16 WRT_PROT_SEC_47 [15:15] 0: Sector protected 1 15 WRT_PROT_SEC_46 [14:14] 0: Sector protected 1 14 WRT_PROT_SEC_45 [13:13] 0: Sector protected 1 13 WRT_PROT_SEC_44 [12:12] 0: Sector protected 1 12 WRT_PROT_SEC_43 [11:11] 0: Sector protected 1 11 WRT_PROT_SEC_42 [10:10] 0: Sector protected 1 10 WRT_PROT_SEC_41 [9:9] 0: Sector protected 1 9 WRT_PROT_SEC_40 [8:8] 0: Sector protected 1 8 WRT_PROT_SEC_39 [7:7] 0: Sector protected 1 7 WRT_PROT_SEC_38 [6:6] 0: Sector protected 1 6 WRT_PROT_SEC_37 [5:5] 0: Sector protected 1 5 WRT_PROT_SEC_36 [4:4] 0: Sector protected 1 4 WRT_PROT_SEC_35 [3:3] 0: Sector protected 1 3 WRT_PROT_SEC_34 [2:2] 0: Sector protected 1 2 WRT_PROT_SEC_33 [1:1] 0: Sector protected 1 1 WRT_PROT_SEC_32 [0:0] 0: Sector protected 1 0 0xFFFFFFFF CCFG_PROT_95_64 0x1ff8 32 Protect Sectors 64-95 Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use. WRT_PROT_SEC_95 [31:31] 0: Sector protected 1 31 WRT_PROT_SEC_94 [30:30] 0: Sector protected 1 30 WRT_PROT_SEC_93 [29:29] 0: Sector protected 1 29 WRT_PROT_SEC_92 [28:28] 0: Sector protected 1 28 WRT_PROT_SEC_91 [27:27] 0: Sector protected 1 27 WRT_PROT_SEC_90 [26:26] 0: Sector protected 1 26 WRT_PROT_SEC_89 [25:25] 0: Sector protected 1 25 WRT_PROT_SEC_88 [24:24] 0: Sector protected 1 24 WRT_PROT_SEC_87 [23:23] 0: Sector protected 1 23 WRT_PROT_SEC_86 [22:22] 0: Sector protected 1 22 WRT_PROT_SEC_85 [21:21] 0: Sector protected 1 21 WRT_PROT_SEC_84 [20:20] 0: Sector protected 1 20 WRT_PROT_SEC_83 [19:19] 0: Sector protected 1 19 WRT_PROT_SEC_82 [18:18] 0: Sector protected 1 18 WRT_PROT_SEC_81 [17:17] 0: Sector protected 1 17 WRT_PROT_SEC_80 [16:16] 0: Sector protected 1 16 WRT_PROT_SEC_79 [15:15] 0: Sector protected 1 15 WRT_PROT_SEC_78 [14:14] 0: Sector protected 1 14 WRT_PROT_SEC_77 [13:13] 0: Sector protected 1 13 WRT_PROT_SEC_76 [12:12] 0: Sector protected 1 12 WRT_PROT_SEC_75 [11:11] 0: Sector protected 1 11 WRT_PROT_SEC_74 [10:10] 0: Sector protected 1 10 WRT_PROT_SEC_73 [9:9] 0: Sector protected 1 9 WRT_PROT_SEC_72 [8:8] 0: Sector protected 1 8 WRT_PROT_SEC_71 [7:7] 0: Sector protected 1 7 WRT_PROT_SEC_70 [6:6] 0: Sector protected 1 6 WRT_PROT_SEC_69 [5:5] 0: Sector protected 1 5 WRT_PROT_SEC_68 [4:4] 0: Sector protected 1 4 WRT_PROT_SEC_67 [3:3] 0: Sector protected 1 3 WRT_PROT_SEC_66 [2:2] 0: Sector protected 1 2 WRT_PROT_SEC_65 [1:1] 0: Sector protected 1 1 WRT_PROT_SEC_64 [0:0] 0: Sector protected 1 0 0xFFFFFFFF CCFG_PROT_127_96 0x1ffc 32 Protect Sectors 96-127 Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use. WRT_PROT_SEC_127 [31:31] 0: Sector protected 1 31 WRT_PROT_SEC_126 [30:30] 0: Sector protected 1 30 WRT_PROT_SEC_125 [29:29] 0: Sector protected 1 29 WRT_PROT_SEC_124 [28:28] 0: Sector protected 1 28 WRT_PROT_SEC_123 [27:27] 0: Sector protected 1 27 WRT_PROT_SEC_122 [26:26] 0: Sector protected 1 26 WRT_PROT_SEC_121 [25:25] 0: Sector protected 1 25 WRT_PROT_SEC_120 [24:24] 0: Sector protected 1 24 WRT_PROT_SEC_119 [23:23] 0: Sector protected 1 23 WRT_PROT_SEC_118 [22:22] 0: Sector protected 1 22 WRT_PROT_SEC_117 [21:21] 0: Sector protected 1 21 WRT_PROT_SEC_116 [20:20] 0: Sector protected 1 20 WRT_PROT_SEC_115 [19:19] 0: Sector protected 1 19 WRT_PROT_SEC_114 [18:18] 0: Sector protected 1 18 WRT_PROT_SEC_113 [17:17] 0: Sector protected 1 17 WRT_PROT_SEC_112 [16:16] 0: Sector protected 1 16 WRT_PROT_SEC_111 [15:15] 0: Sector protected 1 15 WRT_PROT_SEC_110 [14:14] 0: Sector protected 1 14 WRT_PROT_SEC_109 [13:13] 0: Sector protected 1 13 WRT_PROT_SEC_108 [12:12] 0: Sector protected 1 12 WRT_PROT_SEC_107 [11:11] 0: Sector protected 1 11 WRT_PROT_SEC_106 [10:10] 0: Sector protected 1 10 WRT_PROT_SEC_105 [9:9] 0: Sector protected 1 9 WRT_PROT_SEC_104 [8:8] 0: Sector protected 1 8 WRT_PROT_SEC_103 [7:7] 0: Sector protected 1 7 WRT_PROT_SEC_102 [6:6] 0: Sector protected 1 6 WRT_PROT_SEC_101 [5:5] 0: Sector protected 1 5 WRT_PROT_SEC_100 [4:4] 0: Sector protected 1 4 WRT_PROT_SEC_99 [3:3] 0: Sector protected 1 3 WRT_PROT_SEC_98 [2:2] 0: Sector protected 1 2 WRT_PROT_SEC_97 [1:1] 0: Sector protected 1 1 WRT_PROT_SEC_96 [0:0] 0: Sector protected 1 0 0xFFFFFFFF CPU_DWT 0xE0001000 0 0x1000 registers Cortex-M's Data watchpoint and Trace (DWT) CTRL 0x0 32 Control Use the DWT Control Register to enable the DWT unit. RESERVED26 [31:26] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 26 NOCYCCNT [25:25] When set, CYCCNT is not supported. 1 25 NOPRFCNT [24:24] When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. 1 24 RESERVED23 [23:23] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 23 CYCEVTENA [22:22] Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. This event is only emitted if PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. 0: Cycle count events disabled 1: Cycle count events enabled 1 22 FOLDEVTENA [21:21] Enables Folded instruction count event. Emits an event when FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. 0: Folded instruction count events disabled. 1: Folded instruction count events enabled. 1 21 LSUEVTENA [20:20] Enables LSU count event. Emits an event when LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. 0: LSU count events disabled. 1: LSU count events enabled. 1 20 SLEEPEVTENA [19:19] Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 cycles that the processor is sleeping). 0: Sleep count events disabled. 1: Sleep count events enabled. 1 19 EXCEVTENA [18:18] Enables Interrupt overhead event. Emits an event when EXCCNT overflows (every 256 cycles of interrupt overhead). 0x0: Interrupt overhead event disabled. 0x1: Interrupt overhead event enabled. 1 18 CPIEVTENA [17:17] Enables CPI count event. Emits an event when CPICNT overflows (every 256 cycles of multi-cycle instructions). 0: CPI counter events disabled. 1: CPI counter events enabled. 1 17 EXCTRCENA [16:16] Enables Interrupt event tracing. 0: Interrupt event trace disabled. 1: Interrupt event trace enabled. 1 16 RESERVED13 [15:13] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 13 PCSAMPLEENA [12:12] Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling event disabled. 1: Sampling event enabled. 1 12 SYNCTAP [11:10] Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA must also be enabled for this feature. Synchronization packets (if enabled) are generated on tap transitions (0 to1 or 1 to 0). 2 10 BIT28 3 Tap at bit 28 of CYCCNT BIT26 2 Tap at bit 26 of CYCCNT BIT24 1 Tap at bit 24 of CYCCNT DIS 0 Disabled. No synchronization packets CYCTAP [9:9] Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or cycle count event (see details in CYCEVTENA). 1 9 BIT10 1 Selects bit [10] to tap BIT6 0 Selects bit [6] to tap POSTCNT [8:5] Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the value from POSTPRESET. 4 5 POSTPRESET [4:1] Reload value for post-scalar counter POSTCNT. When 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, it forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change. 4 1 CYCCNTENA [0:0] Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. 1 0 0x40000000 CYCCNT 0x4 32 Current PC Sampler Cycle Count This register is used to count the number of core cycles. This counter can measure elapsed execution time. This is a free-running counter (this counter will not advance in power modes where free-running clock to CPU stops). The counter has three functions: 1: When CTRL.PCSAMPLEENA = 1, the PC is sampled and emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. 2: When CTRL.CYCEVTENA = 1 , (and CTRL.PCSAMPLEENA = 0), an event is emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. 3: Applications and debuggers can use the counter to measure elapsed execution time. By subtracting a start and an end time, an application can measure time between in-core clocks (other than when Halted in debug). This is valid to 2^32 core clock cycles (for example, almost 89.5 seconds at 48MHz). CYCCNT [31:0] Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. The cycle counter is a free running counter, counting upwards (this counter will not advance in power modes where free-running clock to CPU stops). It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. 32 0 0x0 CPICNT 0x8 32 CPI Count This register is used to count the total number of instruction cycles beyond the first cycle. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 CPICNT [7:0] Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by LSUCNT. This counter also increments on all instruction fetch stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter overflows. This counter initializes to 0 when it is enabled using CTRL.CPIEVTENA. 8 0 0x0 EXCCNT 0xc 32 Exception Overhead Count This register is used to count the total cycles spent in interrupt processing. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 EXCCNT [7:0] Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. 8 0 0x0 SLEEPCNT 0x10 32 Sleep Count This register is used to count the total number of cycles during which the processor is sleeping. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SLEEPCNT [7:0] Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using CPU's free-running clock. In some power modes the free-running clock to CPU is gated to minimize power consumption. This means that the sleep counter will be invalid in these power modes. 8 0 0x0 LSUCNT 0x14 32 LSU Count This register is used to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 LSUCNT [7:0] LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (i.e. takes four cycles to execute), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. 8 0 0x0 FOLDCNT 0x18 32 Fold Count This register is used to count the total number of folded instructions. The counter increments on each instruction which takes 0 cycles. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 FOLDCNT [7:0] This counts the total number folded instructions. This counter initializes to 0 when it is enabled using CTRL.FOLDEVTENA. 8 0 0x0 PCSR 0x1c 32 Program Counter Sample This register is used to enable coarse-grained software profiling using a debug agent, without changing the currently executing code. If the core is not in debug state, the value returned is the instruction address of a recently executed instruction. If the core is in debug state, the value returned is 0xFFFFFFFF. EIASAMPLE [31:0] Execution instruction address sample, or 0xFFFFFFFF if the core is halted. 32 0 0x0 COMP0 0x20 32 Comparator 0 This register is used to write the reference value for comparator 0. COMP [31:0] Reference value to compare against PC or the data address as given by FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler Counter (CYCCNT). 32 0 0x0 MASK0 0x24 32 Mask 0 Use the DWT Mask Registers 0 to apply a mask to data addresses when matching against COMP0. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 MASK [3:0] Mask on data address when matching against COMP0. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP0. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be within the word. 4 0 0x0 FUNCTION0 0x28 32 Function 0 Use the DWT Function Registers 0 to control the operation of the comparator 0. This comparator can: 1. Match against either the PC or the data address. This is controlled by CYCMATCH. This function is only available for comparator 0 (COMP0). 2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION. RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 MATCHED [24:24] This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 1 24 RESERVED8 [23:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 8 CYCMATCH [7:7] This bit is only available in comparator 0. When set, COMP0 will compare against the cycle counter (CYCCNT). 1 7 RESERVED6 [6:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 6 EMITRANGE [5:5] Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 1 5 RESERVED4 [4:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 4 FUNCTION [3:0] Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 4 0 0x0 COMP1 0x30 32 Comparator 1 This register is used to write the reference value for comparator 1. COMP [31:0] Reference value to compare against PC or the data address as given by FUNCTION1. Comparator 1 can also compare data values. So this register can contain reference values for data matching. 32 0 0x0 MASK1 0x34 32 Mask 1 Use the DWT Mask Registers 1 to apply a mask to data addresses when matching against COMP1. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 MASK [3:0] Mask on data address when matching against COMP1. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP1. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word. 4 0 0x0 FUNCTION1 0x38 32 Function 1 Use the DWT Function Registers 1 to control the operation of the comparator 1. This comparator can: 1. Perform data value comparisons if associated address comparators have performed an address match. This function is only available for comparator 1 (COMP1). 2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION. RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 MATCHED [24:24] This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 1 24 RESERVED20 [23:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 20 DATAVADDR1 [19:16] Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 4 16 DATAVADDR0 [15:12] Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 4 12 DATAVSIZE [11:10] Defines the size of the data in the COMP1 register that is to be matched: 0x0: Byte 0x1: Halfword 0x2: Word 0x3: Unpredictable. 2 10 LNK1ENA [9:9] Read only bit-field only supported in comparator 1. 0: DATAVADDR1 not supported 1: DATAVADDR1 supported (enabled) 1 9 DATAVMATCH [8:8] Data match feature: 0: Perform address comparison 1: Perform data value compare. The comparators given by DATAVADDR0 and DATAVADDR1 provide the address for the data comparison. The FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. This bit is only available in comparator 1. 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 EMITRANGE [5:5] Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 1 5 RESERVED4 [4:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 4 FUNCTION [3:0] Function settings: 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading DATAVMATCH. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 4 0 0x200 COMP2 0x40 32 Comparator 2 This register is used to write the reference value for comparator 2. COMP [31:0] Reference value to compare against PC or the data address as given by FUNCTION2. 32 0 0x0 MASK2 0x44 32 Mask 2 Use the DWT Mask Registers 2 to apply a mask to data addresses when matching against COMP2. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 MASK [3:0] Mask on data address when matching against COMP2. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP2. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be within the word. 4 0 0x0 FUNCTION2 0x48 32 Function 2 Use the DWT Function Registers 2 to control the operation of the comparator 2. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION. RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 MATCHED [24:24] This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 1 24 RESERVED6 [23:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 6 EMITRANGE [5:5] Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 1 5 RESERVED4 [4:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 4 FUNCTION [3:0] Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 4 0 0x0 COMP3 0x50 32 Comparator 3 This register is used to write the reference value for comparator 3. COMP [31:0] Reference value to compare against PC or the data address as given by FUNCTION3. 32 0 0x0 MASK3 0x54 32 Mask 3 Use the DWT Mask Registers 3 to apply a mask to data addresses when matching against COMP3. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 MASK [3:0] Mask on data address when matching against COMP3. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP3. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be within the word. 4 0 0x0 FUNCTION3 0x58 32 Function 3 Use the DWT Function Registers 3 to control the operation of the comparator 3. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION. RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 MATCHED [24:24] This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 1 24 RESERVED6 [23:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 6 EMITRANGE [5:5] Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 1 5 RESERVED4 [4:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 4 FUNCTION [3:0] Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 4 0 0x0 CPU_FPB 0xE0002000 0 0x1000 registers Cortex-M's Flash Patch and Breakpoint (FPB) CTRL 0x0 32 Control This register is used to enable the flash patch block. RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 NUM_CODE2 [13:12] Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE1. This read only field contains 3'b000 to indicate 0 banks for Cortex-M processor. 2 12 NUM_LIT [11:8] Number of literal slots field. 0x0: No literal slots 0x2: Two literal slots 4 8 NUM_CODE1 [7:4] Number of code slots field. 0x0: No code slots 0x2: Two code slots 0x6: Six code slots 4 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 KEY [1:1] Key field. In order to write to this register, this bit-field must be written to '1'. This bit always reads 0. 1 1 ENABLE [0:0] Flash patch unit enable bit 0x0: Flash patch unit disabled 0x1: Flash patch unit enabled 1 0 0x260 REMAP 0x4 32 Remap This register provides the remap base address location where a matched addresses are remapped. The three most significant bits and the five least significant bits of the remap base address are hard-coded to 3'b001 and 5'b00000 respectively. The remap base address must be in system space and is it required to be 8-word aligned, with one word allocated to each of the eight FPB comparators. RESERVED29 [31:29] This field always reads 3'b001. Writing to this field is ignored. 3 29 REMAP [28:5] Remap base address field. 24 5 RESERVED0 [4:0] This field always reads 0. Writing to this field is ignored. 5 0 0x20000000 COMP0 0x8 32 Comparator 0 REPLACE [31:30] This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 0. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 0 disabled 0x1: Compare and remap for comparator 0 enabled 1 0 0x0 COMP1 0xc 32 Comparator 1 REPLACE [31:30] This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 1. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 1 disabled 0x1: Compare and remap for comparator 1 enabled 1 0 0x0 COMP2 0x10 32 Comparator 2 REPLACE [31:30] This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 2. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 2 disabled 0x1: Compare and remap for comparator 2 enabled 1 0 0x0 COMP3 0x14 32 Comparator 3 REPLACE [31:30] This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 3. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 3 disabled 0x1: Compare and remap for comparator 3 enabled 1 0 0x0 COMP4 0x18 32 Comparator 4 REPLACE [31:30] This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 4. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 4 disabled 0x1: Compare and remap for comparator 4 enabled 1 0 0x0 COMP5 0x1c 32 Comparator 5 REPLACE [31:30] This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 5. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 5 disabled 0x1: Compare and remap for comparator 5 enabled 1 0 0x0 COMP6 0x20 32 Comparator 6 REPLACE [31:30] This selects what happens when the COMP address is matched. Comparator 6 is a literal comparator and the only supported setting is 0x0. Other settings will be ignored. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 6. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 6 disabled 0x1: Compare and remap for comparator 6 enabled 1 0 0x0 COMP7 0x24 32 Comparator 7 REPLACE [31:30] This selects what happens when the COMP address is matched. Comparator 7 is a literal comparator and the only supported setting is 0x0. Other settings will be ignored. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. 2 30 RESERVED29 [29:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 29 COMP [28:2] Comparison address. 27 2 RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 ENABLE [0:0] Compare and remap enable comparator 7. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 7 disabled 0x1: Compare and remap for comparator 7 enabled 1 0 0x0 CPU_ITM 0xE0000000 0 0x1000 registers Cortex-M's Instrumentation Trace Macrocell (ITM) STIM0 0x0 32 Stimulus Port 0 STIM0 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM1 0x4 32 Stimulus Port 1 STIM1 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM2 0x8 32 Stimulus Port 2 STIM2 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM3 0xc 32 Stimulus Port 3 STIM3 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM4 0x10 32 Stimulus Port 4 STIM4 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM5 0x14 32 Stimulus Port 5 STIM5 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM6 0x18 32 Stimulus Port 6 STIM6 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM7 0x1c 32 Stimulus Port 7 STIM7 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM8 0x20 32 Stimulus Port 8 STIM8 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM9 0x24 32 Stimulus Port 9 STIM9 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM10 0x28 32 Stimulus Port 10 STIM10 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM11 0x2c 32 Stimulus Port 11 STIM11 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM12 0x30 32 Stimulus Port 12 STIM12 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM13 0x34 32 Stimulus Port 13 STIM13 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM14 0x38 32 Stimulus Port 14 STIM14 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM15 0x3c 32 Stimulus Port 15 STIM15 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM16 0x40 32 Stimulus Port 16 STIM16 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM17 0x44 32 Stimulus Port 17 STIM17 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM18 0x48 32 Stimulus Port 18 STIM18 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM19 0x4c 32 Stimulus Port 19 STIM19 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM20 0x50 32 Stimulus Port 20 STIM20 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM21 0x54 32 Stimulus Port 21 STIM21 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM22 0x58 32 Stimulus Port 22 STIM22 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM23 0x5c 32 Stimulus Port 23 STIM23 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM24 0x60 32 Stimulus Port 24 STIM24 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM25 0x64 32 Stimulus Port 25 STIM25 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM26 0x68 32 Stimulus Port 26 STIM26 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM27 0x6c 32 Stimulus Port 27 STIM27 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM28 0x70 32 Stimulus Port 28 STIM28 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM29 0x74 32 Stimulus Port 29 STIM29 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM30 0x78 32 Stimulus Port 30 STIM30 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 STIM31 0x7c 32 Stimulus Port 31 STIM31 [31:0] A write to this location causes data to be written into the FIFO if TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. 32 0 0x0 TER 0xe00 32 Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required. STIMENA31 [31:31] Bit mask to enable tracing on ITM stimulus port 31. 1 31 STIMENA30 [30:30] Bit mask to enable tracing on ITM stimulus port 30. 1 30 STIMENA29 [29:29] Bit mask to enable tracing on ITM stimulus port 29. 1 29 STIMENA28 [28:28] Bit mask to enable tracing on ITM stimulus port 28. 1 28 STIMENA27 [27:27] Bit mask to enable tracing on ITM stimulus port 27. 1 27 STIMENA26 [26:26] Bit mask to enable tracing on ITM stimulus port 26. 1 26 STIMENA25 [25:25] Bit mask to enable tracing on ITM stimulus port 25. 1 25 STIMENA24 [24:24] Bit mask to enable tracing on ITM stimulus port 24. 1 24 STIMENA23 [23:23] Bit mask to enable tracing on ITM stimulus port 23. 1 23 STIMENA22 [22:22] Bit mask to enable tracing on ITM stimulus port 22. 1 22 STIMENA21 [21:21] Bit mask to enable tracing on ITM stimulus port 21. 1 21 STIMENA20 [20:20] Bit mask to enable tracing on ITM stimulus port 20. 1 20 STIMENA19 [19:19] Bit mask to enable tracing on ITM stimulus port 19. 1 19 STIMENA18 [18:18] Bit mask to enable tracing on ITM stimulus port 18. 1 18 STIMENA17 [17:17] Bit mask to enable tracing on ITM stimulus port 17. 1 17 STIMENA16 [16:16] Bit mask to enable tracing on ITM stimulus port 16. 1 16 STIMENA15 [15:15] Bit mask to enable tracing on ITM stimulus port 15. 1 15 STIMENA14 [14:14] Bit mask to enable tracing on ITM stimulus port 14. 1 14 STIMENA13 [13:13] Bit mask to enable tracing on ITM stimulus port 13. 1 13 STIMENA12 [12:12] Bit mask to enable tracing on ITM stimulus port 12. 1 12 STIMENA11 [11:11] Bit mask to enable tracing on ITM stimulus port 11. 1 11 STIMENA10 [10:10] Bit mask to enable tracing on ITM stimulus port 10. 1 10 STIMENA9 [9:9] Bit mask to enable tracing on ITM stimulus port 9. 1 9 STIMENA8 [8:8] Bit mask to enable tracing on ITM stimulus port 8. 1 8 STIMENA7 [7:7] Bit mask to enable tracing on ITM stimulus port 7. 1 7 STIMENA6 [6:6] Bit mask to enable tracing on ITM stimulus port 6. 1 6 STIMENA5 [5:5] Bit mask to enable tracing on ITM stimulus port 5. 1 5 STIMENA4 [4:4] Bit mask to enable tracing on ITM stimulus port 4. 1 4 STIMENA3 [3:3] Bit mask to enable tracing on ITM stimulus port 3. 1 3 STIMENA2 [2:2] Bit mask to enable tracing on ITM stimulus port 2. 1 2 STIMENA1 [1:1] Bit mask to enable tracing on ITM stimulus port 1. 1 1 STIMENA0 [0:0] Bit mask to enable tracing on ITM stimulus port 0. 1 0 0x0 TPR 0xe40 32 Trace Privilege This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 PRIVMASK [3:0] Bit mask to enable unprivileged (User) access to ITM stimulus ports: Bit [0] enables stimulus ports 0, 1, ..., and 7. Bit [1] enables stimulus ports 8, 9, ..., and 15. Bit [2] enables stimulus ports 16, 17, ..., and 23. Bit [3] enables stimulus ports 24, 25, ..., and 31. 0: User access allowed to stimulus ports 1: Privileged access only to stimulus ports 4 0 0x0 TCR 0xe80 32 Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set. RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 BUSY [23:23] Set when ITM events present and being drained. 1 23 ATBID [22:16] Trace Bus ID for CoreSight system. Optional identifier for multi-source trace stream formatting. If multi-source trace is in use, this field must be written with a non-zero value. 7 16 RESERVED10 [15:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 10 TSPRESCALE [9:8] Timestamp prescaler 2 8 DIV64 3 Divide by 64 DIV16 2 Divide by 16 DIV4 1 Divide by 4 NOPRESCALING 0 No prescaling RESERVED5 [7:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 5 SWOENA [4:4] Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of the timestamp counter. 0x0: Mode disabled. Timestamp counter uses system clock from the core and counts continuously. 0x1: Timestamp counter uses lineout (data related) clock from TPIU interface. The timestamp counter is held in reset while the output line is idle. 1 4 DWTENA [3:3] Enables the DWT stimulus (hardware event packet emission to the TPIU from the DWT) 1 3 SYNCENA [2:2] Enables synchronization packet transmission for a synchronous TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization speed. 1 2 TSENA [1:1] Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle. 1 1 ITMENA [0:0] Enables ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. 1 0 0x0 LAR 0xfb0 32 Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR. LOCK_ACCESS [31:0] A privileged write of 0xC5ACCE55 enables more write access to Control Registers TER, TPR and TCR. An invalid write removes write access. 32 0 0x0 LSR 0xfb4 32 Lock Status Use this register to enable write accesses to the Control Register. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 BYTEACC [2:2] Reads 0 which means 8-bit lock access is not be implemented. 1 2 ACCESS [1:1] Write access to component is blocked. All writes are ignored, reads are permitted. 1 1 PRESENT [0:0] Indicates that a lock mechanism exists for this component. 1 0 0x3 CPU_SCS 0xE000E000 0 0x1000 registers Cortex-M's System Control Space (SCS) RESERVED000 0x0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 ICTR 0x4 32 Interrupt Control Type Read this register to see the number of interrupt lines that the NVIC supports. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 INTLINESNUM [2:0] Total number of interrupt lines in groups of 32. 0: 0...32 1: 33...64 2: 65...96 3: 97...128 4: 129...160 5: 161...192 6: 193...224 7: 225...256 3 0 0x1 ACTLR 0x8 32 Auxiliary Control This register is used to disable certain aspects of functionality within the processor RESERVED10 [31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 10 DISOOFP [9:9] Disables floating point instructions completing out of order with respect to integer instructions. 1 9 DISFPCA [8:8] Disable automatic update of CONTROL.FPCA 1 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 DISFOLD [2:2] Disables folding of IT instruction. 1 2 DISDEFWBUF [1:1] Disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed. 1 1 DISMCYCINT [0:0] Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. 1 0 0x0 STCSR 0x10 32 SysTick Control and Status This register enables the SysTick features and returns status flags related to SysTick. RESERVED17 [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 COUNTFLAG [16:16] Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the **AHB-AP** Control Register is set to 0. Otherwise, COUNTFLAG is not changed by the debugger read. 1 16 RESERVED3 [15:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 13 3 CLKSOURCE [2:2] Clock source: 0: External reference clock. 1: Core clock External clock is not available in this device. Writes to this field will be ignored. 1 2 TICKINT [1:1] 0: Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. 1: Counting down to zero pends the SysTick handler. 1 1 ENABLE [0:0] Enable SysTick counter 0: Counter disabled 1: Counter operates in a multi-shot way. That is, counter loads with the Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting. 1 0 0x4 STRVR 0x14 32 SysTick Reload Value This register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and STCSR.COUNTFLAG are activated when counting from 1 to 0. RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 RELOAD [23:0] Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0. 24 0 0x0 STCVR 0x18 32 SysTick Current Value Read from this register returns the current value of SysTick counter. Writing to this register resets the SysTick counter (as well as STCSR.COUNTFLAG). RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 CURRENT [23:0] Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG. 24 0 0x0 STCR 0x1c 32 SysTick Calibration Value Used to enable software to scale to any required speed using divide and multiply. NOREF [31:31] Reads as one. Indicates that no separate reference clock is provided. 1 31 SKEW [30:30] Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. 1 30 RESERVED24 [29:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 24 TENMS [23:0] An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz. 24 0 0xC0075300 NVIC_ISER0 0x100 32 Irq 0 to 31 Set Enable This register is used to enable interrupts and determine which interrupts are currently enabled. SETENA31 [31:31] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. 1 31 SETENA30 [30:30] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. 1 30 SETENA29 [29:29] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. 1 29 SETENA28 [28:28] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. 1 28 SETENA27 [27:27] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. 1 27 SETENA26 [26:26] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. 1 26 SETENA25 [25:25] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. 1 25 SETENA24 [24:24] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. 1 24 SETENA23 [23:23] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. 1 23 SETENA22 [22:22] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. 1 22 SETENA21 [21:21] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. 1 21 SETENA20 [20:20] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. 1 20 SETENA19 [19:19] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. 1 19 SETENA18 [18:18] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. 1 18 SETENA17 [17:17] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. 1 17 SETENA16 [16:16] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. 1 16 SETENA15 [15:15] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. 1 15 SETENA14 [14:14] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. 1 14 SETENA13 [13:13] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. 1 13 SETENA12 [12:12] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. 1 12 SETENA11 [11:11] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. 1 11 SETENA10 [10:10] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. 1 10 SETENA9 [9:9] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. 1 9 SETENA8 [8:8] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. 1 8 SETENA7 [7:7] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. 1 7 SETENA6 [6:6] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. 1 6 SETENA5 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. 1 5 SETENA4 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. 1 4 SETENA3 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. 1 3 SETENA2 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. 1 2 SETENA1 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. 1 1 SETENA0 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. 1 0 0x0 NVIC_ISER1 0x104 32 Irq 32 to 63 Set Enable This register is used to enable interrupts and determine which interrupts are currently enabled. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 SETENA37 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current enable state. 1 5 SETENA36 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current enable state. 1 4 SETENA35 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current enable state. 1 3 SETENA34 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current enable state. 1 2 SETENA33 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. 1 1 SETENA32 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. 1 0 0x0 NVIC_ICER0 0x180 32 Irq 0 to 31 Clear Enable This register is used to disable interrupts and determine which interrupts are currently enabled. CLRENA31 [31:31] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. 1 31 CLRENA30 [30:30] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. 1 30 CLRENA29 [29:29] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. 1 29 CLRENA28 [28:28] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. 1 28 CLRENA27 [27:27] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. 1 27 CLRENA26 [26:26] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. 1 26 CLRENA25 [25:25] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. 1 25 CLRENA24 [24:24] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. 1 24 CLRENA23 [23:23] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. 1 23 CLRENA22 [22:22] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. 1 22 CLRENA21 [21:21] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. 1 21 CLRENA20 [20:20] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. 1 20 CLRENA19 [19:19] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. 1 19 CLRENA18 [18:18] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. 1 18 CLRENA17 [17:17] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. 1 17 CLRENA16 [16:16] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. 1 16 CLRENA15 [15:15] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. 1 15 CLRENA14 [14:14] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. 1 14 CLRENA13 [13:13] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. 1 13 CLRENA12 [12:12] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. 1 12 CLRENA11 [11:11] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. 1 11 CLRENA10 [10:10] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. 1 10 CLRENA9 [9:9] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. 1 9 CLRENA8 [8:8] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. 1 8 CLRENA7 [7:7] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. 1 7 CLRENA6 [6:6] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. 1 6 CLRENA5 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. 1 5 CLRENA4 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. 1 4 CLRENA3 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. 1 3 CLRENA2 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. 1 2 CLRENA1 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. 1 1 CLRENA0 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. 1 0 0x0 NVIC_ICER1 0x184 32 Irq 32 to 63 Clear Enable This register is used to disable interrupts and determine which interrupts are currently enabled. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 CLRENA37 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current enable state. 1 5 CLRENA36 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current enable state. 1 4 CLRENA35 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current enable state. 1 3 CLRENA34 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current enable state. 1 2 CLRENA33 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. 1 1 CLRENA32 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. 1 0 0x0 NVIC_ISPR0 0x200 32 Irq 0 to 31 Set Pending This register is used to force interrupts into the pending state and determine which interrupts are currently pending. SETPEND31 [31:31] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. 1 31 SETPEND30 [30:30] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. 1 30 SETPEND29 [29:29] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. 1 29 SETPEND28 [28:28] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. 1 28 SETPEND27 [27:27] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. 1 27 SETPEND26 [26:26] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. 1 26 SETPEND25 [25:25] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. 1 25 SETPEND24 [24:24] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. 1 24 SETPEND23 [23:23] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. 1 23 SETPEND22 [22:22] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. 1 22 SETPEND21 [21:21] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. 1 21 SETPEND20 [20:20] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. 1 20 SETPEND19 [19:19] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. 1 19 SETPEND18 [18:18] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. 1 18 SETPEND17 [17:17] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. 1 17 SETPEND16 [16:16] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. 1 16 SETPEND15 [15:15] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. 1 15 SETPEND14 [14:14] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. 1 14 SETPEND13 [13:13] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. 1 13 SETPEND12 [12:12] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. 1 12 SETPEND11 [11:11] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. 1 11 SETPEND10 [10:10] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. 1 10 SETPEND9 [9:9] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. 1 9 SETPEND8 [8:8] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. 1 8 SETPEND7 [7:7] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. 1 7 SETPEND6 [6:6] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. 1 6 SETPEND5 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. 1 5 SETPEND4 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. 1 4 SETPEND3 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. 1 3 SETPEND2 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. 1 2 SETPEND1 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. 1 1 SETPEND0 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. 1 0 0x0 NVIC_ISPR1 0x204 32 Irq 32 to 63 Set Pending This register is used to force interrupts into the pending state and determine which interrupts are currently pending. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 SETPEND37 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current state. 1 5 SETPEND36 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current state. 1 4 SETPEND35 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current state. 1 3 SETPEND34 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current state. 1 2 SETPEND33 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. 1 1 SETPEND32 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. 1 0 0x0 NVIC_ICPR0 0x280 32 Irq 0 to 31 Clear Pending This register is used to clear pending interrupts and determine which interrupts are currently pending. CLRPEND31 [31:31] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. 1 31 CLRPEND30 [30:30] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. 1 30 CLRPEND29 [29:29] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. 1 29 CLRPEND28 [28:28] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. 1 28 CLRPEND27 [27:27] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. 1 27 CLRPEND26 [26:26] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. 1 26 CLRPEND25 [25:25] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. 1 25 CLRPEND24 [24:24] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. 1 24 CLRPEND23 [23:23] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. 1 23 CLRPEND22 [22:22] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. 1 22 CLRPEND21 [21:21] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. 1 21 CLRPEND20 [20:20] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. 1 20 CLRPEND19 [19:19] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. 1 19 CLRPEND18 [18:18] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. 1 18 CLRPEND17 [17:17] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. 1 17 CLRPEND16 [16:16] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. 1 16 CLRPEND15 [15:15] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. 1 15 CLRPEND14 [14:14] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. 1 14 CLRPEND13 [13:13] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. 1 13 CLRPEND12 [12:12] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. 1 12 CLRPEND11 [11:11] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. 1 11 CLRPEND10 [10:10] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. 1 10 CLRPEND9 [9:9] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. 1 9 CLRPEND8 [8:8] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. 1 8 CLRPEND7 [7:7] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. 1 7 CLRPEND6 [6:6] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. 1 6 CLRPEND5 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. 1 5 CLRPEND4 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. 1 4 CLRPEND3 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. 1 3 CLRPEND2 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. 1 2 CLRPEND1 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. 1 1 CLRPEND0 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. 1 0 0x0 NVIC_ICPR1 0x284 32 Irq 32 to 63 Clear Pending This register is used to clear pending interrupts and determine which interrupts are currently pending. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 CLRPEND37 [5:5] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current state. 1 5 CLRPEND36 [4:4] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current state. 1 4 CLRPEND35 [3:3] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current state. 1 3 CLRPEND34 [2:2] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current state. 1 2 CLRPEND33 [1:1] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. 1 1 CLRPEND32 [0:0] Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. 1 0 0x0 NVIC_IABR0 0x300 32 Irq 0 to 31 Active Bit This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt. ACTIVE31 [31:31] Reading 0 from this bit implies that interrupt line 31 is not active. Reading 1 from this bit implies that the interrupt line 31 is active (See EVENT:CPUIRQSEL31.EV for details). 1 31 ACTIVE30 [30:30] Reading 0 from this bit implies that interrupt line 30 is not active. Reading 1 from this bit implies that the interrupt line 30 is active (See EVENT:CPUIRQSEL30.EV for details). 1 30 ACTIVE29 [29:29] Reading 0 from this bit implies that interrupt line 29 is not active. Reading 1 from this bit implies that the interrupt line 29 is active (See EVENT:CPUIRQSEL29.EV for details). 1 29 ACTIVE28 [28:28] Reading 0 from this bit implies that interrupt line 28 is not active. Reading 1 from this bit implies that the interrupt line 28 is active (See EVENT:CPUIRQSEL28.EV for details). 1 28 ACTIVE27 [27:27] Reading 0 from this bit implies that interrupt line 27 is not active. Reading 1 from this bit implies that the interrupt line 27 is active (See EVENT:CPUIRQSEL27.EV for details). 1 27 ACTIVE26 [26:26] Reading 0 from this bit implies that interrupt line 26 is not active. Reading 1 from this bit implies that the interrupt line 26 is active (See EVENT:CPUIRQSEL26.EV for details). 1 26 ACTIVE25 [25:25] Reading 0 from this bit implies that interrupt line 25 is not active. Reading 1 from this bit implies that the interrupt line 25 is active (See EVENT:CPUIRQSEL25.EV for details). 1 25 ACTIVE24 [24:24] Reading 0 from this bit implies that interrupt line 24 is not active. Reading 1 from this bit implies that the interrupt line 24 is active (See EVENT:CPUIRQSEL24.EV for details). 1 24 ACTIVE23 [23:23] Reading 0 from this bit implies that interrupt line 23 is not active. Reading 1 from this bit implies that the interrupt line 23 is active (See EVENT:CPUIRQSEL23.EV for details). 1 23 ACTIVE22 [22:22] Reading 0 from this bit implies that interrupt line 22 is not active. Reading 1 from this bit implies that the interrupt line 22 is active (See EVENT:CPUIRQSEL22.EV for details). 1 22 ACTIVE21 [21:21] Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details). 1 21 ACTIVE20 [20:20] Reading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details). 1 20 ACTIVE19 [19:19] Reading 0 from this bit implies that interrupt line 19 is not active. Reading 1 from this bit implies that the interrupt line 19 is active (See EVENT:CPUIRQSEL19.EV for details). 1 19 ACTIVE18 [18:18] Reading 0 from this bit implies that interrupt line 18 is not active. Reading 1 from this bit implies that the interrupt line 18 is active (See EVENT:CPUIRQSEL18.EV for details). 1 18 ACTIVE17 [17:17] Reading 0 from this bit implies that interrupt line 17 is not active. Reading 1 from this bit implies that the interrupt line 17 is active (See EVENT:CPUIRQSEL17.EV for details). 1 17 ACTIVE16 [16:16] Reading 0 from this bit implies that interrupt line 16 is not active. Reading 1 from this bit implies that the interrupt line 16 is active (See EVENT:CPUIRQSEL16.EV for details). 1 16 ACTIVE15 [15:15] Reading 0 from this bit implies that interrupt line 15 is not active. Reading 1 from this bit implies that the interrupt line 15 is active (See EVENT:CPUIRQSEL15.EV for details). 1 15 ACTIVE14 [14:14] Reading 0 from this bit implies that interrupt line 14 is not active. Reading 1 from this bit implies that the interrupt line 14 is active (See EVENT:CPUIRQSEL14.EV for details). 1 14 ACTIVE13 [13:13] Reading 0 from this bit implies that interrupt line 13 is not active. Reading 1 from this bit implies that the interrupt line 13 is active (See EVENT:CPUIRQSEL13.EV for details). 1 13 ACTIVE12 [12:12] Reading 0 from this bit implies that interrupt line 12 is not active. Reading 1 from this bit implies that the interrupt line 12 is active (See EVENT:CPUIRQSEL12.EV for details). 1 12 ACTIVE11 [11:11] Reading 0 from this bit implies that interrupt line 11 is not active. Reading 1 from this bit implies that the interrupt line 11 is active (See EVENT:CPUIRQSEL11.EV for details). 1 11 ACTIVE10 [10:10] Reading 0 from this bit implies that interrupt line 10 is not active. Reading 1 from this bit implies that the interrupt line 10 is active (See EVENT:CPUIRQSEL10.EV for details). 1 10 ACTIVE9 [9:9] Reading 0 from this bit implies that interrupt line 9 is not active. Reading 1 from this bit implies that the interrupt line 9 is active (See EVENT:CPUIRQSEL9.EV for details). 1 9 ACTIVE8 [8:8] Reading 0 from this bit implies that interrupt line 8 is not active. Reading 1 from this bit implies that the interrupt line 8 is active (See EVENT:CPUIRQSEL8.EV for details). 1 8 ACTIVE7 [7:7] Reading 0 from this bit implies that interrupt line 7 is not active. Reading 1 from this bit implies that the interrupt line 7 is active (See EVENT:CPUIRQSEL7.EV for details). 1 7 ACTIVE6 [6:6] Reading 0 from this bit implies that interrupt line 6 is not active. Reading 1 from this bit implies that the interrupt line 6 is active (See EVENT:CPUIRQSEL6.EV for details). 1 6 ACTIVE5 [5:5] Reading 0 from this bit implies that interrupt line 5 is not active. Reading 1 from this bit implies that the interrupt line 5 is active (See EVENT:CPUIRQSEL5.EV for details). 1 5 ACTIVE4 [4:4] Reading 0 from this bit implies that interrupt line 4 is not active. Reading 1 from this bit implies that the interrupt line 4 is active (See EVENT:CPUIRQSEL4.EV for details). 1 4 ACTIVE3 [3:3] Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details). 1 3 ACTIVE2 [2:2] Reading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details). 1 2 ACTIVE1 [1:1] Reading 0 from this bit implies that interrupt line 1 is not active. Reading 1 from this bit implies that the interrupt line 1 is active (See EVENT:CPUIRQSEL1.EV for details). 1 1 ACTIVE0 [0:0] Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details). 1 0 0x0 NVIC_IABR1 0x304 32 Irq 32 to 63 Active Bit This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 ACTIVE37 [5:5] Reading 0 from this bit implies that interrupt line 37 is not active. Reading 1 from this bit implies that the interrupt line 37 is active (See EVENT:CPUIRQSEL37.EV for details). 1 5 ACTIVE36 [4:4] Reading 0 from this bit implies that interrupt line 36 is not active. Reading 1 from this bit implies that the interrupt line 36 is active (See EVENT:CPUIRQSEL36.EV for details). 1 4 ACTIVE35 [3:3] Reading 0 from this bit implies that interrupt line 35 is not active. Reading 1 from this bit implies that the interrupt line 35 is active (See EVENT:CPUIRQSEL35.EV for details). 1 3 ACTIVE34 [2:2] Reading 0 from this bit implies that interrupt line 34 is not active. Reading 1 from this bit implies that the interrupt line 34 is active (See EVENT:CPUIRQSEL34.EV for details). 1 2 ACTIVE33 [1:1] Reading 0 from this bit implies that interrupt line 33 is not active. Reading 1 from this bit implies that the interrupt line 33 is active (See EVENT:CPUIRQSEL33.EV for details). 1 1 ACTIVE32 [0:0] Reading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details). 1 0 0x0 NVIC_IPR0 0x400 32 Irq 0 to 3 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_3 [31:24] Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). 8 24 PRI_2 [23:16] Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 8 16 PRI_1 [15:8] Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). 8 8 PRI_0 [7:0] Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). 8 0 0x0 NVIC_IPR1 0x404 32 Irq 4 to 7 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_7 [31:24] Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). 8 24 PRI_6 [23:16] Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 8 16 PRI_5 [15:8] Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). 8 8 PRI_4 [7:0] Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). 8 0 0x0 NVIC_IPR2 0x408 32 Irq 8 to 11 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_11 [31:24] Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). 8 24 PRI_10 [23:16] Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 8 16 PRI_9 [15:8] Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). 8 8 PRI_8 [7:0] Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). 8 0 0x0 NVIC_IPR3 0x40c 32 Irq 12 to 15 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_15 [31:24] Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). 8 24 PRI_14 [23:16] Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 8 16 PRI_13 [15:8] Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). 8 8 PRI_12 [7:0] Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). 8 0 0x0 NVIC_IPR4 0x410 32 Irq 16 to 19 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_19 [31:24] Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). 8 24 PRI_18 [23:16] Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 8 16 PRI_17 [15:8] Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). 8 8 PRI_16 [7:0] Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). 8 0 0x0 NVIC_IPR5 0x414 32 Irq 20 to 23 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_23 [31:24] Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). 8 24 PRI_22 [23:16] Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 8 16 PRI_21 [15:8] Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). 8 8 PRI_20 [7:0] Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). 8 0 0x0 NVIC_IPR6 0x418 32 Irq 24 to 27 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_27 [31:24] Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). 8 24 PRI_26 [23:16] Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 8 16 PRI_25 [15:8] Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). 8 8 PRI_24 [7:0] Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). 8 0 0x0 NVIC_IPR7 0x41c 32 Irq 28 to 31 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_31 [31:24] Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). 8 24 PRI_30 [23:16] Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 8 16 PRI_29 [15:8] Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). 8 8 PRI_28 [7:0] Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). 8 0 0x0 NVIC_IPR8 0x420 32 Irq 32 to 35 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. PRI_35 [31:24] Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). 8 24 PRI_34 [23:16] Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). 8 16 PRI_33 [15:8] Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). 8 8 PRI_32 [7:0] Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). 8 0 0x0 NVIC_IPR9 0x424 32 Irq 32 to 35 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 PRI_37 [15:8] Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). 8 8 PRI_36 [7:0] Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). 8 0 0x0 CPUID 0xd00 32 CPUID Base This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core. IMPLEMENTER [31:24] Implementor code. 8 24 VARIANT [23:20] Implementation defined variant number. 4 20 CONSTANT [19:16] Reads as 0xF 4 16 PARTNO [15:4] Number of processor within family. 12 4 REVISION [3:0] Implementation defined revision number. 4 0 0x410FC241 ICSR 0xd04 32 Interrupt Control State This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception. NMIPENDSET [31:31] Set pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 0: No action 1: Set pending NMI 1 31 RESERVED29 [30:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 29 PENDSVSET [28:28] Set pending pendSV bit. 0: No action 1: Set pending PendSV 1 28 PENDSVCLR [27:27] Clear pending pendSV bit 0: No action 1: Clear pending pendSV 1 27 PENDSTSET [26:26] Set a pending SysTick bit. 0: No action 1: Set pending SysTick 1 26 PENDSTCLR [25:25] Clear pending SysTick bit 0: No action 1: Clear pending SysTick 1 25 RESERVED24 [24:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 24 ISRPREEMPT [23:23] This field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced. 0: A pending exception is not serviced. 1: A pending exception is serviced on exit from the debug halt state 1 23 ISRPENDING [22:22] Interrupt pending flag. Excludes NMI and faults. 0x0: Interrupt not pending 0x1: Interrupt pending 1 22 RESERVED18 [21:18] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 18 VECTPENDING [17:12] Pending ISR number field. This field contains the interrupt number of the highest priority pending ISR. 6 12 RETTOBASE [11:11] Indicates whether there are preempted active exceptions: 0: There are preempted active exceptions to execute 1: There are no active exceptions, or the currently-executing exception is the only active exception. 1 11 RESERVED9 [10:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 9 VECTACTIVE [8:0] Active ISR number field. Reset clears this field. 9 0 0x0 VTOR 0xd08 32 Vector Table Offset This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF. RESERVED30 [31:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 30 TBLOFF [29:7] Bits 29 down to 7 of the vector table base offset. 23 7 RESERVED0 [6:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 0 0x0 AIRCR 0xd0c 32 Application Interrupt/Reset Control This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point). VECTKEY [31:16] Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05. 16 16 ENDIANESS [15:15] Data endianness bit 1 15 BIG 1 Big endian LITTLE 0 Little endian RESERVED11 [14:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 11 PRIGROUP [10:8] Interrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices. 3 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 SYSRESETREQ [2:2] Requests a warm reset. Setting this bit does not prevent Halting Debug from running. 1 2 VECTCLRACTIVE [1:1] Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. 1 1 VECTRESET [0:0] System Reset bit. Resets the system, with the exception of debug components. This bit is reserved for debug use and can be written to 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior. 1 0 0xFA050000 SCR 0xd10 32 System Control This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states. RESERVED5 [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 SEVONPEND [4:4] Send Event on Pending bit: 0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 SLEEPDEEP [2:2] Controls whether the processor uses sleep or deep sleep as its low power mode 1 2 DEEPSLEEP 1 Deep sleep SLEEP 0 Sleep SLEEPONEXIT [1:1] Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 0: Do not sleep when returning to thread mode 1: Sleep on ISR exit 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 CCR 0xd14 32 Configuration Control This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode. RESERVED10 [31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 10 STKALIGN [9:9] Stack alignment bit. 0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry. 1: On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. 1 9 BFHFNMIGN [8:8] Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers: 0: Data BusFaults caused by load and store instructions cause a lock-up 1: Data BusFaults caused by load and store instructions are ignored. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect problems. 1 8 RESERVED5 [7:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 5 DIV_0_TRP [4:4] Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. In this mode, a divide by zero returns a quotient of 0. 1: Trap divide by 0. The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO. 1 4 UNALIGN_TRP [3:3] Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses 1: Trap unaligned halfword and word accesses. The relevant Usage Fault Status Register bit is CFSR.UNALIGNED. If this bit is set to 1, an unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the value in UNALIGN_TRP. 1 3 RESERVED2 [2:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 2 USERSETMPEND [1:1] Enables unprivileged software access to STIR: 0: User code is not allowed to write to the Software Trigger Interrupt register (STIR). 1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer. 1 1 NONBASETHREDENA [0:0] Indicates how the processor enters Thread mode: 0: Processor can enter Thread mode only when no exception is active. 1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN). Exception returns occur when one of the following instructions loads a value of 0xFXXXXXXX into the PC while in Handler mode: - POP/LDM which includes loading the PC. - LDR with PC as a destination. - BX with any register. The value written to the PC is intercepted and is referred to as the EXC_RETURN value. 1 0 0x200 SHPR1 0xd18 32 System Handlers 4-7 Priority This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 PRI_6 [23:16] Priority of system handler 6. UsageFault 8 16 PRI_5 [15:8] Priority of system handler 5: BusFault 8 8 PRI_4 [7:0] Priority of system handler 4: MemManage 8 0 0x0 SHPR2 0xd1c 32 System Handlers 8-11 Priority This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. PRI_11 [31:24] Priority of system handler 11. SVCall 8 24 RESERVED0 [23:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 0 0x0 SHPR3 0xd20 32 System Handlers 12-15 Priority This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. PRI_15 [31:24] Priority of system handler 15. SysTick exception 8 24 PRI_14 [23:16] Priority of system handler 14. Pend SV 8 16 RESERVED8 [15:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 8 PRI_12 [7:0] Priority of system handler 12. Debug Monitor 8 0 0x0 SHCSR 0xd24 32 System Handler Control and State This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault. RESERVED19 [31:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 13 19 USGFAULTENA [18:18] Usage fault system handler enable 1 18 EN 1 Exception enabled DIS 0 Exception disabled BUSFAULTENA [17:17] Bus fault system handler enable 1 17 EN 1 Exception enabled DIS 0 Exception disabled MEMFAULTENA [16:16] MemManage fault system handler enable 1 16 EN 1 Exception enabled DIS 0 Exception disabled SVCALLPENDED [15:15] SVCall pending 1 15 PENDING 1 Exception is pending. NOTPENDING 0 Exception is not active BUSFAULTPENDED [14:14] BusFault pending 1 14 PENDING 1 Exception is pending. NOTPENDING 0 Exception is not active MEMFAULTPENDED [13:13] MemManage exception pending 1 13 PENDING 1 Exception is pending. NOTPENDING 0 Exception is not active USGFAULTPENDED [12:12] Usage fault pending 1 12 PENDING 1 Exception is pending. NOTPENDING 0 Exception is not active SYSTICKACT [11:11] SysTick active flag. 0x0: Not active 0x1: Active 1 11 ACTIVE 1 Exception is active NOTACTIVE 0 Exception is not active PENDSVACT [10:10] PendSV active 0x0: Not active 0x1: Active 1 10 RESERVED9 [9:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 9 MONITORACT [8:8] Debug monitor active 1 8 ACTIVE 1 Exception is active NOTACTIVE 0 Exception is not active SVCALLACT [7:7] SVCall active 1 7 ACTIVE 1 Exception is active NOTACTIVE 0 Exception is not active RESERVED4 [6:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 4 USGFAULTACT [3:3] UsageFault exception active 1 3 ACTIVE 1 Exception is active NOTACTIVE 0 Exception is not active RESERVED2 [2:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 2 BUSFAULTACT [1:1] BusFault exception active 1 1 ACTIVE 1 Exception is active NOTACTIVE 0 Exception is not active MEMFAULTACT [0:0] MemManage exception active 1 0 ACTIVE 1 Exception is active NOTACTIVE 0 Exception is not active 0x0 CFSR 0xd28 32 Configurable Fault Status This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit. The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows: The following accesses are possible to the CFSR register: - access the complete register with a word access to 0xE000ED28. - access the MMFSR with a byte access to 0xE000ED28 - access the MMFSR and BFSR with a halfword access to 0xE000ED28 - access the BFSR with a byte access to 0xE000ED29 - access the UFSR with a halfword access to 0xE000ED2A. RESERVED26 [31:26] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 26 DIVBYZERO [25:25] When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. 1 25 UNALIGNED [24:24] When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. 1 24 RESERVED20 [23:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 20 NOCP [19:19] Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. 1 19 INVPC [18:18] Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. 1 18 INVSTATE [17:17] Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state. 1 17 UNDEFINSTR [16:16] This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. 1 16 BFARVALID [15:15] This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. 1 15 RESERVED13 [14:13] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 13 STKERR [12:12] Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written. 1 12 UNSTKERR [11:11] Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written. 1 11 IMPRECISERR [10:10] Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written. 1 10 PRECISERR [9:9] Precise data bus error return. 1 9 IBUSERR [8:8] Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written. 1 8 MMARVALID [7:7] Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten. 1 7 RESERVED5 [6:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 5 MSTKERR [4:4] Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written. 1 4 MUNSTKERR [3:3] Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written. 1 3 RESERVED2 [2:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 2 DACCVIOL [1:1] Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access. 1 1 IACCVIOL [0:0] Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. 1 0 0x0 HFSR 0xd2c 32 Hard Fault Status This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit. DEBUGEVT [31:31] This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. 1 31 FORCED [30:30] Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. 1 30 RESERVED2 [29:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 2 VECTTBL [1:1] This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 DFSR 0xd30 32 Debug Fault Status This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and some are ignored. RESERVED5 [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 EXTERNAL [4:4] External debug request flag. The processor stops on next instruction boundary. 0x0: External debug request signal not asserted 0x1: External debug request signal asserted 1 4 VCATCH [3:3] Vector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. 0x0: No vector catch occurred 0x1: Vector catch occurred 1 3 DWTTRAP [2:2] Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. 0x0: No DWT match 0x1: DWT match 1 2 BKPT [1:1] BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 0x0: No BKPT instruction execution 0x1: BKPT instruction execution 1 1 HALTED [0:0] Halt request flag. The processor is halted on the next instruction. 0x0: No halt request 0x1: Halt requested by NVIC, including step 1 0 0x0 MMFAR 0xd34 32 Mem Manage Fault Address This register is used to read the address of the location that caused a Memory Manage Fault. ADDRESS [31:0] Mem Manage fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault. 32 0 0x0 BFAR 0xd38 32 Bus Fault Address This register is used to read the address of the location that generated a Bus Fault. ADDRESS [31:0] Bus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault. 32 0 0x0 AFSR 0xd3c 32 Auxiliary Fault Status This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0. IMPDEF [31:0] Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 32 0 0x0 ID_PFR0 0xd40 32 Processor Feature 0 RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 STATE1 [7:4] State1 (T-bit == 1) 0x0: N/A 0x1: N/A 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2 basic instructions 4 4 STATE0 [3:0] State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A 4 0 0x30 ID_PFR1 0xd44 32 Processor Feature 1 RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 MICROCONTROLLER_PROGRAMMERS_MODEL [11:8] Microcontroller programmer's model 0x0: Not supported 0x2: Two-stack support 4 8 RESERVED0 [7:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 0 0x200 ID_DFR0 0xd48 32 Debug Feature 0 This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself. RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 MICROCONTROLLER_DEBUG_MODEL [23:20] Microcontroller Debug Model - memory mapped 0x0: Not supported 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) 4 20 RESERVED0 [19:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 0 0x100000 ID_AFR0 0xd4c 32 Auxiliary Feature 0 This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 ID_MMFR0 0xd50 32 Memory Model Feature 0 General information on the memory model and memory management support. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x100030 ID_MMFR1 0xd54 32 Memory Model Feature 1 General information on the memory model and memory management support. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 ID_MMFR2 0xd58 32 Memory Model Feature 2 General information on the memory model and memory management support. RESERVED28 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 WAIT_FOR_INTERRUPT_STALLING [24:24] wait for interrupt stalling 0x0: Not supported 0x1: Wait for interrupt supported 1 24 RESERVED0 [23:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 0 0x1000000 ID_MMFR3 0xd5c 32 Memory Model Feature 3 General information on the memory model and memory management support. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 ID_ISAR0 0xd60 32 ISA Feature 0 Information on the instruction set attributes register RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x1141110 ID_ISAR1 0xd64 32 ISA Feature 1 Information on the instruction set attributes register RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x2112000 ID_ISAR2 0xd68 32 ISA Feature 2 Information on the instruction set attributes register RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x21232231 ID_ISAR3 0xd6c 32 ISA Feature 3 Information on the instruction set attributes register RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x1111131 ID_ISAR4 0xd70 32 ISA Feature 4 Information on the instruction set attributes register RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x1310102 CPACR 0xd88 32 Coprocessor Access Control This register specifies the access privileges for coprocessors. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 MPU_TYPE 0xd90 32 MPU Type This register indicates many regions the MPU supports. RESERVED24 [31:24] Reads 0. 8 24 IREGION [23:16] The processor core uses only a unified MPU, this field always reads 0x0. 8 16 DREGION [15:8] Number of supported MPU regions field. This field reads 0x08 indicating eight MPU regions. 8 8 RESERVED1 [7:1] Reads 0. 7 1 SEPARATE [0:0] The processor core uses only a unified MPU, thus this field is always 0. 1 0 0x800 MPU_CTRL 0xd94 32 MPU Control This register is used to enable the MPU, enable the default memory map (background region), and enable the MPU when in Hard Fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. When the MPU is enabled, at least one region of the memory map must be enabled for the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set and no regions are enabled, then only privileged code can operate. When the MPU is disabled, the default address map is used, as if no MPU is present. When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled. Unless HFNMIENA is set, the MPU is not enabled when the exception priority is -1 or -2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK is enabled. The HFNMIENA bit enables the MPU when operating with these two priorities. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 PRIVDEFENA [2:2] This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit is not set, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the system partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. 1 2 HFNMIENA [1:1] This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit and ENABLE are set, the MPU is enabled when in these handlers. If this bit is not set, the MPU is disabled when in these handlers, regardless of the value of ENABLE bit. If this bit is set and ENABLE is not set, behavior is unpredictable. 1 1 ENABLE [0:0] Enable MPU 0: MPU disabled 1: MPU enabled 1 0 0x0 MPU_RNR 0xd98 32 MPU Region Number This register is used to select which protection region is accessed. The following write to MPU_RASR or MPU_RBAR configures the characteristics of the protection region that is selected by this register. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 REGION [7:0] Region select field. This field selects the region to operate on when using the MPU_RASR and MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID and MPU_RBAR.REGION fields are written, which overwrites this. 8 0 0x0 MPU_RBAR 0xd9c 32 MPU Region Base Address This register writes the base address of a region. It also contains a REGION field that can be used to override MPU_RNR.REGION, if the VALID bit is set. This register sets the base for the region. It is aligned by the size. So, a 64-KB sized region must be aligned on a multiple of 64KB, for example, 0x00010000 or 0x00020000. The region always reads back as the current MPU region number. VALID always reads back as 0. Writing VALID = 1 and REGION = n changes the region number to n. This is a short-hand way to write the MPU_RNR. This register is unpredictable if accessed other than as a word. ADDR [31:5] Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used. 27 5 VALID [4:4] MPU region number valid: 0: MPU_RNR remains unchanged and is interpreted. 1: MPU_RNR is overwritten by REGION. 1 4 REGION [3:0] MPU region override field 4 0 0x0 MPU_RASR 0xda0 32 MPU Region Attribute and Size This register controls the MPU access permissions. The register is made up of two part registers, each of halfword size. These can be accessed using the halfword size, or they can both be simultaneously accessed using a word operation. The sub-region disable bits are not supported for region sizes of 32 bytes, 64 bytes, and 128 bytes. When these region sizes are used, the subregion disable bits must be programmed as 0. RESERVED29 [31:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 29 XN [28:28] Instruction access disable: 0: Enable instruction fetches 1: Disable instruction fetches 1 28 RESERVED27 [27:27] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 27 AP [26:24] Data access permission: 0x0: Priviliged permissions: No access. User permissions: No access. 0x1: Priviliged permissions: Read-write. User permissions: No access. 0x2: Priviliged permissions: Read-write. User permissions: Read-only. 0x3: Priviliged permissions: Read-write. User permissions: Read-write. 0x4: Reserved 0x5: Priviliged permissions: Read-only. User permissions: No access. 0x6: Priviliged permissions: Read-only. User permissions: Read-only. 0x7: Priviliged permissions: Read-only. User permissions: Read-only. 3 24 RESERVED22 [23:22] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 22 TEX [21:19] Type extension 3 19 S [18:18] Shareable bit: 0: Not shareable 1: Shareable 1 18 C [17:17] Cacheable bit: 0: Not cacheable 1: Cacheable 1 17 B [16:16] Bufferable bit: 0: Not bufferable 1: Bufferable 1 16 SRD [15:8] Sub-Region Disable field: Setting a bit in this field disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less. 8 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 SIZE [5:1] MPU Protection Region Size Field: 0x04: 32B 0x05: 64B 0x06: 128B 0x07: 256B 0x08: 512B 0x09: 1KB 0x0A: 2KB 0x0B: 4KB 0x0C: 8KB 0x0D: 16KB 0x0E: 32KB 0x0F: 64KB 0x10: 128KB 0x11: 256KB 0x12: 512KB 0x13: 1MB 0x14: 2MB 0x15: 4MB 0x16: 8MB 0x17: 16MB 0x18: 32MB 0x19: 64MB 0x1A: 128MB 0x1B: 256MB 0x1C: 512MB 0x1D: 1GB 0x1E: 2GB 0x1F: 4GB 5 1 ENABLE [0:0] Region enable bit: 0: Disable region 1: Enable region 1 0 0x0 MPU_RBAR_A1 0xda4 32 MPU Alias 1 Region Base Address Alias for MPU_RBAR MPU_RBAR_A1 [31:0] Alias for MPU_RBAR 32 0 0x0 MPU_RASR_A1 0xda8 32 MPU Alias 1 Region Attribute and Size Alias for MPU_RASR MPU_RASR_A1 [31:0] Alias for MPU_RASR 32 0 0x0 MPU_RBAR_A2 0xdac 32 MPU Alias 2 Region Base Address Alias for MPU_RBAR MPU_RBAR_A2 [31:0] Alias for MPU_RBAR 32 0 0x0 MPU_RASR_A2 0xdb0 32 MPU Alias 2 Region Attribute and Size Alias for MPU_RASR MPU_RASR_A2 [31:0] Alias for MPU_RASR 32 0 0x0 MPU_RBAR_A3 0xdb4 32 MPU Alias 3 Region Base Address Alias for MPU_RBAR MPU_RBAR_A3 [31:0] Alias for MPU_RBAR 32 0 0x0 MPU_RASR_A3 0xdb8 32 MPU Alias 3 Region Attribute and Size Alias for MPU_RASR MPU_RASR_A3 [31:0] Alias for MPU_RASR 32 0 0x0 DHCSR 0xdf0 32 Debug Halting Control and Status The purpose of this register is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register, otherwise the write operation is ignored and no bits are written into the register. If not enabled for Halting mode, C_DEBUGEN = 1, all other fields are disabled. This register is not reset on a core reset. It is reset by a power-on reset. However, C_HALT always clears on a core reset. To halt on a reset, the following bits must be enabled: DEMCR.VC_CORERESET and C_DEBUGEN. Note that writes to this register in any size other than word are unpredictable. It is acceptable to read in any size, and it can be used to avoid or intentionally change a sticky bit. Behavior of the system when writing to this register while CPU is halted (i.e. C_DEBUGEN = 1 and S_HALT= 1): C_HALT=0, C_STEP=0, C_MASKINTS=0 Exit Debug state and start instruction execution. Exceptions activate according to the exception configuration rules. C_HALT=0, C_STEP=0, C_MASKINTS=1 Exit Debug state and start instruction execution. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules. C_HALT=0, C_STEP=1, C_MASKINTS=0 Exit Debug state, step an instruction and halt. Exceptions activate according to the exception configuration rules. C_HALT=0, C_STEP=1, C_MASKINTS=1 Exit Debug state, step an instruction and halt. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules. C_HALT=1, C_STEP=x, C_MASKINTS=x Remain in Debug state RESERVED26 [31:26] Software should not rely on the value of a reserved. When writing to this register, 0x28 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 6 26 S_RESET_ST [25:25] Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 1 25 S_RETIRE_ST [24:24] Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 1 24 RESERVED20 [23:20] Software should not rely on the value of a reserved. When writing to this register, 0x5 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 4 20 S_LOCKUP [19:19] Reads as one if the core is running (not halted) and a lockup condition is present. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 1 19 S_SLEEP [18:18] Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must use C_HALT to gain control or wait for interrupt to wake-up. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 1 18 S_HALT [17:17] The core is in debug state when this bit is set. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 1 17 S_REGRDY [16:16] Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 1 16 RESERVED6 [15:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 10 6 C_SNAPSTALL [5:5] If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE_ST can detect core stalls on load/store operations. 1 5 RESERVED4 [4:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 4 C_MASKINTS [3:3] Mask interrupts when stepping or running in halted debug. This masking does not affect NMI, fault exceptions and SVC caused by execution of the instructions. This bit must only be modified when the processor is halted (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate). Modifying C_MASKINTS while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. 1 3 C_STEP [2:2] Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). Modifying C_STEP while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. 1 2 C_HALT [1:1] Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. 1 1 C_DEBUGEN [0:0] Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0. 1 0 0x0 DCRSR 0xdf4 32 Deubg Core Register Selector The purpose of this register is to select the processor register to transfer data to or from. This write-only register generates a handshake to the core to transfer data to or from Debug Core Register Data Register and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0. Note that writes to this register in any size but word are Unpredictable. Note that PSR registers are fully accessible this way, whereas some read as 0 when using MRS instructions. Note that all bits can be written, but some combinations cause a fault when execution is resumed. RESERVED17 [31:17] Software should not rely on the value of a reserved. Write 0. 15 17 REGWNR [16:16] 1: Write 0: Read 1 16 RESERVED5 [15:5] Software should not rely on the value of a reserved. Write 0. 11 5 REGSEL [4:0] Register select 0x00: R0 0x01: R1 0x02: R2 0x03: R3 0x04: R4 0x05: R5 0x06: R6 0x07: R7 0x08: R8 0x09: R9 0x0A: R10 0x0B: R11 0x0C: R12 0x0D: Current SP 0x0E: LR 0x0F: DebugReturnAddress 0x10: XPSR/flags, execution state information, and exception number 0x11: MSP (Main SP) 0x12: PSP (Process SP) 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK 5 0 0x0 DCRDR 0xdf8 32 Debug Core Register Data DCRDR [31:0] This register holds data for reading and writing registers to and from the processor. This is the data value written to the register selected by DCRSR. When the processor receives a request from DCRSR, this register is read or written by the processor using a normal load-store unit operation. If core register transfers are not being performed, software-based debug monitors can use this register for communication in non-halting debug. This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to. 32 0 0x0 DEMCR 0xdfc 32 Debug Exception and Monitor Control The purpose of this register is vector catching and debug monitor control. This register manages exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception support. This register is not reset on a system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset handler or later, or by the **AHB-AP** port. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 TRCENA [24:24] This bit must be set to 1 to enable use of the trace and debug blocks: DWT, ITM, ETM and TPIU. This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. 1 24 RESERVED20 [23:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 20 MON_REQ [19:19] This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. 0x0: Woken up by debug exception. 0x1: Woken up by MON_PEND 1 19 MON_STEP [18:18] When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. 1 18 MON_PEND [17:17] Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. 1 17 MON_EN [16:16] Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. 1 16 RESERVED11 [15:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 11 VC_HARDERR [10:10] Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. 1 10 VC_INTERR [9:9] Debug trap on a fault occurring during an exception entry or return sequence. Ignored when DHCSR.C_DEBUGEN is cleared. 1 9 VC_BUSERR [8:8] Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. 1 8 VC_STATERR [7:7] Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is cleared. 1 7 VC_CHKERR [6:6] Debug trap on Usage Fault enabled checking errors. Ignored when DHCSR.C_DEBUGEN is cleared. 1 6 VC_NOCPERR [5:5] Debug trap on a UsageFault access to a Coprocessor. Ignored when DHCSR.C_DEBUGEN is cleared. 1 5 VC_MMERR [4:4] Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is cleared. 1 4 RESERVED1 [3:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 1 VC_CORERESET [0:0] Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared. 1 0 0x0 STIR 0xf00 32 Software Trigger Interrupt RESERVED9 [31:9] Software should not rely on the value of a reserved. Write 0. 23 9 INTID [8:0] Interrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. 9 0 0x0 FPCCR 0xf34 32 Floating Point Context Control This register holds control data for the floating-point unit. Accessible only by privileged software. ASPEN [31:31] Automatic State Preservation enable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry. 1 31 LSPEN [30:30] Lazy State Preservation enable. Lazy state preservation is when the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation. 0: Disable automatic lazy state preservation for floating-point context. 1: Enable automatic lazy state preservation for floating-point context. 1 30 RESERVED9 [29:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 21 9 MONRDY [8:8] Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending. 0: DebugMonitor is disabled or priority did not permit setting DEMCR.MON_PEND when the floating-point stack frame was allocated. 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when the floating-point stack frame was allocated. 1 8 RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 BFRDY [6:6] Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending. 0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 1: BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 1 6 MMRDY [5:5] Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending. 0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 1: MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 1 5 HFRDY [4:4] Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending. 0: Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 1: Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 1 4 THREAD [3:3] Indicates the processor mode was Thread when it allocated the FP stack frame. 0: Mode was not Thread Mode when the floating-point stack frame was allocated. 1: Mode was Thread Mode when the floating-point stack frame was allocated. 1 3 RESERVED2 [2:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 2 USER [1:1] Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame: 0: Privilege level was not user when the floating-point stack frame was allocated. 1: Privilege level was user when the floating-point stack frame was allocated. 1 1 LSPACT [0:0] Indicates whether Lazy preservation of the FP state is active: 0: Lazy state preservation is not active. 1: Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. 1 0 0xC0000000 FPCAR 0xf38 32 Floating-Point Context Address This register holds the location of the unpopulated floating-point register space allocated on an exception stack frame. ADDRESS [31:2] Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame. 30 2 RESERVED0 [1:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 0 0x0 FPDSCR 0xf3c 32 Floating Point Default Status Control This register holds the default values for the floating-point status control data that the processor assigns to the FPSCR when it creates a new floating-point context. Accessible only by privileged software. RESERVED27 [31:27] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 27 AHP [26:26] Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected). 1 26 DN [25:25] Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN). 1 25 FZ [24:24] Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled). 1 24 RMODE [23:22] Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode 0b01 Round towards Plus Infinity (RP) mode 0b10 Round towards Minus Infinity (RM) mode 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions). 2 22 RESERVED0 [21:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 0 0x0 MVFR0 0xf40 32 Media and FP Feature 0 Describes the features provided by the Floating-point extension. FP_ROUNDING_MODES [31:28] Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported. 4 28 SHORT_VECTORS [27:24] Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported. 4 24 SQUARE_ROOT [23:20] Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported. 4 20 DIVIDE [19:16] Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported. 4 16 FP_EXCEPTION_TRAPPING [15:12] Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported. 4 12 DOUBLE_PRECISION [11:8] Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported. 4 8 SINGLE_PRECISION [7:4] Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported. 4 4 A_SIMD [3:0] Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers. 4 0 0x10110021 MVFR1 0xf44 32 Media and FP Feature 1 Describes the features provided by the Floating-point extension. FP_FUSED_MAC [31:28] Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported. 4 28 FP_HPFP [27:24] Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported. 4 24 RESERVED8 [23:8] Software should not rely on the value of a reserved. 16 8 D_NAN_MODE [7:4] Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values. 4 4 FTZ_MODE [3:0] Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic. 4 0 0x11000011 CPU_TIPROP 0xE00FE000 0 0x1000 registers Cortex-M's TI proprietary registers RESERVED000 0x0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 TRACECLKMUX 0xff8 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 TRACECLK_N_SWV [0:0] Internal. Only to be used through TI provided API. 1 0 TRACECLK 1 Internal. Only to be used through TI provided API. SWV 0 Internal. Only to be used through TI provided API. 0x0 CPU_TPIU 0xE0040000 0 0x1000 registers Cortex-M's Trace Port Interface Unit (TPIU) SSPSR 0x0 32 Supported Sync Port Sizes This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 FOUR [3:3] 4-bit port size support 0x0: Not supported 0x1: Supported 1 3 THREE [2:2] 3-bit port size support 0x0: Not supported 0x1: Supported 1 2 TWO [1:1] 2-bit port size support 0x0: Not supported 0x1: Supported 1 1 ONE [0:0] 1-bit port size support 0x0: Not supported 0x1: Supported 1 0 0xB CSPSR 0x4 32 Current Sync Port Size This register has the same format as SSPSR but only one bit can be set, and all others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 FOUR [3:3] 4-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. 1 3 THREE [2:2] 3-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. 1 2 TWO [1:1] 2-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. 1 1 ONE [0:0] 1-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. 1 0 0x1 ACPR 0x10 32 Async Clock Prescaler This register scales the baud rate of the asynchronous output. RESERVED13 [31:13] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 19 13 PRESCALER [12:0] Divisor for input trace clock is (PRESCALER + 1). 13 0 0x0 SPPR 0xf0 32 Selected Pin Protocol This register selects the protocol to be used for trace output. Note: If this register is changed while trace data is being output, data corruption occurs. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 PROTOCOL [1:0] Trace output protocol 2 0 SWO_NRZ 2 SerialWire Output (NRZ) SWO_MANCHESTER 1 SerialWire Output (Manchester). This is the reset value. TRACEPORT 0 TracePort mode 0x1 FFSR 0x300 32 Formatter and Flush Status RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 FTNONSTOP [3:3] 0: Formatter can be stopped 1: Formatter cannot be stopped 1 3 RESERVED0 [2:0] This field always reads as zero 3 0 0x8 FFCR 0x304 32 Formatter and Flush Control When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended to be used when it is necessary to connect a device containing an ETM to a trace capture device that is only able to capture Serial Wire Output (SWO) data. Enabling or disabling the formatter causes momentary data corruption. Note: If the selected pin protocol register (SPPR.PROTOCOL) is set to 0x00 (TracePort mode), this register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire modes is then selected, the register reverts to its previously programmed value. RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 TRIGIN [8:8] Indicates that triggers are inserted when a trigger pin is asserted. 1 8 RESERVED2 [7:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 2 ENFCONT [1:1] Enable continuous formatting: 0: Continuous formatting disabled 1: Continuous formatting enabled 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x102 FSCR 0x308 32 Formatter Synchronization Counter FSCR [31:0] The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU. 32 0 0x0 CLAIMMASK 0xfa0 32 Claim Tag Mask CLAIMMASK [31:0] This register forms one half of the Claim Tag value. When reading this register returns the number of bits that can be set (each bit is considered separately): 0: This claim tag bit is not implemented 1: This claim tag bit is not implemented The behavior when writing to this register is described in CLAIMSET. 32 0 0xF CLAIMSET 0xfa0 32 Claim Tag Set CLAIMSET [31:0] This register forms one half of the Claim Tag value. Writing to this location allows individual bits to be set (each bit is considered separately): 0: No effect 1: Set this bit in the claim tag The behavior when reading from this location is described in CLAIMMASK. 32 0 0xF CLAIMTAG 0xfa4 32 Current Claim Tag CLAIMTAG [31:0] This register forms one half of the Claim Tag value. Reading this register returns the current Claim Tag value. Reading CLAIMMASK determines how many bits from this register must be used. The behavior when writing to this register is described in CLAIMCLR. 32 0 0x0 CLAIMCLR 0xfa4 32 Claim Tag Clear CLAIMCLR [31:0] This register forms one half of the Claim Tag value. Writing to this location enables individual bits to be cleared (each bit is considered separately): 0: No effect 1: Clear this bit in the claim tag. The behavior when reading from this location is described in CLAIMTAG. 32 0 0x0 DEVID 0xfc8 32 Device ID DEVID [31:0] This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present. 32 0 0xCA0 CRYPTO 0x40024000 0 0x800 registers DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage. DMACH0CTL 0x0 32 Channel 0 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 PRIO [1:1] Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests. 1 1 EN [0:0] Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. 1 0 0x0 DMACH0EXTADDR 0x4 32 Channel 0 External Address ADDR [31:0] Channel external address value When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned. 32 0 0x0 DMACH0LEN 0xc 32 Channel 0 DMA Length RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DMALEN [15:0] Channel DMA length in bytes During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel. 16 0 0x0 DMASTAT 0x18 32 DMAC Status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer. RESERVED18 [31:18] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14 18 PORT_ERR [17:17] Reflects possible transfer errors on the AHB port. 1 17 RESERVED2 [16:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 2 CH1_ACT [1:1] A value of 1 indicates that channel 1 is active (DMA transfer on-going). 1 1 CH0_ACT [0:0] A value of 1 indicates that channel 0 is active (DMA transfer on-going). 1 0 0x0 DMASWRESET 0x1c 32 DMAC Software Reset Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMASTAT. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 SWRES [0:0] Software reset enable 0 : Disabled 1 : Enabled (self-cleared to 0) Completion of the software reset must be checked through the DMASTAT 1 0 0x0 DMACH1CTL 0x20 32 Channel 1 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 PRIO [1:1] Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests. 1 1 EN [0:0] Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. 1 0 0x0 DMACH1EXTADDR 0x24 32 Channel 1 External Address ADDR [31:0] Channel external address value. When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned. 32 0 0x0 DMACH1LEN 0x2c 32 Channel 1 DMA Length RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DMALEN [15:0] Channel DMA length in bytes. During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel. 16 0 0x0 DMABUSCFG 0x78 32 DMAC Master Run-time Parameters This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter. RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 AHB_MST1_BURST_SIZE [15:12] Maximum burst size that can be performed on the AHB bus 4 12 64_BYTE 6 64 bytes 32_BYTE 5 32 bytes 16_BYTE 4 16 bytes 8_BYTE 3 8 bytes 4_BYTE 2 4 bytes AHB_MST1_IDLE_EN [11:11] Idle insertion between consecutive burst transfers on AHB 1 11 IDLE 1 Idle transfer insertion enabled NO_IDLE 0 Do not insert idle transfers. AHB_MST1_INCR_EN [10:10] Burst length type of AHB transfer 1 10 SPECIFIED 1 Fixed length bursts or single transfers UNSPECIFIED 0 Unspecified length burst transfers AHB_MST1_LOCK_EN [9:9] Locked transform on AHB 1 9 LOCKED 1 Transfers are locked NOT_LOCKED 0 Transfers are not locked AHB_MST1_BIGEND [8:8] Endianess for the AHB master 1 8 BIG_ENDIAN 1 Big Endian LITTLE_ENDIAN 0 Little Endian RESERVED0 [7:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 0 0x2400 DMAPORTERR 0x7c 32 DMAC Port Error Raw Status This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMASWRESET register. RESERVED13 [31:13] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 19 13 PORT1_AHB_ERROR [12:12] A value of 1 indicates that the EIP-101 has detected an AHB bus error 1 12 RESERVED10 [11:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 10 PORT1_CHANNEL [9:9] Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port. 1 9 RESERVED0 [8:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 9 0 0x0 DMAHWVER 0xfc 32 DMAC Version This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers. RESERVED28 [31:28] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 28 HW_MAJOR_VERSION [27:24] Major version number 4 24 HW_MINOR_VERSION [23:20] Minor version number 4 20 HW_PATCH_LEVEL [19:16] Patch level Starts at 0 at first delivery of this version 4 16 EIP_NUMBER_COMPL [15:8] Bit-by-bit complement of the EIP_NUMBER field bits. 8 8 EIP_NUMBER [7:0] Binary encoding of the EIP-number of this DMA controller (209) 8 0 0x1012ED1 KEYWRITEAREA 0x400 32 Key Store Write Area This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected. The key store RAM is divided into 8 areas of 128 bits. 192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 RAM_AREA7 [7:7] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA7 is not selected to be written. 1: RAM_AREA7 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 7 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA6 [6:6] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA6 is not selected to be written. 1: RAM_AREA6 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 6 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA5 [5:5] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA5 is not selected to be written. 1: RAM_AREA5 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 5 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA4 [4:4] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA4 is not selected to be written. 1: RAM_AREA4 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 4 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA3 [3:3] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA3 is not selected to be written. 1: RAM_AREA3 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 3 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA2 [2:2] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA2 is not selected to be written. 1: RAM_AREA2 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 2 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA1 [1:1] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA1 is not selected to be written. 1: RAM_AREA1 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 1 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written RAM_AREA0 [0:0] Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA0 is not selected to be written. 1: RAM_AREA0 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 1 0 SEL 1 This RAM area is selected to be written NOT_SEL 0 This RAM area is not selected to be written 0x0 KEYWRITTENAREA 0x404 32 Key Store Written Area This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and results in an error. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 RAM_AREA_WRITTEN7 [7:7] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 7 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN6 [6:6] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 6 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN5 [5:5] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 5 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN4 [4:4] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 4 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN3 [3:3] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 3 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN2 [2:2] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 2 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN1 [1:1] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 1 WRITTEN 1 This RAM area is written with valid key information NOT_WRITTEN 0 This RAM area is not written with valid key information RAM_AREA_WRITTEN0 [0:0] On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 1 0 0x0 KEYSIZE 0x408 32 Key Store Size This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register. RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 SIZE [1:0] Key size: 00: Reserved When writing this to this register, the KEY_STORE_WRITTEN_AREA register is reset. 2 0 256_BIT 3 256 bits 192_BIT 2 192 bits 128_BIT 1 128 bits 0x1 KEYREADAREA 0x40c 32 Key Store Read Area This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key. BUSY [31:31] Key store operation busy status flag (read only): 0: Operation is complete. 1: Operation is not completed and the key store is busy. 1 31 RESERVED4 [30:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 4 RAM_AREA [3:0] Selects the area of the key store RAM from where the key needs to be read that will be writen to the AES engine RAM_AREA: RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes. Only RAM areas that contain valid written keys can be selected. 4 0 NO_RAM 8 No RAM RAM_AREA7 7 RAM Area 7 RAM_AREA6 6 RAM Area 6 RAM_AREA5 5 RAM Area 5 RAM_AREA4 4 RAM Area 4 RAM_AREA3 3 RAM Area 3 RAM_AREA2 2 RAM Area 2 RAM_AREA1 1 RAM Area 1 RAM_AREA0 0 RAM Area 0 0x8 AESKEY2 0x500 32 AES_KEY2_0 / AES_GHASH_H_IN_0 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. AES_KEY2 [31:0] AES_KEY2/AES_GHASH_H[31:0] For GCM: -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). -[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key. For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. 32 0 0x0 AESKEY3 0x510 32 AES_KEY3_0 / AES_KEY2_4 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. AES_KEY3 [31:0] AES_KEY3[31:0]/AES_KEY2[159:128] For GCM: -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). -[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key. For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. 32 0 0x0 AESIV 0x540 32 AES initialization vector registers These registers are used to provide and read the IV from the AES engine. AES_IV [31:0] AES_IV[31:0] Initialization vector Used for regular non-ECB modes (CBC/CTR): -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers must be written with a new 128-bit IV. After an operation, these registers contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode is selected, this value is incremented with 0x1: After first use - When a new data block is submitted to the engine For GCM: -[127:0] - AES_IV - For GCM operations, these registers must be written with a new 128-bit IV. After an operation, these registers contain the updated 128-bit result IV, generated by the EIP-120t. Note that bits [127:96] of the IV represent the initial counter value (which is 1 for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1: After first use - When a new data block is submitted to the engine. For CCM: -[127:0] - A0: For CCM this field must be written with value A0, this value is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to 0. The total width of A0 is 128-bit. For CBC-MAC: -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the start of each operation. After an operation, these registers contain the 128-bit TAG output, generated by the EIP-120t. 32 0 0x0 AESCTL 0x550 32 AES Control AES input/output buffer control and mode register This register specifies the AES mode of operation for the EIP-120t. Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0. CONTEXT_READY [31:31] If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context. 1 31 SAVED_CONTEXT_RDY [30:30] If 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve. This bit is only asserted if the save_context bit is set to 1. The bit is mutual exclusive with the context_ready bit. Writing one clears the bit to 0, indicating the AES core can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read. Note: All other mode bit writes are ignored when this mode bit is written with 1. Note: This bit is controlled automatically by the EIP-120t for TAG read DMA operations. 1 30 SAVE_CONTEXT [29:29] This bit indicates that an authentication TAG or result IV needs to be stored as a result context. Typically this bit must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV. If this bit is set, the engine retains its full context until the TAG and/or IV registers are read. The TAG or IV must be read before the AES engine can start a new operation. 1 29 RESERVED25 [28:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 25 CCM_M [24:22] Defines M, which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-120t always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. 3 22 CCM_L [21:19] Defines L, which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported. 3 19 CCM [18:18] If set to 1, AES-CCM is selected AES-CCM is a combined mode, using AES for authentication and encryption. Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR; selecting other AES modes than CTR mode is invalid. 1 18 GCM [17:16] Set these bits to 11 to select AES-GCM mode. AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR Bit combination description: 00 = No GCM mode 01 = Reserved, do not select 10 = Reserved, do not select 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), other GCM modes are not allowed. 2 16 CBC_MAC [15:15] Set to 1 to select AES-CBC MAC mode. The direction bit must be set to 1 for this mode. Selecting this mode requires writing the length register after all other registers. 1 15 RESERVED9 [14:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 9 CTR_WIDTH [8:7] Specifies the counter width for AES-CTR mode 00 = 32-bit counter 01 = 64-bit counter 10 = 96-bit counter 11 = 128-bit counter 2 7 128_BIT 3 128 bits 96_BIT 2 96 bits 64_BIT 1 64 bits 32_BIT 0 32 bits CTR [6:6] If set to 1, AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required. 1 6 CBC [5:5] If set to 1, cipher-block-chaining (CBC) mode is selected. 1 5 KEY_SIZE [4:3] This read-only field specifies the key size. The key size is automatically configured when a new key is loaded through the key store module. 00 = N/A - Reserved 01 = 128-bit 10 = 192-bit 11 = 256-bit 2 3 DIR [2:2] If set to 1 an encrypt operation is performed. If set to 0 a decrypt operation is performed. This bit must be written with a 1 when CBC-MAC is selected. 1 2 INPUT_READY [1:1] If 1, this status bit indicates that the 16-byte AES input buffer is empty. The host is permitted to write the next block of data. Writing 0 clears the bit to 0 and indicates that the AES core can use the provided input data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. After reset, this bit is 0. After writing a context, this bit becomes 1. 1 1 OUTPUT_READY [0:0] If 1, this status bit indicates that an AES output block is available to be retrieved by the host. Writing 0 clears the bit to 0 and indicates that output data is read by the host. The AES core can provide a next output data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. 1 0 0x80000000 AESDATALEN0 0x554 32 AES Crypto Length 0 (LSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. C_LENGTH [31:0] C_LENGTH[31:0] Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data; the authentication length is specified in the AESAUTHLEN register All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0. For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a host read operation, these registers return all-0s. 32 0 0x0 AESDATALEN1 0x558 32 AES Crypto Length 1 (MSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. RESERVED29 [31:29] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 29 C_LENGTH [28:0] C_LENGTH[60:32] Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data; the authentication length is specified in the AESAUTHLEN register All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0. For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a host read operation, these registers return all-0s. 29 0 0x0 AESAUTHLEN 0x55c 32 AES Authentication Length AUTH_LENGTH [31:0] Bits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM). Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any value up to (2^32 - 1) bytes can be used. Once processing with this context is started, this length decrements to 0. A write to this register triggers the engine to start using this context for GCM and CCM. For a host read operation, these registers return all-0s. 32 0 0x0 AESDATAOUT0 0x560 32 Data Input/Output DATA [31:0] Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAIN0 0x560 32 AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. AES_DATA_IN_OUT [31:0] AES input data[31:0] / AES output data[31:0] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAOUT1 0x564 32 Data Input/Output DATA [31:0] Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAIN1 0x564 32 AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. AES_DATA_IN_OUT [31:0] AES input data[31:0] / AES output data[63:32] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAOUT2 0x568 32 Data Input/Output DATA [31:0] Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAIN2 0x568 32 AES Data Input_Output 2 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. AES_DATA_IN_OUT [31:0] AES input data[95:64] / AES output data[95:64] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAOUT3 0x56c 32 Data Input/Output DATA [31:0] Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESDATAIN3 0x56c 32 AES Data Input_Output 3 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. AES_DATA_IN_OUT [31:0] AES input data[127:96] / AES output data[127:96] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. 32 0 0x0 AESTAGOUT 0x570 32 AES Tag Out 0 The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice. AES_TAG [31:0] AES_TAG[31:0] Bits [31:0] of this register stores the authentication value for the combined and authentication only modes. For a host read operation, these registers contain the last 128-bit TAG output of the EIP-120t; the TAG is available until the next context is written. This register will only contain valid data if the TAG is available and when the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for operations/modes that do not return a TAG, reads from this register return data from the IV register. 32 0 0x0 HASHDATAIN1 0x604 32 HASH Data Input 1 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[63:32] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN2 0x608 32 HASH Data Input 2 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[95:64] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN3 0x60c 32 HASH Data Input 3 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[127:96] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when the rfd_in bit of the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN4 0x610 32 HASH Data Input 4 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[159:128] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN5 0x614 32 HASH Data Input 5 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[191:160] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN6 0x618 32 HASH Data Input 6 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[223:192] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN7 0x61c 32 HASH Data Input 7 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[255:224] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN8 0x620 32 HASH Data Input 8 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[287:256] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN9 0x624 32 HASH Data Input 9 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[319:288] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN10 0x628 32 HASH Data Input 10 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[351:320] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN11 0x62c 32 HASH Data Input 11 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[383:352] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN12 0x630 32 HASH Data Input 12 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[415:384] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN13 0x634 32 HASH Data Input 13 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[447:416] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN14 0x638 32 HASH Data Input 14 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[479:448] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN15 0x63c 32 HASH Data Input 15 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[511:480] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN16 0x640 32 HASH Data Input 16 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[543:512] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN17 0x644 32 HASH Data Input 17 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[575:544] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN18 0x648 32 HASH Data Input 18 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[607:576] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN19 0x64c 32 HASH Data Input 19 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[639:608] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN20 0x650 32 HASH Data Input 20 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[671:640] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN21 0x654 32 HASH Data Input 21 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[703:672] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN22 0x658 32 HASH Data Input 22 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[735:704] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN23 0x65c 32 HASH Data Input 23 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[767:736] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN24 0x660 32 HASH Data Input 24 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[799:768] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN25 0x664 32 HASH Data Input 25 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[831:800] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN26 0x668 32 HASH Data Input 26 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[863:832] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN27 0x66c 32 HASH Data Input 27 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[895:864] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN28 0x670 32 HASH Data Input 28 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[923:896] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN29 0x674 32 HASH Data Input 29 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[959:924] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN30 0x678 32 HASH Data Input 30 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[991:960] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHDATAIN31 0x67c 32 HASH Data Input 31 The data input registers should be used to provide input data to the hash module through the slave interface. HASH_DATA_IN [31:0] HASH_DATA_IN[1023:992] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. 32 0 0x0 HASHIOBUFCTRL 0x680 32 HASH Input_Output Buffer Control This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PAD_DMA_MESSAGE [7:7] Note: This bit must only be used when data is supplied through the DMA. It should not be used when data is supplied through the slave interface. This bit indicates whether the hash engine has to pad the message, received through the DMA and finalize the hash. When set to 1, the hash engine pads the last block using the programmed length. After padding, the final hash result is calculated. When set to 0, the hash engine treats the last written block as block-size aligned and calculates the intermediate digest. This bit is automatically cleared when the last DMA data block is arrived in the hash engine. 1 7 GET_DIGEST [6:6] Note: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA. This bit indicates whether the hash engine should provide the hash digest. When provided simultaneously with data_in_av, the hash digest is provided after processing the data that is currently in the HASHDATAINn register. When provided without data_in_av, the current internal digest buffer value is copied to the HASHDIGESTn registers. The host must write a 1 to this bit to make the intermediate hash digest available. Writing 0 to this bit has no effect. This bit is automatically cleared (that is, reads 0) when the hash engine has processed the contents of the HASHDATAINn register. In the period between this bit is set by the host and the actual HASHDATAINn processing, this bit reads 1. 1 6 PAD_MESSAGE [5:5] Note: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA. This bit indicates that the HASHDATAINn registers hold the last data of the message and hash padding must be applied. The host must write this bit to 1 in order to indicate to the hash engine that the HASHDATAINn register currently holds the last data of the message. When pad_message is set to 1, the hash engine will add padding bits to the data currently in the HASHDATAINn register. When the last message block is smaller than 512 bits, the pad_message bit must be set to 1 together with the data_in_av bit. When the last message block is equal to 512 bits, pad_message may be set together with data_in_av. In this case the pad_message bit may also be set after the last data block has been written to the hash engine (so when the rfd_in bit has become 1 again after writing the last data block). Writing 0 to this bit has no effect. This bit is automatically cleared (i.e. reads 0) by the hash engine. This bit reads 1 between the time it was set by the host and the hash engine interpreted its value. 1 5 RESERVED3 [4:3] Write 0s and ignore on reading 2 3 RFD_IN [2:2] Note: The bit description below is only applicable when data is sent through the slave interface. This bit can be ignored when data is received through the DMA. Read-only status of the input buffer of the hash engine. When 1, the input buffer of the hash engine can accept new data; the HASHDATAINn registers can safely be populated with new data. When 0, the input buffer of the hash engine is processing the data that is currently in HASHDATAINn; writing new data to these registers is not allowed. 1 2 DATA_IN_AV [1:1] Note: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA. This bit indicates that the HASHDATAINn registers contain new input data for processing. The host must write a 1 to this bit to start processing the data in HASHDATAINn; the hash engine will process the new data as soon as it is ready for it (rfd_in bit is 1). Writing 0 to this bit has no effect. This bit is automatically cleared (i.e. reads as 0) when the hash engine starts processing the HASHDATAINn contents. This bit reads 1 between the time it was set by the host and the hash engine actually starts processing the input data block. 1 1 OUTPUT_FULL [0:0] Indicates that the output buffer registers (HASHDIGESTn) are available for reading by the host. When this bit reads 0, the output buffer registers are released; the hash engine is allowed to write new data to it. In this case, the registers should not be read by the host. When this bit reads 1, the hash engine has stored the result of the latest hash operation in the output buffer registers. As long as this bit reads 1, the host may read output buffer registers and the hash engine is prevented from writing new data to the output buffer. After retrieving the hash result data from the output buffer, the host must write a 1 to this bit to clear it. This makes the digest output buffer available for the hash engine to store new hash results. Writing 0 to this bit has no effect. Note: If this bit is asserted (1) no new operation should be started before the digest is retrieved from the hash engine and this bit is cleared (0). 1 0 0x4 HASHMODE 0x684 32 HASH Mode RESERVED7 [31:7] Write 0s and ignore on reading 25 7 SHA384_MODE [6:6] The host must write this bit with 1 prior to processing a SHA 384 session. 1 6 SHA512_MODE [5:5] The host must write this bit with 1 prior to processing a SHA 512 session. 1 5 SHA224_MODE [4:4] The host must write this bit with 1 prior to processing a SHA 224 session. 1 4 SHA256_MODE [3:3] The host must write this bit with 1 prior to processing a SHA 256 session. 1 3 RESERVED1 [2:1] Write 0s and ignore on reading 2 1 NEW_HASH [0:0] When set to 1, it indicates that the hash engine must start processing a new hash session. The [HASHDIGESTn.* ] registers will automatically be loaded with the initial hash algorithm constants of the selected hash algorithm. When this bit is 0 while the hash processing is started, the initial hash algorithm constants are not loaded in the HASHDIGESTn registers. The hash engine will start processing with the digest that is currently in its internal HASHDIGESTn registers. This bit is automatically cleared when hash processing is started. 1 0 0x0 HASHINLENL 0x688 32 HASH Input Length LSB LENGTH_IN [31:0] LENGTH_IN[31:0] Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine. For a write operation by the host, these registers should be written with the message length in bits. Final hash operations: The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface. Continued hash operations (finalized): For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest. Non-final hash operations: For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation. If the message length in bits is below (2^32-1), then only this register needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case. The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine. host read operations from these register locations will return 0s. Note: When getting data from DMA, this register must be programmed before DMA is programmed to start. 32 0 0x0 HASHINLENH 0x68c 32 HASH Input Length MSB LENGTH_IN [31:0] LENGTH_IN[63:32] Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine. For a write operation by the host, these registers should be written with the message length in bits. Final hash operations: The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface. Continued hash operations (finalized): For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest. Non-final hash operations: For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation. If the message length in bits is below (2^32-1), then only HASHINLENL needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case. The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine. host read operations from these register locations will return 0s. Note: When getting data from DMA, this register must be programmed before DMA is programmed to start. 32 0 0x0 HASHDIGESTA 0x6c0 32 HASH Digest A The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[31:0] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTB 0x6c4 32 HASH Digest B The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[63:32] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTC 0x6c8 32 HASH Digest C The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[95:64] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTD 0x6cc 32 HASH Digest D The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[127:96] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTE 0x6d0 32 HASH Digest E The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[159:128] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTF 0x6d4 32 HASH Digest F The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[191:160] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTG 0x6d8 32 HASH Digest G The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[223:192] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTH 0x6dc 32 HASH Digest H The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[255:224] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTI 0x6e0 32 HASH Digest I The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[287:256] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTJ 0x6e4 32 HASH Digest J The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[319:288] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTK 0x6e8 32 HASH Digest K The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[351:320] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTL 0x6ec 32 HASH Digest L The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[383:352] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTM 0x6f0 32 HASH Digest M The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[415:384] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTN 0x6f4 32 HASH Digest N The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[447:416] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTO 0x6f8 32 HASH Digest 0 The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[479:448] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 HASHDIGESTP 0x6fc 32 HASH Digest P The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. HASH_DIGEST [31:0] HASH_DIGEST[511:480] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. 32 0 0x0 ALGSEL 0x700 32 Algorithm Select This algorithm selection register configures the internal destination of the DMA controller. TAG [31:31] If this bit is cleared to 0, the DMA operation involves only data. If this bit is set, the DMA operation includes a TAG (Authentication Result / Digest). For SHA-256 operation, a DMA must be set up for both input data and TAG. For any other selected module, setting this bit only allows a DMA that reads the TAG. No data allowed to be transferred to or from the selected module via the DMA. 1 31 RESERVED4 [30:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 4 HASH_SHA_256 [2:2] If set to one, selects the hash engine in 256B mode as destination for the DMA The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA). 1 2 AES [1:1] If set to one, selects the AES engine as source/destination for the DMA The read and write maximum transfer size to the DMA engine is set to 16 bytes. 1 1 KEY_STORE [0:0] If set to one, selects the Key Store as destination for the DMA The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed) 1 0 0x0 DMAPROTCTL 0x704 32 DMA Protection Control Master PROT privileged access enable This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 PROT_EN [0:0] Select AHB transfer protection control for DMA transfers using the key store area as destination. 0 : transfers use 'USER' type access. 1 : transfers use 'PRIVILEGED' type access. 1 0 0x0 SWRESET 0x740 32 Software Reset RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 SW_RESET [0:0] If this bit is set to 1, the following modules are reset: - Master control internal state is reset. That includes interrupt, error status register, and result available interrupt generation FSM. - Key store module state is reset. That includes clearing the written area flags; therefore, the keys must be reloaded to the key store module. Writing 0 has no effect. The bit is self cleared after executing the reset. 1 0 0x0 IRQTYPE 0x780 32 Control Interrupt Configuration RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 LEVEL [0:0] If this bit is 0, the interrupt output is a pulse. If this bit is set to 1, the interrupt is a level interrupt that must be cleared by writing the interrupt clear register. This bit is applicable for both interrupt output signals. 1 0 0x0 IRQEN 0x784 32 Control Interrupt Enable RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 DMA_IN_DONE [1:1] If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt output is disabled and remains 0. If this bit is set to 1, the DMA input done interrupt output is enabled. 1 1 RESULT_AVAIL [0:0] If this bit is set to 0, the result available (irq_result_av) interrupt output is disabled and remains 0. If this bit is set to 1, the result available interrupt output is enabled. 1 0 0x0 IRQCLR 0x788 32 Control Interrupt Clear DMA_BUS_ERR [31:31] If 1 is written to this bit, the DMA bus error status is cleared. Writing 0 has no effect. 1 31 KEY_ST_WR_ERR [30:30] If 1 is written to this bit, the key store write error status is cleared. Writing 0 has no effect. 1 30 KEY_ST_RD_ERR [29:29] If 1 is written to this bit, the key store read error status is cleared. Writing 0 has no effect. 1 29 RESERVED2 [28:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 2 DMA_IN_DONE [1:1] If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE). 1 1 RESULT_AVAIL [0:0] If 1 is written to this bit, the result available (irq_result_av) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE). 1 0 0x0 IRQSET 0x78c 32 Control Interrupt Set RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 DMA_IN_DONE [1:1] If 1 is written to this bit, the DMA data in done (irq_dma_in_done) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the DMA data in done (irq_dma_in_done) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.DMA_IN_DONE). 1 1 RESULT_AVAIL [0:0] If 1 is written to this bit, the result available (irq_result_av) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the result available (irq_result_av) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.RESULT_AVAIL). 1 0 0x0 IRQSTAT 0x790 32 Control Interrupt Status DMA_BUS_ERR [31:31] This bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared through the IRQCLR.DMA_BUS_ERR Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation. 1 31 KEY_ST_WR_ERR [30:30] This bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_WR_ERR register. Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected. 1 30 KEY_ST_RD_ERR [29:29] This bit is set when a read error is detected during the read of a key from the key store, while copying it to the AES core. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. Note: This error is asserted if a key location is selected in the key store that is not available. 1 29 RESERVED2 [28:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 2 DMA_IN_DONE [1:1] This read only bit returns the actual DMA data in done (irq_data_in_done) interrupt status of the DMA data in done interrupt output pin (irq_data_in_done). 1 1 RESULT_AVAIL [0:0] This read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av). 1 0 0x0 HWVER 0x7fc 32 Hardware Version RESERVED28 [31:28] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 28 HW_MAJOR_VER [27:24] Major version number 4 24 HW_MINOR_VER [23:20] Minor version number 4 20 HW_PATCH_LVL [19:16] Patch level Starts at 0 at first delivery of this version 4 16 VER_NUM_COMPL [15:8] These bits simply contain the complement of bits [7:0] (0x87), used by a driver to ascertain that the EIP-120t register is indeed read. 8 8 VER_NUM [7:0] These bits encode the EIP number for the EIP-120t, this field contains the value 120 (decimal) or 0x78. 8 0 0x92008778 AUX_DDI0_OSC 0x400CA000 0 0x1000 registers This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated. CTL0 0x0 32 Control 0 Controls clock source selects XTAL_IS_24M [31:31] Set based on the accurate high frequency XTAL. 1 31 24M 1 Internal. Only to be used through TI provided API. 48M 0 Internal. Only to be used through TI provided API. RESERVED30 [30:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 30 BYPASS_XOSC_LF_CLK_QUAL [29:29] Internal. Only to be used through TI provided API. 1 29 BYPASS_RCOSC_LF_CLK_QUAL [28:28] Internal. Only to be used through TI provided API. 1 28 DOUBLER_START_DURATION [27:26] Internal. Only to be used through TI provided API. 2 26 DOUBLER_RESET_DURATION [25:25] Internal. Only to be used through TI provided API. 1 25 CLK_DCDC_SRC_SEL [24:24] Select DCDC clock source. 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC 1: CLK_DCDC is always 48 MHz clock from RCOSC 1 24 RESERVED15 [23:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 9 15 HPOSC_MODE_EN [14:14] Internal. Only to be used through TI provided API. 1 14 RESERVED13 [13:13] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 13 RCOSC_LF_TRIMMED [12:12] Internal. Only to be used through TI provided API. 1 12 XOSC_HF_POWER_MODE [11:11] Internal. Only to be used through TI provided API. 1 11 XOSC_LF_DIG_BYPASS [10:10] Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use digital input (from AON) as xosc_lf clock source. This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf. 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source. 2) Set or clear this bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change. 1 10 CLK_LOSS_EN [9:9] Enable clock loss detection and hence the indicators to the system controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. 0: Disable 1: Enable Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed. 1 9 ACLK_TDC_SRC_SEL [8:7] Source select for aclk_tdc. 00: RCOSC_HF (48MHz) 01: RCOSC_HF (24MHz) 10: XOSC_HF (24MHz) 11: Not used 2 7 ACLK_REF_SRC_SEL [6:4] Source select for aclk_ref 000: RCOSC_HF derived (31.25kHz) 001: XOSC_HF derived (31.25kHz) 010: RCOSC_LF (32kHz) 011: XOSC_LF (32.768kHz) 100: RCOSC_MF (2MHz) 101-111: Not used 3 4 SCLK_LF_SRC_SEL [3:2] Source select for sclk_lf 2 2 XOSCLF 3 Low frequency XOSC RCOSCLF 2 Low frequency RCOSC XOSCHFDLF 1 Low frequency clock derived from High Frequency XOSC RCOSCHFDLF 0 Low frequency clock derived from High Frequency RCOSC RESERVED1 [1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 1 SCLK_HF_SRC_SEL [0:0] Source select for sclk_hf. 1 0 XOSC 1 High frequency XOSC clock RCOSC 0 High frequency RCOSC clock 0x0 CTL1 0x4 32 Control 1 This register contains OSC_DIG configuration RESERVED23 [31:23] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 9 23 RCOSCHFCTRIMFRACT [22:18] Internal. Only to be used through TI provided API. 5 18 RCOSCHFCTRIMFRACT_EN [17:17] Internal. Only to be used through TI provided API. 1 17 SPARE2 [16:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 2 XOSC_HF_FAST_START [1:0] Internal. Only to be used through TI provided API. 2 0 0x0 RADCEXTCFG 0x8 32 RADC External Configuration HPM_IBIAS_WAIT_CNT [31:22] Internal. Only to be used through TI provided API. 10 22 LPM_IBIAS_WAIT_CNT [21:16] Internal. Only to be used through TI provided API. 6 16 IDAC_STEP [15:12] Internal. Only to be used through TI provided API. 4 12 RADC_DAC_TH [11:6] Internal. Only to be used through TI provided API. 6 6 RADC_MODE_IS_SAR [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED0 [4:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 0 0x0 AMPCOMPCTL 0xc 32 Amplitude Compensation Control SPARE31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 AMPCOMP_REQ_MODE [30:30] Internal. Only to be used through TI provided API. 1 30 AMPCOMP_FSM_UPDATE_RATE [29:28] Internal. Only to be used through TI provided API. 2 28 250KHZ 3 Internal. Only to be used through TI provided API. 500KHZ 2 Internal. Only to be used through TI provided API. 1MHZ 1 Internal. Only to be used through TI provided API. 2MHZ 0 Internal. Only to be used through TI provided API. AMPCOMP_SW_CTRL [27:27] Internal. Only to be used through TI provided API. 1 27 AMPCOMP_SW_EN [26:26] Internal. Only to be used through TI provided API. 1 26 RESERVED24 [25:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 24 IBIAS_OFFSET [23:20] Internal. Only to be used through TI provided API. 4 20 IBIAS_INIT [19:16] Internal. Only to be used through TI provided API. 4 16 LPM_IBIAS_WAIT_CNT_FINAL [15:8] Internal. Only to be used through TI provided API. 8 8 CAP_STEP [7:4] Internal. Only to be used through TI provided API. 4 4 IBIASCAP_HPTOLP_OL_CNT [3:0] Internal. Only to be used through TI provided API. 4 0 0x0 AMPCOMPTH1 0x10 32 Amplitude Compensation Threshold 1 This register contains threshold values for amplitude compensation algorithm SPARE24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 HPMRAMP3_LTH [23:18] Internal. Only to be used through TI provided API. 6 18 SPARE16 [17:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 16 HPMRAMP3_HTH [15:10] Internal. Only to be used through TI provided API. 6 10 IBIASCAP_LPTOHP_OL_CNT [9:6] Internal. Only to be used through TI provided API. 4 6 HPMRAMP1_TH [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 AMPCOMPTH2 0x14 32 Amplitude Compensation Threshold 2 This register contains threshold values for amplitude compensation algorithm. LPMUPDATE_LTH [31:26] Internal. Only to be used through TI provided API. 6 26 SPARE24 [25:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 24 LPMUPDATE_HTH [23:18] Internal. Only to be used through TI provided API. 6 18 SPARE16 [17:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 16 ADC_COMP_AMPTH_LPM [15:10] Internal. Only to be used through TI provided API. 6 10 SPARE8 [9:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 8 ADC_COMP_AMPTH_HPM [7:2] Internal. Only to be used through TI provided API. 6 2 SPARE0 [1:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 0 0x0 ANABYPASSVAL1 0x18 32 Analog Bypass Values 1 RESERVED20 [31:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 20 XOSC_HF_ROW_Q12 [19:16] Internal. Only to be used through TI provided API. 4 16 XOSC_HF_COLUMN_Q12 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 ANABYPASSVAL2 0x1c 32 Internal. Only to be used through TI provided API. RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 XOSC_HF_IBIASTHERM [13:0] Internal. Only to be used through TI provided API. 14 0 0x0 ATESTCTL 0x20 32 Analog Test Control SCLK_LF_AUX_EN [31:31] Enable 32 kHz clock to AUX_COMPB. 1 31 RESERVED16 [30:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 16 TEST_RCOSCMF [15:14] Test mode control for RCOSC_MF 0x0: test modes disabled 0x1: boosted bias current into self biased inverter 0x2: clock qualification disabled 0x3: boosted bias current into self biased inverter + clock qualification disabled 2 14 ATEST_RCOSCMF [13:12] ATEST control for RCOSC_MF 0x0: ATEST disabled 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* enabled to send out 2MHz clock. 0x2: ATEST disabled 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* enabled to send out 2MHz clock. 2 12 RESERVED0 [11:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 0 0x0 ADCDOUBLERNANOAMPCTL 0x24 32 ADC Doubler Nanoamp Control RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 NANOAMP_BIAS_ENABLE [24:24] Internal. Only to be used through TI provided API. 1 24 SPARE23 [23:23] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior 1 23 RESERVED6 [22:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 6 ADC_SH_MODE_EN [5:5] Internal. Only to be used through TI provided API. 1 5 ADC_SH_VBUF_EN [4:4] Internal. Only to be used through TI provided API. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 ADC_IREF_CTRL [1:0] Internal. Only to be used through TI provided API. 2 0 0x0 XOSCHFCTL 0x28 32 XOSCHF Control SPARE14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 TCXO_MODE_XOSC_HF_EN [13:13] If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input. 1 13 TCXO_MODE [12:12] If this register is 1 when BYPASS is 1, this will enable clock qualification on the TCXO clock on external input. This register has no effect when BYPASS is 0. 1 12 RESERVED10 [11:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 10 PEAK_DET_ITRIM [9:8] Internal. Only to be used through TI provided API. 2 8 RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 BYPASS [6:6] Internal. Only to be used through TI provided API. 1 6 RESERVED5 [5:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 5 HP_BUF_ITRIM [4:2] Internal. Only to be used through TI provided API. 3 2 LP_BUF_ITRIM [1:0] Internal. Only to be used through TI provided API. 2 0 0x0 LFOSCCTL 0x2c 32 Low Frequency Oscillator Control RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 XOSCLF_REGULATOR_TRIM [23:22] Internal. Only to be used through TI provided API. 2 22 XOSCLF_CMIRRWR_RATIO [21:18] Internal. Only to be used through TI provided API. 4 18 RESERVED10 [17:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 10 RCOSCLF_RTUNE_TRIM [9:8] Internal. Only to be used through TI provided API. 2 8 6P0MEG 3 Internal. Only to be used through TI provided API. 6P5MEG 2 Internal. Only to be used through TI provided API. 7P0MEG 1 Internal. Only to be used through TI provided API. 7P5MEG 0 Internal. Only to be used through TI provided API. RCOSCLF_CTUNE_TRIM [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 RCOSCHFCTL 0x30 32 RCOSCHF Control RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 RCOSCHF_CTRIM [15:8] Internal. Only to be used through TI provided API. 8 8 RESERVED0 [7:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 0 0x0 RCOSCMFCTL 0x34 32 RCOSC_MF Control SPARE16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 RCOSC_MF_CAP_ARRAY [15:9] Adjust RCOSC_MF capacitor array. 0x0: nominal frequency, 0.625pF 0x40: highest frequency, 0.125pF 0x3F: lowest frequency, 1.125pF 7 9 RCOSC_MF_REG_SEL [8:8] Choose regulator type. 0: default 1: alternate 1 8 RCOSC_MF_RES_COARSE [7:6] Select coarse resistor for frequency adjustment. 0x0: 400kohms, default 0x1: 300kohms, min 0x2: 600kohms, max 0x3: 500kohms 2 6 RCOSC_MF_RES_FINE [5:4] Select fine resistor for frequency adjustment. 0x0: 11kohms, minimum resistance, max freq 0x1: 13kohms 0x2: 16kohms 0x3: 20kohms, max resistance, min freq 2 4 RCOSC_MF_BIAS_ADJ [3:0] Adjusts bias current to RCOSC_MF. 0x8 minimum current 0x0 default current 0x7 maximum current 4 0 0x0 STAT0 0x3c 32 Status 0 This register contains status signals from OSC_DIG SPARE31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 SCLK_LF_SRC [30:29] Indicates source for the sclk_lf 2 29 XOSCLF 3 Low frequency XOSC RCOSCLF 2 Low frequency RCOSC XOSCHFDLF 1 Low frequency clock derived from High Frequency XOSC RCOSCHFDLF 0 Low frequency clock derived from High Frequency RCOSC SCLK_HF_SRC [28:28] Indicates source for the sclk_hf 1 28 XOSC 1 High frequency XOSC RCOSC 0 High frequency RCOSC clock RESERVED23 [27:23] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 23 RCOSC_HF_EN [22:22] RCOSC_HF_EN 1 22 RCOSC_LF_EN [21:21] RCOSC_LF_EN 1 21 XOSC_LF_EN [20:20] XOSC_LF_EN 1 20 CLK_DCDC_RDY [19:19] CLK_DCDC_RDY 1 19 CLK_DCDC_RDY_ACK [18:18] CLK_DCDC_RDY_ACK 1 18 SCLK_HF_LOSS [17:17] Indicates sclk_hf is lost 1 17 SCLK_LF_LOSS [16:16] Indicates sclk_lf is lost 1 16 XOSC_HF_EN [15:15] Indicates that XOSC_HF is enabled. 1 15 RESERVED14 [14:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 14 XB_48M_CLK_EN [13:13] Indicates that the 48MHz clock from the DOUBLER is enabled. It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal). 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 XOSC_HF_LP_BUF_EN [11:11] XOSC_HF_LP_BUF_EN 1 11 XOSC_HF_HP_BUF_EN [10:10] XOSC_HF_HP_BUF_EN 1 10 RESERVED9 [9:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 9 ADC_THMET [8:8] ADC_THMET 1 8 ADC_DATA_READY [7:7] indicates when adc_data is ready. 1 7 ADC_DATA [6:1] adc_data 6 1 PENDINGSCLKHFSWITCHING [0:0] Indicates when SCLK_HF clock source is ready to be switched 1 0 0x0 STAT1 0x40 32 Status 1 This register contains status signals from OSC_DIG RAMPSTATE [31:28] AMPCOMP FSM State 4 28 FAST_START_SETTLE 14 FAST_START_SETTLE FAST_START 13 FAST_START DUMMY_TO_INIT_1 12 DUMMY_TO_INIT_1 IDAC_DEC_W_MEASURE 11 IDAC_DECREMENT_WITH_MEASURE IBIAS_INC 10 IBIAS_INCREMENT LPM_UPDATE 9 LPM_UPDATE IBIAS_DEC_W_MEASURE 8 IBIAS_DECREMENT_WITH_MEASURE IBIAS_CAP_UPDATE 7 IBIAS_CAP_UPDATE IDAC_INCREMENT 6 IDAC_INCREMENT HPM_UPDATE 5 HPM_UPDATE HPM_RAMP3 4 HPM_RAMP3 HPM_RAMP2 3 HPM_RAMP2 HPM_RAMP1 2 HPM_RAMP1 INITIALIZATION 1 INITIALIZATION RESET 0 RESET HPM_UPDATE_AMP [27:22] XOSC_HF amplitude during HPM_UPDATE state. When amplitude compensation of XOSC_HF is enabled in high performance mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value. 6 22 LPM_UPDATE_AMP [21:16] XOSC_HF amplitude during LPM_UPDATE state When amplitude compensation of XOSC_HF is enabled in low power mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value. 6 16 FORCE_RCOSC_HF [15:15] force_rcosc_hf 1 15 SCLK_HF_EN [14:14] SCLK_HF_EN 1 14 SCLK_MF_EN [13:13] SCLK_MF_EN 1 13 ACLK_ADC_EN [12:12] ACLK_ADC_EN 1 12 ACLK_TDC_EN [11:11] ACLK_TDC_EN 1 11 ACLK_REF_EN [10:10] ACLK_REF_EN 1 10 CLK_CHP_EN [9:9] CLK_CHP_EN 1 9 CLK_DCDC_EN [8:8] CLK_DCDC_EN 1 8 SCLK_HF_GOOD [7:7] SCLK_HF_GOOD 1 7 SCLK_MF_GOOD [6:6] SCLK_MF_GOOD 1 6 SCLK_LF_GOOD [5:5] SCLK_LF_GOOD 1 5 ACLK_ADC_GOOD [4:4] ACLK_ADC_GOOD 1 4 ACLK_TDC_GOOD [3:3] ACLK_TDC_GOOD 1 3 ACLK_REF_GOOD [2:2] ACLK_REF_GOOD. 1 2 CLK_CHP_GOOD [1:1] CLK_CHP_GOOD 1 1 CLK_DCDC_GOOD [0:0] CLK_DCDC_GOOD 1 0 0x0 STAT2 0x44 32 Status 2 This register contains status signals from AMPCOMP FSM ADC_DCBIAS [31:26] DC Bias read by RADC during SAR mode The value is an unsigned integer. It is used for debug only. 6 26 HPM_RAMP1_THMET [25:25] Indication of threshold is met for hpm_ramp1 1 25 HPM_RAMP2_THMET [24:24] Indication of threshold is met for hpm_ramp2 1 24 HPM_RAMP3_THMET [23:23] Indication of threshold is met for hpm_ramp3 1 23 RESERVED16 [22:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 16 RAMPSTATE [15:12] xosc_hf amplitude compensation FSM This is identical to STAT1.RAMPSTATE. See that description for encoding. 4 12 RESERVED4 [11:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 4 AMPCOMP_REQ [3:3] ampcomp_req 1 3 XOSC_HF_AMPGOOD [2:2] amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status 1 2 XOSC_HF_FREQGOOD [1:1] frequency of xosc_hf is good to use for the digital clocks 1 1 XOSC_HF_RF_FREQGOOD [0:0] frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. 1 0 0x0 EVENT 0x40083000 0 0x1000 registers Event Fabric Component Definition CPUIRQSEL0 0x0 32 Output Selection for CPU Interrupt 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 0x4 CPUIRQSEL1 0x4 32 Output Selection for CPU Interrupt 1 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 I2C_IRQ 9 Interrupt event from I2C 0x9 CPUIRQSEL2 0x8 32 Output Selection for CPU Interrupt 2 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 0x1E CPUIRQSEL3 0xc 32 Output Selection for CPU Interrupt 3 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 PKA_IRQ 31 PKA Interrupt event 0x1F CPUIRQSEL4 0x10 32 Output Selection for CPU Interrupt 4 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 0x7 CPUIRQSEL5 0x14 32 Output Selection for CPU Interrupt 5 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS 0x24 CPUIRQSEL6 0x18 32 Output Selection for CPU Interrupt 6 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_SWEV0 28 AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL 0x1C CPUIRQSEL7 0x1c 32 Output Selection for CPU Interrupt 7 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS 0x22 CPUIRQSEL8 0x20 32 Output Selection for CPU Interrupt 8 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS 0x23 CPUIRQSEL9 0x24 32 Output Selection for CPU Interrupt 9 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 0x1B CPUIRQSEL10 0x28 32 Output Selection for CPU Interrupt 10 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 0x1A CPUIRQSEL11 0x2c 32 Output Selection for CPU Interrupt 11 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 0x19 CPUIRQSEL12 0x30 32 Output Selection for CPU Interrupt 12 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 I2S_IRQ 8 Interrupt event from I2S 0x8 CPUIRQSEL13 0x34 32 Output Selection for CPU Interrupt 13 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_SWEV1 29 AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL 0x1D CPUIRQSEL14 0x38 32 Output Selection for CPU Interrupt 14 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 WDT_IRQ 24 Watchdog interrupt event, controlled by WDT:CTL.INTEN 0x18 CPUIRQSEL15 0x3c 32 Output Selection for CPU Interrupt 15 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT0A 16 GPT0A interrupt event, controlled by GPT0:TAMR 0x10 CPUIRQSEL16 0x40 32 Output Selection for CPU Interrupt 16 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT0B 17 GPT0B interrupt event, controlled by GPT0:TBMR 0x11 CPUIRQSEL17 0x44 32 Output Selection for CPU Interrupt 17 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT1A 18 GPT1A interrupt event, controlled by GPT1:TAMR 0x12 CPUIRQSEL18 0x48 32 Output Selection for CPU Interrupt 18 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT1B 19 GPT1B interrupt event, controlled by GPT1:TBMR 0x13 CPUIRQSEL19 0x4c 32 Output Selection for CPU Interrupt 19 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT2A 12 GPT2A interrupt event, controlled by GPT2:TAMR 0xC CPUIRQSEL20 0x50 32 Output Selection for CPU Interrupt 20 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT2B 13 GPT2B interrupt event, controlled by GPT2:TBMR 0xD CPUIRQSEL21 0x54 32 Output Selection for CPU Interrupt 21 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT3A 14 GPT3A interrupt event, controlled by GPT3:TAMR 0xE CPUIRQSEL22 0x58 32 Output Selection for CPU Interrupt 22 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT3B 15 GPT3B interrupt event, controlled by GPT3:TBMR 0xF CPUIRQSEL23 0x5c 32 Output Selection for CPU Interrupt 23 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 CRYPTO_RESULT_AVAIL_IRQ 93 CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL 0x5D CPUIRQSEL24 0x60 32 Output Selection for CPU Interrupt 24 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 DMA_DONE_COMB 39 Combined DMA done, corresponding flags are here UDMA0:REQDONE 0x27 CPUIRQSEL25 0x64 32 Output Selection for CPU Interrupt 25 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 DMA_ERR 38 DMA bus error, corresponds to UDMA0:ERROR.STATUS 0x26 CPUIRQSEL26 0x68 32 Output Selection for CPU Interrupt 26 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 0x15 CPUIRQSEL27 0x6c 32 Output Selection for CPU Interrupt 27 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV0 100 Software event 0, triggered by SWEV.SWEV0 0x64 CPUIRQSEL28 0x70 32 Output Selection for CPU Interrupt 28 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 0xB CPUIRQSEL29 0x74 32 Output Selection for CPU Interrupt 29 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AON_PROG0 1 AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 0x1 CPUIRQSEL30 0x78 32 Output Selection for CPU Interrupt 30 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV CRYPTO_DMA_DONE_IRQ 94 CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 DMA_CH18_DONE 22 DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ DMA_CH0_DONE 20 DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ AON_AUX_SWEV0 10 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 I2S_IRQ 8 Interrupt event from I2S AON_PROG2 3 AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV AON_PROG1 2 AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV NONE 0 Always inactive 0x0 CPUIRQSEL31 0x7c 32 Output Selection for CPU Interrupt 31 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 0x6A CPUIRQSEL32 0x80 32 Output Selection for CPU Interrupt 32 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 0x73 CPUIRQSEL33 0x84 32 Output Selection for CPU Interrupt 33 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 TRNG_IRQ 104 TRNG Interrupt event, controlled by TRNG:IRQEN.EN 0x68 CPUIRQSEL34 0x88 32 Output Selection for CPU Interrupt 34 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 OSC_COMB 6 Combined event from Oscillator control 0x6 CPUIRQSEL35 0x8c 32 Output Selection for CPU Interrupt 35 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 0x38 CPUIRQSEL36 0x90 32 Output Selection for CPU Interrupt 36 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS 0x25 CPUIRQSEL37 0x94 32 Output Selection for CPU Interrupt 37 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 BATMON_COMB 5 Combined event from battery monitor 0x5 RFCSEL0 0x100 32 Output Selection for RFC Event 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT 0x3D RFCSEL1 0x104 32 Output Selection for RFC Event 1 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT 0x3E RFCSEL2 0x108 32 Output Selection for RFC Event 2 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT 0x3F RFCSEL3 0x10c 32 Output Selection for RFC Event 3 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT 0x40 RFCSEL4 0x110 32 Output Selection for RFC Event 4 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT 0x41 RFCSEL5 0x114 32 Output Selection for RFC Event 5 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT 0x42 RFCSEL6 0x118 32 Output Selection for RFC Event 6 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT 0x43 RFCSEL7 0x11c 32 Output Selection for RFC Event 7 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT 0x44 RFCSEL8 0x120 32 Output Selection for RFC Event 8 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 0x77 RFCSEL9 0x124 32 Output Selection for RFC Event 9 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV SWEV1 101 Software event 1, triggered by SWEV.SWEV1 SWEV0 100 Software event 0, triggered by SWEV.SWEV0 CRYPTO_RESULT_AVAIL_IRQ 93 CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 DMA_DONE_COMB 39 Combined DMA done, corresponding flags are here UDMA0:REQDONE UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS WDT_IRQ 24 Watchdog interrupt event, controlled by WDT:CTL.INTEN AON_AUX_SWEV0 10 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 I2S_IRQ 8 Interrupt event from I2S AON_PROG1 2 AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV AON_PROG0 1 AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV NONE 0 Always inactive 0x2 GPT0ACAPTSEL 0x200 32 Output Selection for GPT0 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT1 86 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here. PORT_EVENT0 85 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x55 GPT0BCAPTSEL 0x204 32 Output Selection for GPT0 1 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT1 86 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here. PORT_EVENT0 85 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x56 GPT1ACAPTSEL 0x300 32 Output Selection for GPT1 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT3 88 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. PORT_EVENT2 87 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x57 GPT1BCAPTSEL 0x304 32 Output Selection for GPT1 1 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT3 88 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. PORT_EVENT2 87 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x58 GPT2ACAPTSEL 0x400 32 Output Selection for GPT2 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT5 90 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. PORT_EVENT4 89 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x59 GPT2BCAPTSEL 0x404 32 Output Selection for GPT2 1 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT5 90 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. PORT_EVENT4 89 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x5A UDMACH0SSEL 0x500 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH0BSEL 0x504 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH1SSEL 0x508 32 Output Selection for DMA Channel 1 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART0_RX_DMASREQ 49 UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE 0x31 UDMACH1BSEL 0x50c 32 Output Selection for DMA Channel 1 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART0_RX_DMABREQ 48 UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE 0x30 UDMACH2SSEL 0x510 32 Output Selection for DMA Channel 2 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART0_TX_DMASREQ 51 UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE 0x33 UDMACH2BSEL 0x514 32 Output Selection for DMA Channel 2 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART0_TX_DMABREQ 50 UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE 0x32 UDMACH3SSEL 0x518 32 Output Selection for DMA Channel 3 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI0_RX_DMASREQ 41 SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE 0x29 UDMACH3BSEL 0x51c 32 Output Selection for DMA Channel 3 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI0_RX_DMABREQ 40 SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE 0x28 UDMACH4SSEL 0x520 32 Output Selection for DMA Channel 4 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI0_TX_DMASREQ 43 SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE 0x2B UDMACH4BSEL 0x524 32 Output Selection for DMA Channel 4 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI0_TX_DMABREQ 42 SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE 0x2A UDMACH5SSEL 0x528 32 Output Selection for DMA Channel 5 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART1_RX_DMASREQ 53 UART1 RX DMA single request, controlled by UART1:DMACTL.RXDMAE 0x35 UDMACH5BSEL 0x52c 32 Output Selection for DMA Channel 5 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART1_RX_DMABREQ 52 UART1 RX DMA burst request, controlled by UART1:DMACTL.RXDMAE 0x34 UDMACH6SSEL 0x530 32 Output Selection for DMA Channel 6 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART1_TX_DMASREQ 55 UART1 TX DMA single request, controlled by UART1:DMACTL.TXDMAE 0x37 UDMACH6BSEL 0x534 32 Output Selection for DMA Channel 6 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 UART1_TX_DMABREQ 54 UART1 TX DMA burst request, controlled by UART1:DMACTL.TXDMAE 0x36 UDMACH7SSEL 0x538 32 Output Selection for DMA Channel 7 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_DMASREQ 117 DMA single request event from AUX, configured by AUX_EVCTL:DMACTL 0x75 UDMACH7BSEL 0x53c 32 Output Selection for DMA Channel 7 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_DMABREQ 118 DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL 0x76 UDMACH8SSEL 0x540 32 Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_SW_DMABREQ 116 DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START 0x74 UDMACH8BSEL 0x544 32 Output Selection for DMA Channel 8 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AUX_SW_DMABREQ 116 DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START 0x74 UDMACH9SSEL 0x548 32 Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV TIE_LOW 69 Not used tied to 0 NONE 0 Always inactive 0x45 UDMACH9BSEL 0x54c 32 Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV NONE 0 Always inactive 0x4D UDMACH10SSEL 0x550 32 Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV TIE_LOW 70 Not used tied to 0 NONE 0 Always inactive 0x46 UDMACH10BSEL 0x554 32 Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV NONE 0 Always inactive 0x4E UDMACH11SSEL 0x558 32 Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV TIE_LOW 71 Not used tied to 0 NONE 0 Always inactive 0x47 UDMACH11BSEL 0x55c 32 Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV NONE 0 Always inactive 0x4F UDMACH12SSEL 0x560 32 Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV TIE_LOW 72 Not used tied to 0 NONE 0 Always inactive 0x48 UDMACH12BSEL 0x564 32 Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV NONE 0 Always inactive 0x50 UDMACH13SSEL 0x568 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 AON_PROG2 3 AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 0x3 UDMACH13BSEL 0x56c 32 Output Selection for DMA Channel 13 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AON_PROG2 3 AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 0x3 UDMACH14SSEL 0x570 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 AON_PROG0 1 AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 0x1 UDMACH14BSEL 0x574 32 Output Selection for DMA Channel 14 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted CPU_HALTED 120 CPU halted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_DMABREQ 118 DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL AUX_DMASREQ 117 DMA single request event from AUX, configured by AUX_EVCTL:DMACTL AUX_SW_DMABREQ 116 DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV TRNG_IRQ 104 TRNG Interrupt event, controlled by TRNG:IRQEN.EN SWEV3 103 Software event 3, triggered by SWEV.SWEV3 SWEV2 102 Software event 2, triggered by SWEV.SWEV2 SWEV1 101 Software event 1, triggered by SWEV.SWEV1 SWEV0 100 Software event 0, triggered by SWEV.SWEV0 WDT_NMI 99 Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE CRYPTO_DMA_DONE_IRQ 94 CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE CRYPTO_RESULT_AVAIL_IRQ 93 CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL PORT_EVENT7 92 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here. PORT_EVENT6 91 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here. PORT_EVENT5 90 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. PORT_EVENT4 89 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. PORT_EVENT3 88 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. PORT_EVENT2 87 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. PORT_EVENT1 86 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here. PORT_EVENT0 85 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here. GPT3B_DMABREQ 84 GPT3B DMA trigger event. Configured by GPT3:DMAEV GPT3A_DMABREQ 83 GPT3A DMA trigger event. Configured by GPT3:DMAEV GPT2B_DMABREQ 82 GPT2B DMA trigger event. Configured by GPT2:DMAEV GPT2A_DMABREQ 81 GPT2A DMA trigger event. Configured by GPT2:DMAEV GPT1B_DMABREQ 80 GPT1B DMA trigger event. Configured by GPT1:DMAEV GPT1A_DMABREQ 79 GPT1A DMA trigger event. Configured by GPT1:DMAEV GPT0B_DMABREQ 78 GPT0B DMA trigger event. Configured by GPT0:DMAEV GPT0A_DMABREQ 77 GPT0A DMA trigger event. Configured by GPT0:DMAEV GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_TX_DMASREQ 55 UART1 TX DMA single request, controlled by UART1:DMACTL.TXDMAE UART1_TX_DMABREQ 54 UART1 TX DMA burst request, controlled by UART1:DMACTL.TXDMAE UART1_RX_DMASREQ 53 UART1 RX DMA single request, controlled by UART1:DMACTL.RXDMAE UART1_RX_DMABREQ 52 UART1 RX DMA burst request, controlled by UART1:DMACTL.RXDMAE UART0_TX_DMASREQ 51 UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE UART0_TX_DMABREQ 50 UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE UART0_RX_DMASREQ 49 UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE UART0_RX_DMABREQ 48 UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE SSI1_TX_DMASREQ 47 SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE SSI1_TX_DMABREQ 46 SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE SSI1_RX_DMASREQ 45 SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE SSI1_RX_DMABREQ 44 SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE SSI0_TX_DMASREQ 43 SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE SSI0_TX_DMABREQ 42 SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE SSI0_RX_DMASREQ 41 SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE SSI0_RX_DMABREQ 40 SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE DMA_DONE_COMB 39 Combined DMA done, corresponding flags are here UDMA0:REQDONE DMA_ERR 38 DMA bus error, corresponds to UDMA0:ERROR.STATUS UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS PKA_IRQ 31 PKA Interrupt event RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event AUX_SWEV1 29 AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG WDT_IRQ 24 Watchdog interrupt event, controlled by WDT:CTL.INTEN DMA_CH18_DONE 22 DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT DMA_CH0_DONE 20 DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ GPT1B 19 GPT1B interrupt event, controlled by GPT1:TBMR GPT1A 18 GPT1A interrupt event, controlled by GPT1:TAMR GPT0B 17 GPT0B interrupt event, controlled by GPT0:TBMR GPT0A 16 GPT0A interrupt event, controlled by GPT0:TAMR GPT3B 15 GPT3B interrupt event, controlled by GPT3:TBMR GPT3A 14 GPT3A interrupt event, controlled by GPT3:TAMR GPT2B 13 GPT2B interrupt event, controlled by GPT2:TBMR GPT2A 12 GPT2A interrupt event, controlled by GPT2:TAMR AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS AON_AUX_SWEV0 10 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 I2C_IRQ 9 Interrupt event from I2C I2S_IRQ 8 Interrupt event from I2S AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings AON_PROG2 3 AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV AON_PROG1 2 AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV AON_PROG0 1 AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV NONE 0 Always inactive 0x1 UDMACH15SSEL 0x578 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 0x7 UDMACH15BSEL 0x57c 32 Output Selection for DMA Channel 15 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 0x7 UDMACH16SSEL 0x580 32 Output Selection for DMA Channel 16 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI1_RX_DMASREQ 45 SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE 0x2D UDMACH16BSEL 0x584 32 Output Selection for DMA Channel 16 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI1_RX_DMABREQ 44 SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE 0x2C UDMACH17SSEL 0x588 32 Output Selection for DMA Channel 17 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI1_TX_DMASREQ 47 SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE 0x2F UDMACH17BSEL 0x58c 32 Output Selection for DMA Channel 17 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SSI1_TX_DMABREQ 46 SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE 0x2E UDMACH18SSEL 0x590 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH18BSEL 0x594 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH19SSEL 0x598 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH19BSEL 0x59c 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH20SSEL 0x5a0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH20BSEL 0x5a4 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH21SSEL 0x5a8 32 Output Selection for DMA Channel 21 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV0 100 Software event 0, triggered by SWEV.SWEV0 0x64 UDMACH21BSEL 0x5ac 32 Output Selection for DMA Channel 21 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV0 100 Software event 0, triggered by SWEV.SWEV0 0x64 UDMACH22SSEL 0x5b0 32 Output Selection for DMA Channel 22 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV1 101 Software event 1, triggered by SWEV.SWEV1 0x65 UDMACH22BSEL 0x5b4 32 Output Selection for DMA Channel 22 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV1 101 Software event 1, triggered by SWEV.SWEV1 0x65 UDMACH23SSEL 0x5b8 32 Output Selection for DMA Channel 23 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV2 102 Software event 2, triggered by SWEV.SWEV2 0x66 UDMACH23BSEL 0x5bc 32 Output Selection for DMA Channel 23 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV2 102 Software event 2, triggered by SWEV.SWEV2 0x66 UDMACH24SSEL 0x5c0 32 Output Selection for DMA Channel 24 SREQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV3 103 Software event 3, triggered by SWEV.SWEV3 0x67 UDMACH24BSEL 0x5c4 32 Output Selection for DMA Channel 24 REQ RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 SWEV3 103 Software event 3, triggered by SWEV.SWEV3 0x67 UDMACH25SSEL 0x5c8 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH25BSEL 0x5cc 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH26SSEL 0x5d0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH26BSEL 0x5d4 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH27SSEL 0x5d8 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH27BSEL 0x5dc 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH28SSEL 0x5e0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH28BSEL 0x5e4 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH29SSEL 0x5e8 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH29BSEL 0x5ec 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH30SSEL 0x5f0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH30BSEL 0x5f4 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH31SSEL 0x5f8 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 UDMACH31BSEL 0x5fc 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. EV [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 NONE 0 Always inactive 0x0 GPT3ACAPTSEL 0x600 32 Output Selection for GPT3 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT7 92 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here. PORT_EVENT6 91 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x5B GPT3BCAPTSEL 0x604 32 Output Selection for GPT3 1 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted AON_RTC_UPD 119 RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN AUX_ADC_IRQ 115 AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS AUX_OBSMUX0 114 Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 AUX_ADC_FIFO_ALMOST_FULL 113 AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL AUX_ADC_DONE 112 AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE AUX_SMPH_AUTOTAKE_DONE 111 Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE AUX_TIMER1_EV 110 AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV AUX_TIMER0_EV 109 AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV AUX_TDC_DONE 108 AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE AUX_COMPB 107 AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB AUX_COMPA 106 AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA AUX_AON_WU_EV 105 AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV PORT_EVENT7 92 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here. PORT_EVENT6 91 Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here. GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT AUX_TIMER2_PULSE 60 AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE AUX_TIMER2_EV3 59 AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 AUX_TIMER2_EV2 58 AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 AUX_TIMER2_EV1 57 AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 AUX_TIMER2_EV0 56 AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 UART1_COMB 37 UART1 combined interrupt, interrupt flags are found here UART1:MIS UART0_COMB 36 UART0 combined interrupt, interrupt flags are found here UART0:MIS SSI1_COMB 35 SSI1 combined interrupt, interrupt flags are found here SSI1:MIS SSI0_COMB 34 SSI0 combined interrupt, interrupt flags are found here SSI0:MIS RFC_CPE_1 30 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event RFC_CPE_0 27 Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event RFC_HW_COMB 26 Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG RFC_CMD_ACK 25 RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG FLASH 21 FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT AUX_COMB 11 AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS I2C_IRQ 9 Interrupt event from I2C AON_RTC_COMB 7 Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting OSC_COMB 6 Combined event from Oscillator control BATMON_COMB 5 Combined event from battery monitor AON_GPIO_EDGE 4 Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings NONE 0 Always inactive 0x5C AUXSEL0 0x700 32 Output Selection for AUX Subscriber 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted GPT3B_CMP 68 GPT3B compare event. Configured by GPT3:TBMR.TCACT GPT3A_CMP 67 GPT3A compare event. Configured by GPT3:TAMR.TCACT GPT2B_CMP 66 GPT2B compare event. Configured by GPT2:TBMR.TCACT GPT2A_CMP 65 GPT2A compare event. Configured by GPT2:TAMR.TCACT GPT1B_CMP 64 GPT1B compare event. Configured by GPT1:TBMR.TCACT GPT1A_CMP 63 GPT1A compare event. Configured by GPT1:TAMR.TCACT GPT0B_CMP 62 GPT0B compare event. Configured by GPT0:TBMR.TCACT GPT0A_CMP 61 GPT0A compare event. Configured by GPT0:TAMR.TCACT GPT1B 19 GPT1B interrupt event, controlled by GPT1:TBMR GPT1A 18 GPT1A interrupt event, controlled by GPT1:TAMR GPT0B 17 GPT0B interrupt event, controlled by GPT0:TBMR GPT0A 16 GPT0A interrupt event, controlled by GPT0:TAMR GPT3B 15 GPT3B interrupt event, controlled by GPT3:TBMR GPT3A 14 GPT3A interrupt event, controlled by GPT3:TAMR GPT2B 13 GPT2B interrupt event, controlled by GPT2:TBMR GPT2A 12 GPT2A interrupt event, controlled by GPT2:TAMR NONE 0 Always inactive 0x10 CM3NMISEL0 0x800 32 Output Selection for NMI Subscriber 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read only selection value 7 0 WDT_NMI 99 Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE 0x63 I2SSTMPSEL0 0x900 32 Output Selection for I2S Subscriber 0 RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted NONE 0 Always inactive 0x5F FRZSEL0 0xa00 32 Output Selection for FRZ Subscriber The halted debug signal is passed to peripherals such as the General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC. When the system CPU halts, the connected peripherals that have freeze enabled also halt. The programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal. RESERVED [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 EV [6:0] Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 7 0 ALWAYS_ACTIVE 121 Always asserted CPU_HALTED 120 CPU halted NONE 0 Always inactive 0x78 SWEV 0xf00 32 Set or Clear Software Events RESERVED3 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 SWEV3 [24:24] Writing "1" to this bit when the value is "0" triggers the Software 3 event. 1 24 RESERVED2 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 SWEV2 [16:16] Writing "1" to this bit when the value is "0" triggers the Software 2 event. 1 16 RESERVED1 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 SWEV1 [8:8] Writing "1" to this bit when the value is "0" triggers the Software 1 event. 1 8 RESERVED0 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 SWEV0 [0:0] Writing "1" to this bit when the value is "0" triggers the Software 0 event. 1 0 0x0 FCFG1 0x50001000 0 0x800 registers Factory configuration area (FCFG1) MISC_CONF_1 0xa0 32 Misc configurations RESERVED [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 DEVICE_MINOR_REV [7:0] HW minor revision number (a value of 0xFF shall be treated equally to 0x00). Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer. Value may change without warning. 8 0 0xFFFFFF00 MISC_CONF_2 0xa4 32 Internal. Only to be used through TI provided API. RESERVED [31:8] Internal. Only to be used through TI provided API. 24 8 HPOSC_COMP_P3 [7:0] Internal. Only to be used through TI provided API. 8 0 0xFFFFFF00 CONFIG_CC26_FE 0xc4 32 Internal. Only to be used through TI provided API. IFAMP_IB [31:28] Internal. Only to be used through TI provided API. 4 28 LNA_IB [27:24] Internal. Only to be used through TI provided API. 4 24 IFAMP_TRIM [23:19] Internal. Only to be used through TI provided API. 5 19 CTL_PA0_TRIM [18:14] Internal. Only to be used through TI provided API. 5 14 PATRIMCOMPLETE_N [13:13] Internal. Only to be used through TI provided API. 1 13 RSSITRIMCOMPLETE_N [12:12] Internal. Only to be used through TI provided API. 1 12 RESERVED [11:8] Internal. Only to be used through TI provided API. 4 8 RSSI_OFFSET [7:0] Internal. Only to be used through TI provided API. 8 0 0x70000F00 CONFIG_CC13_FE 0xc8 32 Internal. Only to be used through TI provided API. IFAMP_IB [31:28] Internal. Only to be used through TI provided API. 4 28 LNA_IB [27:24] Internal. Only to be used through TI provided API. 4 24 IFAMP_TRIM [23:19] Internal. Only to be used through TI provided API. 5 19 CTL_PA0_TRIM [18:14] Internal. Only to be used through TI provided API. 5 14 PATRIMCOMPLETE_N [13:13] Internal. Only to be used through TI provided API. 1 13 RSSITRIMCOMPLETE_N [12:12] Internal. Only to be used through TI provided API. 1 12 RESERVED [11:8] Internal. Only to be used through TI provided API. 4 8 RSSI_OFFSET [7:0] Internal. Only to be used through TI provided API. 8 0 0x70000F00 CONFIG_RF_COMMON 0xcc 32 Internal. Only to be used through TI provided API. DISABLE_CORNER_CAP [31:31] Internal. Only to be used through TI provided API. 1 31 SLDO_TRIM_OUTPUT [30:25] Internal. Only to be used through TI provided API. 6 25 RESERVED [24:22] Internal. Only to be used through TI provided API. 3 22 PA20DBMTRIMCOMPLETE_N [21:21] Internal. Only to be used through TI provided API. 1 21 CTL_PA_20DBM_TRIM [20:16] Internal. Only to be used through TI provided API. 5 16 RFLDO_TRIM_OUTPUT [15:9] Internal. Only to be used through TI provided API. 7 9 QUANTCTLTHRES [8:6] Internal. Only to be used through TI provided API. 3 6 DACTRIM [5:0] Internal. Only to be used through TI provided API. 6 0 0x1C0014D CONFIG_SYNTH_DIV2_CC26_2G4 0xd0 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV2_CC13_2G4 0xd4 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV2_CC26_1G 0xd8 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV2_CC13_1G 0xdc 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV4_CC26 0xe0 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV4_CC13 0xe4 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV5 0xe8 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV6_CC26 0xec 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV6_CC13 0xf0 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV10 0xf4 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV12_CC26 0xf8 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV12_CC13 0xfc 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV15 0x100 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F CONFIG_SYNTH_DIV30 0x104 32 Internal. Only to be used through TI provided API. MIN_ALLOWED_RTRIM [31:28] Internal. Only to be used through TI provided API. 4 28 RFC_MDM_DEMIQMC0 [27:12] Internal. Only to be used through TI provided API. 16 12 LDOVCO_TRIM_OUTPUT [11:6] Internal. Only to be used through TI provided API. 6 6 RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N [5:5] Internal. Only to be used through TI provided API. 1 5 RESERVED [4:0] Internal. Only to be used through TI provided API. 5 0 0x1F FLASH_NUMBER 0x164 32 Flash information LOT_NUMBER [31:0] Number of the manufacturing lot that produced this unit. 32 0 0x0 FLASH_COORDINATE 0x16c 32 Flash information XCOORDINATE [31:16] X coordinate of this unit on the wafer. 16 16 YCOORDINATE [15:0] Y coordinate of this unit on the wafer. 16 0 0x0 FLASH_E_P 0x170 32 Internal. Only to be used through TI provided API. PSU [31:24] Internal. Only to be used through TI provided API. 8 24 ESU [23:16] Internal. Only to be used through TI provided API. 8 16 PVSU [15:8] Internal. Only to be used through TI provided API. 8 8 EVSU [7:0] Internal. Only to be used through TI provided API. 8 0 0x4C644C64 FLASH_C_E_P_R 0x174 32 Internal. Only to be used through TI provided API. RVSU [31:24] Internal. Only to be used through TI provided API. 8 24 PV_ACCESS [23:16] Internal. Only to be used through TI provided API. 8 16 A_EXEZ_SETUP [15:12] Internal. Only to be used through TI provided API. 4 12 CVSU [11:0] Internal. Only to be used through TI provided API. 12 0 0xA0A2000 FLASH_P_R_PV 0x178 32 Internal. Only to be used through TI provided API. PH [31:24] Internal. Only to be used through TI provided API. 8 24 RH [23:16] Internal. Only to be used through TI provided API. 8 16 PVH [15:8] Internal. Only to be used through TI provided API. 8 8 PVH2 [7:0] Internal. Only to be used through TI provided API. 8 0 0x2C10200 FLASH_EH_SEQ 0x17c 32 Internal. Only to be used through TI provided API. EH [31:24] Internal. Only to be used through TI provided API. 8 24 SEQ [23:16] Internal. Only to be used through TI provided API. 8 16 VSTAT [15:12] Internal. Only to be used through TI provided API. 4 12 SM_FREQUENCY [11:0] Internal. Only to be used through TI provided API. 12 0 0x200F000 FLASH_VHV_E 0x180 32 Internal. Only to be used through TI provided API. VHV_E_START [31:16] Internal. Only to be used through TI provided API. 16 16 VHV_E_STEP_HIGHT [15:0] Internal. Only to be used through TI provided API. 16 0 0x1 FLASH_PP 0x184 32 Internal. Only to be used through TI provided API. PUMP_SU [31:24] Internal. Only to be used through TI provided API. 8 24 TRIM3P4 [23:16] Internal. Only to be used through TI provided API. 8 16 MAX_PP [15:0] Internal. Only to be used through TI provided API. 16 0 0x14 FLASH_PROG_EP 0x188 32 Internal. Only to be used through TI provided API. MAX_EP [31:16] Internal. Only to be used through TI provided API. 16 16 PROGRAM_PW [15:0] Internal. Only to be used through TI provided API. 16 0 0xFA00010 FLASH_ERA_PW 0x18c 32 Internal. Only to be used through TI provided API. ERASE_PW [31:0] Internal. Only to be used through TI provided API. 32 0 0xFA0 FLASH_VHV 0x190 32 Internal. Only to be used through TI provided API. RESERVED3 [31:28] Internal. Only to be used through TI provided API. 4 28 TRIM13_P [27:24] Internal. Only to be used through TI provided API. 4 24 RESERVED2 [23:20] Internal. Only to be used through TI provided API. 4 20 VHV_P [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED1 [15:12] Internal. Only to be used through TI provided API. 4 12 TRIM13_E [11:8] Internal. Only to be used through TI provided API. 4 8 RESERVED0 [7:4] Internal. Only to be used through TI provided API. 4 4 VHV_E [3:0] Internal. Only to be used through TI provided API. 4 0 0x4 FLASH_VHV_PV 0x194 32 Internal. Only to be used through TI provided API. RESERVED1 [31:28] Internal. Only to be used through TI provided API. 4 28 TRIM13_PV [27:24] Internal. Only to be used through TI provided API. 4 24 RESERVED0 [23:20] Internal. Only to be used through TI provided API. 4 20 VHV_PV [19:16] Internal. Only to be used through TI provided API. 4 16 VCG2P5 [15:8] Internal. Only to be used through TI provided API. 8 8 VINH [7:0] Internal. Only to be used through TI provided API. 8 0 0x80001 FLASH_V 0x198 32 Internal. Only to be used through TI provided API. VSL_P [31:24] Internal. Only to be used through TI provided API. 8 24 VWL_P [23:16] Internal. Only to be used through TI provided API. 8 16 V_READ [15:8] Internal. Only to be used through TI provided API. 8 8 TRIM0P8 [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 USER_ID 0x294 32 User Identification. Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device. The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone. PG_REV [31:28] Field used to distinguish revisions of the device 4 28 VER [27:26] Version number. 0x0: Bits [25:12] of this register has the stated meaning. Any other setting indicate a different encoding of these bits. 2 26 PA [25:25] 0: Does not support 20dBm PA 1: Supports 20dBM PA 1 25 RESERVED24 [24:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 24 CC13 [23:23] 0: CC26xx device type 1: CC13xx device type 1 23 SEQUENCE [22:19] Sequence. Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range, flash size, voltage range etc) 4 19 PKG [18:16] Package type. 0x0: 4x4mm QFN (RHB) package 0x1: 5x5mm QFN (RSM) package 0x2: 7x7mm QFN (RGZ) package 0x3: Wafer sale package (naked die) 0x4: WCSP (YFV) 0x5: 7x7mm QFN package with Wettable Flanks Other values are reserved for future use. Packages available for a specific device are shown in the device datasheet. 3 16 PROTOCOL [15:12] Protocols supported. 0x1: BLE 0x2: RF4CE 0x4: Zigbee/6lowpan 0x8: Proprietary More than one protocol can be supported on same device - values above are then combined. 4 12 RESERVED0 [11:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 0 0x30000000 FLASH_OTP_DATA3 0x2b0 32 Internal. Only to be used through TI provided API. EC_STEP_SIZE [31:23] Internal. Only to be used through TI provided API. 9 23 DO_PRECOND [22:22] Internal. Only to be used through TI provided API. 1 22 MAX_EC_LEVEL [21:18] Internal. Only to be used through TI provided API. 4 18 TRIM_1P7 [17:16] Internal. Only to be used through TI provided API. 2 16 FLASH_SIZE [15:8] Internal. Only to be used through TI provided API. 8 8 WAIT_SYSCODE [7:0] Internal. Only to be used through TI provided API. 8 0 0x110003 ANA2_TRIM 0x2b4 32 Internal. Only to be used through TI provided API. RCOSCHFCTRIMFRACT_EN [31:31] Internal. Only to be used through TI provided API. 1 31 RCOSCHFCTRIMFRACT [30:26] Internal. Only to be used through TI provided API. 5 26 RESERVED0 [25:25] Internal. Only to be used through TI provided API. 1 25 SET_RCOSC_HF_FINE_RESISTOR [24:23] Internal. Only to be used through TI provided API. 2 23 ATESTLF_UDIGLDO_IBIAS_TRIM [22:22] Internal. Only to be used through TI provided API. 1 22 NANOAMP_RES_TRIM [21:15] Internal. Only to be used through TI provided API. 7 15 RESERVED1 [14:12] Internal. Only to be used through TI provided API. 3 12 DITHER_EN [11:11] Internal. Only to be used through TI provided API. 1 11 DCDC_IPEAK [10:8] Internal. Only to be used through TI provided API. 3 8 DEAD_TIME_TRIM [7:6] Internal. Only to be used through TI provided API. 2 6 DCDC_LOW_EN_SEL [5:3] Internal. Only to be used through TI provided API. 3 3 DCDC_HIGH_EN_SEL [2:0] Internal. Only to be used through TI provided API. 3 0 0x8240787F LDO_TRIM 0x2b8 32 Internal. Only to be used through TI provided API. RESERVED4 [31:29] Internal. Only to be used through TI provided API. 3 29 VDDR_TRIM_SLEEP [28:24] Internal. Only to be used through TI provided API. 5 24 RESERVED3 [23:19] Internal. Only to be used through TI provided API. 5 19 GLDO_CURSRC [18:16] Internal. Only to be used through TI provided API. 3 16 RESERVED2 [15:13] Internal. Only to be used through TI provided API. 3 13 ITRIM_DIGLDO_LOAD [12:11] Internal. Only to be used through TI provided API. 2 11 ITRIM_UDIGLDO [10:8] Internal. Only to be used through TI provided API. 3 8 RESERVED1 [7:3] Internal. Only to be used through TI provided API. 5 3 VTRIM_DELTA [2:0] Internal. Only to be used through TI provided API. 3 0 0xE0F8E0FB MAC_BLE_0 0x2e8 32 MAC BLE Address 0 ADDR_0_31 [31:0] The first 32-bits of the 64-bit MAC BLE address 32 0 0x0 MAC_BLE_1 0x2ec 32 MAC BLE Address 1 ADDR_32_63 [31:0] The last 32-bits of the 64-bit MAC BLE address 32 0 0x0 MAC_15_4_0 0x2f0 32 MAC IEEE 802.15.4 Address 0 ADDR_0_31 [31:0] The first 32-bits of the 64-bit MAC 15.4 address 32 0 0x0 MAC_15_4_1 0x2f4 32 MAC IEEE 802.15.4 Address 1 ADDR_32_63 [31:0] The last 32-bits of the 64-bit MAC 15.4 address 32 0 0x0 FLASH_OTP_DATA4 0x308 32 Internal. Only to be used through TI provided API. STANDBY_MODE_SEL_INT_WRT [31:31] Internal. Only to be used through TI provided API. 1 31 STANDBY_PW_SEL_INT_WRT [30:29] Internal. Only to be used through TI provided API. 2 29 DIS_STANDBY_INT_WRT [28:28] Internal. Only to be used through TI provided API. 1 28 DIS_IDLE_INT_WRT [27:27] Internal. Only to be used through TI provided API. 1 27 VIN_AT_X_INT_WRT [26:24] Internal. Only to be used through TI provided API. 3 24 STANDBY_MODE_SEL_EXT_WRT [23:23] Internal. Only to be used through TI provided API. 1 23 STANDBY_PW_SEL_EXT_WRT [22:21] Internal. Only to be used through TI provided API. 2 21 DIS_STANDBY_EXT_WRT [20:20] Internal. Only to be used through TI provided API. 1 20 DIS_IDLE_EXT_WRT [19:19] Internal. Only to be used through TI provided API. 1 19 VIN_AT_X_EXT_WRT [18:16] Internal. Only to be used through TI provided API. 3 16 STANDBY_MODE_SEL_INT_RD [15:15] Internal. Only to be used through TI provided API. 1 15 STANDBY_PW_SEL_INT_RD [14:13] Internal. Only to be used through TI provided API. 2 13 DIS_STANDBY_INT_RD [12:12] Internal. Only to be used through TI provided API. 1 12 DIS_IDLE_INT_RD [11:11] Internal. Only to be used through TI provided API. 1 11 VIN_AT_X_INT_RD [10:8] Internal. Only to be used through TI provided API. 3 8 STANDBY_MODE_SEL_EXT_RD [7:7] Internal. Only to be used through TI provided API. 1 7 STANDBY_PW_SEL_EXT_RD [6:5] Internal. Only to be used through TI provided API. 2 5 DIS_STANDBY_EXT_RD [4:4] Internal. Only to be used through TI provided API. 1 4 DIS_IDLE_EXT_RD [3:3] Internal. Only to be used through TI provided API. 1 3 VIN_AT_X_EXT_RD [2:0] Internal. Only to be used through TI provided API. 3 0 0x98989F9F MISC_TRIM 0x30c 32 Miscellaneous Trim Parameters RESERVED [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 TRIM_RECHARGE_COMP_OFFSET [16:12] Internal. Only to be used through TI provided API. 5 12 TRIM_RECHARGE_COMP_REFLEVEL [11:8] Internal. Only to be used through TI provided API. 4 8 TEMPVSLOPE [7:0] Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits. 8 0 0xFFFE003B RCOSC_HF_TEMPCOMP 0x310 32 Internal. Only to be used through TI provided API. FINE_RESISTOR [31:24] Internal. Only to be used through TI provided API. 8 24 CTRIM [23:16] Internal. Only to be used through TI provided API. 8 16 CTRIMFRACT_QUAD [15:8] Internal. Only to be used through TI provided API. 8 8 CTRIMFRACT_SLOPE [7:0] Internal. Only to be used through TI provided API. 8 0 0x3 ICEPICK_DEVICE_ID 0x318 32 IcePick Device Identification Reading this register and the FCFG1:USER_ID register is the only supported way of identifying a device. PG_REV [31:28] Field used to distinguish revisions of the device. 4 28 WAFER_ID [27:12] Field used to identify silicon die. 16 12 MANUFACTURER_ID [11:0] Manufacturer code. 0x02F: Texas Instruments 12 0 0x3BB4102F FCFG1_REVISION 0x31c 32 Factory Configuration (FCFG1) Revision REV [31:0] The revision number of the FCFG1 layout. This value will be read by application SW in order to determine which FCFG1 parameters that have valid values. This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices. Value migth change without warning. 32 0 0x28 MISC_OTP_DATA 0x320 32 Misc OTP Data RCOSC_HF_ITUNE [31:28] Internal. Only to be used through TI provided API. 4 28 RCOSC_HF_CRIM [27:20] Internal. Only to be used through TI provided API. 8 20 PER_M [19:15] Internal. Only to be used through TI provided API. 5 15 PER_E [14:12] Internal. Only to be used through TI provided API. 3 12 RESERVED [11:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 8 TEST_PROGRAM_REV [7:0] The revision of the test program used in the production process when FCFG1 was programmed. Value migth change without warning. 8 0 0xCF00 IOCONF 0x344 32 IO Configuration RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 GPIO_CNT [6:0] Number of available DIOs. 7 0 0xFFFFFF00 CONFIG_IF_ADC 0x34c 32 Internal. Only to be used through TI provided API. FF2ADJ [31:28] Internal. Only to be used through TI provided API. 4 28 FF3ADJ [27:24] Internal. Only to be used through TI provided API. 4 24 INT3ADJ [23:20] Internal. Only to be used through TI provided API. 4 20 FF1ADJ [19:16] Internal. Only to be used through TI provided API. 4 16 AAFCAP [15:14] Internal. Only to be used through TI provided API. 2 14 INT2ADJ [13:10] Internal. Only to be used through TI provided API. 4 10 IFDIGLDO_TRIM_OUTPUT [9:5] Internal. Only to be used through TI provided API. 5 5 IFANALDO_TRIM_OUTPUT [4:0] Internal. Only to be used through TI provided API. 5 0 0x3460F400 CONFIG_OSC_TOP 0x350 32 Internal. Only to be used through TI provided API. RESERVED [31:30] Internal. Only to be used through TI provided API. 2 30 XOSC_HF_ROW_Q12 [29:26] Internal. Only to be used through TI provided API. 4 26 XOSC_HF_COLUMN_Q12 [25:10] Internal. Only to be used through TI provided API. 16 10 RCOSCLF_CTUNE_TRIM [9:2] Internal. Only to be used through TI provided API. 8 2 RCOSCLF_RTUNE_TRIM [1:0] Internal. Only to be used through TI provided API. 2 0 0xDC07FC00 SOC_ADC_ABS_GAIN 0x35c 32 AUX_ADC Gain in Absolute Reference Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SOC_ADC_ABS_GAIN_TEMP1 [15:0] SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated in production test.. 16 0 0x0 SOC_ADC_REL_GAIN 0x360 32 AUX_ADC Gain in Relative Reference Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SOC_ADC_REL_GAIN_TEMP1 [15:0] SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated in production test.. 16 0 0x0 SOC_ADC_OFFSET_INT 0x368 32 AUX_ADC Temperature Offsets in Absolute Reference Mode RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 SOC_ADC_REL_OFFSET_TEMP1 [23:16] SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test.. 8 16 RESERVED8 [15:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 8 SOC_ADC_ABS_OFFSET_TEMP1 [7:0] SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test.. 8 0 0x0 SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x36c 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 [5:0] Internal. Only to be used through TI provided API. 6 0 0xC080 AMPCOMP_TH1 0x370 32 Internal. Only to be used through TI provided API. RESERVED1 [31:24] Internal. Only to be used through TI provided API. 8 24 HPMRAMP3_LTH [23:18] Internal. Only to be used through TI provided API. 6 18 RESERVED0 [17:16] Internal. Only to be used through TI provided API. 2 16 HPMRAMP3_HTH [15:10] Internal. Only to be used through TI provided API. 6 10 IBIASCAP_LPTOHP_OL_CNT [9:6] Internal. Only to be used through TI provided API. 4 6 HPMRAMP1_TH [5:0] Internal. Only to be used through TI provided API. 6 0 0xFF7B828E AMPCOMP_TH2 0x374 32 Internal. Only to be used through TI provided API. LPMUPDATE_LTH [31:26] Internal. Only to be used through TI provided API. 6 26 RESERVED3 [25:24] Internal. Only to be used through TI provided API. 2 24 LPMUPDATE_HTM [23:18] Internal. Only to be used through TI provided API. 6 18 RESERVED2 [17:16] Internal. Only to be used through TI provided API. 2 16 ADC_COMP_AMPTH_LPM [15:10] Internal. Only to be used through TI provided API. 6 10 RESERVED1 [9:8] Internal. Only to be used through TI provided API. 2 8 ADC_COMP_AMPTH_HPM [7:2] Internal. Only to be used through TI provided API. 6 2 RESERVED0 [1:0] Internal. Only to be used through TI provided API. 2 0 0x6B8B0303 AMPCOMP_CTRL1 0x378 32 Internal. Only to be used through TI provided API. RESERVED1 [31:31] Internal. Only to be used through TI provided API. 1 31 AMPCOMP_REQ_MODE [30:30] Internal. Only to be used through TI provided API. 1 30 RESERVED0 [29:24] Internal. Only to be used through TI provided API. 6 24 IBIAS_OFFSET [23:20] Internal. Only to be used through TI provided API. 4 20 IBIAS_INIT [19:16] Internal. Only to be used through TI provided API. 4 16 LPM_IBIAS_WAIT_CNT_FINAL [15:8] Internal. Only to be used through TI provided API. 8 8 CAP_STEP [7:4] Internal. Only to be used through TI provided API. 4 4 IBIASCAP_HPTOLP_OL_CNT [3:0] Internal. Only to be used through TI provided API. 4 0 0xFF483F47 ANABYPASS_VALUE2 0x37c 32 Internal. Only to be used through TI provided API. RESERVED [31:14] Internal. Only to be used through TI provided API. 18 14 XOSC_HF_IBIASTHERM [13:0] Internal. Only to be used through TI provided API. 14 0 0xFFFFC3FF VOLT_TRIM 0x388 32 Internal. Only to be used through TI provided API. RESERVED3 [31:29] Internal. Only to be used through TI provided API. 3 29 VDDR_TRIM_HH [28:24] Internal. Only to be used through TI provided API. 5 24 RESERVED2 [23:21] Internal. Only to be used through TI provided API. 3 21 VDDR_TRIM_H [20:16] Internal. Only to be used through TI provided API. 5 16 RESERVED1 [15:13] Internal. Only to be used through TI provided API. 3 13 VDDR_TRIM_SLEEP_H [12:8] Internal. Only to be used through TI provided API. 5 8 RESERVED0 [7:5] Internal. Only to be used through TI provided API. 3 5 TRIMBOD_H [4:0] Internal. Only to be used through TI provided API. 5 0 0xE0E0E0E0 OSC_CONF 0x38c 32 OSC Configuration RESERVED1 [31:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 30 ADC_SH_VBUF_EN [29:29] Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. 1 29 ADC_SH_MODE_EN [28:28] Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. 1 28 ATESTLF_RCOSCLF_IBIAS_TRIM [27:27] Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. 1 27 XOSCLF_REGULATOR_TRIM [26:25] Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. 2 25 XOSCLF_CMIRRWR_RATIO [24:21] Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. 4 21 XOSC_HF_FAST_START [20:19] Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. 2 19 XOSC_OPTION [18:18] 0: XOSC_HF unavailable (may not be bonded out) 1: XOSC_HF available (default) 1 18 HPOSC_OPTION [17:17] Internal. Only to be used through TI provided API. 1 17 HPOSC_BIAS_HOLD_MODE_EN [16:16] Internal. Only to be used through TI provided API. 1 16 HPOSC_CURRMIRR_RATIO [15:12] Internal. Only to be used through TI provided API. 4 12 HPOSC_BIAS_RES_SET [11:8] Internal. Only to be used through TI provided API. 4 8 HPOSC_FILTER_EN [7:7] Internal. Only to be used through TI provided API. 1 7 HPOSC_BIAS_RECHARGE_DELAY [6:5] Internal. Only to be used through TI provided API. 2 5 RESERVED2 [4:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 3 HPOSC_SERIES_CAP [2:1] Internal. Only to be used through TI provided API. 2 1 HPOSC_DIV3_BYPASS [0:0] Internal. Only to be used through TI provided API. 1 0 0xF00900E6 FREQ_OFFSET 0x390 32 Internal. Only to be used through TI provided API. HPOSC_COMP_P0 [31:16] Internal. Only to be used through TI provided API. 16 16 HPOSC_COMP_P1 [15:8] Internal. Only to be used through TI provided API. 8 8 HPOSC_COMP_P2 [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 MISC_OTP_DATA_1 0x398 32 Internal. Only to be used through TI provided API. RESERVED [31:29] Internal. Only to be used through TI provided API. 3 29 PEAK_DET_ITRIM [28:27] Internal. Only to be used through TI provided API. 2 27 HP_BUF_ITRIM [26:24] Internal. Only to be used through TI provided API. 3 24 LP_BUF_ITRIM [23:22] Internal. Only to be used through TI provided API. 2 22 DBLR_LOOP_FILTER_RESET_VOLTAGE [21:20] Internal. Only to be used through TI provided API. 2 20 HPM_IBIAS_WAIT_CNT [19:10] Internal. Only to be used through TI provided API. 10 10 LPM_IBIAS_WAIT_CNT [9:4] Internal. Only to be used through TI provided API. 6 4 IDAC_STEP [3:0] Internal. Only to be used through TI provided API. 4 0 0xE08403F8 SHDW_DIE_ID_0 0x3d0 32 Shadow of DIE_ID_0 register in eFuse ID_31_0 [31:0] Shadow of DIE_ID_0 register in eFuse row number 5 32 0 0x0 SHDW_DIE_ID_1 0x3d4 32 Shadow of DIE_ID_1 register in eFuse ID_63_32 [31:0] Shadow of DIE_ID_1 register in eFuse row number 6 32 0 0x0 SHDW_DIE_ID_2 0x3d8 32 Shadow of DIE_ID_2 register in eFuse ID_95_64 [31:0] Shadow of DIE_ID_2 register in eFuse row number 7 32 0 0x0 SHDW_DIE_ID_3 0x3dc 32 Shadow of DIE_ID_3 register in eFuse ID_127_96 [31:0] Shadow of DIE_ID_3 register in eFuse row number 8 32 0 0x0 SHDW_OSC_BIAS_LDO_TRIM 0x3f8 32 Internal. Only to be used through TI provided API. RESERVED [31:27] Internal. Only to be used through TI provided API. 5 27 TRIMMAG [26:23] Internal. Only to be used through TI provided API. 4 23 TRIMIREF [22:18] Internal. Only to be used through TI provided API. 5 18 ITRIM_DIG_LDO [17:16] Internal. Only to be used through TI provided API. 2 16 VTRIM_DIG [15:12] Internal. Only to be used through TI provided API. 4 12 VTRIM_COARSE [11:8] Internal. Only to be used through TI provided API. 4 8 RCOSCHF_CTRIM [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 SHDW_ANA_TRIM 0x3fc 32 Internal. Only to be used through TI provided API. RESERVED [31:27] Internal. Only to be used through TI provided API. 5 27 BOD_BANDGAP_TRIM_CNF [26:25] Internal. Only to be used through TI provided API. 2 25 VDDR_ENABLE_PG1 [24:24] Internal. Only to be used through TI provided API. 1 24 VDDR_OK_HYS [23:23] Internal. Only to be used through TI provided API. 1 23 IPTAT_TRIM [22:21] Internal. Only to be used through TI provided API. 2 21 VDDR_TRIM [20:16] Internal. Only to be used through TI provided API. 5 16 TRIMBOD_INTMODE [15:11] Internal. Only to be used through TI provided API. 5 11 TRIMBOD_EXTMODE [10:6] Internal. Only to be used through TI provided API. 5 6 TRIMTEMP [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 DAC_BIAS_CNF 0x40c 32 Internal. Only to be used through TI provided API. RESERVED [31:18] Internal. Only to be used through TI provided API. 14 18 LPM_TRIM_IOUT [17:12] Internal. Only to be used through TI provided API. 6 12 LPM_BIAS_WIDTH_TRIM [11:9] Internal. Only to be used through TI provided API. 3 9 LPM_BIAS_BACKUP_EN [8:8] Internal. Only to be used through TI provided API. 1 8 RESERVED1 [7:0] Internal. Only to be used through TI provided API. 8 0 0xFFFC00FF TFW_PROBE 0x418 32 Internal. Only to be used through TI provided API. REV [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 TFW_FT 0x41c 32 Internal. Only to be used through TI provided API. REV [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 DAC_CAL0 0x420 32 Internal. Only to be used through TI provided API. SOC_DAC_VOUT_CAL_DECOUPLE_C2 [31:16] Internal. Only to be used through TI provided API. 16 16 SOC_DAC_VOUT_CAL_DECOUPLE_C1 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 DAC_CAL1 0x424 32 Internal. Only to be used through TI provided API. SOC_DAC_VOUT_CAL_PRECH_C2 [31:16] Internal. Only to be used through TI provided API. 16 16 SOC_DAC_VOUT_CAL_PRECH_C1 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 DAC_CAL2 0x428 32 Internal. Only to be used through TI provided API. SOC_DAC_VOUT_CAL_ADCREF_C2 [31:16] Internal. Only to be used through TI provided API. 16 16 SOC_DAC_VOUT_CAL_ADCREF_C1 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 DAC_CAL3 0x42c 32 Internal. Only to be used through TI provided API. SOC_DAC_VOUT_CAL_VDDS_C2 [31:16] Internal. Only to be used through TI provided API. 16 16 SOC_DAC_VOUT_CAL_VDDS_C1 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 RESERVED_N 0x430 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0xFFFFFFFF FLASH 0x40030000 0 0x4000 registers Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM. STAT 0x1c 32 FMC and Efuse Status RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 EFUSE_BLANK [15:15] Efuse scanning detected if fuse ROM is blank: 0 : Not blank 1 : Blank 1 15 EFUSE_TIMEOUT [14:14] Efuse scanning resulted in timeout error. 0 : No Timeout error 1 : Timeout Error 1 14 SPRS_BYTE_NOT_OK [13:13] Efuse scanning resulted in scan chain Sparse byte error. 0 : No Sparse error 1 : Sparse Error 1 13 EFUSE_ERRCODE [12:8] Same as EFUSEERROR.CODE 5 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 SAMHOLD_DIS [2:2] Status indicator of flash sample and hold sequencing logic. This bit will go to 1 some delay after CFG.DIS_IDLE is set to 1. 0: Not disabled 1: Sample and hold disabled and stable 1 2 BUSY [1:1] Fast version of the FMC FMSTAT.BUSY bit. This flag is valid immediately after the operation setting it (FMSTAT.BUSY is delayed some cycles) 0 : Not busy 1 : Busy 1 1 POWER_MODE [0:0] Power state of the flash sub-system. 0 : Active 1 : Low power 1 0 0x0 CFG 0x24 32 Internal. Only to be used through TI provided API. RESERVED9 [31:9] Internal. Only to be used through TI provided API. 23 9 STANDBY_MODE_SEL [8:8] Internal. Only to be used through TI provided API. 1 8 STANDBY_PW_SEL [7:6] Internal. Only to be used through TI provided API. 2 6 DIS_EFUSECLK [5:5] Internal. Only to be used through TI provided API. 1 5 DIS_READACCESS [4:4] Internal. Only to be used through TI provided API. 1 4 ENABLE_SWINTF [3:3] Internal. Only to be used through TI provided API. 1 3 RESERVED2 [2:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 2 DIS_STANDBY [1:1] Internal. Only to be used through TI provided API. 1 1 DIS_IDLE [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 SYSCODE_START 0x28 32 Internal. Only to be used through TI provided API. RESERVED5 [31:6] Internal. Only to be used through TI provided API. 26 6 SYSCODE_START [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 FLASH_SIZE 0x2c 32 Internal. Only to be used through TI provided API. RESERVED8 [31:8] Internal. Only to be used through TI provided API. 24 8 SECTORS [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 FWLOCK 0x3c 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 FWLOCK [2:0] Internal. Only to be used through TI provided API. 3 0 0x0 FWFLAG 0x40 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 FWFLAG [2:0] Internal. Only to be used through TI provided API. 3 0 0x0 EFUSE 0x1000 32 Internal. Only to be used through TI provided API. RESERVED29 [31:29] Internal. Only to be used through TI provided API. 3 29 INSTRUCTION [28:24] Internal. Only to be used through TI provided API. 5 24 RESERVED16 [23:16] Internal. Only to be used through TI provided API. 8 16 DUMPWORD [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 EFUSEADDR 0x1004 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 BLOCK [15:11] Internal. Only to be used through TI provided API. 5 11 ROW [10:0] Internal. Only to be used through TI provided API. 11 0 0x0 DATAUPPER 0x1008 32 Internal. Only to be used through TI provided API. RESERVED8 [31:8] Internal. Only to be used through TI provided API. 24 8 SPARE [7:3] Internal. Only to be used through TI provided API. 5 3 P [2:2] Internal. Only to be used through TI provided API. 1 2 R [1:1] Internal. Only to be used through TI provided API. 1 1 EEN [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 DATALOWER 0x100c 32 Internal. Only to be used through TI provided API. DATA [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 EFUSECFG 0x1010 32 Internal. Only to be used through TI provided API. RESERVED9 [31:9] Internal. Only to be used through TI provided API. 23 9 IDLEGATING [8:8] Internal. Only to be used through TI provided API. 1 8 RESERVED5 [7:5] Internal. Only to be used through TI provided API. 3 5 SLAVEPOWER [4:3] Internal. Only to be used through TI provided API. 2 3 RESERVED1 [2:1] Internal. Only to be used through TI provided API. 2 1 GATING [0:0] Internal. Only to be used through TI provided API. 1 0 0x1 EFUSESTAT 0x1014 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 RESETDONE [0:0] Internal. Only to be used through TI provided API. 1 0 0x1 ACC 0x1018 32 Internal. Only to be used through TI provided API. RESERVED24 [31:24] Internal. Only to be used through TI provided API. 8 24 ACCUMULATOR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 BOUNDARY 0x101c 32 Internal. Only to be used through TI provided API. RESERVED24 [31:24] Internal. Only to be used through TI provided API. 8 24 DISROW0 [23:23] Internal. Only to be used through TI provided API. 1 23 SPARE [22:22] Internal. Only to be used through TI provided API. 1 22 EFC_SELF_TEST_ERROR [21:21] Internal. Only to be used through TI provided API. 1 21 EFC_INSTRUCTION_INFO [20:20] Internal. Only to be used through TI provided API. 1 20 EFC_INSTRUCTION_ERROR [19:19] Internal. Only to be used through TI provided API. 1 19 EFC_AUTOLOAD_ERROR [18:18] Internal. Only to be used through TI provided API. 1 18 OUTPUTENABLE [17:14] Internal. Only to be used through TI provided API. 4 14 SYS_ECC_SELF_TEST_EN [13:13] Internal. Only to be used through TI provided API. 1 13 SYS_ECC_OVERRIDE_EN [12:12] Internal. Only to be used through TI provided API. 1 12 EFC_FDI [11:11] Internal. Only to be used through TI provided API. 1 11 SYS_DIEID_AUTOLOAD_EN [10:10] Internal. Only to be used through TI provided API. 1 10 SYS_REPAIR_EN [9:8] Internal. Only to be used through TI provided API. 2 8 SYS_WS_READ_STATES [7:4] Internal. Only to be used through TI provided API. 4 4 INPUTENABLE [3:0] Internal. Only to be used through TI provided API. 4 0 0x0 EFUSEFLAG 0x1020 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 KEY [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 EFUSEKEY 0x1024 32 Internal. Only to be used through TI provided API. CODE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 EFUSERELEASE 0x1028 32 Internal. Only to be used through TI provided API. ODPYEAR [31:25] Internal. Only to be used through TI provided API. 7 25 ODPMONTH [24:21] Internal. Only to be used through TI provided API. 4 21 ODPDAY [20:16] Internal. Only to be used through TI provided API. 5 16 EFUSEYEAR [15:9] Internal. Only to be used through TI provided API. 7 9 EFUSEMONTH [8:5] Internal. Only to be used through TI provided API. 4 5 EFUSEDAY [4:0] Internal. Only to be used through TI provided API. 5 0 0x0 EFUSEPINS 0x102c 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 EFC_SELF_TEST_DONE [15:15] Internal. Only to be used through TI provided API. 1 15 EFC_SELF_TEST_ERROR [14:14] Internal. Only to be used through TI provided API. 1 14 SYS_ECC_SELF_TEST_EN [13:13] Internal. Only to be used through TI provided API. 1 13 EFC_INSTRUCTION_INFO [12:12] Internal. Only to be used through TI provided API. 1 12 EFC_INSTRUCTION_ERROR [11:11] Internal. Only to be used through TI provided API. 1 11 EFC_AUTOLOAD_ERROR [10:10] Internal. Only to be used through TI provided API. 1 10 SYS_ECC_OVERRIDE_EN [9:9] Internal. Only to be used through TI provided API. 1 9 EFC_READY [8:8] Internal. Only to be used through TI provided API. 1 8 EFC_FCLRZ [7:7] Internal. Only to be used through TI provided API. 1 7 SYS_DIEID_AUTOLOAD_EN [6:6] Internal. Only to be used through TI provided API. 1 6 SYS_REPAIR_EN [5:4] Internal. Only to be used through TI provided API. 2 4 SYS_WS_READ_STATES [3:0] Internal. Only to be used through TI provided API. 4 0 0x0 EFUSECRA 0x1030 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Internal. Only to be used through TI provided API. 26 6 DATA [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 EFUSEREAD 0x1034 32 Internal. Only to be used through TI provided API. RESERVED10 [31:10] Internal. Only to be used through TI provided API. 22 10 DATABIT [9:8] Internal. Only to be used through TI provided API. 2 8 READCLOCK [7:4] Internal. Only to be used through TI provided API. 4 4 DEBUG [3:3] Internal. Only to be used through TI provided API. 1 3 SPARE [2:2] Internal. Only to be used through TI provided API. 1 2 MARGIN [1:0] Internal. Only to be used through TI provided API. 2 0 0x0 EFUSEPROGRAM 0x1038 32 Internal. Only to be used through TI provided API. RESERVED31 [31:31] Internal. Only to be used through TI provided API. 1 31 COMPAREDISABLE [30:30] Internal. Only to be used through TI provided API. 1 30 CLOCKSTALL [29:14] Internal. Only to be used through TI provided API. 16 14 VPPTOVDD [13:13] Internal. Only to be used through TI provided API. 1 13 ITERATIONS [12:9] Internal. Only to be used through TI provided API. 4 9 WRITECLOCK [8:0] Internal. Only to be used through TI provided API. 9 0 0x0 EFUSEERROR 0x103c 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Internal. Only to be used through TI provided API. 26 6 DONE [5:5] Internal. Only to be used through TI provided API. 1 5 CODE [4:0] Internal. Only to be used through TI provided API. 5 0 0x0 SINGLEBIT 0x1040 32 Internal. Only to be used through TI provided API. FROMN [31:1] Internal. Only to be used through TI provided API. 31 1 FROM0 [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 TWOBIT 0x1044 32 Internal. Only to be used through TI provided API. FROMN [31:1] Internal. Only to be used through TI provided API. 31 1 FROM0 [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 SELFTESTCYC 0x1048 32 Internal. Only to be used through TI provided API. CYCLES [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 SELFTESTSIGN 0x104c 32 Internal. Only to be used through TI provided API. SIGNATURE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FRDCTL 0x2000 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 RWAIT [11:8] Internal. Only to be used through TI provided API. 4 8 RM [7:0] Internal. Only to be used through TI provided API. 8 0 0x200 FSPRD 0x2004 32 Internal. Only to be used through TI provided API. DIS_PREEMPT [31:16] Internal. Only to be used through TI provided API. 16 16 RMBSEM [15:8] Internal. Only to be used through TI provided API. 8 8 RESERVED2 [7:2] Internal. Only to be used through TI provided API. 6 2 RM1 [1:1] Internal. Only to be used through TI provided API. 1 1 RM0 [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 FEDACCTL1 0x2008 32 Internal. Only to be used through TI provided API. RESERVED25 [31:25] Internal. Only to be used through TI provided API. 7 25 SUSP_IGNR [24:24] Internal. Only to be used through TI provided API. 1 24 EDACEN [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FEDACCTL2 0x200c 32 Internal. Only to be used through TI provided API. SEC_THRESHOLD [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCOR_ERR_CNT 0x2010 32 Internal. Only to be used through TI provided API. COR_ERR_CNT [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCOR_ERR_ADD 0x2014 32 Internal. Only to be used through TI provided API. FCOR_ERR_ADD [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCOR_ERR_POS 0x2018 32 Internal. Only to be used through TI provided API. SERR_POS [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FEDACSTAT 0x201c 32 Internal. Only to be used through TI provided API. RESERVED26 [31:26] Internal. Only to be used through TI provided API. 6 26 RVF_INT [25:25] Internal. Only to be used through TI provided API. 1 25 FSM_DONE [24:24] Internal. Only to be used through TI provided API. 1 24 ERR_PRF_FLG [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FUNC_ERR_ADD 0x2020 32 Internal. Only to be used through TI provided API. FUNC_ERR_ADD [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FEDACSDIS 0x2024 32 Internal. Only to be used through TI provided API. SECTORID0 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FPRIM_ADD_TAG 0x2028 32 Internal. Only to be used through TI provided API. PRIM_ADD_TAG [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FREDU_ADD_TAG 0x202c 32 Internal. Only to be used through TI provided API. REDU_ADD_TAG [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FBPROT 0x2030 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 PROTL1DIS [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 FBSE 0x2034 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 BSE [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 FBBUSY 0x2038 32 Internal. Only to be used through TI provided API. RESERVED8 [31:8] Internal. Only to be used through TI provided API. 24 8 BUSY [7:0] Internal. Only to be used through TI provided API. 8 0 0xFE FBAC 0x203c 32 Internal. Only to be used through TI provided API. RESERVED17 [31:17] Internal. Only to be used through TI provided API. 15 17 OTPPROTDIS [16:16] Internal. Only to be used through TI provided API. 1 16 BAGP [15:8] Internal. Only to be used through TI provided API. 8 8 VREADS [7:0] Internal. Only to be used through TI provided API. 8 0 0xF FBFALLBACK 0x2040 32 Internal. Only to be used through TI provided API. RESERVED28 [31:28] Internal. Only to be used through TI provided API. 4 28 FSM_PWRSAV [27:24] Internal. Only to be used through TI provided API. 4 24 RESERVED20 [23:20] Internal. Only to be used through TI provided API. 4 20 REG_PWRSAV [19:16] Internal. Only to be used through TI provided API. 4 16 BANKPWR7 [15:14] Internal. Only to be used through TI provided API. 2 14 BANKPWR6 [13:12] Internal. Only to be used through TI provided API. 2 12 BANKPWR5 [11:10] Internal. Only to be used through TI provided API. 2 10 BANKPWR4 [9:8] Internal. Only to be used through TI provided API. 2 8 BANKPWR3 [7:6] Internal. Only to be used through TI provided API. 2 6 BANKPWR2 [5:4] Internal. Only to be used through TI provided API. 2 4 BANKPWR1 [3:2] Internal. Only to be used through TI provided API. 2 2 BANKPWR0 [1:0] Internal. Only to be used through TI provided API. 2 0 0x505FFFF FBPRDY 0x2044 32 Internal. Only to be used through TI provided API. RESERVED17 [31:17] Internal. Only to be used through TI provided API. 15 17 BANKBUSY [16:16] Internal. Only to be used through TI provided API. 1 16 PUMPRDY [15:15] Internal. Only to be used through TI provided API. 1 15 RESERVED1 [14:1] Internal. Only to be used through TI provided API. 14 1 BANKRDY [0:0] Internal. Only to be used through TI provided API. 1 0 0xFF00FE FPAC1 0x2048 32 Internal. Only to be used through TI provided API. RESERVED28 [31:28] Internal. Only to be used through TI provided API. 4 28 PSLEEPTDIS [27:16] Internal. Only to be used through TI provided API. 12 16 PUMPRESET_PW [15:4] Internal. Only to be used through TI provided API. 12 4 RESERVED1 [3:2] Internal. Only to be used through TI provided API. 2 2 PUMPPWR [1:0] Internal. Only to be used through TI provided API. 2 0 0x2082081 FPAC2 0x204c 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 PAGP [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 FMAC 0x2050 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 BANK [2:0] Internal. Only to be used through TI provided API. 3 0 0x0 FMSTAT 0x2054 32 Internal. Only to be used through TI provided API. RESERVED18 [31:18] Internal. Only to be used through TI provided API. 14 18 RVSUSP [17:17] Internal. Only to be used through TI provided API. 1 17 RDVER [16:16] Internal. Only to be used through TI provided API. 1 16 RVF [15:15] Internal. Only to be used through TI provided API. 1 15 ILA [14:14] Internal. Only to be used through TI provided API. 1 14 DBF [13:13] Internal. Only to be used through TI provided API. 1 13 PGV [12:12] Internal. Only to be used through TI provided API. 1 12 PCV [11:11] Internal. Only to be used through TI provided API. 1 11 EV [10:10] Internal. Only to be used through TI provided API. 1 10 CV [9:9] Internal. Only to be used through TI provided API. 1 9 BUSY [8:8] Internal. Only to be used through TI provided API. 1 8 ERS [7:7] Internal. Only to be used through TI provided API. 1 7 PGM [6:6] Internal. Only to be used through TI provided API. 1 6 INVDAT [5:5] Internal. Only to be used through TI provided API. 1 5 CSTAT [4:4] Internal. Only to be used through TI provided API. 1 4 VOLSTAT [3:3] Internal. Only to be used through TI provided API. 1 3 ESUSP [2:2] Internal. Only to be used through TI provided API. 1 2 PSUSP [1:1] Internal. Only to be used through TI provided API. 1 1 SLOCK [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 FEMU_DMSW 0x2058 32 Internal. Only to be used through TI provided API. FEMU_DMSW [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FEMU_DLSW 0x205c 32 Internal. Only to be used through TI provided API. FEMU_DLSW [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FEMU_ECC 0x2060 32 Internal. Only to be used through TI provided API. EMU_ECC [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FLOCK 0x2064 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 ENCOM [15:0] Internal. Only to be used through TI provided API. 16 0 0x55AA FEMU_ADDR 0x2068 32 Internal. Only to be used through TI provided API. EMU_ADDR [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FDIAGCTL 0x206c 32 Internal. Only to be used through TI provided API. DIAGMODE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FRAW_DATAH 0x2070 32 Internal. Only to be used through TI provided API. FRAW_DATAH [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FRAW_DATAL 0x2074 32 Internal. Only to be used through TI provided API. FRAW_DATAL [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FRAW_ECC 0x2078 32 Internal. Only to be used through TI provided API. RAW_ECC [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FPAR_OVR 0x207c 32 Internal. Only to be used through TI provided API. DAT_INV_PAR [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FVREADCT 0x2080 32 Internal. Only to be used through TI provided API. RESERVED4 [31:4] Internal. Only to be used through TI provided API. 28 4 VREADCT [3:0] Internal. Only to be used through TI provided API. 4 0 0x8 FVHVCT1 0x2084 32 Internal. Only to be used through TI provided API. RESERVED24 [31:24] Internal. Only to be used through TI provided API. 8 24 TRIM13_E [23:20] Internal. Only to be used through TI provided API. 4 20 VHVCT_E [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED8 [15:8] Internal. Only to be used through TI provided API. 8 8 TRIM13_PV [7:4] Internal. Only to be used through TI provided API. 4 4 VHVCT_PV [3:0] Internal. Only to be used through TI provided API. 4 0 0x840088 FVHVCT2 0x2088 32 Internal. Only to be used through TI provided API. RESERVED24 [31:24] Internal. Only to be used through TI provided API. 8 24 TRIM13_P [23:20] Internal. Only to be used through TI provided API. 4 20 VHVCT_P [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED0 [15:0] Internal. Only to be used through TI provided API. 16 0 0xA20000 FVHVCT3 0x208c 32 Internal. Only to be used through TI provided API. RESERVED20 [31:20] Internal. Only to be used through TI provided API. 12 20 WCT [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED4 [15:4] Internal. Only to be used through TI provided API. 12 4 VHVCT_READ [3:0] Internal. Only to be used through TI provided API. 4 0 0xF0000 FVNVCT 0x2090 32 Internal. Only to be used through TI provided API. RESERVED13 [31:13] Internal. Only to be used through TI provided API. 19 13 VCG2P5CT [12:8] Internal. Only to be used through TI provided API. 5 8 RESERVED5 [7:5] Internal. Only to be used through TI provided API. 3 5 VIN_CT [4:0] Internal. Only to be used through TI provided API. 5 0 0x800 FVSLP 0x2094 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 VSL_P [15:12] Internal. Only to be used through TI provided API. 4 12 RESERVED0 [11:0] Internal. Only to be used through TI provided API. 12 0 0x8000 FVWLCT 0x2098 32 Internal. Only to be used through TI provided API. RESERVED5 [31:5] Internal. Only to be used through TI provided API. 27 5 VWLCT_P [4:0] Internal. Only to be used through TI provided API. 5 0 0x8 FEFUSECTL 0x209c 32 Internal. Only to be used through TI provided API. RESERVED27 [31:27] Internal. Only to be used through TI provided API. 5 27 CHAIN_SEL [26:24] Internal. Only to be used through TI provided API. 3 24 RESERVED18 [23:18] Internal. Only to be used through TI provided API. 6 18 WRITE_EN [17:17] Internal. Only to be used through TI provided API. 1 17 BP_SEL [16:16] Internal. Only to be used through TI provided API. 1 16 RESERVED9 [15:9] Internal. Only to be used through TI provided API. 7 9 EF_CLRZ [8:8] Internal. Only to be used through TI provided API. 1 8 RESERVED5 [7:5] Internal. Only to be used through TI provided API. 3 5 EF_TEST [4:4] Internal. Only to be used through TI provided API. 1 4 EFUSE_EN [3:0] Internal. Only to be used through TI provided API. 4 0 0x701010A FEFUSESTAT 0x20a0 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 SHIFT_DONE [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 FEFUSEDATA 0x20a4 32 Internal. Only to be used through TI provided API. FEFUSEDATA [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSEQPMP 0x20a8 32 Internal. Only to be used through TI provided API. RESERVED28 [31:28] Internal. Only to be used through TI provided API. 4 28 TRIM_3P4 [27:24] Internal. Only to be used through TI provided API. 4 24 RESERVED22 [23:22] Internal. Only to be used through TI provided API. 2 22 TRIM_1P7 [21:20] Internal. Only to be used through TI provided API. 2 20 TRIM_0P8 [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED15 [15:15] Internal. Only to be used through TI provided API. 1 15 VIN_AT_X [14:12] Internal. Only to be used through TI provided API. 3 12 RESERVED9 [11:9] Internal. Only to be used through TI provided API. 3 9 VIN_BY_PASS [8:8] Internal. Only to be used through TI provided API. 1 8 SEQ_PUMP [7:0] Internal. Only to be used through TI provided API. 8 0 0x85080000 FCLKTRIM 0x20ac 32 Internal. Only to be used through TI provided API. TRIM_EN [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 ROM_TEST 0x20b0 32 Internal. Only to be used through TI provided API. ROM_KEY [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FEDACSDIS2 0x20c0 32 Internal. Only to be used through TI provided API. SECTORID2 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FBSTROBES 0x2100 32 Internal. Only to be used through TI provided API. RESERVED25 [31:25] Internal. Only to be used through TI provided API. 7 25 ECBIT [24:24] Internal. Only to be used through TI provided API. 1 24 RESERVED19 [23:19] Internal. Only to be used through TI provided API. 5 19 RWAIT2_FLCLK [18:18] Internal. Only to be used through TI provided API. 1 18 RWAIT_FLCLK [17:17] Internal. Only to be used through TI provided API. 1 17 FLCLKEN [16:16] Internal. Only to be used through TI provided API. 1 16 RESERVED9 [15:9] Internal. Only to be used through TI provided API. 7 9 CTRLENZ [8:8] Internal. Only to be used through TI provided API. 1 8 RESERVED7 [7:7] Internal. Only to be used through TI provided API. 1 7 NOCOLRED [6:6] Internal. Only to be used through TI provided API. 1 6 PRECOL [5:5] Internal. Only to be used through TI provided API. 1 5 TI_OTP [4:4] Internal. Only to be used through TI provided API. 1 4 OTP [3:3] Internal. Only to be used through TI provided API. 1 3 TEZ [2:2] Internal. Only to be used through TI provided API. 1 2 RESERVED0 [1:0] Internal. Only to be used through TI provided API. 2 0 0x104 FPSTROBES 0x2104 32 Internal. Only to be used through TI provided API. RESERVED9 [31:9] Internal. Only to be used through TI provided API. 23 9 EXECUTEZ [8:8] Internal. Only to be used through TI provided API. 1 8 RESERVED2 [7:2] Internal. Only to be used through TI provided API. 6 2 V3PWRDNZ [1:1] Internal. Only to be used through TI provided API. 1 1 V5PWRDNZ [0:0] Internal. Only to be used through TI provided API. 1 0 0x103 FBMODE 0x2108 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 MODE [2:0] Internal. Only to be used through TI provided API. 3 0 0x0 FTCR 0x210c 32 Internal. Only to be used through TI provided API. RESERVED7 [31:7] Internal. Only to be used through TI provided API. 25 7 TCR [6:0] Internal. Only to be used through TI provided API. 7 0 0x0 FADDR 0x2110 32 Internal. Only to be used through TI provided API. FADDR [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FPMTCTL 0x2114 32 Internal. Only to be used through TI provided API. ADDR_INCR [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 PBISTCTL 0x2118 32 Internal. Only to be used through TI provided API. PBIST_KEY [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FTCTL 0x211c 32 Internal. Only to be used through TI provided API. RESERVED17 [31:17] Internal. Only to be used through TI provided API. 15 17 WDATA_BLK_CLR [16:16] Internal. Only to be used through TI provided API. 1 16 RESERVED2 [15:2] Internal. Only to be used through TI provided API. 14 2 TEST_EN [1:1] Internal. Only to be used through TI provided API. 1 1 RESERVED0 [0:0] Internal. Only to be used through TI provided API. 1 0 0x0 FWPWRITE0 0x2120 32 Internal. Only to be used through TI provided API. FWPWRITE0 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE1 0x2124 32 Internal. Only to be used through TI provided API. FWPWRITE1 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE2 0x2128 32 Internal. Only to be used through TI provided API. FWPWRITE2 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE3 0x212c 32 Internal. Only to be used through TI provided API. FWPWRITE3 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE4 0x2130 32 Internal. Only to be used through TI provided API. FWPWRITE4 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE5 0x2134 32 Internal. Only to be used through TI provided API. FWPWRITE5 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE6 0x2138 32 Internal. Only to be used through TI provided API. FWPWRITE6 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE7 0x213c 32 Internal. Only to be used through TI provided API. FWPWRITE7 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FWPWRITE_ECC 0x2140 32 Internal. Only to be used through TI provided API. ECCBYTES07_00 [31:24] Internal. Only to be used through TI provided API. 8 24 ECCBYTES15_08 [23:16] Internal. Only to be used through TI provided API. 8 16 ECCBYTES23_16 [15:8] Internal. Only to be used through TI provided API. 8 8 ECCBYTES31_24 [7:0] Internal. Only to be used through TI provided API. 8 0 0xFFFFFFFF FSWSTAT 0x2144 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 SAFELV [0:0] Internal. Only to be used through TI provided API. 1 0 0x1 FSM_GLBCTL 0x2200 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 CLKSEL [0:0] Internal. Only to be used through TI provided API. 1 0 0x1 FSM_STATE 0x2204 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 CTRLENZ [11:11] Internal. Only to be used through TI provided API. 1 11 EXECUTEZ [10:10] Internal. Only to be used through TI provided API. 1 10 RESERVED9 [9:9] Internal. Only to be used through TI provided API. 1 9 FSM_ACT [8:8] Internal. Only to be used through TI provided API. 1 8 TIOTP_ACT [7:7] Internal. Only to be used through TI provided API. 1 7 OTP_ACT [6:6] Internal. Only to be used through TI provided API. 1 6 RESERVED0 [5:0] Internal. Only to be used through TI provided API. 6 0 0xC00 FSM_STAT 0x2208 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 NON_OP [2:2] Internal. Only to be used through TI provided API. 1 2 OVR_PUL_CNT [1:1] Internal. Only to be used through TI provided API. 1 1 INV_DAT [0:0] Internal. Only to be used through TI provided API. 1 0 0x4 FSM_CMD 0x220c 32 Internal. Only to be used through TI provided API. RESERVED6 [31:6] Internal. Only to be used through TI provided API. 26 6 FSMCMD [5:0] Internal. Only to be used through TI provided API. 6 0 0x0 FSM_PE_OSU 0x2210 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 PGM_OSU [15:8] Internal. Only to be used through TI provided API. 8 8 ERA_OSU [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 FSM_VSTAT 0x2214 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 VSTAT_CNT [15:12] Internal. Only to be used through TI provided API. 4 12 RESERVED0 [11:0] Internal. Only to be used through TI provided API. 12 0 0x3000 FSM_PE_VSU 0x2218 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 PGM_VSU [15:8] Internal. Only to be used through TI provided API. 8 8 ERA_VSU [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 FSM_CMP_VSU 0x221c 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 ADD_EXZ [15:12] Internal. Only to be used through TI provided API. 4 12 RESERVED0 [11:0] Internal. Only to be used through TI provided API. 12 0 0x0 FSM_EX_VAL 0x2220 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 REP_VSU [15:8] Internal. Only to be used through TI provided API. 8 8 EXE_VALD [7:0] Internal. Only to be used through TI provided API. 8 0 0x301 FSM_RD_H 0x2224 32 Internal. Only to be used through TI provided API. RESERVED8 [31:8] Internal. Only to be used through TI provided API. 24 8 RD_H [7:0] Internal. Only to be used through TI provided API. 8 0 0x5A FSM_P_OH 0x2228 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 PGM_OH [15:8] Internal. Only to be used through TI provided API. 8 8 RESERVED0 [7:0] Internal. Only to be used through TI provided API. 8 0 0x100 FSM_ERA_OH 0x222c 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 ERA_OH [15:0] Internal. Only to be used through TI provided API. 16 0 0x1 FSM_SAV_PPUL 0x2230 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 SAV_P_PUL [11:0] Internal. Only to be used through TI provided API. 12 0 0x0 FSM_PE_VH 0x2234 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 PGM_VH [15:8] Internal. Only to be used through TI provided API. 8 8 ERA_VH [7:0] Internal. Only to be used through TI provided API. 8 0 0x100 FSM_PRG_PW 0x2240 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 PROG_PUL_WIDTH [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 FSM_ERA_PW 0x2244 32 Internal. Only to be used through TI provided API. FSM_ERA_PW [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_SAV_ERA_PUL 0x2254 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 SAV_ERA_PUL [11:0] Internal. Only to be used through TI provided API. 12 0 0x0 FSM_TIMER 0x2258 32 Internal. Only to be used through TI provided API. FSM_TIMER [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_MODE 0x225c 32 Internal. Only to be used through TI provided API. RESERVED20 [31:20] Internal. Only to be used through TI provided API. 12 20 RDV_SUBMODE [19:18] Internal. Only to be used through TI provided API. 2 18 PGM_SUBMODE [17:16] Internal. Only to be used through TI provided API. 2 16 ERA_SUBMODE [15:14] Internal. Only to be used through TI provided API. 2 14 SUBMODE [13:12] Internal. Only to be used through TI provided API. 2 12 SAV_PGM_CMD [11:9] Internal. Only to be used through TI provided API. 3 9 SAV_ERA_MODE [8:6] Internal. Only to be used through TI provided API. 3 6 MODE [5:3] Internal. Only to be used through TI provided API. 3 3 CMD [2:0] Internal. Only to be used through TI provided API. 3 0 0x0 FSM_PGM 0x2260 32 Internal. Only to be used through TI provided API. RESERVED26 [31:26] Internal. Only to be used through TI provided API. 6 26 PGM_BANK [25:23] Internal. Only to be used through TI provided API. 3 23 PGM_ADDR [22:0] Internal. Only to be used through TI provided API. 23 0 0x0 FSM_ERA 0x2264 32 Internal. Only to be used through TI provided API. RESERVED26 [31:26] Internal. Only to be used through TI provided API. 6 26 ERA_BANK [25:23] Internal. Only to be used through TI provided API. 3 23 ERA_ADDR [22:0] Internal. Only to be used through TI provided API. 23 0 0x0 FSM_PRG_PUL 0x2268 32 Internal. Only to be used through TI provided API. RESERVED20 [31:20] Internal. Only to be used through TI provided API. 12 20 BEG_EC_LEVEL [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED12 [15:12] Internal. Only to be used through TI provided API. 4 12 MAX_PRG_PUL [11:0] Internal. Only to be used through TI provided API. 12 0 0x40032 FSM_ERA_PUL 0x226c 32 Internal. Only to be used through TI provided API. RESERVED20 [31:20] Internal. Only to be used through TI provided API. 12 20 MAX_EC_LEVEL [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED12 [15:12] Internal. Only to be used through TI provided API. 4 12 MAX_ERA_PUL [11:0] Internal. Only to be used through TI provided API. 12 0 0x40BB8 FSM_STEP_SIZE 0x2270 32 Internal. Only to be used through TI provided API. RESERVED25 [31:25] Internal. Only to be used through TI provided API. 7 25 EC_STEP_SIZE [24:16] Internal. Only to be used through TI provided API. 9 16 RESERVED0 [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 FSM_PUL_CNTR 0x2274 32 Internal. Only to be used through TI provided API. RESERVED25 [31:25] Internal. Only to be used through TI provided API. 7 25 CUR_EC_LEVEL [24:16] Internal. Only to be used through TI provided API. 9 16 RESERVED12 [15:12] Internal. Only to be used through TI provided API. 4 12 PUL_CNTR [11:0] Internal. Only to be used through TI provided API. 12 0 0x0 FSM_EC_STEP_HEIGHT 0x2278 32 Internal. Only to be used through TI provided API. RESERVED4 [31:4] Internal. Only to be used through TI provided API. 28 4 EC_STEP_HEIGHT [3:0] Internal. Only to be used through TI provided API. 4 0 0x0 FSM_ST_MACHINE 0x227c 32 Internal. Only to be used through TI provided API. RESERVED24 [31:24] Internal. Only to be used through TI provided API. 8 24 DO_PRECOND [23:23] Internal. Only to be used through TI provided API. 1 23 FSM_INT_EN [22:22] Internal. Only to be used through TI provided API. 1 22 ALL_BANKS [21:21] Internal. Only to be used through TI provided API. 1 21 CMPV_ALLOWED [20:20] Internal. Only to be used through TI provided API. 1 20 RANDOM [19:19] Internal. Only to be used through TI provided API. 1 19 RV_SEC_EN [18:18] Internal. Only to be used through TI provided API. 1 18 RV_RES [17:17] Internal. Only to be used through TI provided API. 1 17 RV_INT_EN [16:16] Internal. Only to be used through TI provided API. 1 16 RESERVED15 [15:15] Internal. Only to be used through TI provided API. 1 15 ONE_TIME_GOOD [14:14] Internal. Only to be used through TI provided API. 1 14 RESERVED12 [13:12] Internal. Only to be used through TI provided API. 2 12 DO_REDU_COL [11:11] Internal. Only to be used through TI provided API. 1 11 DBG_SHORT_ROW [10:7] Internal. Only to be used through TI provided API. 4 7 RESERVED6 [6:6] Internal. Only to be used through TI provided API. 1 6 PGM_SEC_COF_EN [5:5] Internal. Only to be used through TI provided API. 1 5 PREC_STOP_EN [4:4] Internal. Only to be used through TI provided API. 1 4 DIS_TST_EN [3:3] Internal. Only to be used through TI provided API. 1 3 CMD_EN [2:2] Internal. Only to be used through TI provided API. 1 2 INV_DATA [1:1] Internal. Only to be used through TI provided API. 1 1 OVERRIDE [0:0] Internal. Only to be used through TI provided API. 1 0 0x800500 FSM_FLES 0x2280 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 BLK_TIOTP [11:8] Internal. Only to be used through TI provided API. 4 8 BLK_OTP [7:0] Internal. Only to be used through TI provided API. 8 0 0x0 FSM_WR_ENA 0x2288 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 WR_ENA [2:0] Internal. Only to be used through TI provided API. 3 0 0x2 FSM_ACC_PP 0x228c 32 Internal. Only to be used through TI provided API. FSM_ACC_PP [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_ACC_EP 0x2290 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 ACC_EP [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 FSM_ADDR 0x22a0 32 Internal. Only to be used through TI provided API. RESERVED31 [31:31] Internal. Only to be used through TI provided API. 1 31 BANK [30:28] Internal. Only to be used through TI provided API. 3 28 CUR_ADDR [27:0] Internal. Only to be used through TI provided API. 28 0 0x0 FSM_SECTOR 0x22a4 32 Internal. Only to be used through TI provided API. SECT_ERASED [31:16] Internal. Only to be used through TI provided API. 16 16 FSM_SECTOR_EXTENSION [15:8] Internal. Only to be used through TI provided API. 8 8 SECTOR [7:4] Internal. Only to be used through TI provided API. 4 4 SEC_OUT [3:0] Internal. Only to be used through TI provided API. 4 0 0xFFFF0000 FMC_REV_ID 0x22a8 32 Internal. Only to be used through TI provided API. MOD_VERSION [31:12] Internal. Only to be used through TI provided API. 20 12 CONFIG_CRC [11:0] Internal. Only to be used through TI provided API. 12 0 0x0 FSM_ERR_ADDR 0x22ac 32 Internal. Only to be used through TI provided API. FSM_ERR_ADDR [31:8] Internal. Only to be used through TI provided API. 24 8 RESERVED4 [7:4] Internal. Only to be used through TI provided API. 4 4 FSM_ERR_BANK [3:0] Internal. Only to be used through TI provided API. 4 0 0x0 FSM_PGM_MAXPUL 0x22b0 32 Internal. Only to be used through TI provided API. RESERVED12 [31:12] Internal. Only to be used through TI provided API. 20 12 FSM_PGM_MAXPUL [11:0] Internal. Only to be used through TI provided API. 12 0 0x0 FSM_EXECUTE 0x22b4 32 Internal. Only to be used through TI provided API. RESERVED20 [31:20] Internal. Only to be used through TI provided API. 12 20 SUSPEND_NOW [19:16] Internal. Only to be used through TI provided API. 4 16 RESERVED5 [15:5] Internal. Only to be used through TI provided API. 11 5 FSMEXECUTE [4:0] Internal. Only to be used through TI provided API. 5 0 0xA000A EEPROM_CFG 0x22b8 32 Internal. Only to be used through TI provided API. AUTOSTART_GRACE [31:0] Internal. Only to be used through TI provided API. 32 0 0x10000 FSM_SECTOR1 0x22c0 32 Internal. Only to be used through TI provided API. FSM_SECTOR1 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFFFFFFF FSM_SECTOR2 0x22c4 32 Internal. Only to be used through TI provided API. FSM_SECTOR2 [31:0] Internal. Only to be used through TI provided API. 32 0 0xFFF FSM_BSLE0 0x22e0 32 Internal. Only to be used through TI provided API. FSM_BSLE0 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_BSLE1 0x22e4 32 Internal. Only to be used through TI provided API. FSM_BSL1 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_BSLP0 0x22f0 32 Internal. Only to be used through TI provided API. FSM_BSLP0 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_BSLP1 0x22f4 32 Internal. Only to be used through TI provided API. FSM_BSL1 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FSM_PGM128 0x22f8 32 FMC FSM Enable 128-bit Wide Programming RESERVED [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 EN_PGM128 [0:0] 1: Enables 128-bit wide programming. This mode requires programming supply voltage to be greater than 2.5v at the Flash Pump. The primary use case for this mode is manufacturing test for test time reduction. 0: 64-bit wide programming. Valid at any programming voltage. A 128-bit word is divided into two 64-bit words for programming. [default] This register is write protected with the FSM_WR_ENA register. 1 0 0x0 FCFG_BANK 0x2400 32 Internal. Only to be used through TI provided API. EE_BANK_WIDTH [31:20] Internal. Only to be used through TI provided API. 12 20 EE_NUM_BANK [19:16] Internal. Only to be used through TI provided API. 4 16 MAIN_BANK_WIDTH [15:4] Internal. Only to be used through TI provided API. 12 4 MAIN_NUM_BANK [3:0] Internal. Only to be used through TI provided API. 4 0 0x801 FCFG_WRAPPER 0x2404 32 Internal. Only to be used through TI provided API. FAMILY_TYPE [31:24] Internal. Only to be used through TI provided API. 8 24 RESERVED21 [23:21] Internal. Only to be used through TI provided API. 3 21 MEM_MAP [20:20] Internal. Only to be used through TI provided API. 1 20 CPU2 [19:16] Internal. Only to be used through TI provided API. 4 16 EE_IN_MAIN [15:12] Internal. Only to be used through TI provided API. 4 12 ROM [11:11] Internal. Only to be used through TI provided API. 1 11 IFLUSH [10:10] Internal. Only to be used through TI provided API. 1 10 SIL3 [9:9] Internal. Only to be used through TI provided API. 1 9 ECCA [8:8] Internal. Only to be used through TI provided API. 1 8 AUTO_SUSP [7:6] Internal. Only to be used through TI provided API. 2 6 UERR [5:4] Internal. Only to be used through TI provided API. 2 4 CPU_TYPE1 [3:0] Internal. Only to be used through TI provided API. 4 0 0x50009007 FCFG_BNK_TYPE 0x2408 32 Internal. Only to be used through TI provided API. B7_TYPE [31:28] Internal. Only to be used through TI provided API. 4 28 B6_TYPE [27:24] Internal. Only to be used through TI provided API. 4 24 B5_TYPE [23:20] Internal. Only to be used through TI provided API. 4 20 B4_TYPE [19:16] Internal. Only to be used through TI provided API. 4 16 B3_TYPE [15:12] Internal. Only to be used through TI provided API. 4 12 B2_TYPE [11:8] Internal. Only to be used through TI provided API. 4 8 B1_TYPE [7:4] Internal. Only to be used through TI provided API. 4 4 B0_TYPE [3:0] Internal. Only to be used through TI provided API. 4 0 0x4 FCFG_B0_START 0x2410 32 Internal. Only to be used through TI provided API. B0_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B0_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B0_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x2000000 FCFG_B1_START 0x2414 32 Internal. Only to be used through TI provided API. B1_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B1_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B1_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B2_START 0x2418 32 Internal. Only to be used through TI provided API. B2_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B2_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B2_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B3_START 0x241c 32 Internal. Only to be used through TI provided API. B3_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B3_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B3_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B4_START 0x2420 32 Internal. Only to be used through TI provided API. B4_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B4_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B4_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B5_START 0x2424 32 Internal. Only to be used through TI provided API. B5_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B5_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B5_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B6_START 0x2428 32 Internal. Only to be used through TI provided API. B6_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B6_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B6_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B7_START 0x242c 32 Internal. Only to be used through TI provided API. B7_MAX_SECTOR [31:28] Internal. Only to be used through TI provided API. 4 28 B7_MUX_FACTOR [27:24] Internal. Only to be used through TI provided API. 4 24 B7_START_ADDR [23:0] Internal. Only to be used through TI provided API. 24 0 0x0 FCFG_B0_SSIZE0 0x2430 32 Internal. Only to be used through TI provided API. RESERVED28 [31:28] Internal. Only to be used through TI provided API. 4 28 B0_NUM_SECTORS [27:16] Internal. Only to be used through TI provided API. 12 16 RESERVED4 [15:4] Internal. Only to be used through TI provided API. 12 4 B0_SECT_SIZE [3:0] Internal. Only to be used through TI provided API. 4 0 0x2C0008 FCFG_B0_SSIZE1 0x2434 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B0_SSIZE2 0x2438 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B0_SSIZE3 0x243c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B1_SSIZE0 0x2440 32 Internal. Only to be used through TI provided API. B1_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B1_SSIZE1 0x2444 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B1_SSIZE2 0x2448 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B1_SSIZE3 0x244c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B2_SSIZE0 0x2450 32 Internal. Only to be used through TI provided API. B2_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B2_SSIZE1 0x2454 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B2_SSIZE2 0x2458 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B2_SSIZE3 0x245c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B3_SSIZE0 0x2460 32 Internal. Only to be used through TI provided API. B3_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B3_SSIZE1 0x2464 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B3_SSIZE2 0x2468 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B3_SSIZE3 0x246c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B4_SSIZE0 0x2470 32 Internal. Only to be used through TI provided API. B4_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B4_SSIZE1 0x2474 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B4_SSIZE2 0x2478 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B4_SSIZE3 0x247c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B5_SSIZE0 0x2480 32 Internal. Only to be used through TI provided API. B5_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B5_SSIZE1 0x2484 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B5_SSIZE2 0x2488 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B5_SSIZE3 0x248c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B6_SSIZE0 0x2490 32 Internal. Only to be used through TI provided API. B6_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B6_SSIZE1 0x2494 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B6_SSIZE2 0x2498 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B6_SSIZE3 0x249c 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B7_SSIZE0 0x24a0 32 Internal. Only to be used through TI provided API. B7_SECT_SIZE [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B7_SSIZE1 0x24a4 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B7_SSIZE2 0x24a8 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 FCFG_B7_SSIZE3 0x24ac 32 Internal. Only to be used through TI provided API. RESERVED [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 GPIO 0x40022000 0 0x400 registers MCU GPIO - I/F for controlling and reading IO status and IO event status DOUT3_0 0x0 32 Data Out 0 to 3 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO3 [24:24] Sets the state of the pin that is configured as DIO#3, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO2 [16:16] Sets the state of the pin that is configured as DIO#2, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO1 [8:8] Sets the state of the pin that is configured as DIO#1, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO0 [0:0] Sets the state of the pin that is configured as DIO#0, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT7_4 0x4 32 Data Out 4 to 7 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO7 [24:24] Sets the state of the pin that is configured as DIO#7, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO6 [16:16] Sets the state of the pin that is configured as DIO#6, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO5 [8:8] Sets the state of the pin that is configured as DIO#5, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO4 [0:0] Sets the state of the pin that is configured as DIO#4, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT11_8 0x8 32 Data Out 8 to 11 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO11 [24:24] Sets the state of the pin that is configured as DIO#11, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO10 [16:16] Sets the state of the pin that is configured as DIO#10, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO9 [8:8] Sets the state of the pin that is configured as DIO#9, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO8 [0:0] Sets the state of the pin that is configured as DIO#8, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT15_12 0xc 32 Data Out 12 to 15 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO15 [24:24] Sets the state of the pin that is configured as DIO#15, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO14 [16:16] Sets the state of the pin that is configured as DIO#14, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO13 [8:8] Sets the state of the pin that is configured as DIO#13, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO12 [0:0] Sets the state of the pin that is configured as DIO#12, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT19_16 0x10 32 Data Out 16 to 19 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO19 [24:24] Sets the state of the pin that is configured as DIO#19, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO18 [16:16] Sets the state of the pin that is configured as DIO#18, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO17 [8:8] Sets the state of the pin that is configured as DIO#17, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO16 [0:0] Sets the state of the pin that is configured as DIO#16, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT23_20 0x14 32 Data Out 20 to 23 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO23 [24:24] Sets the state of the pin that is configured as DIO#23, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO22 [16:16] Sets the state of the pin that is configured as DIO#22, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO21 [8:8] Sets the state of the pin that is configured as DIO#21, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO20 [0:0] Sets the state of the pin that is configured as DIO#20, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT27_24 0x18 32 Data Out 24 to 27 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO27 [24:24] Sets the state of the pin that is configured as DIO#27, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO26 [16:16] Sets the state of the pin that is configured as DIO#26, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO25 [8:8] Sets the state of the pin that is configured as DIO#25, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO24 [0:0] Sets the state of the pin that is configured as DIO#24, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT31_28 0x1c 32 Data Out 28 to 31 Alias register for byte access to each bit in DOUT31_0 RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DIO31 [24:24] Sets the state of the pin that is configured as DIO#31, if the corresponding DOE31_0 bitfield is set. 1 24 RESERVED17 [23:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 17 DIO30 [16:16] Sets the state of the pin that is configured as DIO#30, if the corresponding DOE31_0 bitfield is set. 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DIO29 [8:8] Sets the state of the pin that is configured as DIO#29, if the corresponding DOE31_0 bitfield is set. 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 DIO28 [0:0] Sets the state of the pin that is configured as DIO#28, if the corresponding DOE31_0 bitfield is set. 1 0 0x0 DOUT31_0 0x80 32 Data Output for DIO 0 to 31 DIO31 [31:31] Data output for DIO 31 1 31 DIO30 [30:30] Data output for DIO 30 1 30 DIO29 [29:29] Data output for DIO 29 1 29 DIO28 [28:28] Data output for DIO 28 1 28 DIO27 [27:27] Data output for DIO 27 1 27 DIO26 [26:26] Data output for DIO 26 1 26 DIO25 [25:25] Data output for DIO 25 1 25 DIO24 [24:24] Data output for DIO 24 1 24 DIO23 [23:23] Data output for DIO 23 1 23 DIO22 [22:22] Data output for DIO 22 1 22 DIO21 [21:21] Data output for DIO 21 1 21 DIO20 [20:20] Data output for DIO 20 1 20 DIO19 [19:19] Data output for DIO 19 1 19 DIO18 [18:18] Data output for DIO 18 1 18 DIO17 [17:17] Data output for DIO 17 1 17 DIO16 [16:16] Data output for DIO 16 1 16 DIO15 [15:15] Data output for DIO 15 1 15 DIO14 [14:14] Data output for DIO 14 1 14 DIO13 [13:13] Data output for DIO 13 1 13 DIO12 [12:12] Data output for DIO 12 1 12 DIO11 [11:11] Data output for DIO 11 1 11 DIO10 [10:10] Data output for DIO 10 1 10 DIO9 [9:9] Data output for DIO 9 1 9 DIO8 [8:8] Data output for DIO 8 1 8 DIO7 [7:7] Data output for DIO 7 1 7 DIO6 [6:6] Data output for DIO 6 1 6 DIO5 [5:5] Data output for DIO 5 1 5 DIO4 [4:4] Data output for DIO 4 1 4 DIO3 [3:3] Data output for DIO 3 1 3 DIO2 [2:2] Data output for DIO 2 1 2 DIO1 [1:1] Data output for DIO 1 1 1 DIO0 [0:0] Data output for DIO 0 1 0 0x0 DOUTSET31_0 0x90 32 Data Out Set Writing 1 to a bit position sets the corresponding bit in the DOUT31_0 register DIO31 [31:31] Set bit 31 1 31 DIO30 [30:30] Set bit 30 1 30 DIO29 [29:29] Set bit 29 1 29 DIO28 [28:28] Set bit 28 1 28 DIO27 [27:27] Set bit 27 1 27 DIO26 [26:26] Set bit 26 1 26 DIO25 [25:25] Set bit 25 1 25 DIO24 [24:24] Set bit 24 1 24 DIO23 [23:23] Set bit 23 1 23 DIO22 [22:22] Set bit 22 1 22 DIO21 [21:21] Set bit 21 1 21 DIO20 [20:20] Set bit 20 1 20 DIO19 [19:19] Set bit 19 1 19 DIO18 [18:18] Set bit 18 1 18 DIO17 [17:17] Set bit 17 1 17 DIO16 [16:16] Set bit 16 1 16 DIO15 [15:15] Set bit 15 1 15 DIO14 [14:14] Set bit 14 1 14 DIO13 [13:13] Set bit 13 1 13 DIO12 [12:12] Set bit 12 1 12 DIO11 [11:11] Set bit 11 1 11 DIO10 [10:10] Set bit 10 1 10 DIO9 [9:9] Set bit 9 1 9 DIO8 [8:8] Set bit 8 1 8 DIO7 [7:7] Set bit 7 1 7 DIO6 [6:6] Set bit 6 1 6 DIO5 [5:5] Set bit 5 1 5 DIO4 [4:4] Set bit 4 1 4 DIO3 [3:3] Set bit 3 1 3 DIO2 [2:2] Set bit 2 1 2 DIO1 [1:1] Set bit 1 1 1 DIO0 [0:0] Set bit 0 1 0 0x0 DOUTCLR31_0 0xa0 32 Data Out Clear Writing 1 to a bit position clears the corresponding bit in the DOUT31_0 register DIO31 [31:31] Clears bit 31 1 31 DIO30 [30:30] Clears bit 30 1 30 DIO29 [29:29] Clears bit 29 1 29 DIO28 [28:28] Clears bit 28 1 28 DIO27 [27:27] Clears bit 27 1 27 DIO26 [26:26] Clears bit 26 1 26 DIO25 [25:25] Clears bit 25 1 25 DIO24 [24:24] Clears bit 24 1 24 DIO23 [23:23] Clears bit 23 1 23 DIO22 [22:22] Clears bit 22 1 22 DIO21 [21:21] Clears bit 21 1 21 DIO20 [20:20] Clears bit 20 1 20 DIO19 [19:19] Clears bit 19 1 19 DIO18 [18:18] Clears bit 18 1 18 DIO17 [17:17] Clears bit 17 1 17 DIO16 [16:16] Clears bit 16 1 16 DIO15 [15:15] Clears bit 15 1 15 DIO14 [14:14] Clears bit 14 1 14 DIO13 [13:13] Clears bit 13 1 13 DIO12 [12:12] Clears bit 12 1 12 DIO11 [11:11] Clears bit 11 1 11 DIO10 [10:10] Clears bit 10 1 10 DIO9 [9:9] Clears bit 9 1 9 DIO8 [8:8] Clears bit 8 1 8 DIO7 [7:7] Clears bit 7 1 7 DIO6 [6:6] Clears bit 6 1 6 DIO5 [5:5] Clears bit 5 1 5 DIO4 [4:4] Clears bit 4 1 4 DIO3 [3:3] Clears bit 3 1 3 DIO2 [2:2] Clears bit 2 1 2 DIO1 [1:1] Clears bit 1 1 1 DIO0 [0:0] Clears bit 0 1 0 0x0 DOUTTGL31_0 0xb0 32 Data Out Toggle Writing 1 to a bit position will invert the corresponding DIO output. DIO31 [31:31] Toggles bit 31 1 31 DIO30 [30:30] Toggles bit 30 1 30 DIO29 [29:29] Toggles bit 29 1 29 DIO28 [28:28] Toggles bit 28 1 28 DIO27 [27:27] Toggles bit 27 1 27 DIO26 [26:26] Toggles bit 26 1 26 DIO25 [25:25] Toggles bit 25 1 25 DIO24 [24:24] Toggles bit 24 1 24 DIO23 [23:23] Toggles bit 23 1 23 DIO22 [22:22] Toggles bit 22 1 22 DIO21 [21:21] Toggles bit 21 1 21 DIO20 [20:20] Toggles bit 20 1 20 DIO19 [19:19] Toggles bit 19 1 19 DIO18 [18:18] Toggles bit 18 1 18 DIO17 [17:17] Toggles bit 17 1 17 DIO16 [16:16] Toggles bit 16 1 16 DIO15 [15:15] Toggles bit 15 1 15 DIO14 [14:14] Toggles bit 14 1 14 DIO13 [13:13] Toggles bit 13 1 13 DIO12 [12:12] Toggles bit 12 1 12 DIO11 [11:11] Toggles bit 11 1 11 DIO10 [10:10] Toggles bit 10 1 10 DIO9 [9:9] Toggles bit 9 1 9 DIO8 [8:8] Toggles bit 8 1 8 DIO7 [7:7] Toggles bit 7 1 7 DIO6 [6:6] Toggles bit 6 1 6 DIO5 [5:5] Toggles bit 5 1 5 DIO4 [4:4] Toggles bit 4 1 4 DIO3 [3:3] Toggles bit 3 1 3 DIO2 [2:2] Toggles bit 2 1 2 DIO1 [1:1] Toggles bit 1 1 1 DIO0 [0:0] Toggles bit 0 1 0 0x0 DIN31_0 0xc0 32 Data Input from DIO 0 to 31 DIO31 [31:31] Data input from DIO 31 1 31 DIO30 [30:30] Data input from DIO 30 1 30 DIO29 [29:29] Data input from DIO 29 1 29 DIO28 [28:28] Data input from DIO 28 1 28 DIO27 [27:27] Data input from DIO 27 1 27 DIO26 [26:26] Data input from DIO 26 1 26 DIO25 [25:25] Data input from DIO 25 1 25 DIO24 [24:24] Data input from DIO 24 1 24 DIO23 [23:23] Data input from DIO 23 1 23 DIO22 [22:22] Data input from DIO 22 1 22 DIO21 [21:21] Data input from DIO 21 1 21 DIO20 [20:20] Data input from DIO 20 1 20 DIO19 [19:19] Data input from DIO 19 1 19 DIO18 [18:18] Data input from DIO 18 1 18 DIO17 [17:17] Data input from DIO 17 1 17 DIO16 [16:16] Data input from DIO 16 1 16 DIO15 [15:15] Data input from DIO 15 1 15 DIO14 [14:14] Data input from DIO 14 1 14 DIO13 [13:13] Data input from DIO 13 1 13 DIO12 [12:12] Data input from DIO 12 1 12 DIO11 [11:11] Data input from DIO 11 1 11 DIO10 [10:10] Data input from DIO 10 1 10 DIO9 [9:9] Data input from DIO 9 1 9 DIO8 [8:8] Data input from DIO 8 1 8 DIO7 [7:7] Data input from DIO 7 1 7 DIO6 [6:6] Data input from DIO 6 1 6 DIO5 [5:5] Data input from DIO 5 1 5 DIO4 [4:4] Data input from DIO 4 1 4 DIO3 [3:3] Data input from DIO 3 1 3 DIO2 [2:2] Data input from DIO 2 1 2 DIO1 [1:1] Data input from DIO 1 1 1 DIO0 [0:0] Data input from DIO 0 1 0 0x0 DOE31_0 0xd0 32 Data Output Enable for DIO 0 to 31 DIO31 [31:31] Data output enable for DIO 31 1 31 DIO30 [30:30] Data output enable for DIO 30 1 30 DIO29 [29:29] Data output enable for DIO 29 1 29 DIO28 [28:28] Data output enable for DIO 28 1 28 DIO27 [27:27] Data output enable for DIO 27 1 27 DIO26 [26:26] Data output enable for DIO 26 1 26 DIO25 [25:25] Data output enable for DIO 25 1 25 DIO24 [24:24] Data output enable for DIO 24 1 24 DIO23 [23:23] Data output enable for DIO 23 1 23 DIO22 [22:22] Data output enable for DIO 22 1 22 DIO21 [21:21] Data output enable for DIO 21 1 21 DIO20 [20:20] Data output enable for DIO 20 1 20 DIO19 [19:19] Data output enable for DIO 19 1 19 DIO18 [18:18] Data output enable for DIO 18 1 18 DIO17 [17:17] Data output enable for DIO 17 1 17 DIO16 [16:16] Data output enable for DIO 16 1 16 DIO15 [15:15] Data output enable for DIO 15 1 15 DIO14 [14:14] Data output enable for DIO 14 1 14 DIO13 [13:13] Data output enable for DIO 13 1 13 DIO12 [12:12] Data output enable for DIO 12 1 12 DIO11 [11:11] Data output enable for DIO 11 1 11 DIO10 [10:10] Data output enable for DIO 10 1 10 DIO9 [9:9] Data output enable for DIO 9 1 9 DIO8 [8:8] Data output enable for DIO 8 1 8 DIO7 [7:7] Data output enable for DIO 7 1 7 DIO6 [6:6] Data output enable for DIO 6 1 6 DIO5 [5:5] Data output enable for DIO 5 1 5 DIO4 [4:4] Data output enable for DIO 4 1 4 DIO3 [3:3] Data output enable for DIO 3 1 3 DIO2 [2:2] Data output enable for DIO 2 1 2 DIO1 [1:1] Data output enable for DIO 1 1 1 DIO0 [0:0] Data output enable for DIO 0 1 0 0x0 EVFLAGS31_0 0xe0 32 Event Register for DIO 0 to 31 Reading this registers will return 1 for triggered event and 0 for non-triggered events. Writing a 1 to a bit field will clear the event. The configuration of events is done inside MCU IOC, e.g. events for DIO #0 is configured in IOC:IOCFG0.EDGE_DET and IOC:IOCFG0.EDGE_IRQ_EN. DIO31 [31:31] Event for DIO 31 1 31 DIO30 [30:30] Event for DIO 30 1 30 DIO29 [29:29] Event for DIO 29 1 29 DIO28 [28:28] Event for DIO 28 1 28 DIO27 [27:27] Event for DIO 27 1 27 DIO26 [26:26] Event for DIO 26 1 26 DIO25 [25:25] Event for DIO 25 1 25 DIO24 [24:24] Event for DIO 24 1 24 DIO23 [23:23] Event for DIO 23 1 23 DIO22 [22:22] Event for DIO 22 1 22 DIO21 [21:21] Event for DIO 21 1 21 DIO20 [20:20] Event for DIO 20 1 20 DIO19 [19:19] Event for DIO 19 1 19 DIO18 [18:18] Event for DIO 18 1 18 DIO17 [17:17] Event for DIO 17 1 17 DIO16 [16:16] Event for DIO 16 1 16 DIO15 [15:15] Event for DIO 15 1 15 DIO14 [14:14] Event for DIO 14 1 14 DIO13 [13:13] Event for DIO 13 1 13 DIO12 [12:12] Event for DIO 12 1 12 DIO11 [11:11] Event for DIO 11 1 11 DIO10 [10:10] Event for DIO 10 1 10 DIO9 [9:9] Event for DIO 9 1 9 DIO8 [8:8] Event for DIO 8 1 8 DIO7 [7:7] Event for DIO 7 1 7 DIO6 [6:6] Event for DIO 6 1 6 DIO5 [5:5] Event for DIO 5 1 5 DIO4 [4:4] Event for DIO 4 1 4 DIO3 [3:3] Event for DIO 3 1 3 DIO2 [2:2] Event for DIO 2 1 2 DIO1 [1:1] Event for DIO 1 1 1 DIO0 [0:0] Event for DIO 0 1 0 0x0 GPT0 0x40010000 0 0x1000 registers General Purpose Timer. CFG 0x0 32 Configuration RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 CFG [2:0] GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved 3 0 16BIT_TIMER 4 16-bit timer configuration. Configure for two 16-bit timers. Also see TAMR.TAMR and TBMR.TBMR. 32BIT_TIMER 0 32-bit timer configuration 0x0 TAMR 0x4 32 Timer A Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TACINTD [12:12] One-Shot/Periodic Interrupt Disable 1 12 DIS_TO_INTR 1 Time-out interrupt are disabled EN_TO_INTR 0 Time-out interrupt function as normal TAPLO [11:11] GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TAMRSU [10:10] Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TAMATCHR and TAPR, if used, on the next time-out. CYCLEUPDATE 0 Update TAMATCHR and TAPR, if used, on the next cycle. TAPWMIE [9:9] GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TAILD [8:8] GPT Timer A PWM Interval Load Write 1 8 TOUPDATE 1 Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout. CYCLEUPDATE 0 Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle. TASNAPS [7:7] GPT Timer A Snap-Shot Mode 1 7 EN 1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register. DIS 0 Snap-shot mode is disabled. TAWOT [6:6] GPT Timer A Wait-On-Trigger 1 6 WAIT 1 If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer A begins counting as soon as it is enabled. TAMIE [5:5] GPT Timer A Match Interrupt Enable 1 5 EN 1 An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TACDIR [4:4] GPT Timer A Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TAAMS [3:3] GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TACM [2:2] GPT Timer A Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TAMR [1:0] GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 TBMR 0x8 32 Timer B Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TBCINTD [12:12] One-Shot/Periodic Interrupt Mode 1 12 DIS_TO_INTR 1 Mask Time-Out Interrupt EN_TO_INTR 0 Normal Time-Out Interrupt TBPLO [11:11] GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TBMRSU [10:10] Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TBMATCHR and TBPR, if used, on the next time-out. CYCLEUPDATE 0 Update TBMATCHR and TBPR, if used, on the next cycle. TBPWMIE [9:9] GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TBILD [8:8] GPT Timer B PWM Interval Load Write 1 8 TOUPDATE 1 Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout. CYCLEUPDATE 0 Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle. TBSNAPS [7:7] GPT Timer B Snap-Shot Mode 1 7 EN 1 If Timer B is configured in the periodic mode DIS 0 Snap-shot mode is disabled. TBWOT [6:6] GPT Timer B Wait-On-Trigger 1 6 WAIT 1 If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer B begins counting as soon as it is enabled. TBMIE [5:5] GPT Timer B Match Interrupt Enable. 1 5 EN 1 An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TBCDIR [4:4] GPT Timer B Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TBAMS [3:3] GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TBCM [2:2] GPT Timer B Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TBMR [1:0] GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 CTL 0xc 32 Control RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 TBPWML [14:14] GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted. 1 14 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED12 [13:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 12 TBEVENT [11:10] GPT Timer B Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 10 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TBSTALL [9:9] GPT Timer B Stall Enable 1 9 EN 1 Timer B freezes counting while the processor is halted by the debugger. DIS 0 Timer B continues counting while the processor is halted by the debugger. TBEN [8:8] GPT Timer B Enable 1 8 EN 1 Timer B is enabled and begins counting or the capture logic is enabled based on CFG register. DIS 0 Timer B is disabled. RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 TAPWML [6:6] GPT Timer A PWM Output Level 1 6 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED4 [5:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 4 TAEVENT [3:2] GPT Timer A Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 2 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TASTALL [1:1] GPT Timer A Stall Enable 1 1 EN 1 Timer A freezes counting while the processor is halted by the debugger. DIS 0 Timer A continues counting while the processor is halted by the debugger. TAEN [0:0] GPT Timer A Enable 1 0 EN 1 Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register. DIS 0 Timer A is disabled. 0x0 SYNC 0x10 32 Synch Register RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SYNC3 [7:6] Synchronize GPT Timer 3. 2 6 BOTH 3 A timeout event for both Timer A and Timer B of GPT3 is triggered TIMERB 2 A timeout event for Timer B of GPT3 is triggered TIMERA 1 A timeout event for Timer A of GPT3 is triggered NOSYNC 0 No Sync. GPT3 is not affected. SYNC2 [5:4] Synchronize GPT Timer 2. 2 4 BOTH 3 A timeout event for both Timer A and Timer B of GPT2 is triggered TIMERB 2 A timeout event for Timer B of GPT2 is triggered TIMERA 1 A timeout event for Timer A of GPT2 is triggered NOSYNC 0 No Sync. GPT2 is not affected. SYNC1 [3:2] Synchronize GPT Timer 1 2 2 BOTH 3 A timeout event for both Timer A and Timer B of GPT1 is triggered TIMERB 2 A timeout event for Timer B of GPT1 is triggered TIMERA 1 A timeout event for Timer A of GPT1 is triggered NOSYNC 0 No Sync. GPT1 is not affected. SYNC0 [1:0] Synchronize GPT Timer 0 2 0 BOTH 3 A timeout event for both Timer A and Timer B of GPT0 is triggered TIMERB 2 A timeout event for Timer B of GPT0 is triggered TIMERA 1 A timeout event for Timer A of GPT0 is triggered NOSYNC 0 No Sync. GPT0 is not affected. 0x0 IMR 0x18 32 Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABIM [13:13] Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS 1 13 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMIM [11:11] Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS 1 11 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBEIM [10:10] Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS 1 10 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBMIM [9:9] Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS 1 9 EN 1 Enable Interrupt DIS 0 Disable Interrupt TBTOIM [8:8] Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS 1 8 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAIM [5:5] Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS 1 5 EN 1 Enable Interrupt DIS 0 Disable Interrupt TAMIM [4:4] Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS 1 4 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEIM [2:2] Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS 1 2 EN 1 Enable Interrupt DIS 0 Disable Interrupt CAMIM [1:1] Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS 1 1 EN 1 Enable Interrupt DIS 0 Disable Interrupt TATOIM [0:0] Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS 1 0 EN 1 Enable Interrupt DIS 0 Disable Interrupt 0x0 RIS 0x1c 32 Raw Interrupt Status Associated registers: IMR, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABRIS [13:13] GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMRIS [11:11] GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. 1 11 CBERIS [10:10] GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 10 CBMRIS [9:9] GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. 1 9 TBTORIS [8:8] GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAARIS [5:5] GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 5 TAMRIS [4:4] GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAERIS [2:2] GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 2 CAMRIS [1:1] GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. 1 1 TATORIS [0:0] GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. 1 0 0x0 MIS 0x20 32 Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABMIS [13:13] 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMMIS [11:11] 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 1 11 CBEMIS [10:10] 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 1 10 CBMMIS [9:9] 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 1 9 TBTOMIS [8:8] 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAMIS [5:5] 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 1 5 TAMMIS [4:4] 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEMIS [2:2] 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 1 2 CAMMIS [1:1] 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 1 1 TATOMIS [0:0] 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 1 0 0x0 ICLR 0x24 32 Interrupt Clear This register is used to clear status bits in the RIS and MIS registers RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABINT [13:13] 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMCINT [11:11] 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS 1 11 CBECINT [10:10] 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS 1 10 CBMCINT [9:9] 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS 1 9 TBTOCINT [8:8] 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAINT [5:5] 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS 1 5 TAMCINT [4:4] 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAECINT [2:2] 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS 1 2 CAMCINT [1:1] 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS 1 1 TATOCINT [0:0] 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS 1 0 0x0 TAILR 0x28 32 Timer A Interval Load Register TAILR [31:0] GPT Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of TAILR. 32 0 0xFFFFFFFF TBILR 0x2c 32 Timer B Interval Load Register TBILR [31:0] GPT Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of TBILR. 32 0 0xFFFF TAMATCHR 0x30 32 Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU TAMATCHR [31:0] GPT Timer A Match Register 32 0 0xFFFFFFFF TBMATCHR 0x34 32 Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TBMATCHR [15:0] GPT Timer B Match Register 16 0 0xFFFF TAPR 0x38 32 Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSR [7:0] Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TBPR 0x3c 32 Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSR [7:0] Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TAPMR 0x40 32 Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSMR [7:0] GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TBPMR 0x44 32 Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSMR [7:0] GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TAR 0x48 32 Timer A Register This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the Timer B (TBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (TAPS) register. TAR [31:0] GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFFFFFF TBR 0x4c 32 Timer B Register This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register. TBR [31:0] GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFF TAV 0x50 32 Timer A Value When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use this value to determine the time elapsed between an interrupt and the ISR entry when using the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the TAR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TAV [31:0] GPT Timer A Register A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the TAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFFFFFF TBV 0x54 32 Timer B Value When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the TBR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TBV [31:0] GPT Timer B Register A read returns the current, free-running value of Timer B in all modes. When written, the value written into this register is loaded into the TBR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFF TAPS 0x5c 32 Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer A Pre-scaler 8 0 0x0 TBPS 0x60 32 Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer B Pre-scaler 8 0 0x0 TAPV 0x64 32 Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer A Pre-scaler Value 8 0 0x0 TBPV 0x68 32 Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer B Pre-scaler Value 8 0 0x0 DMAEV 0x6c 32 DMA Event This register allows software to enable/disable GPT DMA trigger events. RESERVED12 [31:12] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 20 12 TBMDMAEN [11:11] GPT Timer B Match DMA Trigger Enable 1 11 CBEDMAEN [10:10] GPT Timer B Capture Event DMA Trigger Enable 1 10 CBMDMAEN [9:9] GPT Timer B Capture Match DMA Trigger Enable 1 9 TBTODMAEN [8:8] GPT Timer B Time-Out DMA Trigger Enable 1 8 RESERVED5 [7:5] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 3 5 TAMDMAEN [4:4] GPT Timer A Match DMA Trigger Enable 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEDMAEN [2:2] GPT Timer A Capture Event DMA Trigger Enable 1 2 CAMDMAEN [1:1] GPT Timer A Capture Match DMA Trigger Enable 1 1 TATODMAEN [0:0] GPT Timer A Time-Out DMA Trigger Enable 1 0 0x0 VERSION 0xfb0 32 Peripheral Version This register provides information regarding the GPT version VERSION [31:0] Timer Revision. 32 0 0x400 ANDCCP 0xfb4 32 Combined CCP Output This register is used to logically AND CCP output pairs for each timer RESERVED1 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 LD_TO_EN [1:1] PWM assertion would happen at timeout 0: PWM assertion happens when counter matches load value 1: PWM assertion happens at timeout of the counter 1 1 CCP_AND_EN [0:0] Enables AND operation of the CCP outputs for timers A and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. 1 0 0x0 GPT1 0x40011000 0 0x1000 registers General Purpose Timer. CFG 0x0 32 Configuration RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 CFG [2:0] GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved 3 0 16BIT_TIMER 4 16-bit timer configuration. Configure for two 16-bit timers. Also see TAMR.TAMR and TBMR.TBMR. 32BIT_TIMER 0 32-bit timer configuration 0x0 TAMR 0x4 32 Timer A Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TACINTD [12:12] One-Shot/Periodic Interrupt Disable 1 12 DIS_TO_INTR 1 Time-out interrupt are disabled EN_TO_INTR 0 Time-out interrupt function as normal TAPLO [11:11] GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TAMRSU [10:10] Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TAMATCHR and TAPR, if used, on the next time-out. CYCLEUPDATE 0 Update TAMATCHR and TAPR, if used, on the next cycle. TAPWMIE [9:9] GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TAILD [8:8] GPT Timer A PWM Interval Load Write 1 8 TOUPDATE 1 Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout. CYCLEUPDATE 0 Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle. TASNAPS [7:7] GPT Timer A Snap-Shot Mode 1 7 EN 1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register. DIS 0 Snap-shot mode is disabled. TAWOT [6:6] GPT Timer A Wait-On-Trigger 1 6 WAIT 1 If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer A begins counting as soon as it is enabled. TAMIE [5:5] GPT Timer A Match Interrupt Enable 1 5 EN 1 An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TACDIR [4:4] GPT Timer A Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TAAMS [3:3] GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TACM [2:2] GPT Timer A Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TAMR [1:0] GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 TBMR 0x8 32 Timer B Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TBCINTD [12:12] One-Shot/Periodic Interrupt Mode 1 12 DIS_TO_INTR 1 Mask Time-Out Interrupt EN_TO_INTR 0 Normal Time-Out Interrupt TBPLO [11:11] GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TBMRSU [10:10] Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TBMATCHR and TBPR, if used, on the next time-out. CYCLEUPDATE 0 Update TBMATCHR and TBPR, if used, on the next cycle. TBPWMIE [9:9] GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TBILD [8:8] GPT Timer B PWM Interval Load Write 1 8 TOUPDATE 1 Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout. CYCLEUPDATE 0 Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle. TBSNAPS [7:7] GPT Timer B Snap-Shot Mode 1 7 EN 1 If Timer B is configured in the periodic mode DIS 0 Snap-shot mode is disabled. TBWOT [6:6] GPT Timer B Wait-On-Trigger 1 6 WAIT 1 If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer B begins counting as soon as it is enabled. TBMIE [5:5] GPT Timer B Match Interrupt Enable. 1 5 EN 1 An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TBCDIR [4:4] GPT Timer B Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TBAMS [3:3] GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TBCM [2:2] GPT Timer B Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TBMR [1:0] GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 CTL 0xc 32 Control RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 TBPWML [14:14] GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted. 1 14 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED12 [13:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 12 TBEVENT [11:10] GPT Timer B Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 10 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TBSTALL [9:9] GPT Timer B Stall Enable 1 9 EN 1 Timer B freezes counting while the processor is halted by the debugger. DIS 0 Timer B continues counting while the processor is halted by the debugger. TBEN [8:8] GPT Timer B Enable 1 8 EN 1 Timer B is enabled and begins counting or the capture logic is enabled based on CFG register. DIS 0 Timer B is disabled. RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 TAPWML [6:6] GPT Timer A PWM Output Level 1 6 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED4 [5:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 4 TAEVENT [3:2] GPT Timer A Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 2 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TASTALL [1:1] GPT Timer A Stall Enable 1 1 EN 1 Timer A freezes counting while the processor is halted by the debugger. DIS 0 Timer A continues counting while the processor is halted by the debugger. TAEN [0:0] GPT Timer A Enable 1 0 EN 1 Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register. DIS 0 Timer A is disabled. 0x0 SYNC 0x10 32 Synch Register RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SYNC3 [7:6] Synchronize GPT Timer 3. 2 6 BOTH 3 A timeout event for both Timer A and Timer B of GPT3 is triggered TIMERB 2 A timeout event for Timer B of GPT3 is triggered TIMERA 1 A timeout event for Timer A of GPT3 is triggered NOSYNC 0 No Sync. GPT3 is not affected. SYNC2 [5:4] Synchronize GPT Timer 2. 2 4 BOTH 3 A timeout event for both Timer A and Timer B of GPT2 is triggered TIMERB 2 A timeout event for Timer B of GPT2 is triggered TIMERA 1 A timeout event for Timer A of GPT2 is triggered NOSYNC 0 No Sync. GPT2 is not affected. SYNC1 [3:2] Synchronize GPT Timer 1 2 2 BOTH 3 A timeout event for both Timer A and Timer B of GPT1 is triggered TIMERB 2 A timeout event for Timer B of GPT1 is triggered TIMERA 1 A timeout event for Timer A of GPT1 is triggered NOSYNC 0 No Sync. GPT1 is not affected. SYNC0 [1:0] Synchronize GPT Timer 0 2 0 BOTH 3 A timeout event for both Timer A and Timer B of GPT0 is triggered TIMERB 2 A timeout event for Timer B of GPT0 is triggered TIMERA 1 A timeout event for Timer A of GPT0 is triggered NOSYNC 0 No Sync. GPT0 is not affected. 0x0 IMR 0x18 32 Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABIM [13:13] Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS 1 13 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMIM [11:11] Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS 1 11 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBEIM [10:10] Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS 1 10 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBMIM [9:9] Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS 1 9 EN 1 Enable Interrupt DIS 0 Disable Interrupt TBTOIM [8:8] Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS 1 8 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAIM [5:5] Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS 1 5 EN 1 Enable Interrupt DIS 0 Disable Interrupt TAMIM [4:4] Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS 1 4 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEIM [2:2] Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS 1 2 EN 1 Enable Interrupt DIS 0 Disable Interrupt CAMIM [1:1] Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS 1 1 EN 1 Enable Interrupt DIS 0 Disable Interrupt TATOIM [0:0] Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS 1 0 EN 1 Enable Interrupt DIS 0 Disable Interrupt 0x0 RIS 0x1c 32 Raw Interrupt Status Associated registers: IMR, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABRIS [13:13] GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMRIS [11:11] GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. 1 11 CBERIS [10:10] GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 10 CBMRIS [9:9] GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. 1 9 TBTORIS [8:8] GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAARIS [5:5] GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 5 TAMRIS [4:4] GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAERIS [2:2] GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 2 CAMRIS [1:1] GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. 1 1 TATORIS [0:0] GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. 1 0 0x0 MIS 0x20 32 Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABMIS [13:13] 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMMIS [11:11] 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 1 11 CBEMIS [10:10] 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 1 10 CBMMIS [9:9] 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 1 9 TBTOMIS [8:8] 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAMIS [5:5] 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 1 5 TAMMIS [4:4] 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEMIS [2:2] 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 1 2 CAMMIS [1:1] 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 1 1 TATOMIS [0:0] 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 1 0 0x0 ICLR 0x24 32 Interrupt Clear This register is used to clear status bits in the RIS and MIS registers RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABINT [13:13] 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMCINT [11:11] 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS 1 11 CBECINT [10:10] 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS 1 10 CBMCINT [9:9] 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS 1 9 TBTOCINT [8:8] 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAINT [5:5] 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS 1 5 TAMCINT [4:4] 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAECINT [2:2] 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS 1 2 CAMCINT [1:1] 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS 1 1 TATOCINT [0:0] 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS 1 0 0x0 TAILR 0x28 32 Timer A Interval Load Register TAILR [31:0] GPT Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of TAILR. 32 0 0xFFFFFFFF TBILR 0x2c 32 Timer B Interval Load Register TBILR [31:0] GPT Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of TBILR. 32 0 0xFFFF TAMATCHR 0x30 32 Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU TAMATCHR [31:0] GPT Timer A Match Register 32 0 0xFFFFFFFF TBMATCHR 0x34 32 Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TBMATCHR [15:0] GPT Timer B Match Register 16 0 0xFFFF TAPR 0x38 32 Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSR [7:0] Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TBPR 0x3c 32 Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSR [7:0] Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TAPMR 0x40 32 Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSMR [7:0] GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TBPMR 0x44 32 Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSMR [7:0] GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TAR 0x48 32 Timer A Register This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the Timer B (TBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (TAPS) register. TAR [31:0] GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFFFFFF TBR 0x4c 32 Timer B Register This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register. TBR [31:0] GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFF TAV 0x50 32 Timer A Value When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use this value to determine the time elapsed between an interrupt and the ISR entry when using the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the TAR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TAV [31:0] GPT Timer A Register A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the TAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFFFFFF TBV 0x54 32 Timer B Value When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the TBR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TBV [31:0] GPT Timer B Register A read returns the current, free-running value of Timer B in all modes. When written, the value written into this register is loaded into the TBR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFF TAPS 0x5c 32 Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer A Pre-scaler 8 0 0x0 TBPS 0x60 32 Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer B Pre-scaler 8 0 0x0 TAPV 0x64 32 Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer A Pre-scaler Value 8 0 0x0 TBPV 0x68 32 Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer B Pre-scaler Value 8 0 0x0 DMAEV 0x6c 32 DMA Event This register allows software to enable/disable GPT DMA trigger events. RESERVED12 [31:12] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 20 12 TBMDMAEN [11:11] GPT Timer B Match DMA Trigger Enable 1 11 CBEDMAEN [10:10] GPT Timer B Capture Event DMA Trigger Enable 1 10 CBMDMAEN [9:9] GPT Timer B Capture Match DMA Trigger Enable 1 9 TBTODMAEN [8:8] GPT Timer B Time-Out DMA Trigger Enable 1 8 RESERVED5 [7:5] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 3 5 TAMDMAEN [4:4] GPT Timer A Match DMA Trigger Enable 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEDMAEN [2:2] GPT Timer A Capture Event DMA Trigger Enable 1 2 CAMDMAEN [1:1] GPT Timer A Capture Match DMA Trigger Enable 1 1 TATODMAEN [0:0] GPT Timer A Time-Out DMA Trigger Enable 1 0 0x0 VERSION 0xfb0 32 Peripheral Version This register provides information regarding the GPT version VERSION [31:0] Timer Revision. 32 0 0x400 ANDCCP 0xfb4 32 Combined CCP Output This register is used to logically AND CCP output pairs for each timer RESERVED1 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 LD_TO_EN [1:1] PWM assertion would happen at timeout 0: PWM assertion happens when counter matches load value 1: PWM assertion happens at timeout of the counter 1 1 CCP_AND_EN [0:0] Enables AND operation of the CCP outputs for timers A and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. 1 0 0x0 GPT2 0x40012000 0 0x1000 registers General Purpose Timer. CFG 0x0 32 Configuration RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 CFG [2:0] GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved 3 0 16BIT_TIMER 4 16-bit timer configuration. Configure for two 16-bit timers. Also see TAMR.TAMR and TBMR.TBMR. 32BIT_TIMER 0 32-bit timer configuration 0x0 TAMR 0x4 32 Timer A Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TACINTD [12:12] One-Shot/Periodic Interrupt Disable 1 12 DIS_TO_INTR 1 Time-out interrupt are disabled EN_TO_INTR 0 Time-out interrupt function as normal TAPLO [11:11] GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TAMRSU [10:10] Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TAMATCHR and TAPR, if used, on the next time-out. CYCLEUPDATE 0 Update TAMATCHR and TAPR, if used, on the next cycle. TAPWMIE [9:9] GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TAILD [8:8] GPT Timer A PWM Interval Load Write 1 8 TOUPDATE 1 Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout. CYCLEUPDATE 0 Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle. TASNAPS [7:7] GPT Timer A Snap-Shot Mode 1 7 EN 1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register. DIS 0 Snap-shot mode is disabled. TAWOT [6:6] GPT Timer A Wait-On-Trigger 1 6 WAIT 1 If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer A begins counting as soon as it is enabled. TAMIE [5:5] GPT Timer A Match Interrupt Enable 1 5 EN 1 An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TACDIR [4:4] GPT Timer A Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TAAMS [3:3] GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TACM [2:2] GPT Timer A Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TAMR [1:0] GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 TBMR 0x8 32 Timer B Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TBCINTD [12:12] One-Shot/Periodic Interrupt Mode 1 12 DIS_TO_INTR 1 Mask Time-Out Interrupt EN_TO_INTR 0 Normal Time-Out Interrupt TBPLO [11:11] GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TBMRSU [10:10] Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TBMATCHR and TBPR, if used, on the next time-out. CYCLEUPDATE 0 Update TBMATCHR and TBPR, if used, on the next cycle. TBPWMIE [9:9] GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TBILD [8:8] GPT Timer B PWM Interval Load Write 1 8 TOUPDATE 1 Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout. CYCLEUPDATE 0 Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle. TBSNAPS [7:7] GPT Timer B Snap-Shot Mode 1 7 EN 1 If Timer B is configured in the periodic mode DIS 0 Snap-shot mode is disabled. TBWOT [6:6] GPT Timer B Wait-On-Trigger 1 6 WAIT 1 If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer B begins counting as soon as it is enabled. TBMIE [5:5] GPT Timer B Match Interrupt Enable. 1 5 EN 1 An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TBCDIR [4:4] GPT Timer B Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TBAMS [3:3] GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TBCM [2:2] GPT Timer B Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TBMR [1:0] GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 CTL 0xc 32 Control RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 TBPWML [14:14] GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted. 1 14 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED12 [13:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 12 TBEVENT [11:10] GPT Timer B Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 10 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TBSTALL [9:9] GPT Timer B Stall Enable 1 9 EN 1 Timer B freezes counting while the processor is halted by the debugger. DIS 0 Timer B continues counting while the processor is halted by the debugger. TBEN [8:8] GPT Timer B Enable 1 8 EN 1 Timer B is enabled and begins counting or the capture logic is enabled based on CFG register. DIS 0 Timer B is disabled. RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 TAPWML [6:6] GPT Timer A PWM Output Level 1 6 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED4 [5:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 4 TAEVENT [3:2] GPT Timer A Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 2 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TASTALL [1:1] GPT Timer A Stall Enable 1 1 EN 1 Timer A freezes counting while the processor is halted by the debugger. DIS 0 Timer A continues counting while the processor is halted by the debugger. TAEN [0:0] GPT Timer A Enable 1 0 EN 1 Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register. DIS 0 Timer A is disabled. 0x0 SYNC 0x10 32 Synch Register RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SYNC3 [7:6] Synchronize GPT Timer 3. 2 6 BOTH 3 A timeout event for both Timer A and Timer B of GPT3 is triggered TIMERB 2 A timeout event for Timer B of GPT3 is triggered TIMERA 1 A timeout event for Timer A of GPT3 is triggered NOSYNC 0 No Sync. GPT3 is not affected. SYNC2 [5:4] Synchronize GPT Timer 2. 2 4 BOTH 3 A timeout event for both Timer A and Timer B of GPT2 is triggered TIMERB 2 A timeout event for Timer B of GPT2 is triggered TIMERA 1 A timeout event for Timer A of GPT2 is triggered NOSYNC 0 No Sync. GPT2 is not affected. SYNC1 [3:2] Synchronize GPT Timer 1 2 2 BOTH 3 A timeout event for both Timer A and Timer B of GPT1 is triggered TIMERB 2 A timeout event for Timer B of GPT1 is triggered TIMERA 1 A timeout event for Timer A of GPT1 is triggered NOSYNC 0 No Sync. GPT1 is not affected. SYNC0 [1:0] Synchronize GPT Timer 0 2 0 BOTH 3 A timeout event for both Timer A and Timer B of GPT0 is triggered TIMERB 2 A timeout event for Timer B of GPT0 is triggered TIMERA 1 A timeout event for Timer A of GPT0 is triggered NOSYNC 0 No Sync. GPT0 is not affected. 0x0 IMR 0x18 32 Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABIM [13:13] Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS 1 13 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMIM [11:11] Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS 1 11 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBEIM [10:10] Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS 1 10 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBMIM [9:9] Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS 1 9 EN 1 Enable Interrupt DIS 0 Disable Interrupt TBTOIM [8:8] Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS 1 8 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAIM [5:5] Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS 1 5 EN 1 Enable Interrupt DIS 0 Disable Interrupt TAMIM [4:4] Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS 1 4 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEIM [2:2] Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS 1 2 EN 1 Enable Interrupt DIS 0 Disable Interrupt CAMIM [1:1] Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS 1 1 EN 1 Enable Interrupt DIS 0 Disable Interrupt TATOIM [0:0] Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS 1 0 EN 1 Enable Interrupt DIS 0 Disable Interrupt 0x0 RIS 0x1c 32 Raw Interrupt Status Associated registers: IMR, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABRIS [13:13] GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMRIS [11:11] GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. 1 11 CBERIS [10:10] GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 10 CBMRIS [9:9] GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. 1 9 TBTORIS [8:8] GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAARIS [5:5] GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 5 TAMRIS [4:4] GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAERIS [2:2] GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 2 CAMRIS [1:1] GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. 1 1 TATORIS [0:0] GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. 1 0 0x0 MIS 0x20 32 Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABMIS [13:13] 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMMIS [11:11] 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 1 11 CBEMIS [10:10] 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 1 10 CBMMIS [9:9] 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 1 9 TBTOMIS [8:8] 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAMIS [5:5] 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 1 5 TAMMIS [4:4] 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEMIS [2:2] 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 1 2 CAMMIS [1:1] 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 1 1 TATOMIS [0:0] 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 1 0 0x0 ICLR 0x24 32 Interrupt Clear This register is used to clear status bits in the RIS and MIS registers RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABINT [13:13] 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMCINT [11:11] 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS 1 11 CBECINT [10:10] 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS 1 10 CBMCINT [9:9] 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS 1 9 TBTOCINT [8:8] 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAINT [5:5] 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS 1 5 TAMCINT [4:4] 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAECINT [2:2] 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS 1 2 CAMCINT [1:1] 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS 1 1 TATOCINT [0:0] 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS 1 0 0x0 TAILR 0x28 32 Timer A Interval Load Register TAILR [31:0] GPT Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of TAILR. 32 0 0xFFFFFFFF TBILR 0x2c 32 Timer B Interval Load Register TBILR [31:0] GPT Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of TBILR. 32 0 0xFFFF TAMATCHR 0x30 32 Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU TAMATCHR [31:0] GPT Timer A Match Register 32 0 0xFFFFFFFF TBMATCHR 0x34 32 Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TBMATCHR [15:0] GPT Timer B Match Register 16 0 0xFFFF TAPR 0x38 32 Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSR [7:0] Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TBPR 0x3c 32 Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSR [7:0] Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TAPMR 0x40 32 Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSMR [7:0] GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TBPMR 0x44 32 Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSMR [7:0] GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TAR 0x48 32 Timer A Register This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the Timer B (TBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (TAPS) register. TAR [31:0] GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFFFFFF TBR 0x4c 32 Timer B Register This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register. TBR [31:0] GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFF TAV 0x50 32 Timer A Value When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use this value to determine the time elapsed between an interrupt and the ISR entry when using the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the TAR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TAV [31:0] GPT Timer A Register A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the TAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFFFFFF TBV 0x54 32 Timer B Value When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the TBR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TBV [31:0] GPT Timer B Register A read returns the current, free-running value of Timer B in all modes. When written, the value written into this register is loaded into the TBR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFF TAPS 0x5c 32 Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer A Pre-scaler 8 0 0x0 TBPS 0x60 32 Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer B Pre-scaler 8 0 0x0 TAPV 0x64 32 Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer A Pre-scaler Value 8 0 0x0 TBPV 0x68 32 Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer B Pre-scaler Value 8 0 0x0 DMAEV 0x6c 32 DMA Event This register allows software to enable/disable GPT DMA trigger events. RESERVED12 [31:12] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 20 12 TBMDMAEN [11:11] GPT Timer B Match DMA Trigger Enable 1 11 CBEDMAEN [10:10] GPT Timer B Capture Event DMA Trigger Enable 1 10 CBMDMAEN [9:9] GPT Timer B Capture Match DMA Trigger Enable 1 9 TBTODMAEN [8:8] GPT Timer B Time-Out DMA Trigger Enable 1 8 RESERVED5 [7:5] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 3 5 TAMDMAEN [4:4] GPT Timer A Match DMA Trigger Enable 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEDMAEN [2:2] GPT Timer A Capture Event DMA Trigger Enable 1 2 CAMDMAEN [1:1] GPT Timer A Capture Match DMA Trigger Enable 1 1 TATODMAEN [0:0] GPT Timer A Time-Out DMA Trigger Enable 1 0 0x0 VERSION 0xfb0 32 Peripheral Version This register provides information regarding the GPT version VERSION [31:0] Timer Revision. 32 0 0x400 ANDCCP 0xfb4 32 Combined CCP Output This register is used to logically AND CCP output pairs for each timer RESERVED1 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 LD_TO_EN [1:1] PWM assertion would happen at timeout 0: PWM assertion happens when counter matches load value 1: PWM assertion happens at timeout of the counter 1 1 CCP_AND_EN [0:0] Enables AND operation of the CCP outputs for timers A and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. 1 0 0x0 GPT3 0x40013000 0 0x1000 registers General Purpose Timer. CFG 0x0 32 Configuration RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 CFG [2:0] GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved 3 0 16BIT_TIMER 4 16-bit timer configuration. Configure for two 16-bit timers. Also see TAMR.TAMR and TBMR.TBMR. 32BIT_TIMER 0 32-bit timer configuration 0x0 TAMR 0x4 32 Timer A Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TACINTD [12:12] One-Shot/Periodic Interrupt Disable 1 12 DIS_TO_INTR 1 Time-out interrupt are disabled EN_TO_INTR 0 Time-out interrupt function as normal TAPLO [11:11] GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TAMRSU [10:10] Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TAMATCHR and TAPR, if used, on the next time-out. CYCLEUPDATE 0 Update TAMATCHR and TAPR, if used, on the next cycle. TAPWMIE [9:9] GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TAILD [8:8] GPT Timer A PWM Interval Load Write 1 8 TOUPDATE 1 Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout. CYCLEUPDATE 0 Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle. TASNAPS [7:7] GPT Timer A Snap-Shot Mode 1 7 EN 1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register. DIS 0 Snap-shot mode is disabled. TAWOT [6:6] GPT Timer A Wait-On-Trigger 1 6 WAIT 1 If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer A begins counting as soon as it is enabled. TAMIE [5:5] GPT Timer A Match Interrupt Enable 1 5 EN 1 An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TACDIR [4:4] GPT Timer A Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TAAMS [3:3] GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TACM [2:2] GPT Timer A Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TAMR [1:0] GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 TBMR 0x8 32 Timer B Mode RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TCACT [15:13] Timer Compare Action Select 3 13 CLRSET_ON_TO 7 Clear CCP output pin immediately and set on Time-Out SETCLR_ON_TO 6 Set CCP output pin immediately and clear on Time-Out CLRTOG_ON_TO 5 Clear CCP output pin immediately and toggle on Time-Out SETTOG_ON_TO 4 Set CCP output pin immediately and toggle on Time-Out SET_ON_TO 3 Set CCP output pin on Time-Out CLR_ON_TO 2 Clear CCP output pin on Time-Out TOG_ON_TO 1 Toggle State on Time-Out DIS_CMP 0 Disable compare operations TBCINTD [12:12] One-Shot/Periodic Interrupt Mode 1 12 DIS_TO_INTR 1 Mask Time-Out Interrupt EN_TO_INTR 0 Normal Time-Out Interrupt TBPLO [11:11] GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 1 11 CCP_ON_TO 1 CCP output pin is set to 1 on time-out LEGACY 0 Legacy operation TBMRSU [10:10] Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit. 1 10 TOUPDATE 1 Update TBMATCHR and TBPR, if used, on the next time-out. CYCLEUPDATE 0 Update TBMATCHR and TBPR, if used, on the next cycle. TBPWMIE [9:9] GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 1 9 EN 1 Interrupt is enabled. This bit is only valid in PWM mode. DIS 0 Interrupt is disabled. TBILD [8:8] GPT Timer B PWM Interval Load Write 1 8 TOUPDATE 1 Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout. CYCLEUPDATE 0 Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle. TBSNAPS [7:7] GPT Timer B Snap-Shot Mode 1 7 EN 1 If Timer B is configured in the periodic mode DIS 0 Snap-shot mode is disabled. TBWOT [6:6] GPT Timer B Wait-On-Trigger 1 6 WAIT 1 If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This function is valid for one-shot, periodic, and PWM modes NOWAIT 0 Timer B begins counting as soon as it is enabled. TBMIE [5:5] GPT Timer B Match Interrupt Enable. 1 5 EN 1 An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes. DIS 0 The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. TBCDIR [4:4] GPT Timer B Count Direction 1 4 UP 1 The timer counts up. When counting up, the timer starts from a value of 0x0. DOWN 0 The timer counts down. TBAMS [3:3] GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2. 1 3 PWM 1 PWM mode is enabled CAP_COMP 0 Capture/Compare mode is enabled. TBCM [2:2] GPT Timer B Capture Mode 1 2 EDGTIME 1 Edge-Time mode EDGCNT 0 Edge-Count mode TBMR [1:0] GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 2 0 CAPTURE 3 Capture mode PERIODIC 2 Periodic Timer mode ONE_SHOT 1 One-Shot Timer mode 0x0 CTL 0xc 32 Control RESERVED15 [31:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 17 15 TBPWML [14:14] GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted. 1 14 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED12 [13:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 12 TBEVENT [11:10] GPT Timer B Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 10 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TBSTALL [9:9] GPT Timer B Stall Enable 1 9 EN 1 Timer B freezes counting while the processor is halted by the debugger. DIS 0 Timer B continues counting while the processor is halted by the debugger. TBEN [8:8] GPT Timer B Enable 1 8 EN 1 Timer B is enabled and begins counting or the capture logic is enabled based on CFG register. DIS 0 Timer B is disabled. RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 TAPWML [6:6] GPT Timer A PWM Output Level 1 6 INVERTED 1 Inverted NORMAL 0 Not inverted RESERVED4 [5:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 4 TAEVENT [3:2] GPT Timer A Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 2 2 BOTH 3 Both edges NEG 1 Negative edge POS 0 Positive edge TASTALL [1:1] GPT Timer A Stall Enable 1 1 EN 1 Timer A freezes counting while the processor is halted by the debugger. DIS 0 Timer A continues counting while the processor is halted by the debugger. TAEN [0:0] GPT Timer A Enable 1 0 EN 1 Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register. DIS 0 Timer A is disabled. 0x0 SYNC 0x10 32 Synch Register RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SYNC3 [7:6] Synchronize GPT Timer 3. 2 6 BOTH 3 A timeout event for both Timer A and Timer B of GPT3 is triggered TIMERB 2 A timeout event for Timer B of GPT3 is triggered TIMERA 1 A timeout event for Timer A of GPT3 is triggered NOSYNC 0 No Sync. GPT3 is not affected. SYNC2 [5:4] Synchronize GPT Timer 2. 2 4 BOTH 3 A timeout event for both Timer A and Timer B of GPT2 is triggered TIMERB 2 A timeout event for Timer B of GPT2 is triggered TIMERA 1 A timeout event for Timer A of GPT2 is triggered NOSYNC 0 No Sync. GPT2 is not affected. SYNC1 [3:2] Synchronize GPT Timer 1 2 2 BOTH 3 A timeout event for both Timer A and Timer B of GPT1 is triggered TIMERB 2 A timeout event for Timer B of GPT1 is triggered TIMERA 1 A timeout event for Timer A of GPT1 is triggered NOSYNC 0 No Sync. GPT1 is not affected. SYNC0 [1:0] Synchronize GPT Timer 0 2 0 BOTH 3 A timeout event for both Timer A and Timer B of GPT0 is triggered TIMERB 2 A timeout event for Timer B of GPT0 is triggered TIMERA 1 A timeout event for Timer A of GPT0 is triggered NOSYNC 0 No Sync. GPT0 is not affected. 0x0 IMR 0x18 32 Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABIM [13:13] Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS 1 13 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMIM [11:11] Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS 1 11 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBEIM [10:10] Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS 1 10 EN 1 Enable Interrupt DIS 0 Disable Interrupt CBMIM [9:9] Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS 1 9 EN 1 Enable Interrupt DIS 0 Disable Interrupt TBTOIM [8:8] Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS 1 8 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAIM [5:5] Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS 1 5 EN 1 Enable Interrupt DIS 0 Disable Interrupt TAMIM [4:4] Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS 1 4 EN 1 Enable Interrupt DIS 0 Disable Interrupt RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEIM [2:2] Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS 1 2 EN 1 Enable Interrupt DIS 0 Disable Interrupt CAMIM [1:1] Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS 1 1 EN 1 Enable Interrupt DIS 0 Disable Interrupt TATOIM [0:0] Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS 1 0 EN 1 Enable Interrupt DIS 0 Disable Interrupt 0x0 RIS 0x1c 32 Raw Interrupt Status Associated registers: IMR, MIS, ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABRIS [13:13] GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMRIS [11:11] GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. 1 11 CBERIS [10:10] GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 10 CBMRIS [9:9] GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. 1 9 TBTORIS [8:8] GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAARIS [5:5] GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed 1 5 TAMRIS [4:4] GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAERIS [2:2] GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode 1 2 CAMRIS [1:1] GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. 1 1 TATORIS [0:0] GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. 1 0 0x0 MIS 0x20 32 Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABMIS [13:13] 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMMIS [11:11] 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 1 11 CBEMIS [10:10] 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 1 10 CBMMIS [9:9] 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 1 9 TBTOMIS [8:8] 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAMIS [5:5] 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 1 5 TAMMIS [4:4] 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEMIS [2:2] 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 1 2 CAMMIS [1:1] 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 1 1 TATOMIS [0:0] 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 1 0 0x0 ICLR 0x24 32 Interrupt Clear This register is used to clear status bits in the RIS and MIS registers RESERVED14 [31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 18 14 DMABINT [13:13] 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS 1 13 RESERVED12 [12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 12 TBMCINT [11:11] 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS 1 11 CBECINT [10:10] 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS 1 10 CBMCINT [9:9] 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS 1 9 TBTOCINT [8:8] 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS 1 8 RESERVED6 [7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 6 DMAAINT [5:5] 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS 1 5 TAMCINT [4:4] 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAECINT [2:2] 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS 1 2 CAMCINT [1:1] 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS 1 1 TATOCINT [0:0] 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS 1 0 0x0 TAILR 0x28 32 Timer A Interval Load Register TAILR [31:0] GPT Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of TAILR. 32 0 0xFFFFFFFF TBILR 0x2c 32 Timer B Interval Load Register TBILR [31:0] GPT Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of TBILR. 32 0 0xFFFF TAMATCHR 0x30 32 Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU TAMATCHR [31:0] GPT Timer A Match Register 32 0 0xFFFFFFFF TBMATCHR 0x34 32 Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 TBMATCHR [15:0] GPT Timer B Match Register 16 0 0xFFFF TAPR 0x38 32 Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSR [7:0] Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TBPR 0x3c 32 Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSR [7:0] Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 8 0 0x0 TAPMR 0x40 32 Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TAPSMR [7:0] GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TBPMR 0x44 32 Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TBPSMR [7:0] GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. 8 0 0x0 TAR 0x48 32 Timer A Register This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the Timer B (TBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (TAPS) register. TAR [31:0] GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFFFFFF TBR 0x4c 32 Timer B Register This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register. TBR [31:0] GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 32 0 0xFFFF TAV 0x50 32 Timer A Value When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use this value to determine the time elapsed between an interrupt and the ISR entry when using the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the TAR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TAV [31:0] GPT Timer A Register A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the TAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFFFFFF TBV 0x54 32 Timer B Value When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the TBR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. TBV [31:0] GPT Timer B Register A read returns the current, free-running value of Timer B in all modes. When written, the value written into this register is loaded into the TBR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect 32 0 0xFFFF TAPS 0x5c 32 Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer A Pre-scaler 8 0 0x0 TBPS 0x60 32 Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSS [7:0] GPT Timer B Pre-scaler 8 0 0x0 TAPV 0x64 32 Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer A Pre-scaler Value 8 0 0x0 TBPV 0x68 32 Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PSV [7:0] GPT Timer B Pre-scaler Value 8 0 0x0 DMAEV 0x6c 32 DMA Event This register allows software to enable/disable GPT DMA trigger events. RESERVED12 [31:12] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 20 12 TBMDMAEN [11:11] GPT Timer B Match DMA Trigger Enable 1 11 CBEDMAEN [10:10] GPT Timer B Capture Event DMA Trigger Enable 1 10 CBMDMAEN [9:9] GPT Timer B Capture Match DMA Trigger Enable 1 9 TBTODMAEN [8:8] GPT Timer B Time-Out DMA Trigger Enable 1 8 RESERVED5 [7:5] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 3 5 TAMDMAEN [4:4] GPT Timer A Match DMA Trigger Enable 1 4 RESERVED3 [3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 3 CAEDMAEN [2:2] GPT Timer A Capture Event DMA Trigger Enable 1 2 CAMDMAEN [1:1] GPT Timer A Capture Match DMA Trigger Enable 1 1 TATODMAEN [0:0] GPT Timer A Time-Out DMA Trigger Enable 1 0 0x0 VERSION 0xfb0 32 Peripheral Version This register provides information regarding the GPT version VERSION [31:0] Timer Revision. 32 0 0x400 ANDCCP 0xfb4 32 Combined CCP Output This register is used to logically AND CCP output pairs for each timer RESERVED1 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 LD_TO_EN [1:1] PWM assertion would happen at timeout 0: PWM assertion happens when counter matches load value 1: PWM assertion happens at timeout of the counter 1 1 CCP_AND_EN [0:0] Enables AND operation of the CCP outputs for timers A and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. 1 0 0x0 I2C0 0x40002000 0 0x1000 registers I2CMaster/Slave Serial Controler SOAR 0x0 32 Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus. RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 OAR [6:0] I2C slave own address This field specifies bits a6 through a0 of the slave address. 7 0 0x0 SSTAT 0x4 32 Slave Status Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 FBR [2:2] First byte received 0: The first byte has not been received. 1: The first byte following the slave's own address has been received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR register. Note: This bit is not used for slave transmit operations. 1 2 TREQ [1:1] Transmit request 0: No outstanding transmit request. 1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register. 1 1 RREQ [0:0] Receive request 0: No outstanding receive data 1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register. 1 0 0x0 SCTL 0x4 32 Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read. RESERVED1 [31:1] Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. 31 1 DA [0:0] Device active 0: Disables the I2C slave operation 1: Enables the I2C slave operation 1 0 0x0 SDR 0x8 32 Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 DATA [7:0] Data for transfer This field contains the data for transfer during a slave receive or transmit operation. When written the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write for transmit or by an external master for receive. 8 0 0x0 SIMR 0xc 32 Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 STOPIM [2:2] Stop condition interrupt mask 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller. 1 2 EN 1 Enable Interrupt DIS 0 Disable Interrupt STARTIM [1:1] Start condition interrupt mask 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller. 1 1 EN 1 Enable Interrupt DIS 0 Disable Interrupt DATAIM [0:0] Data interrupt mask 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller. 1 0 0x0 SRIS 0x10 32 Slave Raw Interrupt Status This register shows the unmasked interrupt status. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 STOPRIS [2:2] Stop condition raw interrupt status 0: No interrupt 1: A Stop condition interrupt is pending. This bit is cleared by writing a 1 to SICR.STOPIC. 1 2 STARTRIS [1:1] Start condition raw interrupt status 0: No interrupt 1: A Start condition interrupt is pending. This bit is cleared by writing a 1 to SICR.STARTIC. 1 1 DATARIS [0:0] Data raw interrupt status 0: No interrupt 1: A data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC. 1 0 0x0 SMIS 0x14 32 Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR). RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 STOPMIS [2:2] Stop condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Stop condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STOPIC. 1 2 STARTMIS [1:1] Start condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Start condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STARTIC. 1 1 DATAMIS [0:0] Data masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC. 1 0 0x0 SICR 0x18 32 Slave Interrupt Clear This register clears the raw interrupt SRIS. RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 STOPIC [2:2] Stop condition interrupt clear Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. 1 2 STARTIC [1:1] Start condition interrupt clear Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. 1 1 DATAIC [0:0] Data interrupt clear Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. 1 0 0x0 MSA 0x800 32 Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SA [7:1] I2C master slave address Defines which slave is addressed for the transaction in master mode 7 1 RS [0:0] Receive or Send This bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA. 1 0 RX 1 Receive data from slave TX 0 Transmit/send data to slave 0x0 MSTAT 0x804 32 Master Status RESERVED7 [31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 25 7 BUSBSY [6:6] Bus busy 0: The I2C bus is idle. 1: The I2C bus is busy. The bit changes based on the MCTRL.START and MCTRL.STOP conditions. 1 6 IDLE [5:5] I2C idle 0: The I2C controller is not idle. 1: The I2C controller is idle. 1 5 ARBLST [4:4] Arbitration lost 0: The I2C controller won arbitration. 1: The I2C controller lost arbitration. 1 4 DATACK_N [3:3] Data Was Not Acknowledge 0: The transmitted data was acknowledged. 1: The transmitted data was not acknowledged. 1 3 ADRACK_N [2:2] Address Was Not Acknowledge 0: The transmitted address was acknowledged. 1: The transmitted address was not acknowledged. 1 2 ERR [1:1] Error 0: No error was detected on the last operation. 1: An error occurred on the last operation. 1 1 BUSY [0:0] I2C busy 0: The controller is idle. 1: The controller is busy. When this bit-field is set, the other status bits are not valid. Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been initiated through MCTRL register. Hence after programming MCTRL register, application is requested to wait for four SYSBUS clock cycles before issuing a controller status inquiry through MSTAT register. Any prior inquiry would result in wrong status being reported. 1 0 0x20 MCTRL 0x804 32 Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register. RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 ACK [3:3] Data acknowledge enable 0: The received data byte is not acknowledged automatically by the master. 1: The received data byte is acknowledged automatically by the master. This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. 1 3 EN 1 Enable acknowledge DIS 0 Disable acknowledge STOP [2:2] This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. 0: The controller does not generate the Stop condition. 1: The controller generates the Stop condition. 1 2 EN 1 Enable STOP DIS 0 Disable STOP START [1:1] This bit-field generates the Start or Repeated Start condition. 0: The controller does not generate the Start condition. 1: The controller generates the Start condition. 1 1 EN 1 Enable START DIS 0 Disable START RUN [0:0] I2C master enable 0: The master is disabled. 1: The master is enabled to transmit or receive data. 1 0 EN 1 Enable Master DIS 0 Disable Master 0x0 MDR 0x808 32 Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 DATA [7:0] When Read: Last RX Data is returned When Written: Data is transferred during TX transaction 8 0 0x0 MTPR 0x80c 32 I2C Master Timer Period This register specifies the period of the SCL clock. RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TPR_7 [7:7] Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. 1 7 TPR [6:0] SCL clock period This field specifies the period of the SCL clock. SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the timer period register value (range of 1 to 127) SCL_LP is the SCL low period (fixed at 6). SCL_HP is the SCL high period (fixed at 4). CLK_PRD is the system clock period in ns. 7 0 0x1 MIMR 0x810 32 Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 IM [0:0] Interrupt mask 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller. 1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set. 1 0 EN 1 Enable Interrupt DIS 0 Disable Interrupt 0x0 MRIS 0x814 32 Master Raw Interrupt Status This register show the unmasked interrupt status. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 RIS [0:0] Raw interrupt status 0: No interrupt 1: A master interrupt is pending. This bit is cleared by writing 1 to the MICR.IC bit . 1 0 0x0 MMIS 0x818 32 Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR). RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 MIS [0:0] Masked interrupt status 0: An interrupt has not occurred or is masked. 1: A master interrupt is pending. This bit is cleared by writing 1 to the MICR.IC bit . 1 0 0x0 MICR 0x81c 32 Master Interrupt Clear This register clears the raw and masked interrupt. RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 IC [0:0] Interrupt clear Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . Reading this register returns no meaningful data. 1 0 0x0 MCR 0x820 32 Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 SFE [5:5] I2C slave function enable 1 5 EN 1 Slave mode is enabled. DIS 0 Slave mode is disabled. MFE [4:4] I2C master function enable 1 4 EN 1 Master mode is enabled. DIS 0 Master mode is disabled. RESERVED1 [3:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 1 LPBK [0:0] I2C loopback 0: Normal operation 1: Loopback operation (test mode) 1 0 EN 1 Enable Test Mode DIS 0 Disable Test Mode 0x0 I2S0 0x40021000 0 0x1000 registers I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP AIFWCLKSRC 0x0 32 WCLK Source Selection RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 WCLK_INV [2:2] Inverts WCLK source (pad or internal) when set. 0: Not inverted 1: Inverted 1 2 WCLK_SRC [1:0] Selects WCLK source for AIF (should be the same as the BCLK source). The BCLK source is defined in the PRCM:I2SBCLKSEL.SRC 2 0 RESERVED 3 Not supported. Will give same WCLK as 'NONE' ('00') INT 2 Internal WCLK generator, from module PRCM EXT 1 External WCLK generator, from pad NONE 0 None ('0') 0x0 AIFDMACFG 0x4 32 DMA Buffer Size Configuration RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 END_FRAME_IDX [7:0] Defines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes AIF. Note that before doing so, all other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must have been loaded. 8 0 0x0 AIFDIRCFG 0x8 32 Pin Direction RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 AD1 [5:4] Configures the AD1 audio data pin usage: 0x3: Reserved 2 4 OUT 2 Output mode IN 1 Input mode DIS 0 Not in use (disabled) RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 AD0 [1:0] Configures the AD0 audio data pin usage: 0x3: Reserved 2 0 OUT 2 Output mode IN 1 Input mode DIS 0 Not in use (disabled) 0x0 AIFFMTCFG 0xc 32 Serial Interface Format Configuration RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DATA_DELAY [15:8] The number of BCLK periods between a WCLK edge and MSB of the first word in a phase: 0x00: LJF and DSP format 0x01: I2S and DSP format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired. 8 8 MEM_LEN_24 [7:7] The size of each word stored to or loaded from memory: 1 7 24BIT 1 24-bit (one 8 bit and one 16 bit locked access per sample) 16BIT 0 16-bit (one 16 bit access per sample) SMPL_EDGE [6:6] On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK. 1 6 POS 1 Data is sampled on the positive edge and clocked out on the negative edge. NEG 0 Data is sampled on the negative edge and clocked out on the positive edge. DUAL_PHASE [5:5] Selects dual- or single-phase format. 0: Single-phase: DSP format 1: Dual-phase: I2S, LJF and RJF formats 1 5 WORD_LEN [4:0] Number of bits per word (8-24): In single-phase format, this is the exact number of bits per word. In dual-phase format, this is the maximum number of bits per word. Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from this alignment will either be truncated or zero padded. 5 0 0x170 AIFWMASK0 0x10 32 Word Selection Bit Mask for Pin 0 RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 MASK [7:0] Bit-mask indicating valid channels in a frame on AD0. In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins. 8 0 0x3 AIFWMASK1 0x14 32 Word Selection Bit Mask for Pin 1 RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 MASK [7:0] Bit-mask indicating valid channels in a frame on AD1. In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins. 8 0 0x3 AIFWMASK2 0x18 32 Internal. Only to be used through TI provided API. RESERVED0 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 AIFPWMVALUE 0x1c 32 Audio Interface PWM Debug Value RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 PULSE_WIDTH [15:0] The value written to this register determines the width of the active high PWM pulse (pwm_debug), which starts together with MSB of the first output word in a DMA buffer: 0x0000: Constant low 0x0001: Width of the pulse (number of BCLK cycles, here 1). ... 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). 0xFFFF: Constant high 16 0 0x0 AIFINPTRNEXT 0x20 32 DMA Input Buffer Next Pointer PTR [31:0] Pointer to the first byte in the next DMA input buffer. The read value equals the last written value until the currently used DMA input buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.AIF_DMA_IN. At startup, the value must be written once before and once after configuring the DMA buffer size in AIFDMACFG. The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. 32 0 0x0 AIFINPTR 0x24 32 DMA Input Buffer Current Pointer PTR [31:0] Value of the DMA input buffer pointer currently used by the DMA controller. Incremented by 1 (byte) or 2 (word) for each AHB access. 32 0 0x0 AIFOUTPTRNEXT 0x28 32 DMA Output Buffer Next Pointer PTR [31:0] Pointer to the first byte in the next DMA output buffer. The read value equals the last written value until the currently used DMA output buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.AIF_DMA_OUT. At startup, the value must be written once before and once after configuring the DMA buffer size in AIFDMACFG. At this time, the first two samples will be fetched from memory. The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. 32 0 0x0 AIFOUTPTR 0x2c 32 DMA Output Buffer Current Pointer PTR [31:0] Value of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 (byte) or 2 (word) for each AHB access. 32 0 0x0 STMPCTL 0x34 32 Samplestamp Generator Control Register RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 OUT_RDY [2:2] Low until the output pins are ready to be started by the samplestamp generator. When started (that is STMPOUTTRIG equals the WCLK counter) the bit goes back low. 1 2 IN_RDY [1:1] Low until the input pins are ready to be started by the samplestamp generator. When started (that is STMPINTRIG equals the WCLK counter) the bit goes back low. 1 1 STMP_EN [0:0] Enables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured. When cleared, all samplestamp generator counters and capture values are cleared. 1 0 0x0 STMPXCNTCAPT0 0x38 32 Captured XOSC Counter Value, Capture Channel 0 RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CAPT_VALUE [15:0] The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK. The value is cleared when STMPCTL.STMP_EN = 0. Note: Due to buffering and synchronization, WCLK is delayed by a small number of BCLK periods and clk periods. Note: When calculating the fractional part of the sample stamp, STMPXPER may be less than this bit field. 16 0 0x0 STMPXPER 0x3c 32 XOSC Period Value RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge, had it not been reset to 0). The value is cleared when STMPCTL.STMP_EN = 0. 16 0 0x0 STMPWCNTCAPT0 0x40 32 Captured WCLK Counter Value, Capture Channel 0 RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CAPT_VALUE [15:0] The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 0). This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled (not taking modification through STMPWADD/STMPWSET into account). The value is cleared when STMPCTL.STMP_EN = 0. 16 0 0x0 STMPWPER 0x44 32 WCLK Counter Period Value RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer. This is thus a modulo value for the WCLK counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1). 16 0 0x0 STMPINTRIG 0x48 32 WCLK Counter Trigger Value for Input Pins RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 IN_START_WCNT [15:0] Compare value used to start the incoming audio streams. This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first DMA input buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as inputs in AIFDIRCFG. - AIFDMACFG has been configured for the correct buffer size, and at least 32 BCLK cycle ticks have happened. Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE. 16 0 0x0 STMPOUTTRIG 0x4c 32 WCLK Counter Trigger Value for Output Pins RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 OUT_START_WCNT [15:0] Compare value used to start the outgoing audio streams. This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first DMA output buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as outputs in AIFDIRCFG. - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK cycle ticks have happened. - 2 samples have been preloaded from memory (examine the AIFOUTPTR register if necessary). Note: The memory read access is only performed when required, that is channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE. 16 0 0x0 STMPWSET 0x50 32 WCLK Counter Set Operation RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] WCLK counter modification: Sets the running WCLK counter equal to the written value. 16 0 0x0 STMPWADD 0x54 32 WCLK Counter Add Operation RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE_INC [15:0] WCLK counter modification: Adds the written value to the running WCLK counter. If a positive edge of WCLK occurs at the same time as the operation, this will be taken into account. To add a negative value, write "STMPWPER.VALUE - value". 16 0 0x0 STMPXPERMIN 0x58 32 XOSC Minimum Period Value Minimum Value of STMPXPER RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 VALUE [15:0] Each time STMPXPER is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register. When written, the register is reset to 0xFFFF (65535), regardless of the value written. The minimum value can be used to detect extra WCLK pulses (this registers value will be significantly smaller than STMPXPER.VALUE). 16 0 0xFFFF STMPWCNT 0x5c 32 Current Value of WCNT RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CURR_VALUE [15:0] Current value of the WCLK counter 16 0 0x0 STMPXCNT 0x60 32 Current Value of XCNT RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CURR_VALUE [15:0] Current value of the XOSC counter, latched when reading STMPWCNT. 16 0 0x0 STMPXCNTCAPT1 0x64 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 CAPT_VALUE [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 STMPWCNTCAPT1 0x68 32 Internal. Only to be used through TI provided API. RESERVED16 [31:16] Internal. Only to be used through TI provided API. 16 16 CAPT_VALUE [15:0] Internal. Only to be used through TI provided API. 16 0 0x0 IRQMASK 0x70 32 Interrupt Mask Register Selects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event. RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 AIF_DMA_IN [5:5] IRQFLAGS.AIF_DMA_IN interrupt mask 0: Disable 1: Enable 1 5 AIF_DMA_OUT [4:4] IRQFLAGS.AIF_DMA_OUT interrupt mask 0: Disable 1: Enable 1 4 WCLK_TIMEOUT [3:3] IRQFLAGS.WCLK_TIMEOUT interrupt mask 0: Disable 1: Enable 1 3 BUS_ERR [2:2] IRQFLAGS.BUS_ERR interrupt mask 0: Disable 1: Enable 1 2 WCLK_ERR [1:1] IRQFLAGS.WCLK_ERR interrupt mask 0: Disable 1: Enable 1 1 PTR_ERR [0:0] IRQFLAGS.PTR_ERR interrupt mask. 0: Disable 1: Enable 1 0 0x0 IRQFLAGS 0x74 32 Raw Interrupt Status Register RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 AIF_DMA_IN [5:5] Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register for details. 1 5 AIF_DMA_OUT [4:4] Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT register for details 1 4 WCLK_TIMEOUT [3:3] Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_TIMEOUT). 1 3 BUS_ERR [2:2] Set when a DMA operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow). This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.BUS_ERR). Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined. 1 2 WCLK_ERR [1:1] Set when: - An unexpected WCLK edge occurs during the data delay period of a phase. Note unexpected WCLK edges during the word and idle periods of the phase are not detected. - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles apart. - In single-phase mode, when a WCLK pulse occurs before the last channel. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_ERR). 1 1 PTR_ERR [0:0] Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.PTR_ERR). 1 0 0x0 IRQSET 0x78 32 Interrupt Set Register RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 AIF_DMA_IN [5:5] 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria was given at the same time, in which the set will be ignored) 1 5 AIF_DMA_OUT [4:4] 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria was given at the same time, in which the set will be ignored) 1 4 WCLK_TIMEOUT [3:3] 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT 1 3 BUS_ERR [2:2] 1: Sets the interrupt of IRQFLAGS.BUS_ERR 1 2 WCLK_ERR [1:1] 1: Sets the interrupt of IRQFLAGS.WCLK_ERR 1 1 PTR_ERR [0:0] 1: Sets the interrupt of IRQFLAGS.PTR_ERR 1 0 0x0 IRQCLR 0x7c 32 Interrupt Clear Register RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 AIF_DMA_IN [5:5] 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was given at the same time in which the clear will be ignored) 1 5 AIF_DMA_OUT [4:4] 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was given at the same time in which the clear will be ignored) 1 4 WCLK_TIMEOUT [3:3] 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was given at the same time in which the clear will be ignored) 1 3 BUS_ERR [2:2] 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given at the same time in which the clear will be ignored) 1 2 WCLK_ERR [1:1] 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was given at the same time in which the clear will be ignored) 1 1 PTR_ERR [0:0] 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given at the same time in which the clear will be ignored) 1 0 0x0 IOC 0x40081000 0 0x1000 registers IO Controller (IOC) - configures all the DIOs and resides in the MCU domain. IOCFG0 0x0 32 Configuration of DIO0 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input/output OPENSRC 6 Open Source Normal input / outut OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO0 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG1 0x4 32 Configuration of DIO1 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO1 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG2 0x8 32 Configuration of DIO2 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO2 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG3 0xc 32 Configuration of DIO3 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO3 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG4 0x10 32 Configuration of DIO4 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO4 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG5 0x14 32 Configuration of DIO5 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO5 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG6 0x18 32 Configuration of DIO6 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO6 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG7 0x1c 32 Configuration of DIO7 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO7 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG8 0x20 32 Configuration of DIO8 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO8 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG9 0x24 32 Configuration of DIO9 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO9 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG10 0x28 32 Configuration of DIO10 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO10 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG11 0x2c 32 Configuration of DIO11 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO11 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG12 0x30 32 Configuration of DIO12 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO12 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG13 0x34 32 Configuration of DIO13 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO13 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG14 0x38 32 Configuration of DIO14 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO14 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG15 0x3c 32 Configuration of DIO15 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO15 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG16 0x40 32 Configuration of DIO16 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO16 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x86000 IOCFG17 0x44 32 Configuration of DIO17 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO17 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x106000 IOCFG18 0x48 32 Configuration of DIO18 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO18 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG19 0x4c 32 Configuration of DIO19 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO19 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG20 0x50 32 Configuration of DIO20 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO20 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG21 0x54 32 Configuration of DIO21 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO21 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG22 0x58 32 Configuration of DIO22 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO22 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG23 0x5c 32 Configuration of DIO23 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO23 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG24 0x60 32 Configuration of DIO24 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO24 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG25 0x64 32 Configuration of DIO25 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO25 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG26 0x68 32 Configuration of DIO26 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO26 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG27 0x6c 32 Configuration of DIO27 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO27 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG28 0x70 32 Configuration of DIO28 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO28 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG29 0x74 32 Configuration of DIO29 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO29 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG30 0x78 32 Configuration of DIO30 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO30 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 IOCFG31 0x7c 32 Configuration of DIO31 RESERVED31 [31:31] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 31 HYST_EN [30:30] 0: Input hysteresis disable 1: Input hysteresis enable 1 30 IE [29:29] 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. 1 29 WU_CFG [28:27] If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. 2 27 IOMODE [26:24] IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 3 24 OPENSRC_INV 7 Open Source Inverted input / output OPENSRC 6 Open Source Normal input / output OPENDR_INV 5 Open Drain Inverted input / output OPENDR 4 Open Drain, Normal input / output INV 1 Inverted input / ouput NORMAL 0 Normal input / output IOEV_AON_PROG2_EN [23:23] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event 1 23 IOEV_AON_PROG1_EN [22:22] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event 1 22 IOEV_AON_PROG0_EN [21:21] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event 1 21 RESERVED19 [20:19] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 19 EDGE_IRQ_EN [18:18] 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) 1 18 EDGE_DET [17:16] Enable generation of edge detection events on this IO 2 16 BOTH 3 Positive and negative edge detection POS 2 Positive edge detection NEG 1 Negative edge detection NONE 0 No edge detection RESERVED15 [15:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 15 PULL_CTL [14:13] Pull control 2 13 DIS 3 No pull UP 2 Pull up DWN 1 Pull down SLEW_RED [12:12] 0: Normal slew rate 1: Enables reduced slew rate in output driver. 1 12 IOCURR [11:10] Selects IO current mode of this IO. 2 10 4_8MA 2 Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO 4MA 1 High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2MA 0 Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO IOSTR [9:8] Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 2 8 MAX 3 Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) MED 2 Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) MIN 1 Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) AUTO 0 Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) IOEV_RTC_EN [7:7] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event 1 7 IOEV_MCU_WU_EN [6:6] Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event 1 6 PORT_ID [5:0] Selects usage for DIO31 6 0 RFC_SMI_CL_IN 56 RF Core SMI Command Link In RFC_SMI_CL_OUT 55 RF Core SMI Command Link Out RFC_SMI_DL_IN 54 RF Core SMI Data Link In RFC_SMI_DL_OUT 53 RF Core SMI Data Link Out RFC_GPI1 52 RF Core Data In 1 RFC_GPI0 51 RF Core Data In 0 RFC_GPO3 50 RF Core Data Out 3 RFC_GPO2 49 RF Core Data Out 2 RFC_GPO1 48 RF Core Data Out 1 RFC_GPO0 47 RF Core Data Out 0 RFC_TRC 46 RF Core Trace I2S_MCLK 41 I2S MCLK I2S_BCLK 40 I2S BCLK I2S_WCLK 39 I2S WCLK I2S_AD1 38 I2S Data 1 I2S_AD0 37 I2S Data 0 SSI1_CLK 36 SSI1 CLK SSI1_FSS 35 SSI1 FSS SSI1_TX 34 SSI1 TX SSI1_RX 33 SSI1 RX CPU_SWV 32 CPU SWV PORT_EVENT7 30 PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT6 29 PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT5 28 PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT4 27 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT3 26 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT2 25 PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT1 24 PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on PORT_EVENT0 23 PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on UART1_RTS 22 UART1 RTS UART1_CTS 21 UART1 CTS UART1_TX 20 UART1 TX UART1_RX 19 UART1 RX UART0_RTS 18 UART0 RTS UART0_CTS 17 UART0 CTS UART0_TX 16 UART0 TX UART0_RX 15 UART0 RX I2C_MSSCL 14 I2C Clock I2C_MSSDA 13 I2C Data SSI0_CLK 12 SSI0 CLK SSI0_FSS 11 SSI0 FSS SSI0_TX 10 SSI0 TX SSI0_RX 9 SSI0 RX AUX_IO 8 AUX IO AON_CLK32K 7 AON 32 KHz clock (SCLK_LF) GPIO 0 General Purpose IO 0x6000 PKA 0x40025000 0 0x1000 registers Integrated module which combines the Public Key Acceleration module, optional True Random Gnerator, optional interrupt controller and a standard bus interface APTR 0x0 32 PKA Vector A Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. RESERVED11 [31:11] Set to zero on write, ignore on read 21 11 APTR [10:0] This register specifies the location of vector A within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. 11 0 0x0 BPTR 0x4 32 PKA Vector B Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. RESERVED11 [31:11] Set to zero on write, ignore on read 21 11 BPTR [10:0] This register specifies the location of vector B within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. 11 0 0x0 CPTR 0x8 32 PKA Vector C Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. RESERVED11 [31:11] Set to zero on write, ignore on read 21 11 CPTR [10:0] This register specifies the location of vector C within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. 11 0 0x0 DPTR 0xc 32 PKA Vector D Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. RESERVED11 [31:11] Set to zero on write, ignore on read 21 11 DPTR [10:0] This register specifies the location of vector D within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. 11 0 0x0 ALENGTH 0x10 32 PKA Vector A Length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. RESERVED11 [31:9] Set to zero on write, ignore on read 23 9 ALENGTH [8:0] This register specifies the length (in 32-bit words) of Vector A. 9 0 0x0 BLENGTH 0x14 32 PKA Vector B Length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. RESERVED11 [31:9] Set to zero on write, ignore on read 23 9 BLENGTH [8:0] This register specifies the length (in 32-bit words) of Vector B. 9 0 0x0 SHIFT 0x18 32 PKA Bit Shift Value For basic PKCP operations, modifying the contents of this register is made impossible while the operation is being performed. For the ExpMod-variable and ExpMod-CRT operations, this register is used to indicate the number of odd powers to use (directly as a value in the range 1-16). For the ModInv and ECC operations, this register is used to hold a completion code. RESERVED11 [31:5] Set to zero on write, ignore on read 27 5 NUM_BITS_TO_SHIFT [4:0] This register specifies the number of bits to shift the input vector (in the range 0-31) during a Rshift or Lshift operation. 5 0 0x0 FUNCTION 0x1c 32 PKA Function This register contains the control bits to start basic PKCP as well as complex sequencer operations. The run bit can be used to poll for the completion of the operation. Modifying bits [11:0] is made impossible during the execution of a basic PKCP operation. During the execution of sequencer-controlled complex operations, this register is modified, the run and stall result bits are set to zero at the conclusion, but other bits are undefined. NOTE: Continuously reading this register to poll the run bit is not allowed when executing complex sequencer operations (the sequencer cannot access the PKCP when this is done). Leave at least one sysclk cycle between poll operations. RESERVED25 [31:25] Set to zero on write, ignore on read 7 25 STALL_RESULT [24:24] When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW registers, as well as resetting the run bit is stalled beyond the point that a running operation is actually finished. Use this to allow software enough time to read results from a previous operation when the newly started operation is known to take only a short amount of time. If a result is waiting, the result registers is updated and the run bit is reset in the clock cycle following writing the stall result bit back to 0b. The Stall result function may only be used for basic PKCP operations. 1 24 RESERVED16 [23:16] Set to zero on write, ignore on read 8 16 RUN [15:15] The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation. This bit is reset low automatically when the operation is complete. After a reset, the run bit is always set to 1b. Depending on the option, program ROM or program RAM, the following applies: Program ROM - The first sequencer instruction sets the bit to 0b. This is done immediately after the hardware reset is released. Program RAM - The sequencer must set the bit to 0b. As a valid firmware may not have been loaded, the sequencer is held in software reset after the hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the FW image is loaded and the Reset bit is cleared, the sequencer starts to execute the FW. The first instruction clears the run bit. In both cases a few clock cycles are needed before the first instruction is executed and the run bit state has been propagated. 1 15 SEQUENCER_OPERATIONS [14:12] These bits select the complex sequencer operation to perform: 0x0: None 0x1: ExpMod-CRT 0x2: ECmontMUL 0x3: ECC-ADD (if available in firmware, otherwise reserved) 0x4: ExpMod-ACT2 0x5: ECC-MUL (if available in firmware, otherwise reserved) 0x6: ExpMod-variable 0x7: ModInv (if available in firmware, otherwise reserved) The encoding of these operations is determined by sequencer firmware. 3 12 COPY [11:11] Perform copy operation 1 11 COMPARE [10:10] Perform compare operation 1 10 MODULO [9:9] Perform modulo operation 1 9 DIVIDE [8:8] Perform divide operation 1 8 LSHIFT [7:7] Perform left shift operation 1 7 RSHIFT [6:6] Perform right shift operation 1 6 SUBTRACT [5:5] Perform subtract operation 1 5 ADD [4:4] Perform add operation 1 4 MS_ONE [3:3] Loads the location of the Most Significant one bit within the result word indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS register - can only be used with basic PKCP operations, except for Divide, Modulo and Compare. 1 3 RESERVED2 [2:2] Set to zero on write, ignore on read 1 2 ADDSUB [1:1] Perform combined add/subtract operation 1 1 MULTIPLY [0:0] Perform multiply operation 1 0 0x8000 COMPARE 0x20 32 PKA compare result This register provides the result of a basic PKCP compare operation. It is updated when the FUNCTION.RUN bit is reset at the end of that operation. Status after a complex sequencer operation is unknown RESERVED3 [31:3] Ignore on read 29 3 A_GREATER_THAN_B [2:2] Vector_A is greater than Vector_B 1 2 A_LESS_THAN_B [1:1] Vector_A is less than Vector_B 1 1 A_EQUALS_B [0:0] Vector_A is equal to Vector_B 1 0 0x1 MSW 0x24 32 PKA most-significant-word of result vector This register indicates the (word) address in the PKA RAM where the most significant nonzero 32-bit word of the result is stored. Should be ignored for modulo operations. For basic PKCP operations, this register is updated FUNCTION.RUN bit is reset at the end of the operation. For the complex-sequencer controlled operations, updating of the final value matching the actual result is done near the end of the operation; note that the result is only meaningful if no errors were detected and that for ECC operations, this register will provide information for the x-coordinate of the result point only. RESERVED16 [31:16] Ignore on read 16 16 RESULT_IS_ZERO [15:15] The result vector is all zeroes, ignore the address returned in bits [10:0] 1 15 RESERVED11 [14:11] Ignore on read 4 11 MSW_ADDRESS [10:0] Address of the most-significant nonzero 32-bit word of the result vector in PKA RAM 11 0 0x8000 DIVMSW 0x28 32 PKA most-significant-word of divide remainder This register indicates the (32-bit word) address in the PKA RAM where the most significant nonzero 32-bit word of the remainder result for the basic divide and modulo operations is stored. Bits [4:0] are loaded with the bit number of the most-significant nonzero bit in the most-significant nonzero word when MS one control bit is set. For divide, modulo, and MS one reporting, this register is updated when FUNCTION.RUN bit is reset at the end of the operation. For the complex sequencer controlled operations, updating of bits [4:0] of this register with the most-significant bit location of the actual result is done near the end of the operation. The result is meaningful only if no errors were detected and that for ECC operations; this register provides information for the x-coordinate of the result point only. RESERVED16 [31:16] Ignore on read 16 16 RESULT_IS_ZERO [15:15] The result vector is all zeroes, ignore the address returned in bits [10:0] 1 15 RESERVED11 [14:11] Ignore on read 4 11 MSW_ADDRESS [10:0] Address of the most significant nonzero 32-bit word of the remainder result vector in PKA RAM 11 0 0x8000 SEQCTRL 0xc8 32 PKA sequencer control and status register The sequencer is interfaced with the outside world through a single control and status register. With the exception of bit [31], the actual use of bits in the separate sub-fields of this register is determined by the sequencer firmware. This register need only be accessed when the sequencer program is stored in RAM. The reset value of the RESET bit depends upon the option chosen for sequencer program storage. NOTE: For Agama the sequencer firmware is executed from ROM. RESET [31:31] Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO). Writing 1b resets the sequencer, write to 0b to restart operations again. As the reset value is 0b, the sequencer will automatically start operations executing from program ROM. This bit should always be written with zero and ignored when reading this register. Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is accessible for loading the sequencer program (while the PKA_DATA_RAM is inaccessible), write to 0b to (re)start sequencer operations and disable PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). Resetting the sequencer (in order to load other firmware) should only be done when the PKA Engine is not performing any operations (i.e. the FUNCTION.RUN bit should be zero). 1 31 RESERVED16 [30:16] Set to zero on write, ignore on read 15 16 SEQUENCER_STAT [15:8] These read-only bits can be used by the sequencer to communicate status to the outside world. Bit [8] is also used as sequencer interrupt, with the complement of this bit ORed into the FUNCTION.RUN bit. This field should always be written with zeroes and ignored when reading this register. 8 8 SW_CONTROL_STAT [7:0] These bits can be used by software to trigger sequencer operations. External logic can set these bits by writing 1b, cannot reset them by writing 0b. The sequencer can reset these bits by writing 0b, cannot set them by writing 1b. Setting the FUNCTION.RUN bit together with a nonzero sequencer operations field automatically sets bit [0] here. This field should always be written with zeroes and ignored when reading this register. 8 0 0x100 OPTIONS 0xf4 32 PKA hardware options register This register provides the host with a means to determine the hardware configuration implemented in this PKA engine, focused on options that have an effect on software interacting with the module. RESERVED12 [31:12] Ignore on read 20 12 INT_MASKING [11:11] Interrupt Masking 0x0: indicates that the main interrupt output (bit [1] of the interrupts output bus) is the direct complement of the run bit in the PKA_CONTROL register, 0x1 : indicates that interrupt masking logic is present for this output. Note: Reset value is undefined 1 11 PROTECTION_OPTION [10:8] Protection Option 0x0: indicates no additional protection against side channel attacks, 0x1: indicates the SCAP option 0x2: Reserved 0x3: indicates the PROT option; Note: Reset value is undefined 3 8 PROGRAM_RAM [7:7] Program RAM 0x1: indicates sequencer program storage in RAM, 0x0: indicates sequencer program storage in ROM. Note: Reset value is undefined 1 7 SEQUENCER_CONFIGURATION [6:5] Sequencer Configuration 0x0: Reserved 0x1 : Indicates a standard sequencer 0x2: Reserved 0x3: Reserved 2 5 RESERVED2 [4:2] Ignore on read 3 2 PKCP_CONFIGURATION [1:0] PKCP Configuration 0x0 : Reserved 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved Note: Reset value is undefined. 2 0 0x20 FWREV 0xf8 32 PKA firmware revision and capabilities register This register allows the host access to the internal firmware revision number of the PKA Engine for software driver matching and diagnostic purposes. This register also contains a field that encodes the capabilities of the embedded firmware. This register is written by the firmware within a few clock cycles after starting up that firmware. The hardware reset value is zero, indicating that the information has not been written yet. FW_CAPABILITIES [31:28] Firmware Capabilities 4-bit binary encoding for the functionality implemented in the firmware. 0x0: indicates basic ModExp with/without CRT. 0x1: adds Modular Inversion, 0x2: value 2 adds Modular Inversion and ECC operations. 0x3-0xF : Reserved. 4 28 MAJOR_FW_REVISION [27:24] 4-bit binary encoding of the major firmware revision number 4 24 MINOR_FW_REVISION [23:20] 4-bit binary encoding of the minor firmware revision number 4 20 FW_PATCH_LEVEL [19:16] 4-bit binary encoding of the firmware patch level, initial release will carry value zero Patches are used to remove bugs without changing the functionality or interface of a module. 4 16 RESERVED0 [15:0] Ignore on read 16 0 0x21500000 HWREV 0xfc 32 PKA hardware revision register This register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes. It is always located at the highest address in the access space of the module and contains an encoding of the EIP number (with its complement as signature) for recognition of the hardware module. RESERVED28 [31:28] Ignore on read 4 28 MAJOR_HW_REVISION [27:24] 4-bit binary encoding of the major hardware revision number 4 24 MINOR_HW_REVISION [23:20] 4-bit binary encoding of the minor hardware revision number 4 20 HW_PATCH_LEVEL [19:16] 4-bit binary encoding of the hardware patch level, initial release will carry value zero Patches are used to remove bugs without changing the functionality or interface of a module. 4 16 COMPLEMENT_OF_BASIC_EIP_NUMBER [15:8] Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 8 8 BASIC_EIP_NUMBER [7:0] 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C 8 0 0x151E31C PKA_INT 0x40027000 0 0x1000 registers Integrated module which includes the PKA K RESERVED_0 0x0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED0 [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0xFFFFFFFF OPTIONS 0xff8 32 PKA Options register RESERVED11 [31:11] Ignore on read 21 11 AIC_PRESENT [10:10] When set to '1', indicates that an EIP201 AIC is included in the EIP150 1 10 EIP76_PRESENT [9:9] When set to '1', indicates that the EIP76 TRNG is included in the EIP150 1 9 EIP28_PRESENT [8:8] When set to '1', indicates that the EIP28 PKA is included in the EIP150 1 8 RESERVED4 [7:4] Ignore on read 4 4 AXI_INTERFACE [3:3] When set to '1', indicates that the EIP150 is equipped with a AXI interface 1 3 AHB_IS_ASYNC [2:2] When set to '1', indicates that AHB interface is asynchronous Only applicable when AHB_INTERFACE is 1 1 2 AHB_INTERFACE [1:1] When set to '1', indicates that the EIP150 is equipped with a AHB interface 1 1 PLB_INTERFACE [0:0] When set to '1', indicates that the EIP150 is equipped with a PLB interface 1 0 0x102 REVISION 0xffc 32 PKA hardware revision register This register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes. It is always located at the highest address in the access space of the module and contains an encoding of the EIP number (with its complement as signature) for recognition of the hardware module. RESERVED28 [31:28] These bits should be ignored on read 4 28 MAJOR_REVISION [27:24] These bits encode the major version number for this module 4 24 MINOR_REVISION [23:20] These bits encode the minor version number for this module 4 20 PATCH_LEVEL [19:16] These bits encode the hardware patch level for this module they start at value 0 on the first release 4 16 COMP_EIP_NUM [15:8] These bits simply contain the complement of bits [7:0], used by a driver to ascertain that the EIP150 revision register is indeed read 8 8 EIP_NUM [7:0] These bits encode the AuthenTec EIP number for the EIP150 8 0 0x2006996 PRCM 0x40082000 0 0x1000 registers Power, Reset and Clock Management INFRCLKDIVR 0x0 32 Infrastructure Clock Division Factor For Run Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 RATIO [1:0] Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock. 2 0 DIV32 3 Divide by 32 DIV8 2 Divide by 8 DIV2 1 Divide by 2 DIV1 0 Divide by 1 0x0 INFRCLKDIVS 0x4 32 Infrastructure Clock Division Factor For Sleep Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 RATIO [1:0] Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock. 2 0 DIV32 3 Divide by 32 DIV8 2 Divide by 8 DIV2 1 Divide by 2 DIV1 0 Divide by 1 0x0 INFRCLKDIVDS 0x8 32 Infrastructure Clock Division Factor For DeepSleep Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 RATIO [1:0] Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode. Division ratio affects both infrastructure clock and perbusull clock. 2 0 DIV32 3 Divide by 32 DIV8 2 Divide by 8 DIV2 1 Divide by 2 DIV1 0 Divide by 1 0x0 VDCTL 0xc 32 MCU Voltage Domain Control SPARE1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ULDO [0:0] Request PMCTL to switch to uLDO. 0: No request 1: Assert request when possible The bit will have no effect before the following requirements are met: 1. PDCTL1.CPU_ON = 0 2. PDCTL1.VIMS_MODE = x0 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 6. RFC do no request access to BUS 7. System CPU in deepsleep 1 0 0x0 CLKLOADCTL 0x28 32 Load PRCM Settings To CLKCTRL Power Domain RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 LOAD_DONE [1:1] Status of LOAD. Will be cleared to 0 when any of the registers requiring a LOAD is written to, and be set to 1 when a LOAD is done. Note that writing no change to a register will result in the LOAD_DONE being cleared. 0 : One or more registers have been write accessed after last LOAD 1 : No registers are write accessed after last LOAD 1 1 LOAD [0:0] 0: No action 1: Load settings to CLKCTRL. Bit is HW cleared. Multiple changes to settings may be done before LOAD is written once so all changes takes place at the same time. LOAD can also be done after single setting updates. Registers that needs to be followed by LOAD before settings being applied are: - SYSBUSCLKDIV - CPUCLKDIV - PERBUSCPUCLKDIV - PERDMACLKDIV - PERBUSCPUCLKG - RFCCLKG - VIMSCLKG - SECDMACLKGR - SECDMACLKGS - SECDMACLKGDS - GPIOCLKGR - GPIOCLKGS - GPIOCLKGDS - GPTCLKGR - GPTCLKGS - GPTCLKGDS - GPTCLKDIV - I2CCLKGR - I2CCLKGS - I2CCLKGDS - SSICLKGR - SSICLKGS - SSICLKGDS - UARTCLKGR - UARTCLKGS - UARTCLKGDS - I2SCLKGR - I2SCLKGS - I2SCLKGDS - I2SBCLKSEL - I2SCLKCTL - I2SMCLKDIV - I2SBCLKDIV - I2SWCLKDIV 1 0 0x2 RFCCLKG 0x2c 32 RFC Clock Gate RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable Clock 1: Enable clock if RFC power domain is on For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x1 VIMSCLKG 0x30 32 VIMS Clock Gate RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CLK_EN [1:0] 00: Disable clock 01: Disable clock when SYSBUS clock is disabled 11: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 0x3 SECDMACLKGR 0x3c 32 SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes RESERVED25 [31:25] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 25 DMA_AM_CLK_EN [24:24] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 24 RESERVED20 [23:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 20 PKA_ZERIOZE_RESET_N [19:19] Zeroization logic hardware reset. 0: pka_zeroize logic inactive. 1: pka_zeroize of memory is enabled. This register must remain active until the memory are completely zeroized which requires 256 periods on systembus clock. 1 19 PKA_AM_CLK_EN [18:18] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 18 TRNG_AM_CLK_EN [17:17] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 17 CRYPTO_AM_CLK_EN [16:16] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and SECDMACLKGDS.CRYPTO_CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 16 RESERVED9 [15:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 9 DMA_CLK_EN [8:8] 0: Disable clock 1: Enable clock Can be forced on by DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 PKA_CLK_EN [2:2] 0: Disable clock 1: Enable clock Can be forced on by PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 2 TRNG_CLK_EN [1:1] 0: Disable clock 1: Enable clock Can be forced on by TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 1 CRYPTO_CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 SECDMACLKGS 0x40 32 SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 DMA_CLK_EN [8:8] 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 PKA_CLK_EN [2:2] 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 2 TRNG_CLK_EN [1:1] 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 1 CRYPTO_CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 SECDMACLKGDS 0x44 32 SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 DMA_CLK_EN [8:8] 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 PKA_CLK_EN [2:2] 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 2 TRNG_CLK_EN [1:1] 0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 1 CRYPTO_CLK_EN [0:0] 0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 GPIOCLKGR 0x48 32 GPIO Clock Gate For Run And All Modes RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 AM_CLK_EN [8:8] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 GPIOCLKGS 0x4c 32 GPIO Clock Gate For Sleep Mode RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by GPIOCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 GPIOCLKGDS 0x50 32 GPIO Clock Gate For Deep Sleep Mode RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by GPIOCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 GPTCLKGR 0x54 32 GPT Clock Gate For Run And All Modes RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 AM_CLK_EN [11:8] Each bit below has the following meaning: 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 4 8 AM_GPT3 8 Enable clock for GPT3 in all modes AM_GPT2 4 Enable clock for GPT2 in all modes AM_GPT1 2 Enable clock for GPT1 in all modes AM_GPT0 1 Enable clock for GPT0 in all modes RESERVED4 [7:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 4 CLK_EN [3:0] Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 4 0 GPT3 8 Enable clock for GPT3 GPT2 4 Enable clock for GPT2 GPT1 2 Enable clock for GPT1 GPT0 1 Enable clock for GPT0 0x0 GPTCLKGS 0x58 32 GPT Clock Gate For Sleep Mode RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 CLK_EN [3:0] Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by GPTCLKGR.AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 4 0 GPT3 8 Enable clock for GPT3 GPT2 4 Enable clock for GPT2 GPT1 2 Enable clock for GPT1 GPT0 1 Enable clock for GPT0 0x0 GPTCLKGDS 0x5c 32 GPT Clock Gate For Deep Sleep Mode RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 CLK_EN [3:0] Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by GPTCLKGR.AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 4 0 GPT3 8 Enable clock for GPT3 GPT2 4 Enable clock for GPT2 GPT1 2 Enable clock for GPT1 GPT0 1 Enable clock for GPT0 0x0 I2CCLKGR 0x60 32 I2C Clock Gate For Run And All Modes RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 AM_CLK_EN [8:8] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 I2CCLKGS 0x64 32 I2C Clock Gate For Sleep Mode SPARE1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by I2CCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 I2CCLKGDS 0x68 32 I2C Clock Gate For Deep Sleep Mode SPARE1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by I2CCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 UARTCLKGR 0x6c 32 UART Clock Gate For Run And All Modes RESERVED10 [31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 10 AM_CLK_EN [9:8] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 8 AM_UART1 2 Enable clock for UART1 AM_UART0 1 Enable clock for UART0 RESERVED2 [7:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 2 CLK_EN [1:0] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 UART1 2 Enable clock for UART1 UART0 1 Enable clock for UART0 0x0 UARTCLKGS 0x70 32 UART Clock Gate For Sleep Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CLK_EN [1:0] 0: Disable clock 1: Enable clock Can be forced on by UARTCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 AM_UART1 2 Enable clock for UART1 AM_UART0 1 Enable clock for UART0 0x0 UARTCLKGDS 0x74 32 UART Clock Gate For Deep Sleep Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CLK_EN [1:0] 0: Disable clock 1: Enable clock Can be forced on by UARTCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 AM_UART1 2 Enable clock for UART1 AM_UART0 1 Enable clock for UART0 0x0 SSICLKGR 0x78 32 SSI Clock Gate For Run And All Modes RESERVED10 [31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 10 AM_CLK_EN [9:8] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 8 SSI1 2 Enable clock for SSI1 SSI0 1 Enable clock for SSI0 RESERVED2 [7:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 2 CLK_EN [1:0] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 SSI1 2 Enable clock for SSI1 SSI0 1 Enable clock for SSI0 0x0 SSICLKGS 0x7c 32 SSI Clock Gate For Sleep Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CLK_EN [1:0] 0: Disable clock 1: Enable clock Can be forced on by SSICLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 SSI1 2 Enable clock for SSI1 SSI0 1 Enable clock for SSI0 0x0 SSICLKGDS 0x80 32 SSI Clock Gate For Deep Sleep Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CLK_EN [1:0] 0: Disable clock 1: Enable clock Can be forced on by SSICLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 0 SSI1 2 Enable clock for SSI1 SSI0 1 Enable clock for SSI0 0x0 I2SCLKGR 0x84 32 I2S Clock Gate For Run And All Modes RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 AM_CLK_EN [8:8] 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 I2SCLKGS 0x88 32 I2S Clock Gate For Sleep Mode RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock Can be forced on by I2SCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 I2SCLKGDS 0x8c 32 I2S Clock Gate For Deep Sleep Mode RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 CLK_EN [0:0] 0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by I2SCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 SYSBUSCLKDIV 0xb4 32 Internal. Only to be used through TI provided API. RESERVED3 [31:3] Internal. Only to be used through TI provided API. 29 3 RATIO [2:0] Internal. Only to be used through TI provided API. 3 0 DIV2 1 Internal. Only to be used through TI provided API. DIV1 0 Internal. Only to be used through TI provided API. 0x0 CPUCLKDIV 0xb8 32 Internal. Only to be used through TI provided API. RESERVED1 [31:1] Internal. Only to be used through TI provided API. 31 1 RATIO [0:0] Internal. Only to be used through TI provided API. 1 0 DIV2 1 Internal. Only to be used through TI provided API. DIV1 0 Internal. Only to be used through TI provided API. 0x0 PERBUSCPUCLKDIV 0xbc 32 Internal. Only to be used through TI provided API. RESERVED4 [31:4] Internal. Only to be used through TI provided API. 28 4 RATIO [3:0] Internal. Only to be used through TI provided API. 4 0 DIV256 8 Internal. Only to be used through TI provided API. DIV128 7 Internal. Only to be used through TI provided API. DIV64 6 Internal. Only to be used through TI provided API. DIV32 5 Internal. Only to be used through TI provided API. DIV16 4 Internal. Only to be used through TI provided API. DIV8 3 Internal. Only to be used through TI provided API. DIV4 2 Internal. Only to be used through TI provided API. DIV2 1 Internal. Only to be used through TI provided API. DIV1 0 Internal. Only to be used through TI provided API. 0x0 PERBUSDMACLKDIV 0xc0 32 Internal. Only to be used through TI provided API. SPARE0 [31:0] Internal. Only to be used through TI provided API. 32 0 0x0 PERDMACLKDIV 0xc4 32 Internal. Only to be used through TI provided API. RESERVED4 [31:4] Internal. Only to be used through TI provided API. 28 4 RATIO [3:0] Internal. Only to be used through TI provided API. 4 0 DIV256 8 Internal. Only to be used through TI provided API. DIV128 7 Internal. Only to be used through TI provided API. DIV64 6 Internal. Only to be used through TI provided API. DIV32 5 Internal. Only to be used through TI provided API. DIV16 4 Internal. Only to be used through TI provided API. DIV8 3 Internal. Only to be used through TI provided API. DIV4 2 Internal. Only to be used through TI provided API. DIV2 1 Internal. Only to be used through TI provided API. DIV1 0 Internal. Only to be used through TI provided API. 0x0 I2SBCLKSEL 0xc8 32 I2S Clock Control SPARE1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 SRC [0:0] BCLK source selector 0: Use external BCLK 1: Use internally generated clock For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 GPTCLKDIV 0xcc 32 GPT Scalar RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 RATIO [3:0] Scalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD needs to be written Other values are not supported. 4 0 DIV256 8 Divide by 256 DIV128 7 Divide by 128 DIV64 6 Divide by 64 DIV32 5 Divide by 32 DIV16 4 Divide by 16 DIV8 3 Divide by 8 DIV4 2 Divide by 4 DIV2 1 Divide by 2 DIV1 0 Divide by 1 0x0 I2SCLKCTL 0xd0 32 I2S Clock Control RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 SMPL_ON_POSEDGE [3:3] On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK. 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 3 WCLK_PHASE [2:1] Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV). 0: Single phase 1: Dual phase 2: User Defined 3: Reserved/Undefined For changes to take effect, CLKLOADCTL.LOAD needs to be written 2 1 EN [0:0] 0: MCLK, BCLK and WCLK will be static low 1: Enables the generation of MCLK, BCLK and WCLK For changes to take effect, CLKLOADCTL.LOAD needs to be written 1 0 0x0 I2SMCLKDIV 0xd4 32 MCLK Division Ratio RESERVED10 [31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 10 MDIV [9:0] An unsigned factor of the division ratio used to generate MCLK [2-1024]: MCLK = MCUCLK/MDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written 10 0 0x0 I2SBCLKDIV 0xd8 32 BCLK Division Ratio RESERVED10 [31:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 22 10 BDIV [9:0] An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: BCLK = MCUCLK/BDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written 10 0 0x0 I2SWCLKDIV 0xdc 32 WCLK Division Ratio RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 WDIV [15:0] If I2SCLKCTL.WCLK_PHASE = 0, Single phase. WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] MCUCLK is 48MHz. If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] If I2SCLKCTL.WCLK_PHASE = 2, User defined. WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods. WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] For changes to take effect, CLKLOADCTL.LOAD needs to be written 16 0 0x0 RESETSECDMA 0xf0 32 RESET For SEC (PKA And TRNG And CRYPTO) And UDMA RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 DMA [8:8] Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 8 RESERVED3 [7:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 3 PKA [2:2] Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 2 TRNG [1:1] Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 1 CRYPTO [0:0] Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 0 0x0 RESETGPIO 0xf4 32 RESET For GPIO IPs RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 GPIO [0:0] 0: No action 1: Reset GPIO. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 0 0x0 RESETGPT 0xf8 32 RESET For GPT Ips RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 GPT [0:0] 0: No action 1: Reset all GPTs. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 0 0x0 RESETI2C 0xfc 32 RESET For I2C IPs SPARE1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 I2C [0:0] 0: No action 1: Reset I2C. HW cleared. Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 0 0x0 RESETUART 0x100 32 RESET For UART IPs RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 UART1 [1:1] 0: No action 1: Reset UART1. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 1 UART0 [0:0] 0: No action 1: Reset UART0. HW cleared. Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 0 0x0 RESETSSI 0x104 32 RESET For SSI IPs RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 SSI [1:0] SSI 0: 0: No action 1: Reset SSI. HW cleared. Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. SSI 1: 0: No action 1: Reset SSI. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 2 0 0x0 RESETI2S 0x108 32 RESET For I2S IP RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 I2S [0:0] 0: No action 1: Reset module. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. 1 0 0x0 PDCTL0 0x12c 32 Power Domain Control RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 PERIPH_ON [2:2] PERIPH Power domain. 0: PERIPH power domain is powered down 1: PERIPH power domain is powered up 1 2 SERIAL_ON [1:1] SERIAL Power domain. 0: SERIAL power domain is powered down 1: SERIAL power domain is powered up 1 1 RFC_ON [0:0] 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1: RFC power domain powered on 1 0 0x0 PDCTL0RFC 0x130 32 RFC Power Domain Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] Alias for PDCTL0.RFC_ON 1 0 0x0 PDCTL0SERIAL 0x134 32 SERIAL Power Domain Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] Alias for PDCTL0.SERIAL_ON 1 0 0x0 PDCTL0PERIPH 0x138 32 PERIPH Power Domain Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] Alias for PDCTL0.PERIPH_ON 1 0 0x0 PDSTAT0 0x140 32 Power Domain Status RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 PERIPH_ON [2:2] PERIPH Power domain. 0: Domain may be powered down 1: Domain powered up (guaranteed) 1 2 SERIAL_ON [1:1] SERIAL Power domain. 0: Domain may be powered down 1: Domain powered up (guaranteed) 1 1 RFC_ON [0:0] RFC Power domain 0: Domain may be powered down 1: Domain powered up (guaranteed) 1 0 0x0 PDSTAT0RFC 0x144 32 RFC Power Domain Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] Alias for PDSTAT0.RFC_ON 1 0 0x0 PDSTAT0SERIAL 0x148 32 SERIAL Power Domain Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] Alias for PDSTAT0.SERIAL_ON 1 0 0x0 PDSTAT0PERIPH 0x14c 32 PERIPH Power Domain Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] Alias for PDSTAT0.PERIPH_ON 1 0 0x0 PDCTL1 0x17c 32 Power Domain Control RESERVED5 [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 VIMS_MODE [4:3] 00: VIMS power domain is only powered when CPU power domain is powered. 01: VIMS power domain is powered whenever the BUS power domain is powered. 1X: Block power up of VIMS power domain at next wake up. This mode only has effect when VIMS power domain is not powered. Used for Autonomous RF Core. 2 3 RFC_ON [2:2] 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power domain powered on Bit shall be used by RFC in autonomous mode but there is no HW restrictions fom system CPU to access the bit. 1 2 CPU_ON [1:1] 0: Causes a power down of the CPU power domain when system CPU indicates it is idle. 1: Initiates power-on of the CPU power domain. This bit is automatically set by a WIC power-on event. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0xA PDCTL1CPU 0x184 32 CPU Power Domain Direct Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] This is an alias for PDCTL1.CPU_ON 1 0 0x1 PDCTL1RFC 0x188 32 RFC Power Domain Direct Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] This is an alias for PDCTL1.RFC_ON 1 0 0x0 PDCTL1VIMS 0x18c 32 VIMS Mode Direct Control RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 MODE [1:0] This is an alias for PDCTL1.VIMS_MODE 2 0 0x1 PDSTAT1 0x194 32 Power Manager Status RESERVED5 [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 BUS_ON [4:4] 0: BUS domain not accessible 1: BUS domain is currently accessible 1 4 VIMS_ON [3:3] 0: VIMS domain not accessible 1: VIMS domain is currently accessible 1 3 RFC_ON [2:2] 0: RFC domain not accessible 1: RFC domain is currently accessible 1 2 CPU_ON [1:1] 0: CPU and BUS domain not accessible 1: CPU and BUS domains are both currently accessible 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x1A PDSTAT1BUS 0x198 32 BUS Power Domain Direct Read Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] This is an alias for PDSTAT1.BUS_ON 1 0 0x1 PDSTAT1RFC 0x19c 32 RFC Power Domain Direct Read Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] This is an alias for PDSTAT1.RFC_ON 1 0 0x0 PDSTAT1CPU 0x1a0 32 CPU Power Domain Direct Read Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] This is an alias for PDSTAT1.CPU_ON 1 0 0x1 PDSTAT1VIMS 0x1a4 32 VIMS Mode Direct Read Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ON [0:0] This is an alias for PDSTAT1.VIMS_ON 1 0 0x1 RFCBITS 0x1cc 32 Control To RFC READ [31:0] Control bits for RFC. The RF core CPE processor will automatically check this register when it boots, and it can be used to immediately instruct CPE to perform some tasks at its start-up. The supported functionality is ROM-defined and may vary. See the technical reference manual for more details. 32 0 0x0 RFCMODESEL 0x1d0 32 Selected RFC Mode RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 CURR [2:0] Selects the set of commands that the RFC will accept. Only modes permitted by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for details. 3 0 MODE7 7 Select Mode 7 MODE6 6 Select Mode 6 MODE5 5 Select Mode 5 MODE4 4 Select Mode 4 MODE3 3 Select Mode 3 MODE2 2 Select Mode 2 MODE1 1 Select Mode 1 MODE0 0 Select Mode 0 0x0 RFCMODEHWOPT 0x1d4 32 Allowed RFC Modes RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 AVAIL [7:0] Permitted RFC modes. More than one mode can be permitted. 8 0 MODE7 128 Mode 7 permitted MODE6 64 Mode 6 permitted MODE5 32 Mode 5 permitted MODE4 16 Mode 4 permitted MODE3 8 Mode 3 permitted MODE2 4 Mode 2 permitted MODE1 2 Mode 1 permitted MODE0 1 Mode 0 permitted 0x0 PWRPROFSTAT 0x1e0 32 Power Profiler Register RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 VALUE [7:0] SW can use these bits to timestamp the application. These bits are also available through the testtap and can thus be used by the emulator to profile in real time. 8 0 0x1 MCUSRAMCFG 0x21c 32 MCU SRAM configuration RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 BM_OFF [5:5] Burst Mode disable 0: Burst Mode enabled. 1: Burst Mode off. 1 5 PAGE [4:4] Page Mode select 0: Page Mode disabled. Memory works in standard mode 1: Page Mode enabled. Only one half of butterfly array selected. Page Mode will select either LSB half or MSB half of the word based on PGS setting. This mode can be used for additional power saving 1 4 PGS [3:3] 0: Select LSB half of word during Page Mode, PAGE = 1 1: Select MSB half of word during Page Mode, PAGE = 1 1 3 BM [2:2] Burst Mode Enable 0: Burst Mode Disable. Memory works in standard mode. 1: Burst Mode Enable When in Burst Mode bitline precharge and wordline firing depends on PCH_F and PCH_L. Burst Mode results in reduction in active power. 1 2 PCH_F [1:1] 0: No bitline precharge in second half of cycle 1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1 1 1 PCH_L [0:0] 0: No bitline precharge in first half of cycle 1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1 1 0 0x20 RAMRETEN 0x224 32 Memory Retention Control RESERVED4 [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 RFCULL [3:3] 0: Retention for RFC ULL SRAM disabled 1: Retention for RFC ULL SRAM enabled Memories controlled: CPEULLRAM 1 3 RFC [2:2] 0: Retention for RFC SRAM disabled 1: Retention for RFC SRAM enabled Memories controlled: CPERAM MCERAM RFERAM DSBRAM 1 2 VIMS [1:0] 0: Memory retention disabled 1: Memory retention enabled Bit 0: VIMS_TRAM Bit 1: VIMS_CRAM Legal modes depend on settings in VIMS:CTL.MODE 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode after waking up again 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPILT mode. 10: Illegal mode 11: No restrictions 2 0 0xB OSCIMSC 0x290 32 Oscillator Interrupt Mask RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 HFSRCPENDIM [7:7] 0: Disable interrupt generation when HFSRCPEND is qualified 1: Enable interrupt generation when HFSRCPEND is qualified 1 7 LFSRCDONEIM [6:6] 0: Disable interrupt generation when LFSRCDONE is qualified 1: Enable interrupt generation when LFSRCDONE is qualified 1 6 XOSCDLFIM [5:5] 0: Disable interrupt generation when XOSCDLF is qualified 1: Enable interrupt generation when XOSCDLF is qualified 1 5 XOSCLFIM [4:4] 0: Disable interrupt generation when XOSCLF is qualified 1: Enable interrupt generation when XOSCLF is qualified 1 4 RCOSCDLFIM [3:3] 0: Disable interrupt generation when RCOSCDLF is qualified 1: Enable interrupt generation when RCOSCDLF is qualified 1 3 RCOSCLFIM [2:2] 0: Disable interrupt generation when RCOSCLF is qualified 1: Enable interrupt generation when RCOSCLF is qualified 1 2 XOSCHFIM [1:1] 0: Disable interrupt generation when XOSCHF is qualified 1: Enable interrupt generation when XOSCHF is qualified 1 1 RCOSCHFIM [0:0] 0: Disable interrupt generation when RCOSCHF is qualified 1: Enable interrupt generation when RCOSCHF is qualified 1 0 0x36 OSCRIS 0x294 32 Oscillator Raw Interrupt Status RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 HFSRCPENDRIS [7:7] 0: HFSRCPEND has not been qualified 1: HFSRCPEND has been qualified since last clear Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.HFSRCPENDC 1 7 LFSRCDONERIS [6:6] 0: LFSRCDONE has not been qualified 1: LFSRCDONE has been qualified since last clear Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.LFSRCDONEC 1 6 XOSCDLFRIS [5:5] 0: XOSCDLF has not been qualified 1: XOSCDLF has been qualified since last clear. Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCDLFC 1 5 XOSCLFRIS [4:4] 0: XOSCLF has not been qualified 1: XOSCLF has been qualified since last clear. Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCLFC 1 4 RCOSCDLFRIS [3:3] 0: RCOSCDLF has not been qualified 1: RCOSCDLF has been qualified since last clear. Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCDLFC 1 3 RCOSCLFRIS [2:2] 0: RCOSCLF has not been qualified 1: RCOSCLF has been qualified since last clear. Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCLFC 1 2 XOSCHFRIS [1:1] 0: XOSCHF has not been qualified 1: XOSCHF has been qualified since last clear. Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCHFC 1 1 RCOSCHFRIS [0:0] 0: RCOSCHF has not been qualified 1: RCOSCHF has been qualified since last clear. Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCHFC 1 0 0x0 OSCICR 0x298 32 Oscillator Raw Interrupt Clear RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 HFSRCPENDC [7:7] Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 has no effect. 1 7 LFSRCDONEC [6:6] Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 has no effect. 1 6 XOSCDLFC [5:5] Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 has no effect. 1 5 XOSCLFC [4:4] Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 has no effect. 1 4 RCOSCDLFC [3:3] Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 has no effect. 1 3 RCOSCLFC [2:2] Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 has no effect. 1 2 XOSCHFC [1:1] Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 has no effect. 1 1 RCOSCHFC [0:0] Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 has no effect. 1 0 0x0 RFC_DBELL 0x40041000 0 0x40 registers RF core doorbell The doorbell module is the main user interface to the radio sub-system. It contains the registers used for both submitting commands to the radio, and for configuring radio interrupts from the RF core. CMDR 0x0 32 Doorbell Command Register CMD [31:0] Command register. Raises an interrupt to the Command and packet engine (CPE) upon write. 32 0 0x0 CMDSTA 0x4 32 Doorbell Command Status Register STAT [31:0] Status of the last command used 32 0 0x0 RFHWIFG 0x8 32 Interrupt Flags From RF Hardware Modules RESERVED20 [31:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 20 RATCH7 [19:19] Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 19 RATCH6 [18:18] Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 18 RATCH5 [17:17] Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 17 RATCH4 [16:16] Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 16 RATCH3 [15:15] Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 15 RATCH2 [14:14] Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 14 RATCH1 [13:13] Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 13 RATCH0 [12:12] Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one has no effect. 1 12 RFESOFT2 [11:11] RF engine software defined interrupt 2 flag. Write zero to clear flag. Write to one has no effect. 1 11 RFESOFT1 [10:10] RF engine software defined interrupt 1 flag. Write zero to clear flag. Write to one has no effect. 1 10 RFESOFT0 [9:9] RF engine software defined interrupt 0 flag. Write zero to clear flag. Write to one has no effect. 1 9 RFEDONE [8:8] RF engine command done interrupt flag. Write zero to clear flag. Write to one has no effect. 1 8 RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 TRCTK [6:6] Debug tracer system tick interrupt flag. Write zero to clear flag. Write to one has no effect. 1 6 MDMSOFT [5:5] Modem software defined interrupt flag. Write zero to clear flag. Write to one has no effect. 1 5 MDMOUT [4:4] Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has no effect. 1 4 MDMIN [3:3] Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has no effect. 1 3 MDMDONE [2:2] Modem command done interrupt flag. Write zero to clear flag. Write to one has no effect. 1 2 FSCA [1:1] Frequency synthesizer calibration accelerator interrupt flag. Write zero to clear flag. Write to one has no effect. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 RFHWIEN 0xc 32 Interrupt Enable For RF Hardware Modules RESERVED20 [31:20] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 20 RATCH7 [19:19] Interrupt enable for RFHWIFG.RATCH7. 1 19 RATCH6 [18:18] Interrupt enable for RFHWIFG.RATCH6. 1 18 RATCH5 [17:17] Interrupt enable for RFHWIFG.RATCH5. 1 17 RATCH4 [16:16] Interrupt enable for RFHWIFG.RATCH4. 1 16 RATCH3 [15:15] Interrupt enable for RFHWIFG.RATCH3. 1 15 RATCH2 [14:14] Interrupt enable for RFHWIFG.RATCH2. 1 14 RATCH1 [13:13] Interrupt enable for RFHWIFG.RATCH1. 1 13 RATCH0 [12:12] Interrupt enable for RFHWIFG.RATCH0. 1 12 RFESOFT2 [11:11] Interrupt enable for RFHWIFG.RFESOFT2. 1 11 RFESOFT1 [10:10] Interrupt enable for RFHWIFG.RFESOFT1. 1 10 RFESOFT0 [9:9] Interrupt enable for RFHWIFG.RFESOFT0. 1 9 RFEDONE [8:8] Interrupt enable for RFHWIFG.RFEDONE. 1 8 RESERVED7 [7:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 7 TRCTK [6:6] Interrupt enable for RFHWIFG.TRCTK. 1 6 MDMSOFT [5:5] Interrupt enable for RFHWIFG.MDMSOFT. 1 5 MDMOUT [4:4] Interrupt enable for RFHWIFG.MDMOUT. 1 4 MDMIN [3:3] Interrupt enable for RFHWIFG.MDMIN. 1 3 MDMDONE [2:2] Interrupt enable for RFHWIFG.MDMDONE. 1 2 FSCA [1:1] Interrupt enable for RFHWIFG.FSCA. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 RFCPEIFG 0x10 32 Interrupt Flags For Command and Packet Engine Generated Interrupts INTERNAL_ERROR [31:31] Interrupt flag 31. The command and packet engine (CPE) has observed an unexpected error. A reset of the CPE is needed. This can be done by switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero to clear flag. Write to one has no effect. 1 31 BOOT_DONE [30:30] Interrupt flag 30. The command and packet engine (CPE) boot is finished. Write zero to clear flag. Write to one has no effect. 1 30 MODULES_UNLOCKED [29:29] Interrupt flag 29. As part of command and packet engine (CPE) boot process, it has opened access to RF Core modules and memories. Write zero to clear flag. Write to one has no effect. 1 29 SYNTH_NO_LOCK [28:28] Interrupt flag 28. The phase-locked loop in frequency synthesizer has reported loss of lock. Write zero to clear flag. Write to one has no effect. 1 28 IRQ27 [27:27] Interrupt flag 27. Write zero to clear flag. Write to one has no effect. 1 27 RX_ABORTED [26:26] Interrupt flag 26. Packet reception stopped before packet was done. Write zero to clear flag. Write to one has no effect. 1 26 RX_N_DATA_WRITTEN [25:25] Interrupt flag 25. Specified number of bytes written to partial read Rx buffer. Write zero to clear flag. Write to one has no effect. 1 25 RX_DATA_WRITTEN [24:24] Interrupt flag 24. Data written to partial read Rx buffer. Write zero to clear flag. Write to one has no effect. 1 24 RX_ENTRY_DONE [23:23] Interrupt flag 23. Rx queue data entry changing state to finished. Write zero to clear flag. Write to one has no effect. 1 23 RX_BUF_FULL [22:22] Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame received that did not fit in the Rx queue. Write zero to clear flag. Write to one has no effect. 1 22 RX_CTRL_ACK [21:21] Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, not to be ignored, then acknowledgement sent. Write zero to clear flag. Write to one has no effect. 1 21 RX_CTRL [20:20] Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, not to be ignored. Write zero to clear flag. Write to one has no effect. 1 20 RX_EMPTY [19:19] Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be ignored, no payload. Write zero to clear flag. Write to one has no effect. 1 19 RX_IGNORED [18:18] Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received with ignore flag set. Write zero to clear flag. Write to one has no effect. 1 18 RX_NOK [17:17] Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write zero to clear flag. Write to one has no effect. 1 17 RX_OK [16:16] Interrupt flag 16. Packet received correctly. BLE mode: Packet received with CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received with CRC OK. Write zero to clear flag. Write to one has no effect. 1 16 IRQ15 [15:15] Interrupt flag 15. Write zero to clear flag. Write to one has no effect. 1 15 IRQ14 [14:14] Interrupt flag 14. Write zero to clear flag. Write to one has no effect. 1 14 FG_COMMAND_STARTED [13:13] Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation command has gone into active state. 1 13 COMMAND_STARTED [12:12] Interrupt flag 12. A radio operation command has gone into active state. 1 12 TX_BUFFER_CHANGED [11:11] Interrupt flag 11. BLE mode only: A buffer change is complete after CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. 1 11 TX_ENTRY_DONE [10:10] Interrupt flag 10. Tx queue data entry state changed to finished. Write zero to clear flag. Write to one has no effect. 1 10 TX_RETRANS [9:9] Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear flag. Write to one has no effect. 1 9 TX_CTRL_ACK_ACK [8:8] Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted LL control packet, and acknowledgement transmitted for that packet. Write zero to clear flag. Write to one has no effect. 1 8 TX_CTRL_ACK [7:7] Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL control packet. Write zero to clear flag. Write to one has no effect. 1 7 TX_CTRL [6:6] Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to clear flag. Write to one has no effect. 1 6 TX_ACK [5:5] Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to clear flag. Write to one has no effect. 1 5 TX_DONE [4:4] Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero to clear flag. Write to one has no effect. 1 4 LAST_FG_COMMAND_DONE [3:3] Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio operation command in a chain of commands has finished. Write zero to clear flag. Write to one has no effect. 1 3 FG_COMMAND_DONE [2:2] Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation command has finished. Write zero to clear flag. Write to one has no effect. 1 2 LAST_COMMAND_DONE [1:1] Interrupt flag 1. The last radio operation command in a chain of commands has finished. (IEEE 802.15.4 mode: The last background level radio operation command in a chain of commands has finished.) Write zero to clear flag. Write to one has no effect. 1 1 COMMAND_DONE [0:0] Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A background level radio operation command has finished.) Write zero to clear flag. Write to one has no effect. 1 0 0x0 RFCPEIEN 0x14 32 Interrupt Enable For Command and Packet Engine Generated Interrupts INTERNAL_ERROR [31:31] Interrupt enable for RFCPEIFG.INTERNAL_ERROR. 1 31 BOOT_DONE [30:30] Interrupt enable for RFCPEIFG.BOOT_DONE. 1 30 MODULES_UNLOCKED [29:29] Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. 1 29 SYNTH_NO_LOCK [28:28] Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. 1 28 IRQ27 [27:27] Interrupt enable for RFCPEIFG.IRQ27. 1 27 RX_ABORTED [26:26] Interrupt enable for RFCPEIFG.RX_ABORTED. 1 26 RX_N_DATA_WRITTEN [25:25] Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. 1 25 RX_DATA_WRITTEN [24:24] Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. 1 24 RX_ENTRY_DONE [23:23] Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. 1 23 RX_BUF_FULL [22:22] Interrupt enable for RFCPEIFG.RX_BUF_FULL. 1 22 RX_CTRL_ACK [21:21] Interrupt enable for RFCPEIFG.RX_CTRL_ACK. 1 21 RX_CTRL [20:20] Interrupt enable for RFCPEIFG.RX_CTRL. 1 20 RX_EMPTY [19:19] Interrupt enable for RFCPEIFG.RX_EMPTY. 1 19 RX_IGNORED [18:18] Interrupt enable for RFCPEIFG.RX_IGNORED. 1 18 RX_NOK [17:17] Interrupt enable for RFCPEIFG.RX_NOK. 1 17 RX_OK [16:16] Interrupt enable for RFCPEIFG.RX_OK. 1 16 IRQ15 [15:15] Interrupt enable for RFCPEIFG.IRQ15. 1 15 IRQ14 [14:14] Interrupt enable for RFCPEIFG.IRQ14. 1 14 FG_COMMAND_STARTED [13:13] Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED. 1 13 COMMAND_STARTED [12:12] Interrupt enable for RFCPEIFG.COMMAND_STARTED. 1 12 TX_BUFFER_CHANGED [11:11] Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. 1 11 TX_ENTRY_DONE [10:10] Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. 1 10 TX_RETRANS [9:9] Interrupt enable for RFCPEIFG.TX_RETRANS. 1 9 TX_CTRL_ACK_ACK [8:8] Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. 1 8 TX_CTRL_ACK [7:7] Interrupt enable for RFCPEIFG.TX_CTRL_ACK. 1 7 TX_CTRL [6:6] Interrupt enable for RFCPEIFG.TX_CTRL. 1 6 TX_ACK [5:5] Interrupt enable for RFCPEIFG.TX_ACK. 1 5 TX_DONE [4:4] Interrupt enable for RFCPEIFG.TX_DONE. 1 4 LAST_FG_COMMAND_DONE [3:3] Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. 1 3 FG_COMMAND_DONE [2:2] Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. 1 2 LAST_COMMAND_DONE [1:1] Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. 1 1 COMMAND_DONE [0:0] Interrupt enable for RFCPEIFG.COMMAND_DONE. 1 0 0xFFFFFFFF RFCPEISL 0x18 32 Interrupt Vector Selection For Command and Packet Engine Generated Interrupts INTERNAL_ERROR [31:31] Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt should use. 1 31 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector BOOT_DONE [30:30] Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should use. 1 30 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector MODULES_UNLOCKED [29:29] Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt should use. 1 29 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector SYNTH_NO_LOCK [28:28] Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt should use. 1 28 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector IRQ27 [27:27] Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. 1 27 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_ABORTED [26:26] Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should use. 1 26 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_N_DATA_WRITTEN [25:25] Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt should use. 1 25 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_DATA_WRITTEN [24:24] Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt should use. 1 24 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_ENTRY_DONE [23:23] Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt should use. 1 23 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_BUF_FULL [22:22] Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should use. 1 22 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_CTRL_ACK [21:21] Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should use. 1 21 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_CTRL [20:20] Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. 1 20 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_EMPTY [19:19] Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should use. 1 19 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_IGNORED [18:18] Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should use. 1 18 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_NOK [17:17] Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. 1 17 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector RX_OK [16:16] Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. 1 16 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector IRQ15 [15:15] Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. 1 15 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector IRQ14 [14:14] Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. 1 14 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector FG_COMMAND_STARTED [13:13] Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt should use. 1 13 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector COMMAND_STARTED [12:12] Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt should use. 1 12 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_BUFFER_CHANGED [11:11] Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt should use. 1 11 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_ENTRY_DONE [10:10] Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt should use. 1 10 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_RETRANS [9:9] Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should use. 1 9 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_CTRL_ACK_ACK [8:8] Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt should use. 1 8 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_CTRL_ACK [7:7] Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should use. 1 7 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_CTRL [6:6] Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. 1 6 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_ACK [5:5] Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. 1 5 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector TX_DONE [4:4] Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. 1 4 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector LAST_FG_COMMAND_DONE [3:3] Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE interrupt should use. 1 3 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector FG_COMMAND_DONE [2:2] Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt should use. 1 2 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector LAST_COMMAND_DONE [1:1] Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt should use. 1 1 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector COMMAND_DONE [0:0] Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should use. 1 0 CPE1 1 Associate this interrupt line with INT_RF_CPE1 interrupt vector CPE0 0 Associate this interrupt line with INT_RF_CPE0 interrupt vector 0xFFFF0000 RFACKIFG 0x1c 32 Doorbell Command Acknowledgement Interrupt Flag RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 ACKFLAG [0:0] Interrupt flag for Command ACK 1 0 0x0 SYSGPOCTL 0x20 32 RF Core General Purpose Output Control RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 GPOCTL3 [15:12] RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO line 3. 4 12 RATGPO3 15 RAT GPO line 3 RATGPO2 14 RAT GPO line 2 RATGPO1 13 RAT GPO line 1 RATGPO0 12 RAT GPO line 0 RFEGPO3 11 RFE GPO line 3 RFEGPO2 10 RFE GPO line 2 RFEGPO1 9 RFE GPO line 1 RFEGPO0 8 RFE GPO line 0 MCEGPO3 7 MCE GPO line 3 MCEGPO2 6 MCE GPO line 2 MCEGPO1 5 MCE GPO line 1 MCEGPO0 4 MCE GPO line 0 CPEGPO3 3 CPE GPO line 3 CPEGPO2 2 CPE GPO line 2 CPEGPO1 1 CPE GPO line 1 CPEGPO0 0 CPE GPO line 0 GPOCTL2 [11:8] RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO line 2. 4 8 RATGPO3 15 RAT GPO line 3 RATGPO2 14 RAT GPO line 2 RATGPO1 13 RAT GPO line 1 RATGPO0 12 RAT GPO line 0 RFEGPO3 11 RFE GPO line 3 RFEGPO2 10 RFE GPO line 2 RFEGPO1 9 RFE GPO line 1 RFEGPO0 8 RFE GPO line 0 MCEGPO3 7 MCE GPO line 3 MCEGPO2 6 MCE GPO line 2 MCEGPO1 5 MCE GPO line 1 MCEGPO0 4 MCE GPO line 0 CPEGPO3 3 CPE GPO line 3 CPEGPO2 2 CPE GPO line 2 CPEGPO1 1 CPE GPO line 1 CPEGPO0 0 CPE GPO line 0 GPOCTL1 [7:4] RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO line 1. 4 4 RATGPO3 15 RAT GPO line 3 RATGPO2 14 RAT GPO line 2 RATGPO1 13 RAT GPO line 1 RATGPO0 12 RAT GPO line 0 RFEGPO3 11 RFE GPO line 3 RFEGPO2 10 RFE GPO line 2 RFEGPO1 9 RFE GPO line 1 RFEGPO0 8 RFE GPO line 0 MCEGPO3 7 MCE GPO line 3 MCEGPO2 6 MCE GPO line 2 MCEGPO1 5 MCE GPO line 1 MCEGPO0 4 MCE GPO line 0 CPEGPO3 3 CPE GPO line 3 CPEGPO2 2 CPE GPO line 2 CPEGPO1 1 CPE GPO line 1 CPEGPO0 0 CPE GPO line 0 GPOCTL0 [3:0] RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO line 0. 4 0 RATGPO3 15 RAT GPO line 3 RATGPO2 14 RAT GPO line 2 RATGPO1 13 RAT GPO line 1 RATGPO0 12 RAT GPO line 0 RFEGPO3 11 RFE GPO line 3 RFEGPO2 10 RFE GPO line 2 RFEGPO1 9 RFE GPO line 1 RFEGPO0 8 RFE GPO line 0 MCEGPO3 7 MCE GPO line 3 MCEGPO2 6 MCE GPO line 2 MCEGPO1 5 MCE GPO line 1 MCEGPO0 4 MCE GPO line 0 CPEGPO3 3 CPE GPO line 3 CPEGPO2 2 CPE GPO line 2 CPEGPO1 1 CPE GPO line 1 CPEGPO0 0 CPE GPO line 0 0x0 RFC_PWR 0x40040000 0 0x4 registers RF core power management This module contains clock control for all RF core sub-modules. PWMCLKEN 0x0 32 RF Core Power Management and Clock Enable RESERVED11 [31:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 21 11 RFCTRC [10:10] Enable clock to the RF Core Tracer (RFCTRC) module. 1 10 FSCA [9:9] Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module. 1 9 PHA [8:8] Enable clock to the Packet Handling Accelerator (PHA) module. 1 8 RAT [7:7] Enable clock to the Radio Timer (RAT) module. 1 7 RFERAM [6:6] Enable clock to the RF Engine RAM module. 1 6 RFE [5:5] Enable clock to the RF Engine (RFE) module. 1 5 MDMRAM [4:4] Enable clock to the Modem RAM module. 1 4 MDM [3:3] Enable clock to the Modem (MDM) module. 1 3 CPERAM [2:2] Enable clock to the Command and Packet Engine (CPE) RAM module. As part of RF Core initialization, set this bit together with CPE bit to enable CPE to boot. 1 2 CPE [1:1] Enable processor clock (hclk) to the Command and Packet Engine (CPE). As part of RF Core initialization, set this bit together with CPERAM bit to enable CPE to boot. 1 1 RFC [0:0] Enable essential clocks for the RF Core interface. This includes the interconnect, the radio doorbell DBELL command interface, the power management (PWR) clock control module, and bus clock (sclk) for the CPE. To remove possibility of locking yourself out from the RF Core, this bit can not be cleared. If you need to disable all clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register. 1 0 0x1 RFC_RAT 0x40043000 0 0x100 registers RF core radio timer RATCNT 0x4 32 Radio Timer Counter Value CNT [31:0] Counter value. This is not writable while radio timer counter is enabled. 32 0 0x0 RATCH0VAL 0x80 32 Timer Channel 0 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH1VAL 0x84 32 Timer Channel 1 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH2VAL 0x88 32 Timer Channel 2 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH3VAL 0x8c 32 Timer Channel 3 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH4VAL 0x90 32 Timer Channel 4 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH5VAL 0x94 32 Timer Channel 5 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH6VAL 0x98 32 Timer Channel 6 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 RATCH7VAL 0x9c 32 Timer Channel 7 Capture/Compare Register VAL [31:0] Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. 32 0 0x0 SMPH 0x40084000 0 0x1000 registers MCU Semaphore Module This module provides 32 binary semaphores. The state of a binary semaphore is either taken or available. A semaphore does not implement any ownership attribute. Still, a semaphore can be used to handle mutual exclusion scenarios. SMPH0 0x0 32 MCU SEMAPHORE 0 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH1 0x4 32 MCU SEMAPHORE 1 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH2 0x8 32 MCU SEMAPHORE 2 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH3 0xc 32 MCU SEMAPHORE 3 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH4 0x10 32 MCU SEMAPHORE 4 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH5 0x14 32 MCU SEMAPHORE 5 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH6 0x18 32 MCU SEMAPHORE 6 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH7 0x1c 32 MCU SEMAPHORE 7 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH8 0x20 32 MCU SEMAPHORE 8 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH9 0x24 32 MCU SEMAPHORE 9 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH10 0x28 32 MCU SEMAPHORE 10 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH11 0x2c 32 MCU SEMAPHORE 11 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH12 0x30 32 MCU SEMAPHORE 12 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH13 0x34 32 MCU SEMAPHORE 13 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH14 0x38 32 MCU SEMAPHORE 14 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH15 0x3c 32 MCU SEMAPHORE 15 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH16 0x40 32 MCU SEMAPHORE 16 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH17 0x44 32 MCU SEMAPHORE 17 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH18 0x48 32 MCU SEMAPHORE 18 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH19 0x4c 32 MCU SEMAPHORE 19 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH20 0x50 32 MCU SEMAPHORE 20 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH21 0x54 32 MCU SEMAPHORE 21 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH22 0x58 32 MCU SEMAPHORE 22 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH23 0x5c 32 MCU SEMAPHORE 23 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH24 0x60 32 MCU SEMAPHORE 24 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH25 0x64 32 MCU SEMAPHORE 25 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH26 0x68 32 MCU SEMAPHORE 26 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH27 0x6c 32 MCU SEMAPHORE 27 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH28 0x70 32 MCU SEMAPHORE 28 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH29 0x74 32 MCU SEMAPHORE 29 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH30 0x78 32 MCU SEMAPHORE 30 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 SMPH31 0x7c 32 MCU SEMAPHORE 31 RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Reading the register causes it to change value to 0. Releasing the semaphore is done by writing 1. 1 0 0x1 PEEK0 0x800 32 MCU SEMAPHORE 0 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK1 0x804 32 MCU SEMAPHORE 1 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK2 0x808 32 MCU SEMAPHORE 2 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK3 0x80c 32 MCU SEMAPHORE 3 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK4 0x810 32 MCU SEMAPHORE 4 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK5 0x814 32 MCU SEMAPHORE 5 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK6 0x818 32 MCU SEMAPHORE 6 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK7 0x81c 32 MCU SEMAPHORE 7 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK8 0x820 32 MCU SEMAPHORE 8 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK9 0x824 32 MCU SEMAPHORE 9 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK10 0x828 32 MCU SEMAPHORE 10 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK11 0x82c 32 MCU SEMAPHORE 11 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK12 0x830 32 MCU SEMAPHORE 12 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK13 0x834 32 MCU SEMAPHORE 13 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK14 0x838 32 MCU SEMAPHORE 14 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK15 0x83c 32 MCU SEMAPHORE 15 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK16 0x840 32 MCU SEMAPHORE 16 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK17 0x844 32 MCU SEMAPHORE 17 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK18 0x848 32 MCU SEMAPHORE 18 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK19 0x84c 32 MCU SEMAPHORE 19 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK20 0x850 32 MCU SEMAPHORE 20 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK21 0x854 32 MCU SEMAPHORE 21 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK22 0x858 32 MCU SEMAPHORE 22 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK23 0x85c 32 MCU SEMAPHORE 23 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK24 0x860 32 MCU SEMAPHORE 24 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK25 0x864 32 MCU SEMAPHORE 25 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK26 0x868 32 MCU SEMAPHORE 26 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK27 0x86c 32 MCU SEMAPHORE 27 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK28 0x870 32 MCU SEMAPHORE 28 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK29 0x874 32 MCU SEMAPHORE 29 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK30 0x878 32 MCU SEMAPHORE 30 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 PEEK31 0x87c 32 MCU SEMAPHORE 31 ALIAS RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] Status when reading: 0: Semaphore is taken 1: Semaphore is available Used for semaphore debugging. A read operation will not change register value. Register writing is not possible. 1 0 0x1 SRAM_MMR 0x40035000 0 0x5000 registers General Purpose RAM PER_CTL 0x0 32 Parity Error Control Parity error check controls RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 PER_DISABLE [8:8] Parity Status Disable 0: A parity error will update PER_CHK.PER_ADDR field 1: Parity error does not update PER_CHK.PER_ADDR field 1 8 RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 PER_DEBUG_ENABLE [0:0] Parity Error Debug Enable 0: Normal operation 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity errors will be generated on reads from within this offset 1 0 0x0 PER_CHK 0x4 32 Parity Error Check Parity error check results RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 PER_ADDR [23:0] Parity Error Address Offset Returns the last address offset which resulted in a parity error during an SRAM read. The address offset returned is always the word-aligned address that contains the location with the parity error. For parity faults on non word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the location that resulted in parity error. 24 0 0x0 PER_DBG 0x8 32 Parity Error Debug Parity error check debug address setting RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 PER_DEBUG_ADDR [23:0] Debug Parity Error Address Offset When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug address offset. The address offset must be a word-aligned address. Writes within this address offset will force incorrect parity bits to be stored together with the data written. The following reads within this same address offset will thus result in parity errors to be generated. 24 0 0x0 MEM_CTL 0xc 32 Memory Control Controls memory initialization RESERVED24 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 MEM_BUSY [1:1] Memory Busy status 0: Memory accepts transfers 1: Memory controller is busy during initialization. Read and write transfers are not performed. 1 1 MEM_CLR_EN [0:0] Memory Contents Initialization enable Writing 1 to MEM_CLR_EN will start memory initialization. The contents of all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until memory initialization has completed. 1 0 0x0 SSI0 0x40000000 0 0x1000 registers Synchronous Serial Interface with master and slave capabilities CR0 0x0 32 Control 0 RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SCR [15:8] Serial clock rate: This is used to generate the transmit and receive bit rate of the SSI. The bit rate is (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). SCR is a value from 0-255. 8 8 SPH [7:7] CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 1 7 2ND_CLK_EDGE 1 Data is captured on the second clock edge transition. 1ST_CLK_EDGE 0 Data is captured on the first clock edge transition. SPO [6:6] CLKOUT polarity (Motorola SPI frame format only) 1 6 HIGH 1 SSI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred. LOW 0 SSI produces a steady state LOW value on the CLKOUT pin when data is not being transferred. FRF [5:4] Frame format. The supported frame formats are Motorola SPI, TI synchronous serial and National Microwire. Value 0'b11 is reserved and shall not be used. 2 4 NATIONAL_MICROWIRE 2 National Microwire frame format TI_SYNC_SERIAL 1 TI synchronous serial frame format MOTOROLA_SPI 0 Motorola SPI frame format DSS [3:0] Data Size Select. Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. 4 0 16_BIT 15 16-bit data 15_BIT 14 15-bit data 14_BIT 13 14-bit data 13_BIT 12 13-bit data 12_BIT 11 12-bit data 11_BIT 10 11-bit data 10_BIT 9 10-bit data 9_BIT 8 9-bit data 8_BIT 7 8-bit data 7_BIT 6 7-bit data 6_BIT 5 6-bit data 5_BIT 4 5-bit data 4_BIT 3 4-bit data 0x0 CR1 0x4 32 Control 1 RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 SOD [3:3] Slave-mode output disabled This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SSI slave is not supposed to drive the TXD line: 0: SSI can drive the TXD output in slave mode. 1: SSI cannot drive the TXD output in slave mode. 1 3 MS [2:2] Master or slave mode select. This bit can be modified only when SSI is disabled, SSE=0. 1 2 SLAVE 1 Device configured as slave MASTER 0 Device configured as master SSE [1:1] Synchronous serial interface enable. 1 1 SSI_ENABLED 1 Operation enabled SSI_DISABLED 0 Operation disabled LBM [0:0] Loop back mode: 0: Normal serial port operation enabled. 1: Output of transmit serial shifter is connected to input of receive serial shifter internally. 1 0 0x0 DR 0x8 32 Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DATA [15:0] Transmit/receive data The values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. 16 0 0x0 SR 0xc 32 Status RESERVED [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 BSY [4:4] Serial interface busy: 0: SSI is idle 1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. 1 4 RFF [3:3] Receive FIFO full: 0: Receive FIFO is not full. 1: Receive FIFO is full. 1 3 RNE [2:2] Receive FIFO not empty 0: Receive FIFO is empty. 1: Receive FIFO is not empty. 1 2 TNF [1:1] Transmit FIFO not full: 0: Transmit FIFO is full. 1: Transmit FIFO is not full. 1 1 TFE [0:0] Transmit FIFO empty: 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty. 1 0 0x3 CPSR 0x10 32 Clock Prescale RESERVED [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 CPSDVSR [7:0] Clock prescale divisor: This field specifies the division factor by which the input system clock to SSI must be internally divided before further use. The value programmed into this field must be an even non-zero number (2-254). The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 8 0 0x0 IMSC 0x14 32 Interrupt Mask Set and Clear RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 TXIM [3:3] Transmit FIFO interrupt mask: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 1 3 RXIM [2:2] Receive FIFO interrupt mask: A read returns the current mask for receive FIFO interrupt. On a write of 1, the mask for receive FIFO interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. 1 2 RTIM [1:1] Receive timeout interrupt mask: A read returns the current mask for receive timeout interrupt. On a write of 1, the mask for receive timeout interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means MIS.RTMIS will not reflect the interrupt. 1 1 RORIM [0:0] Receive overrun interrupt mask: A read returns the current mask for receive overrun interrupt. On a write of 1, the mask for receive overrun interrupt is set which means the interrupt state will be reflected in MIS.RORMIS. A write of 0 clears the mask which means MIS.RORMIS will not reflect the interrupt. 1 0 0x0 RIS 0x18 32 Raw Interrupt Status RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 TXRIS [3:3] Raw transmit FIFO interrupt status: The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO. The transmit interrupt is not qualified with the SSI enable signal. Therefore one of the following ways can be used: - data can be written to the transmit FIFO prior to enabling the SSI and the interrupts. - SSI and interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine. 1 3 RXRIS [2:2] Raw interrupt state of receive FIFO interrupt: The receive interrupt is asserted when there are four or more valid entries in the receive FIFO. 1 2 RTRIS [1:1] Raw interrupt state of receive timeout interrupt: The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period. This mechanism can be used to notify the user that data is still present in the receive FIFO and requires servicing. This interrupt is deasserted if the receive FIFO becomes empty by subsequent reads, or if new data is received on RXD. It can also be cleared by writing to ICR.RTIC. 1 1 RORRIS [0:0] Raw interrupt state of receive overrun interrupt: The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is over-written in the receive shift register, but not the FIFO so the FIFO contents stay valid. It can also be cleared by writing to ICR.RORIC. 1 0 0x8 MIS 0x1c 32 Masked Interrupt Status RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 TXMIS [3:3] Masked interrupt state of transmit FIFO interrupt: This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. 1 3 RXMIS [2:2] Masked interrupt state of receive FIFO interrupt: This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. 1 2 RTMIS [1:1] Masked interrupt state of receive timeout interrupt: This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM. 1 1 RORMIS [0:0] Masked interrupt state of receive overrun interrupt: This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM. 1 0 0x0 ICR 0x20 32 Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. RESERVED [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 RTIC [1:1] Clear the receive timeout interrupt: Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 has no effect. 1 1 RORIC [0:0] Clear the receive overrun interrupt: Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). Writing 0 has no effect. 1 0 0x0 DMACR 0x24 32 DMA Control RESERVED [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 TXDMAE [1:1] Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. 1 1 RXDMAE [0:0] Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. 1 0 0x0 RESERVED1 0x28 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 RESERVED2 0x90 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 SSI1 0x40008000 0 0x1000 registers Synchronous Serial Interface with master and slave capabilities CR0 0x0 32 Control 0 RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 SCR [15:8] Serial clock rate: This is used to generate the transmit and receive bit rate of the SSI. The bit rate is (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). SCR is a value from 0-255. 8 8 SPH [7:7] CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 1 7 2ND_CLK_EDGE 1 Data is captured on the second clock edge transition. 1ST_CLK_EDGE 0 Data is captured on the first clock edge transition. SPO [6:6] CLKOUT polarity (Motorola SPI frame format only) 1 6 HIGH 1 SSI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred. LOW 0 SSI produces a steady state LOW value on the CLKOUT pin when data is not being transferred. FRF [5:4] Frame format. The supported frame formats are Motorola SPI, TI synchronous serial and National Microwire. Value 0'b11 is reserved and shall not be used. 2 4 NATIONAL_MICROWIRE 2 National Microwire frame format TI_SYNC_SERIAL 1 TI synchronous serial frame format MOTOROLA_SPI 0 Motorola SPI frame format DSS [3:0] Data Size Select. Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. 4 0 16_BIT 15 16-bit data 15_BIT 14 15-bit data 14_BIT 13 14-bit data 13_BIT 12 13-bit data 12_BIT 11 12-bit data 11_BIT 10 11-bit data 10_BIT 9 10-bit data 9_BIT 8 9-bit data 8_BIT 7 8-bit data 7_BIT 6 7-bit data 6_BIT 5 6-bit data 5_BIT 4 5-bit data 4_BIT 3 4-bit data 0x0 CR1 0x4 32 Control 1 RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 SOD [3:3] Slave-mode output disabled This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SSI slave is not supposed to drive the TXD line: 0: SSI can drive the TXD output in slave mode. 1: SSI cannot drive the TXD output in slave mode. 1 3 MS [2:2] Master or slave mode select. This bit can be modified only when SSI is disabled, SSE=0. 1 2 SLAVE 1 Device configured as slave MASTER 0 Device configured as master SSE [1:1] Synchronous serial interface enable. 1 1 SSI_ENABLED 1 Operation enabled SSI_DISABLED 0 Operation disabled LBM [0:0] Loop back mode: 0: Normal serial port operation enabled. 1: Output of transmit serial shifter is connected to input of receive serial shifter internally. 1 0 0x0 DR 0x8 32 Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DATA [15:0] Transmit/receive data The values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. 16 0 0x0 SR 0xc 32 Status RESERVED [31:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 27 5 BSY [4:4] Serial interface busy: 0: SSI is idle 1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. 1 4 RFF [3:3] Receive FIFO full: 0: Receive FIFO is not full. 1: Receive FIFO is full. 1 3 RNE [2:2] Receive FIFO not empty 0: Receive FIFO is empty. 1: Receive FIFO is not empty. 1 2 TNF [1:1] Transmit FIFO not full: 0: Transmit FIFO is full. 1: Transmit FIFO is not full. 1 1 TFE [0:0] Transmit FIFO empty: 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty. 1 0 0x3 CPSR 0x10 32 Clock Prescale RESERVED [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 CPSDVSR [7:0] Clock prescale divisor: This field specifies the division factor by which the input system clock to SSI must be internally divided before further use. The value programmed into this field must be an even non-zero number (2-254). The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 8 0 0x0 IMSC 0x14 32 Interrupt Mask Set and Clear RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 TXIM [3:3] Transmit FIFO interrupt mask: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 1 3 RXIM [2:2] Receive FIFO interrupt mask: A read returns the current mask for receive FIFO interrupt. On a write of 1, the mask for receive FIFO interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. 1 2 RTIM [1:1] Receive timeout interrupt mask: A read returns the current mask for receive timeout interrupt. On a write of 1, the mask for receive timeout interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means MIS.RTMIS will not reflect the interrupt. 1 1 RORIM [0:0] Receive overrun interrupt mask: A read returns the current mask for receive overrun interrupt. On a write of 1, the mask for receive overrun interrupt is set which means the interrupt state will be reflected in MIS.RORMIS. A write of 0 clears the mask which means MIS.RORMIS will not reflect the interrupt. 1 0 0x0 RIS 0x18 32 Raw Interrupt Status RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 TXRIS [3:3] Raw transmit FIFO interrupt status: The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO. The transmit interrupt is not qualified with the SSI enable signal. Therefore one of the following ways can be used: - data can be written to the transmit FIFO prior to enabling the SSI and the interrupts. - SSI and interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine. 1 3 RXRIS [2:2] Raw interrupt state of receive FIFO interrupt: The receive interrupt is asserted when there are four or more valid entries in the receive FIFO. 1 2 RTRIS [1:1] Raw interrupt state of receive timeout interrupt: The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period. This mechanism can be used to notify the user that data is still present in the receive FIFO and requires servicing. This interrupt is deasserted if the receive FIFO becomes empty by subsequent reads, or if new data is received on RXD. It can also be cleared by writing to ICR.RTIC. 1 1 RORRIS [0:0] Raw interrupt state of receive overrun interrupt: The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is over-written in the receive shift register, but not the FIFO so the FIFO contents stay valid. It can also be cleared by writing to ICR.RORIC. 1 0 0x8 MIS 0x1c 32 Masked Interrupt Status RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 TXMIS [3:3] Masked interrupt state of transmit FIFO interrupt: This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. 1 3 RXMIS [2:2] Masked interrupt state of receive FIFO interrupt: This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. 1 2 RTMIS [1:1] Masked interrupt state of receive timeout interrupt: This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM. 1 1 RORMIS [0:0] Masked interrupt state of receive overrun interrupt: This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM. 1 0 0x0 ICR 0x20 32 Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. RESERVED [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 RTIC [1:1] Clear the receive timeout interrupt: Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 has no effect. 1 1 RORIC [0:0] Clear the receive overrun interrupt: Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). Writing 0 has no effect. 1 0 0x0 DMACR 0x24 32 DMA Control RESERVED [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 TXDMAE [1:1] Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. 1 1 RXDMAE [0:0] Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. 1 0 0x0 RESERVED1 0x28 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 RESERVED2 0x90 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 TRNG 0x40028000 0 0x2000 registers True Random Number Generator OUT0 0x0 32 Random Number Lower Word Readout Value VALUE_31_0 [31:0] LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. 32 0 0x0 OUT1 0x4 32 Random Number Upper Word Readout Value VALUE_63_32 [31:0] MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. 32 0 0x0 IRQFLAGSTAT 0x8 32 Interrupt Status NEED_CLOCK [31:31] 1: Indicates that the TRNG is busy generating entropy or is in one of its test modes - clocks may not be turned off and the power supply voltage must be kept stable. 0: TRNG is idle and can be shut down 1 31 RESERVED2 [30:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 2 SHUTDOWN_OVF [1:1] 1: The number of FROs shut down (i.e. the number of '1' bits in the ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. 1 1 RDY [0:0] 1: Data are available in OUT0 and OUT1. Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to '0'. If a new number is already available in the internal register of the TRNG, the number is directly clocked into the result register. In this case the status bit is asserted again, after one clock cycle. 1 0 0x0 IRQFLAGMASK 0xc 32 Interrupt Mask RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 SHUTDOWN_OVF [1:1] 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this module. 1 1 RDY [0:0] 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. 1 0 0x0 IRQFLAGCLR 0x10 32 Interrupt Flag Clear RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 SHUTDOWN_OVF [1:1] 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. 1 1 RDY [0:0] 1: Clear IRQFLAGSTAT.RDY. 1 0 0x0 CTL 0x14 32 Control STARTUP_CYCLES [31:16] This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup. If the written value of this field is zero, the number of samples is 2^24, otherwise the number of samples equals the written value times 2^8. 0x0000: 2^24 samples 0x0001: 1*2^8 samples 0x0002: 2*2^8 samples 0x0003: 3*2^8 samples ... 0x8000: 32768*2^8 samples 0xC000: 49152*2^8 samples ... 0xFFFF: 65535*2^8 samples This field can only be modified while TRNG_EN is 0. If 1 an update will be ignored. 16 16 RESERVED11 [15:11] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 5 11 TRNG_EN [10:10] 0: Forces all TRNG logic back into the idle state immediately. 1: Starts TRNG, gathering entropy from the FROs for the number of samples determined by STARTUP_CYCLES. 1 10 RESERVED3 [9:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 3 NO_LFSR_FB [2:2] 1: Remove XNOR feedback from the main LFSR, converting it into a normal shift register for the XOR-ed outputs of the FROs (shifting data in on the LSB side). A '1' also forces the LFSR to sample continuously. This bit can only be set to '1' when TEST_MODE is also set to '1' and should not be used for other than test purposes 1 2 TEST_MODE [1:1] 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter are automatically cleared before enabling access) and keeps IRQFLAGSTAT.NEED_CLOCK at '1'. This bit shall not be used unless you need to change the LFSR seed prior to creating a new random value. All other testing is done external to register control. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 CFG0 0x18 32 Configuration 0 MAX_REFILL_CYCLES [31:16] This field determines the maximum number of samples (between 2^8 and 2^24) taken to re-generate entropy from the FROs after reading out a 64 bits random number. If the written value of this field is zero, the number of samples is 2^24, otherwise the number of samples equals the written value times 2^8. 0x0000: 2^24 samples 0x0001: 1*2^8 samples 0x0002: 2*2^8 samples 0x0003: 3*2^8 samples ... 0x8000: 32768*2^8 samples 0xC000: 49152*2^8 samples ... 0xFFFF: 65535*2^8 samples This field can only be modified while CTL.TRNG_EN is 0. 16 16 RESERVED12 [15:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 12 SMPL_DIV [11:8] This field directly controls the number of clock cycles between samples taken from the FROs. Default value 0 indicates that samples are taken every clock cycle, maximum value 0xF takes one sample every 16 clock cycles. This field must be set to a value such that the slowest FRO (even under worst-case conditions) has a cycle time less than twice the sample period. This field can only be modified while CTL.TRNG_EN is '0'. 4 8 MIN_REFILL_CYCLES [7:0] This field determines the minimum number of samples (between 2^6 and 2^14) taken to re-generate entropy from the FROs after reading out a 64 bits random number. If the value of this field is zero, the number of samples is fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the minimum number of samples equals the written value times 64 (which can be up to 2^14). To ensure same entropy in all generated random numbers the value 0 should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. The number of samples defined here cannot be higher than the number defined by the 'max_refill_cycles' field (i.e. that field takes precedence). No random value will be created if min refill > max refill. This field can only be modified while CTL.TRNG_EN = 0. 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) 0x01: 1*2^6 samples 0x02: 2*2^6 samples ... 0xFF: 255*2^6 samples 8 0 0x0 ALARMCNT 0x1c 32 Alarm Control RESERVED30 [31:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 30 SHUTDOWN_CNT [29:24] Read-only, indicates the number of '1' bits in ALARMSTOP register. The maximum value equals the number of FROs. 6 24 RESERVED21 [23:21] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 21 SHUTDOWN_THR [20:16] Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. 5 16 RESERVED8 [15:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 8 ALARM_THR [7:0] Alarm detection threshold for the repeating pattern detectors on each FRO. An FRO 'alarm event' is declared when a repeating pattern (of up to four samples length) is detected continuously for the number of samples defined by this field's value. Reset value 0xFF should keep the number of 'alarm events' to a manageable level. 8 0 0xFF FROEN 0x20 32 FRO Enable RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 FRO_MASK [23:0] Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. Default state is all '1's to enable all FROs after power-up. Note that they are not actually started up before the CTL.TRNG_EN bit is set to '1'. Bits are automatically forced to '0' here (and cannot be written to '1') while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. 24 0 0xFFFFFF FRODETUNE 0x24 32 FRO De-tune Bit RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 FRO_MASK [23:0] De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run approximately 5% faster. The value of one of these bits may only be changed while the corresponding FRO is turned off (by temporarily writing a '0' in the corresponding bit of the FROEN.FRO_MASK register). 24 0 0x0 ALARMMASK 0x28 32 Alarm Event RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 FRO_MASK [23:0] Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced an 'alarm event'. 24 0 0x0 ALARMSTOP 0x2c 32 Alarm Shutdown RESERVED24 [31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 24 FRO_FLAGS [23:0] Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced more than one 'alarm event' in quick succession and has been turned off. A '1' in this field forces the corresponding bit in FROEN.FRO_MASK to '0'. 24 0 0x0 LFSR0 0x30 32 LFSR Readout Value LFSR_31_0 [31:0] Bits [31:0] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. 32 0 0x0 LFSR1 0x34 32 LFSR Readout Value LFSR_63_32 [31:0] Bits [63:32] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. 32 0 0x0 LFSR2 0x38 32 LFSR Readout Value RESERVED17 [31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 15 17 LFSR_80_64 [16:0] Bits [80:64] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. 17 0 0x0 HWOPT 0x78 32 TRNG Engine Options Information RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 NR_OF_FROS [11:6] Number of FROs implemented in this TRNG, value 24 (decimal). 6 6 RESERVED0 [5:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 0 0x600 HWVER0 0x7c 32 HW Version 0 EIP Number And Core Revision RESERVED28 [31:28] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 28 HW_MAJOR_VER [27:24] 4 bits binary encoding of the major hardware revision number. 4 24 HW_MINOR_VER [23:20] 4 bits binary encoding of the minor hardware revision number. 4 20 HW_PATCH_LVL [19:16] 4 bits binary encoding of the hardware patch level, initial release will carry value zero. 4 16 EIP_NUM_COMPL [15:8] Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. 8 8 EIP_NUM [7:0] 8 bits binary encoding of the module number. This TRNG gives 0x4B. 8 0 0x200B44B IRQSTATMASK 0x1fd8 32 Interrupt Status After Masking RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 SHUTDOWN_OVF [1:1] Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF) 1 1 RDY [0:0] New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY) 1 0 0x0 HWVER1 0x1fe0 32 HW Version 1 TRNG Revision Number RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 REV [7:0] The revision number of this module is Rev 2.0. 8 0 0x20 IRQSET 0x1fec 32 Interrupt Set RDY [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 SWRESET 0x1ff0 32 SW Reset Control RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 RESET [0:0] Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 for reset to be completed. 1 0 0x0 IRQSTAT 0x1ff8 32 Interrupt Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STAT [0:0] TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and IRQFLAGSTAT.RDY 1 0 0x0 UART0 0x40001000 0 0x1000 registers Universal Asynchronous Receiver/Transmitter (UART) interface DR 0x0 32 Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register. RESERVED [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 OE [11:11] UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. 1 11 BE [10:10] UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO (that is., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. 1 10 PE [9:9] UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. In FIFO mode, this error is associated with the character at the top of the FIFO (that is, the oldest received data character since last read). 1 9 FE [8:8] UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO (that is., the oldest received data character since last read). 1 8 DATA [7:0] Data transmitted or received: On writes, the transmit data character is pushed into the FIFO. On reads, the oldest received data character since the last read is returned. 8 0 0x0 RSR 0x4 32 Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs. RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 OE [3:3] UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. 1 3 BE [2:2] UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. 1 2 PE [1:1] UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. 1 1 FE [0:0] UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). 1 0 0x0 ECR 0x4 32 Error Clear This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 OE [3:3] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 3 BE [2:2] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 2 PE [1:1] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 1 FE [0:0] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 0 0x0 RESERVED0 0x8 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 FR 0x18 32 Flag Reads from this register return the UART flags. RESERVED1 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TXFE [7:7] UART Transmit FIFO Empty: The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the transmit holding register is empty. - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. 1 7 RXFF [6:6] UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is full. - If the FIFO is enabled, this bit is set when the receive FIFO is full. 1 6 TXFF [5:5] UART Transmit FIFO Full: Transmit FIFO full. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the transmit holding register is full. - If the FIFO is enabled, this bit is set when the transmit FIFO is full. 1 5 RXFE [4:4] UART Receive FIFO Empty: Receive FIFO empty. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is empty. - If the FIFO is enabled, this bit is set when the receive FIFO is empty. 1 4 BUSY [3:3] UART Busy: If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. 1 3 RESERVED0 [2:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 1 CTS [0:0] Clear To Send: This bit is the complement of the active-low UART CTS input pin. That is, the bit is 1 when CTS input pin is LOW. 1 0 0x90 RESERVED2 0x1c 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 IBRD 0x24 32 Integer Baud-Rate Divisor If this register is modified while transmission or reception is on-going, the baud rate will not be updated until transmission or reception of the current character is complete. RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DIVINT [15:0] The integer baud rate divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, DIVINT=0 does not give a valid baud rate. Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. 16 0 0x0 FBRD 0x28 32 Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. RESERVED [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 DIVFRAC [5:0] Fractional Baud-Rate Divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, IBRD.DIVINT=0 does not give a valid baud rate. Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. 6 0 0x0 LCRH 0x2c 32 Line Control RESERVED [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SPS [7:7] UART Stick Parity Select: 0: Stick parity is disabled 1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0). This bit has no effect when PEN disables parity checking and generation. 1 7 WLEN [6:5] UART Word Length: These bits indicate the number of data bits transmitted or received in a frame. 2 5 8 3 Word Length 8 bits 7 2 Word Length 7 bits 6 1 Word Length 6 bits 5 0 Word Length 5 bits FEN [4:4] UART Enable FIFOs 1 4 EN 1 Transmit and receive FIFO buffers are enabled (FIFO mode) DIS 0 FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers. STP2 [3:3] UART Two Stop Bits Select: If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. 1 3 EPS [2:2] UART Even Parity Select 1 2 EVEN 1 Even parity: The UART generates or checks for an even number of 1s in the data and parity bits. ODD 0 Odd parity: The UART generates or checks for an odd number of 1s in the data and parity bits. PEN [1:1] UART Parity Enable This bit controls generation and checking of parity bit. 1 1 EN 1 Parity checking and generation is enabled. DIS 0 Parity is disabled and no parity bit is added to the data frame BRK [0:0] UART Send Break If this bit is set to 1, a low-level is continually output on the UARTTXD output pin, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. 1 0 0x0 CTL 0x30 32 Control RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CTSEN [15:15] CTS hardware flow control enable 1 15 EN 1 CTS hardware flow control enabled DIS 0 CTS hardware flow control disabled RTSEN [14:14] RTS hardware flow control enable 1 14 EN 1 RTS hardware flow control enabled DIS 0 RTS hardware flow control disabled RESERVED12 [13:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 12 RTS [11:11] Request to Send This bit is the complement of the active-low UART RTS output. That is, when the bit is programmed to a 1 then RTS output on the pins is LOW. 1 11 RESERVED10 [10:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 10 RXE [9:9] UART Receive Enable If the UART is disabled in the middle of reception, it completes the current character before stopping. 1 9 EN 1 UART Receive enabled DIS 0 UART Receive disabled TXE [8:8] UART Transmit Enable If the UART is disabled in the middle of transmission, it completes the current character before stopping. 1 8 EN 1 UART Transmit enabled DIS 0 UART Transmit disabled LBE [7:7] UART Loop Back Enable: Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART. 1 7 EN 1 Loop Back enabled DIS 0 Loop Back disabled RESERVED1 [6:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 1 UARTEN [0:0] UART Enable 1 0 EN 1 UART enabled DIS 0 UART disabled 0x300 IFLS 0x34 32 Interrupt FIFO Level Select RESERVED [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 RXSEL [5:3] Receive interrupt FIFO level select: This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved. 3 3 7_8 4 Receive FIFO becomes >= 7/8 full 6_8 3 Receive FIFO becomes >= 3/4 full 4_8 2 Receive FIFO becomes >= 1/2 full 2_8 1 Receive FIFO becomes >= 1/4 full 1_8 0 Receive FIFO becomes >= 1/8 full TXSEL [2:0] Transmit interrupt FIFO level select: This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved. 3 0 7_8 4 Transmit FIFO becomes <= 7/8 full 6_8 3 Transmit FIFO becomes <= 3/4 full 4_8 2 Transmit FIFO becomes <= 1/2 full 2_8 1 Transmit FIFO becomes <= 1/4 full 1_8 0 Transmit FIFO becomes <= 1/8 full 0x12 IMSC 0x38 32 Interrupt Mask Set/Clear RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTIM [11:11] End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOTMIS. A write of 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. 1 11 OEIM [10:10] Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not reflect the interrupt. 1 10 BEIM [9:9] Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BEMIS. A write of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. 1 9 PEIM [8:8] Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not reflect the interrupt. 1 8 FEIM [7:7] Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not reflect the interrupt. 1 7 RTIM [6:6] Receive timeout interrupt mask. A read returns the current mask for UART's receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not reflect the interrupt. The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the mask is set (RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. 1 6 TXIM [5:5] Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 1 5 RXIM [4:4] Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 CTSMIM [1:1] Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not reflect the interrupt. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 RIS 0x3c 32 Raw Interrupt Status RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTRIS [11:11] End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is tranmitted. 1 11 OERIS [10:10] Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt. Overrun error occurs if data is received and the receive FIFO is full. 1 10 BERIS [9:9] Break error interrupt status: This field returns the raw interrupt state of UART's break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). 1 9 PERIS [8:8] Parity error interrupt status: This field returns the raw interrupt state of UART's parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. 1 8 FERIS [7:7] Framing error interrupt status: This field returns the raw interrupt state of UART's framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1). 1 7 RTRIS [6:6] Receive timeout interrupt status: This field returns the raw interrupt state of UART's receive timeout interrupt. The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data, or when a 1 is written to ICR.RTIC. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RTRIS. 1 6 TXRIS [5:5] Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt through ICR.TXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. 1 5 RXRIS [4:4] Receive interrupt status: This field returns the raw interrupt state of UART's receive interrupt. When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if the receive FIFO reaches the programmed trigger level (IFLS.RXSEL). The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt through ICR.RXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received thereby filling the location. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt through ICR.RXIC. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 CTSRMIS [1:1] Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0xD MIS 0x40 32 Masked Interrupt Status RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTMIS [11:11] End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM. 1 11 OEMIS [10:10] Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM. 1 10 BEMIS [9:9] Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM. 1 9 PEMIS [8:8] Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM. 1 8 FEMIS [7:7] Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM. 1 7 RTMIS [6:6] Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS. 1 6 TXMIS [5:5] Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. 1 5 RXMIS [4:4] Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 CTSMMIS [1:1] Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 ICR 0x44 32 Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTIC [11:11] End of Transmission interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). Writing 0 has no effect. 1 11 OEIC [10:10] Overrun error interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). Writing 0 has no effect. 1 10 BEIC [9:9] Break error interrupt clear: Writing 1 to this field clears the break error interrupt (RIS.BERIS). Writing 0 has no effect. 1 9 PEIC [8:8] Parity error interrupt clear: Writing 1 to this field clears the parity error interrupt (RIS.PERIS). Writing 0 has no effect. 1 8 FEIC [7:7] Framing error interrupt clear: Writing 1 to this field clears the framing error interrupt (RIS.FERIS). Writing 0 has no effect. 1 7 RTIC [6:6] Receive timeout interrupt clear: Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). Writing 0 has no effect. 1 6 TXIC [5:5] Transmit interrupt clear: Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 has no effect. 1 5 RXIC [4:4] Receive interrupt clear: Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 has no effect. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0 2 2 CTSMIC [1:1] Clear to Send (CTS) modem interrupt clear: Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). Writing 0 has no effect. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0. 1 0 0x0 DMACTL 0x48 32 DMA Control RESERVED [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 DMAONERR [2:2] DMA on error. If this bit is set to 1, the DMA receive request outputs (for single and burst requests) are disabled when the UART error interrupt is asserted (more specifically if any of the error interrupts RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). 1 2 TXDMAE [1:1] Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. 1 1 RXDMAE [0:0] Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. 1 0 0x0 RESERVED1 0x4c 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 RESERVED3 0x90 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 RESERVED4 0xfd0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 UART1 0x4000B000 0 0x1000 registers Universal Asynchronous Receiver/Transmitter (UART) interface DR 0x0 32 Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register. RESERVED [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 OE [11:11] UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. 1 11 BE [10:10] UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO (that is., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. 1 10 PE [9:9] UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. In FIFO mode, this error is associated with the character at the top of the FIFO (that is, the oldest received data character since last read). 1 9 FE [8:8] UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO (that is., the oldest received data character since last read). 1 8 DATA [7:0] Data transmitted or received: On writes, the transmit data character is pushed into the FIFO. On reads, the oldest received data character since the last read is returned. 8 0 0x0 RSR 0x4 32 Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs. RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 OE [3:3] UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. 1 3 BE [2:2] UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. 1 2 PE [1:1] UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. 1 1 FE [0:0] UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). 1 0 0x0 ECR 0x4 32 Error Clear This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). RESERVED [31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 28 4 OE [3:3] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 3 BE [2:2] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 2 PE [1:1] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 1 FE [0:0] The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. 1 0 0x0 RESERVED0 0x8 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 FR 0x18 32 Flag Reads from this register return the UART flags. RESERVED1 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 TXFE [7:7] UART Transmit FIFO Empty: The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the transmit holding register is empty. - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. 1 7 RXFF [6:6] UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is full. - If the FIFO is enabled, this bit is set when the receive FIFO is full. 1 6 TXFF [5:5] UART Transmit FIFO Full: Transmit FIFO full. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the transmit holding register is full. - If the FIFO is enabled, this bit is set when the transmit FIFO is full. 1 5 RXFE [4:4] UART Receive FIFO Empty: Receive FIFO empty. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is empty. - If the FIFO is enabled, this bit is set when the receive FIFO is empty. 1 4 BUSY [3:3] UART Busy: If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. 1 3 RESERVED0 [2:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 1 CTS [0:0] Clear To Send: This bit is the complement of the active-low UART CTS input pin. That is, the bit is 1 when CTS input pin is LOW. 1 0 0x90 RESERVED2 0x1c 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 IBRD 0x24 32 Integer Baud-Rate Divisor If this register is modified while transmission or reception is on-going, the baud rate will not be updated until transmission or reception of the current character is complete. RESERVED [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 DIVINT [15:0] The integer baud rate divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, DIVINT=0 does not give a valid baud rate. Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. 16 0 0x0 FBRD 0x28 32 Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. RESERVED [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 DIVFRAC [5:0] Fractional Baud-Rate Divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, IBRD.DIVINT=0 does not give a valid baud rate. Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. 6 0 0x0 LCRH 0x2c 32 Line Control RESERVED [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 SPS [7:7] UART Stick Parity Select: 0: Stick parity is disabled 1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0). This bit has no effect when PEN disables parity checking and generation. 1 7 WLEN [6:5] UART Word Length: These bits indicate the number of data bits transmitted or received in a frame. 2 5 8 3 Word Length 8 bits 7 2 Word Length 7 bits 6 1 Word Length 6 bits 5 0 Word Length 5 bits FEN [4:4] UART Enable FIFOs 1 4 EN 1 Transmit and receive FIFO buffers are enabled (FIFO mode) DIS 0 FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers. STP2 [3:3] UART Two Stop Bits Select: If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. 1 3 EPS [2:2] UART Even Parity Select 1 2 EVEN 1 Even parity: The UART generates or checks for an even number of 1s in the data and parity bits. ODD 0 Odd parity: The UART generates or checks for an odd number of 1s in the data and parity bits. PEN [1:1] UART Parity Enable This bit controls generation and checking of parity bit. 1 1 EN 1 Parity checking and generation is enabled. DIS 0 Parity is disabled and no parity bit is added to the data frame BRK [0:0] UART Send Break If this bit is set to 1, a low-level is continually output on the UARTTXD output pin, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. 1 0 0x0 CTL 0x30 32 Control RESERVED16 [31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 16 16 CTSEN [15:15] CTS hardware flow control enable 1 15 EN 1 CTS hardware flow control enabled DIS 0 CTS hardware flow control disabled RTSEN [14:14] RTS hardware flow control enable 1 14 EN 1 RTS hardware flow control enabled DIS 0 RTS hardware flow control disabled RESERVED12 [13:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 12 RTS [11:11] Request to Send This bit is the complement of the active-low UART RTS output. That is, when the bit is programmed to a 1 then RTS output on the pins is LOW. 1 11 RESERVED10 [10:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 10 RXE [9:9] UART Receive Enable If the UART is disabled in the middle of reception, it completes the current character before stopping. 1 9 EN 1 UART Receive enabled DIS 0 UART Receive disabled TXE [8:8] UART Transmit Enable If the UART is disabled in the middle of transmission, it completes the current character before stopping. 1 8 EN 1 UART Transmit enabled DIS 0 UART Transmit disabled LBE [7:7] UART Loop Back Enable: Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART. 1 7 EN 1 Loop Back enabled DIS 0 Loop Back disabled RESERVED1 [6:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 6 1 UARTEN [0:0] UART Enable 1 0 EN 1 UART enabled DIS 0 UART disabled 0x300 IFLS 0x34 32 Interrupt FIFO Level Select RESERVED [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 RXSEL [5:3] Receive interrupt FIFO level select: This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved. 3 3 7_8 4 Receive FIFO becomes >= 7/8 full 6_8 3 Receive FIFO becomes >= 3/4 full 4_8 2 Receive FIFO becomes >= 1/2 full 2_8 1 Receive FIFO becomes >= 1/4 full 1_8 0 Receive FIFO becomes >= 1/8 full TXSEL [2:0] Transmit interrupt FIFO level select: This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved. 3 0 7_8 4 Transmit FIFO becomes <= 7/8 full 6_8 3 Transmit FIFO becomes <= 3/4 full 4_8 2 Transmit FIFO becomes <= 1/2 full 2_8 1 Transmit FIFO becomes <= 1/4 full 1_8 0 Transmit FIFO becomes <= 1/8 full 0x12 IMSC 0x38 32 Interrupt Mask Set/Clear RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTIM [11:11] End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOTMIS. A write of 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. 1 11 OEIM [10:10] Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not reflect the interrupt. 1 10 BEIM [9:9] Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BEMIS. A write of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. 1 9 PEIM [8:8] Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not reflect the interrupt. 1 8 FEIM [7:7] Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not reflect the interrupt. 1 7 RTIM [6:6] Receive timeout interrupt mask. A read returns the current mask for UART's receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not reflect the interrupt. The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the mask is set (RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. 1 6 TXIM [5:5] Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 1 5 RXIM [4:4] Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 CTSMIM [1:1] Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not reflect the interrupt. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 RIS 0x3c 32 Raw Interrupt Status RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTRIS [11:11] End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is tranmitted. 1 11 OERIS [10:10] Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt. Overrun error occurs if data is received and the receive FIFO is full. 1 10 BERIS [9:9] Break error interrupt status: This field returns the raw interrupt state of UART's break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). 1 9 PERIS [8:8] Parity error interrupt status: This field returns the raw interrupt state of UART's parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. 1 8 FERIS [7:7] Framing error interrupt status: This field returns the raw interrupt state of UART's framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1). 1 7 RTRIS [6:6] Receive timeout interrupt status: This field returns the raw interrupt state of UART's receive timeout interrupt. The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data, or when a 1 is written to ICR.RTIC. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RTRIS. 1 6 TXRIS [5:5] Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt through ICR.TXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. 1 5 RXRIS [4:4] Receive interrupt status: This field returns the raw interrupt state of UART's receive interrupt. When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if the receive FIFO reaches the programmed trigger level (IFLS.RXSEL). The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt through ICR.RXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received thereby filling the location. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt through ICR.RXIC. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 CTSRMIS [1:1] Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0xD MIS 0x40 32 Masked Interrupt Status RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTMIS [11:11] End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM. 1 11 OEMIS [10:10] Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM. 1 10 BEMIS [9:9] Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM. 1 9 PEMIS [8:8] Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM. 1 8 FEMIS [7:7] Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM. 1 7 RTMIS [6:6] Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS. 1 6 TXMIS [5:5] Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. 1 5 RXMIS [4:4] Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 2 2 CTSMMIS [1:1] Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 1 0 0x0 ICR 0x44 32 Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. RESERVED12 [31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 20 12 EOTIC [11:11] End of Transmission interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). Writing 0 has no effect. 1 11 OEIC [10:10] Overrun error interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). Writing 0 has no effect. 1 10 BEIC [9:9] Break error interrupt clear: Writing 1 to this field clears the break error interrupt (RIS.BERIS). Writing 0 has no effect. 1 9 PEIC [8:8] Parity error interrupt clear: Writing 1 to this field clears the parity error interrupt (RIS.PERIS). Writing 0 has no effect. 1 8 FEIC [7:7] Framing error interrupt clear: Writing 1 to this field clears the framing error interrupt (RIS.FERIS). Writing 0 has no effect. 1 7 RTIC [6:6] Receive timeout interrupt clear: Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). Writing 0 has no effect. 1 6 TXIC [5:5] Transmit interrupt clear: Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 has no effect. 1 5 RXIC [4:4] Receive interrupt clear: Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 has no effect. 1 4 RESERVED2 [3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0 2 2 CTSMIC [1:1] Clear to Send (CTS) modem interrupt clear: Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). Writing 0 has no effect. 1 1 RESERVED0 [0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0. 1 0 0x0 DMACTL 0x48 32 DMA Control RESERVED [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 DMAONERR [2:2] DMA on error. If this bit is set to 1, the DMA receive request outputs (for single and burst requests) are disabled when the UART error interrupt is asserted (more specifically if any of the error interrupts RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). 1 2 TXDMAE [1:1] Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. 1 1 RXDMAE [0:0] Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. 1 0 0x0 RESERVED1 0x4c 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 RESERVED3 0x90 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 RESERVED4 0xfd0 32 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RESERVED [31:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 32 0 0x0 UDMA0 0x40020000 0 0x1000 registers ARM Micro Direct Memory Access Controller STATUS 0x0 32 Status TEST [31:28] 0x0: Controller does not include the integration test logic 0x1: Controller includes the integration test logic 0x2: Undefined ... 0xF: Undefined 4 28 RESERVED21 [27:21] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 21 TOTALCHANNELS [20:16] Register value returns number of available uDMA channels minus one. For example a read out value of: 0x00: Show that the controller is configured to use 1 uDMA channel 0x01: Shows that the controller is configured to use 2 uDMA channels ... 0x1F: Shows that the controller is configured to use 32 uDMA channels (32-1=31=0x1F) 5 16 RESERVED8 [15:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 8 8 STATE [7:4] Current state of the control state machine. State can be one of the following: 0x0: Idle 0x1: Reading channel controller data 0x2: Reading source data end pointer 0x3: Reading destination data end pointer 0x4: Reading source data 0x5: Writing destination data 0x6: Waiting for uDMA request to clear 0x7: Writing channel controller data 0x8: Stalled 0x9: Done 0xA: Peripheral scatter-gather transition 0xB: Undefined ... 0xF: Undefined. 4 4 RESERVED1 [3:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 3 1 MASTERENABLE [0:0] Shows the enable status of the controller as configured by CFG.MASTERENABLE: 0: Controller is disabled 1: Controller is enabled 1 0 0x1F0000 CFG 0x4 32 Configuration RESERVED8 [31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 24 8 PRTOCTRL [7:5] Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows: Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. When bit [n] = 1 then the corresponding HProt bit is high. When bit [n] = 0 then the corresponding HProt bit is low. This field controls HProt[3:1] signal for all transactions initiated by uDMA except two transactions below: - the read from the address indicated by source address pointer - the write to the address indicated by destination address pointer HProt[3:1] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor. 3 5 RESERVED1 [4:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 4 1 MASTERENABLE [0:0] Enables the controller: 0: Disables the controller 1: Enables the controller 1 0 0x0 CTRL 0x8 32 Channel Control Data Base Pointer BASEPTR [31:10] This register point to the base address for the primary data structures of each DMA channel. This is not stored in module, but in system memory, thus space must be allocated for this usage when DMA is in usage 22 10 RESERVED0 [9:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 10 0 0x0 ALTCTRL 0xc 32 Channel Alternate Control Data Base Pointer BASEPTR [31:0] This register shows the base address for the alternate data structures and is calculated by module, thus read only 32 0 0x200 WAITONREQ 0x10 32 Channel Wait On Request Status CHNLSTATUS [31:0] Channel wait on request status: Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, this channel may come out of active state even if request is still present. Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it keeps channel Ch in active state until the requests are deasserted. This handshake is necessary for channels where the requester is in an asynchronous domain or can run at slower clock speed than uDMA 32 0 0xFFFF1EFF SOFTREQ 0x14 32 Channel Software Request CHNLS [31:0] Set the appropriate bit to generate a software uDMA request on the corresponding uDMA channel Bit [Ch] = 0: Does not create a uDMA request for channel Ch Bit [Ch] = 1: Creates a uDMA request for channel Ch Writing to a bit where a uDMA channel is not implemented does not create a uDMA request for that channel 32 0 0x0 SETBURST 0x18 32 Channel Set UseBurst CHNLS [31:0] Returns the useburst status, or disables individual channels from generating single uDMA requests. The value R is the arbitration rate and stored in the controller data structure. Read as: Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on channel C. The controller performs 2^R, or single, bus transfers. Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. The controller only responds to burst transfer requests and performs 2^R transfers. Write as: Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. Bit [Ch] = 1: Disables single transfer requests on channel Ch. The controller performs 2^R transfers for burst requests. Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 CLEARBURST 0x1c 32 Channel Clear UseBurst CHNLS [31:0] Set the appropriate bit to enable single transfer requests. Write as: Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer requests. Bit [Ch] = 1: Enables single transfer requests on channel Ch. Writing to a bit where a DMA channel is not implemented has no effect. 32 0 0x0 SETREQMASK 0x20 32 Channel Set Request Mask CHNLS [31:0] Returns the burst and single request mask status, or disables the corresponding channel from generating uDMA requests. Read as: Bit [Ch] = 0: External requests are enabled for channel Ch. Bit [Ch] = 1: External requests are disabled for channel Ch. Write as: Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single request channel [C] input from generating uDMA requests. Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 CLEARREQMASK 0x24 32 Clear Channel Request Mask CHNLS [31:0] Set the appropriate bit to enable DMA request for the channel. Write as: Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from generating requests. Bit [Ch] = 1: Enables channel [C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 32 0 0x0 SETCHANNELEN 0x28 32 Set Channel Enable CHNLS [31:0] Returns the enable status of the channels, or enables the corresponding channels. Read as: Bit [Ch] = 0: Channel Ch is disabled. Bit [Ch] = 1: Channel Ch is enabled. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel Bit [Ch] = 1: Enables channel Ch Writing to a bit where a DMA channel is not implemented has no effect 32 0 0x0 CLEARCHANNELEN 0x2c 32 Clear Channel Enable CHNLS [31:0] Set the appropriate bit to disable the corresponding uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. Bit [Ch] = 1: Disables channel Ch Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 SETCHNLPRIALT 0x30 32 Channel Set Primary-Alternate CHNLS [31:0] Returns the channel control data structure status, or selects the alternate data structure for the corresponding uDMA channel. Read as: Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel Bit [Ch] = 1: Selects the alternate data structure for channel Ch Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 CLEARCHNLPRIALT 0x34 32 Channel Clear Primary-Alternate CHNLS [31:0] Clears the appropriate bit to select the primary data structure for the corresponding uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate data structure. Bit [Ch] = 1: Selects the primary data structure for channel Ch. Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 SETCHNLPRIORITY 0x38 32 Set Channel Priority CHNLS [31:0] Returns the channel priority mask status, or sets the channel priority to high. Read as: Bit [Ch] = 0: uDMA channel Ch is using the default priority level. Bit [Ch] = 1: uDMA channel Ch is using a high priority level. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch to the default priority level. Bit [Ch] = 1: Channel Ch uses the high priority level. Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 CLEARCHNLPRIORITY 0x3c 32 Clear Channel Priority CHNLS [31:0] Clear the appropriate bit to select the default priority level for the specified uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to the high priority level. Bit [Ch] = 1: Channel Ch uses the default priority level. Writing to a bit where a uDMA channel is not implemented has no effect 32 0 0x0 ERROR 0x4c 32 Error Status and Clear RESERVED [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 STATUS [0:0] Returns the status of bus error flag in uDMA, or clears this bit Read as: 0: No bus error detected 1: Bus error detected Write as: 0: No effect, status of bus error flag is unchanged. 1: Clears the bus error flag. 1 0 0x0 REQDONE 0x504 32 Channel Request Done CHNLS [31:0] Reflects the uDMA done status for the given channel, channel [Ch]. It's a sticky done bit. Unless cleared by writing a 1, it holds the value of 1. Read as: Bit [Ch] = 0: Request has not completed for channel Ch Bit [Ch] = 1: Request has completed for the channel Ch Writing a 1 to individual bits would clear the corresponding bit. Write as: Bit [Ch] = 0: No effect. Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 32 0 0x0 DONEMASK 0x520 32 Channel Request Done Mask CHNLS [31:0] Controls the propagation of the uDMA done and active state to the assigned peripheral. Specifically used for software channels. Read as: Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from reaching to the peripherals. Note that the uDMA done state for channel [Ch] is blocked from contributing to generation of combined uDMA done signal Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from reaching to the peripherals. Note that the uDMA done state for channel [Ch] is not blocked from contributing to generation of combined uDMA done signal Write as: Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the peripherals. Note that this disables uDMA done state for channel [Ch] from contributing to generation of combined uDMA done signal Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the peripherals. Note that this enables uDMA done for channel [Ch] to contribute to generation of combined uDMA done signal. 32 0 0x0 VIMS 0x40034000 0 0x400 registers Versatile Instruction Memory System Controls memory access to the Flash and encapsulates the following instruction memories: - Boot ROM - Cache / GPRAM STAT 0x0 32 Status Displays current VIMS mode and line buffer status RESERVED6 [31:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 26 6 IDCODE_LB_DIS [5:5] Icode/Dcode flash line buffer status 0: Enabled or in transition to disabled 1: Disabled and flushed 1 5 SYSBUS_LB_DIS [4:4] Sysbus flash line buffer control 0: Enabled or in transition to disabled 1: Disabled and flushed 1 4 MODE_CHANGING [3:3] VIMS mode change status 0: VIMS is in the mode defined by MODE 1: VIMS is in the process of changing to the mode given in CTL.MODE 1 3 INV [2:2] This bit is set when invalidation of the cache memory is active / ongoing 1 2 MODE [1:0] Current VIMS mode 2 0 OFF 3 VIMS Off mode CACHE 1 VIMS Cache mode GPRAM 0 VIMS GPRAM mode 0x0 CTL 0x4 32 Control Configure VIMS mode and line buffer settings STATS_CLR [31:31] Set this bit to clear statistic counters. 1 31 STATS_EN [30:30] Set this bit to enable statistic counters. 1 30 DYN_CG_EN [29:29] 0: The in-built clock gate functionality is bypassed. 1: The in-built clock gate functionality is enabled, automatically gating the clock when not needed. 1 29 RESERVED6 [28:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 6 IDCODE_LB_DIS [5:5] Icode/Dcode flash line buffer control 0: Enable 1: Disable 1 5 SYSBUS_LB_DIS [4:4] Sysbus flash line buffer control 0: Enable 1: Disable 1 4 ARB_CFG [3:3] Icode/Dcode and sysbus arbitation scheme 0: Static arbitration (icode/docde > sysbus) 1: Round-robin arbitration 1 3 PREF_EN [2:2] Tag prefetch control 0: Disabled 1: Enabled 1 2 MODE [1:0] VIMS mode request. Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1. 2 0 OFF 3 VIMS Off mode CACHE 1 VIMS Cache mode GPRAM 0 VIMS GPRAM mode 0x0 WDT 0x40080000 0 0x1000 registers Watchdog Timer LOAD 0x0 32 Configuration WDTLOAD [31:0] This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter is restarted to count down from the new value. If this register is loaded with 0x0000.0000, an interrupt is immediately generated. 32 0 0xFFFFFFFF VALUE 0x4 32 Current Count Value WDTVALUE [31:0] This register contains the current count value of the timer. 32 0 0xFFFFFFFF CTL 0x8 32 Control RESERVED3 [31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 29 3 INTTYPE [2:2] WDT Interrupt Type 0: WDT interrupt is a standard interrupt. 1: WDT interrupt is a non-maskable interrupt. 1 2 NONMASKABLE 1 Non-maskable interrupt MASKABLE 0 Maskable interrupt RESEN [1:1] WDT Reset Enable. Defines the function of the WDT reset source (see PRCM:WARMRESET.WDT_STAT if enabled) 0: Disabled. 1: Enable the Watchdog reset output. 1 1 EN 1 Reset output Enabled DIS 0 Reset output Disabled INTEN [0:0] WDT Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event enabled. Once set, this bit can only be cleared by a hardware reset. 1 0 EN 1 Interrupt Enabled DIS 0 Interrupt Disabled 0x0 ICR 0xc 32 Interrupt Clear WDTICR [31:0] This register is the interrupt clear register. A write of any value to this register clears the WDT interrupt and reloads the 32-bit counter from the LOAD register. 32 0 0x0 RIS 0x10 32 Raw Interrupt Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 WDTRIS [0:0] This register is the raw interrupt status register. WDT interrupt events can be monitored via this register if the controller interrupt is masked. Value Description 0: The WDT has not timed out 1: A WDT time-out event has occurred 1 0 0x0 MIS 0x14 32 Masked Interrupt Status RESERVED1 [31:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 31 1 WDTMIS [0:0] This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the WDT interrupt enable bit CTL.INTEN. Value Description 0: The WDT has not timed out or is masked. 1: An unmasked WDT time-out event has occurred. 1 0 0x0 TEST 0x418 32 Test Mode RESERVED9 [31:9] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 23 9 STALL [8:8] WDT Stall Enable 0: The WDT timer continues counting if the CPU is stopped with a debugger. 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the CPU is restarted, the WDT resumes counting. 1 8 EN 1 Enable STALL DIS 0 Disable STALL RESERVED1 [7:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 7 1 TEST_EN [0:0] The test enable bit 0: Enable external reset 1: Disables the generation of an external reset. Instead bit 1 of the INT_CAUS register is set and an interrupt is generated 1 0 EN 1 Test mode Enabled DIS 0 Test mode Disabled 0x0 INT_CAUS 0x41c 32 Interrupt Cause Test Mode RESERVED2 [31:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 30 2 CAUSE_RESET [1:1] Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). 1 1 CAUSE_INTR [0:0] Replica of RIS.WDTRIS 1 0 0x0 LOCK 0xc00 32 Lock WDTLOCK [31:0] WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates (NOTE: TEST.TEST_EN bit is not lockable). A read of this register returns the following values: 0x0000.0000: Unlocked 0x0000.0001: Locked 32 0 0x0