ARM Ltd. ARM SSE300 ARMv8.1-M Mainline 1.0 ARM 32-bit v8.1-M Mainline based device ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM55 r0p0 little true true 3 false 8 8 32 32 read-write 0x00000000 0xFFFFFFFF SYSCOUNTER_CNTRL System counter control 0x58100000 32 read-write 0 0x1000 registers System_Timestamp_Counter 32 CNTCR Counter Control Register 0x00 32 read-write 0x0 EN Enable Counter 0 1 Disabled Count is not incrementing 0 Enabled Count is incrementing 1 HDBG Halt on debug 1 1 Nohalt HALTREQ signal into the Counter has no effect 0 Halt HALTREQ signal into the Counter halts the Count 1 SCEN Scale enable 2 1 ScaleDisabled Scaling is not enabled 0 ScaleEnabled Scaling is enabled 1 INTRMASK Interrupt mask 3 1 InterruptDisabled Interrupt output disabled 0 InterruptEnabled Interrupt output enabled 1 PSLVERRDIS PSLVERR output disable 4 1 PSLVERRDisabled PSLVERR is permanently driven to 0 0 PSLVERREnabled PSLVERR output that the System Counter generates dynamically 1 INTRCLR Interrupt clear bit, only writes of 0 are permitted, and writes of 1 are ignored. 5 1 CNTSR Counter frequency status information 0x4 32 read-only DBGH Indicates whether the counter is halted because the Halt-on-Debug signal is asserted 1 4 Nohalt Counter is not halted 0 Halt Counter is halted 1 CNTCV Current count value 0x8 64 read-write Countvalue Indicates the countvalue 0 64 CNTSCR Stores the Counter Scaling value 0x10 32 read-write 0x01000000 ScaleVal The amount added to the Counter Count Value for every period of the counter as determined by 1/Frequency from the current operating frequency of the system counter, the counter tick 0 32 CNTID Indicates additional information about Counter Scaling implementation 0x1C 32 read-only CNTSC Indicates whether Counter Scaling is implemented 0 4 CNTSCNotimplemented Counter Scaling is not implemented 0 CNTSCImplemented Counter Scaling is implemented 1 CNTCS Indicates whether Clock Switching is implemented 16 1 CNTCSNotimplemented HW-based Counter Clock Switching is not implemented 0 CNTCSImplemented HW-based Counter Clock Switching is implemented 1 CNTSELCLK Indicates the clock source that the Counter is using 17 2 Invalid0 Invalid status, Counter not incrementing 0 CLK0 CLK0 (REFCLK) 1 CLK1 CLK1 (FASTCLK) 2 Invalid1 Invalid status, Counter not incrementing 3 CNTSCR_OVR Override counter enable condition for writing to CNTSCR* registers 19 1 COND1 CNTSCR* can be written only when CNTCR.EN=0 0 COND2 CNTSCR* can be written when CNTCR.EN=0 or 1 1 CNTSCR0 Counter Scaling register 0xD0 32 read-write 0x01000000 ScaleVal The amount added to the Counter Count Value for every period of the counter as determined by 1/Frequency from the current operating frequency of the system counter, the counter tick 0 32 CNTSCR1 Counter Scaling register 0xD4 32 read-write 0x01000000 ScaleVal The amount added to the Counter Count Value for every period of the counter as determined by 1/Frequency from the current operating frequency of the system counter, the counter tick 0 32 CNTPIDR4 Peripheral Identification Register 4 0xFD0 32 read-only 0x00000004 CNTPIDR0 Peripheral Identification Register 0 0xFE0 32 read-only 0x000000BA CNTPIDR1 Peripheral Identification Register 1 0xFE4 32 read-only 0x00000B0 CNTPIDR2 Peripheral Identification Register 2 0xFE8 32 read-only 0x000000B CNTPIDR3 Peripheral Identification Register 3 0xFEC 32 read-only 0x0000000 CNTCIDR0 Component Identification Register 0. 0xFF0 32 read-only 0x0000000D CNTCIDR1 Component Identification Register 1 0xFF4 32 read-only 0x00000F0 CNTCIDR2 Component Identification Register 2 0xFF8 32 read-only 0x0000005 CNTCIDR3 Component Identification Register 3 0xFFC 32 read-only 0x00000B1 SYSCOUNTER_READ System counter read 0x48101000 32 read-write 0 0x1000 registers CNTCV Current count value 0x0 64 read-write Countvalue Indicates the countvalue 0 64 CNTPIDR4 Peripheral Identification Register 4 0xFD0 32 read-only 0x00000004 CNTPIDR0 Peripheral Identification Register 0 0xFE0 32 read-only 0x000000BB CNTPIDR1 Peripheral Identification Register 1 0xFE4 32 read-only 0x00000B0 CNTPIDR2 Peripheral Identification Register 2 0xFE8 32 read-only 0x000000B CNTPIDR3 Peripheral Identification Register 3 0xFEC 32 read-only 0x0000000 CNTCIDR0 Component Identification Register 0. 0xFF0 32 read-only 0x0000000D CNTCIDR1 Component Identification Register 1 0xFF4 32 read-only 0x00000F0 CNTCIDR2 Component Identification Register 2 0xFF8 32 read-only 0x0000005 CNTCIDR3 Component Identification Register 3 0xFFC 32 read-only 0x00000B1 SYSCOUNTER_READ_Secure System Counter Read (Secure) 0x58101000 SYSINFO 1.0 System Information SYSINFO 0x48020000 32 read-only 0 0x1000 registers SOC_IDENTITY System Identity Register 0x00 read-only SOC_IMPLEMENTATOR JEP106 code of the company that implemented the SoC [11:0] SOC_REVISION IMPL_DEF value used to distinguish minor revisions of the SoC. [15:12] SOC_VARIANT IMPL_DEF value variant or major revision of the SoC. [19:16] SOC_PRODUCT_ID IMPL_DEF value identifying the SoC. [31:20] SYS_CONFIG0 System Hardware Configuration 0 register 0x004 read-only NUM_VM_BANK Number of Volatile Memory Banks. [3:0] VM_ADDR_WIDTH Volatile Memory Bank Address Width, where the size of each bank is equal to 2VM_ADDR_WIDTH bytes. [8:4] HAS_CRYPTO CryptoCell Included. [9:9] No CryptoCell Not Included 0 Yes CryptoCell Included 1 HAS_CSS Include CoreSight SoC-600 based Debug infrastructure. [10:10] No Not included. 0 Yes Included. 1 PI_LEVEL Power Infrastructure Level [12:11] IntermediateLevel Intermediate Level 01 CPU0_TYPE CPU 0 Core Type [18:16] CortexM55 Cortex-M55 0x3 CPU0_HAS_SYSTCM CPU 0 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level. [19:19] No Not included. 0 Yes Included. 1 CPU0_TCM_BANK_NUM The VM Bank that is the TCM memory for CPU 0. [23:20] CPU1_TYPE CPU 1 Core Type [26:24] No Does not exist. 000 CPU1_HAS_SYSTCM CPU 1 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level. [27:27] No Not included. 0 Yes Included. 1 CPU1_TCM_BANK_NUM The VM Bank that is the TCM memory for CPU 1. [31:28] SYS_CONFIG1 System Hardware Configuration 0 register 0x008 read-only CPU2_TYPE CPU 2 Core Type. [2:0] No Does not exist. 000 CPU2_HAS_SYSTCM CPU 2 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level. [3:3] No Not included. 0 Yes Included. 1 CPU2_TCM_BANK_NUM The VM Bank that is the TCM memory for CPU 2. [7:4] CPU3_TYPE CPU 3 Core Type. [10:8] No Does not exist. 000 CPU3_HAS_SYSTCM CPU 3 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level. [11:11] No Not included. 0 Yes Included. 1 CPU3_TCM_BANK_NUM The VM Bank that is the TCM memory for CPU 3. [15:12] IIDR Subsystem Implementation Identity Register. 0xFC8 read-only IMP_IMPLEMENTATOR Contains the JEP106 code of the company that implemented the subsystem implementation. [11:0] IMP_REVISION IMPL_DEF value used to distinguish minor revisions of the subsystem implementation. [15:12] IMP_VARIANT IMPL_DEF value variant or major revision of the subsystem implementation. [19:16] IMP_PRODUCT_ID IMPL_DEF value identifying the subsystem implementation. [31:20] PIDR4 Peripheral ID 4 0xFD0 read-only 0x00000004 PIDR0 Peripheral ID 0 0xFE0 read-only 0x00000058 PIDR1 Peripheral ID 1 0xFE4 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 read-only 0x0000001B PIDR3 Peripheral ID 3 0xFEC read-only 0x00000000 CIDR0 Component ID 0 0xFF0 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 read-only 0x00000005 CIDR3 Component ID 3 0xFFC read-only 0x000000B1 SYSINFO_Secure System Information (Secure) SYSINFO_Secure 0x58020000 SYSCONTROL 1.0 System Control SYSCTRL 0x58021000 32 read-write 0 0x1000 registers MGMT_PPU 14 SYS_PPU 15 CPU0_PPU 16 PPU_DEBUG 26 SECDBGSTAT Secure Debug Configuration Status 0x00 read-only 0x00000000 DBGEN_I_STATUS Debug enable value [0:0] enable debug enable 1 disable debug disable 0 DBGEN_SEL_STATUS Debug enable selector value [1:1] enable debug enable selector 1 disable debug disable selector 0 NIDEN_I_STATUS Non-invasive debug enable value [2:2] enable non-invasive debug enable 1 disable non-invasive debug disable 0 NIDEN_SEL_STATUS Non-invasive debug enable selector value [3:3] enable non-invasive debug enable selector 1 disable non-invasive debug disable selector 0 SPIDEN_I_STATUS Secure privilege invasive debug enable value [4:4] enable Secure privilege invasive debug enable 1 disable Secure privilege invasive debug disable 0 SPIDEN_SEL_STATUS Secure privilege invasive debug enable selector value [5:5] enable Secure privilege invasive debug enable selector 1 disable Secure privilege invasive debug disable selector 0 SPNIDEN_STATUS Secure privilege non-invasive debug enable value [6:6] enable Secure privilege non-invasive debug enable 1 disable Secure privilege non-invasive debug disable 0 SPNIDEN_SEL_STATUS Secure privilege non-invasive debug enable selector value [7:7] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPACCEN_STATUS Active High DAP Access Enable Value. This bit reflects the value on the DAPACCEN pin. [8:8] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPACCEN_SEL_STATUS Active High DAP Access Enable Selector Value. This bit returns the DAPACCEN_SEL value. Forced to Zero if DAPACCENSELDIS = 1. [9:9] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCEN_STATUS Active High DAP to Debug Subsystem Access Enable Value. This bit reflects the value on the DAPDSSACCEN pin. [10:10] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCEN_SEL_STATUS Active High DAP to Debug Subsystem Access Enable Selector Value. This bit returns the DAPDSSACCEN_SEL value. Forced to Zero if DAPDSSACCENSELDIS = 1. [11:11] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DBGENSELDIS_STATUS Returns the DBGENSELDIS configuration value when read. [24:24] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 NIDENSELDIS_STATUS Returns the NIDENSELDIS configuration value when read. [25:25] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 SPIDENSELDIS_STATUS Returns the SPIDENSELDIS configuration value when read. [26:26] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 SPNIDENSELDIS_STATUS Returns the SPNIDENSELDIS configuration value when read. [27:27] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPACCENSELDIS_STATUS Returns the DAPACCENSELDIS configuration value when read. [28:28] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCENSELDIS_STATUS Returns the DAPDSSACCENSELDIS configuration value when read. [29:29] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 SECDBGSET Secure Debug Configuration Set 0x04 write-only DBGEN_I_SET High active debug enable set control [0:0] DBGEN_SEL_SET Debug enable selector set control [1:1] enable debug enable selector set control 1 disable debug disable selector set control 0 NIDEN_I_SET Non-invasive debug enable set control [2:2] enable non-invasive debug enable set control 1 disable non-invasive debug disable set control 0 NIDEN_SEL_SET Non-invasive debug enable selector set control [3:3] enable non-invasive debug enable selector set control 1 disable non-invasive debug disable selector set control 0 SPIDEN_I_SET Secure privilege invasive debug enable set control [4:4] enable Secure privilege invasive debug enable set control 1 disable Secure privilege invasive debug disable set control 0 SPIDEN_SEL_SET Secure privilege invasive debug enable selector set control [5:5] enable Secure privilege invasive debug enable selector set control 1 disable Secure privilege invasive debug disable selector set control 0 SPNIDEN_I_SET Secure privilege non-invasive debug enable set control [6:6] enable Secure privilege non-invasive debug enable set control 1 disable Secure privilege non-invasive debug disable set control 0 SPNIDEN_SEL_SET Secure privilege non-invasive debug enable selector set control [7:7] enable Secure privilege non-invasive debug enable selector set control 1 disable Secure privilege non-invasive debug disable selector set control 0 DAPACCEN_I_SET Set internal version of Active High DAP Access Enable. Write HIGH to set DAPACCEN_I. When read returns DAPACCEN_I. RAZWI if DAPACCENSELDIS = 1. [8:8] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPACCEN_SEL_SET Set Active High DAP Access Enable Selector. Write HIGH to set DAPACCEN_SEL. RAZWI if DAPACCENSELDIS = 1. [9:9] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCEN_I_SET Set internal version of Active High DAP to Debug Subsystem Access Enable. Write HIGH to set DAPDSSACCEN_I. When read returns DAPDSSACCEN_I. RAZWI if DAPDSSACCENSELDIS = 1. [10:10] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCEN_SEL_SET Set Active High DAP to Debug Subsystem Access Enable Selector. Write HIGH to set DAPDSSACCEN_SEL. RAZWI if DAPDSSACCENSELDIS = 1. [11:11] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 SECDBGCLR Secure Debug Configuration Clear 0x08 write-only DBGEN_I_CLR Debug enable clear control [0:0] enable debug enable clear control 1 disable debug disable clear control 0 DBGEN_SEL_CLR Debug enable selector clear control [1:1] enable debug enable selector clear control 1 disable debug disable selector clear control 0 NIDEN_I_CLR Non-invasive debug enable clear control [2:2] enable non-invasive debug enable clear control 1 disable non-invasive debug disable clear control 0 NIDEN_SEL_CLR Non-invasive debug enable selector clear control [3:3] enable non-invasive debug enable selector clear control 1 disable non-invasive debug disable selector clear control 0 SPIDEN_I_CLR Secure privilege invasive debug enable clear control [4:4] enable Secure privilege invasive debug enable clear control 1 disable Secure privilege invasive debug disable clear control 0 SPIDEN_SEL_CLR Secure privilege invasive debug enable selector clear control [5:5] enable Secure privilege invasive debug enable selector clear control 1 disable Secure privilege invasive debug disable selector clear control 0 SPNIDEN_I_CLR Secure privilege non-invasive debug enable clear control [6:6] enable Secure privilege non-invasive debug enable clear control 1 disable Secure privilege non-invasive debug disable clear control 0 SPNIDEN_SEL_CLR Secure privilege non-invasive debug enable selector clear control [7:7] enable Secure privilege non-invasive debug enable selector clear control 1 disable Secure privilege non-invasive debug disable selector clear control 0 DAPACCEN_I_CLR Clear internal version of Active High DAP Access Enable. Write HIGH to clear DAPACCEN_I. When read returns DAPACCEN_I. RAZWI if DAPACCENSELDIS = 1. [8:8] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPACCEN_SEL_CLR Clear Active High DAP Access Enable Selector. Write HIGH to clear DAPACCEN_SEL. RAZWI if DAPACCENSELDIS = 1. [9:9] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCEN_I_CLR Clears internal version of Active High DAP to Debug Subsystem Access Enable. Write HIGH to clear DAPDSSACCEN_I. Always RAZ. WI if DAPDSSACCENSELDIS = 1. [10:10] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 DAPDSSACCEN_SEL_CLR Clear Active High DAP to Debug Subsystem Access Enable Selector. Write HIGH to clear DAPDSSACCEN_SEL. RAZWI if DAPDSSACCENSELDIS = 1. [11:11] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 SCSECCTRL System Security Control 0x0C read-write 0x00000000 SCSECCFGLOCK Control to disable writes to security-related control registers in this register block [2:2] disable control to disable writes to security-related control registers in this register block 1 enable control to enable writes to security-related control registers in this register block 0 CLK_CFG0 Clock Configuration Register 0. 0x10 read-write CPU0CLKCFG Clock Configuration value that drives CPU0CLKCFG signals. [3:0] CPU0CLKCFGSTATUS Clock Configuration Status value that reports the status of clock control for CPU0CLK. [19:16] read-only CLK_CFG1 Clock Configuration Register 1. 0x14 read-write SYSCLKCFG Clock Configuration value that drives SYSCLKCFG signals. [3:0] AONCLKCFG Clock Configuration value that drives AONCLKCFG signals. [7:4] SYSCLKCFGSTATUS Clock Configuration Status value that reports the status of clock control for SYSCLK. [19:16] read-only AONCLKCFGSTATUS Clock Configuration Status value that reports the status of clock control for AONCLK. [23:20] CLOCK_FORCE Clock Force 0x18 read-write MGMT_CLKFORCE Set HIGH to force all clocks in PD_AON domain that runs on SYSCLK to run. [0:0] SYS_CLKFORCE Set HIGH to force all clocks in PD_SYS to run. [1:1] DEBUG_CLKFORCE Set HIGH to force all clocks in PD_DEBUG to run. [2:2] CPU0_CLKFORCE Set HIGH to force PD_CPU0 Local clocks to run. [4:4] AONCLK_FORCE Set HIGH to request the input AONCLK source to stay ON. [16:16] SYSCLK_FORCE Set HIGH to request the input SYSCLK source to stay ON. [17:17] CPU0CLK_FORCE Set HIGH to request the input CPU0CLK source to stay ON.. [19:19] RESET_SYNDROME Reset Syndrome 0x100 read-write 0x00000001 PoR Power-on [0:0] write-only NSWDRSTREQ Non-Secure Watchdog Cold Reset Request. [1:1] write-only SWDRSTREQ Secure Watchdog Cold Reset Request. [2:2] write-only SLOWCLKWDRSTREQ SLOWCLK Watchdog Cold Reset Request. [3:3] write-only RESETREQ Subsystem Hardware Cold Reset Request Input. [4:4] write-only SWRESETREQ Software Cold Reset Request. [5:5] write-only HOSTRESETREQ Host Level Cold Reset Request Input. [7:7] write-only CPU0RSTREQ CPU 0 Warm Reset Request. [8:8] write-only CPU0LOCKUP CPU 0 Lockup Status. [12:12] write-only RESET_MASK Reset Mask 0x104 read-write NSWDRSTREQEN Enable NON-SECURE WATCHDOG Reset [1:1] read-write enabled Enable NON-SECURE WATCHDOG Reset 1 disabled Disabled NON-SECURE WATCHDOG Reset 0 CPU0RSTREQENRST CPU 0 Warm Reset Request Enable. [8:8] read-write enabled Enable Merging CPU 0 System Reset Request 1 disabled Disabled Merging CPU 0 System Reset Request 0 SWRESET Software Reset 0x108 write-only 0x00000000 SWRESETREQ High Active Software Reset Request [9:9] write-only GRETREG General Purpose Retention 0x10C read-write 0x00000000 GRETREG General Purpose Retention Register [15:0] read-write INITSVRTOR0 Initial Secure Reset Vector Register For CPU 0 0x110 read-write INITSVTOR0LOCK Lock INITSVTOR0. When set to 1, will stop any further writes to INITSVTOR0 and INITSVTOR0LOCK fields. Cleared only by Warm reset. [0:0] write-only INITSVTOR0 Default Secure Vector table offset at reset for CPU 0 [31:7] read-write CPUWAIT CPU Boot wait control after reset 0x120 read-write CPU0WAIT CPU 0 waits at boot and whether CPU1 powers up [0:0] read-write normally_or_powerup CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up 0 wait_or_no_powerup CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up 1 NMI_ENABLE NMI Enable Register 0x124 read-write CPU0_INTNMI_ENABLE CPU0 Internally Sourced NMI Enable [0:0] read-write enable CPU0 Internally Sourced NMI Enabled 1 disabled CPU0 Internally Sourced NMI Disabled 0 CPU1_INTNMI_ENABLE CPU1 Internally Sourced NMI Enable [1:1] read-write enable CPU1 Internally Sourced NMI Enabled 1 disabled CPU1 Internally Sourced NMI Disabled 0 CPU0_EXPNMI_ENABLE CPU0 Externally Sourced NMI Enable [16:16] read-write enable CPU0 Externally Sourced NMI Enabled 1 disabled CPU0 Externally Sourced NMI Disabled 0 CPU1_EXPNMI_ENABLE CPU1 Externally Sourced NMI Enable [17:17] read-write enable CPU1 Externally Sourced NMI Enabled 1 disabled CPU1 Externally Sourced NMI Disabled 0 PWRCTRL Power Configuration and Control. 0x1FC read-write 0x00000003 PPU_ACCESS_UNLOCK PPU_ACCESS_FILTER write unlock. When 1, Both PPU_ACCESS_FILTER and this register bits can be written. When set to '0' the PPU_ACCESS_FILTER and this register bit will no longer writable, and PPU_ACCESS_UNLOCK will stay '0'. [0:0] write-only PPU_ACCESS_FILTER Filter Access to PPU Registers. When set to '1' only key PPU interrupt handling registers are open to write access, and all other PPU registers are read only. When set to '0' releases all PPU register to full access. [1:1] read-write PDCM_PD_SYS_SENSE External Wakeup Control 0x200 read-write S_PD_SYS_ON Enable PD_SYS ON Sensitivity [0:0] read-write enable Keep PD_SYS awake after powered ON 1 S_PD_CPU0CORE_ON Tied to HIGH [1:1] read-only high PD_SYS always tries to stay ON if PD_CPU0CORE is ON 1 S_PD_DEBUG_ON Tied to LOW [13:13] read-only S_PDCMQREQ0 Enable PDCMQREQn[0] signal Sensitivity [16:16] read-write enable Enable PDCMQREQn[0] signal Sensitivity. 1 disabled Disable PDCMQREQn[0] signal Sensitivity. 0 S_PDCMQREQ1 Enable PDCMQREQn[1] signal Sensitivity [17:17] read-write enable Enable PDCMQREQn[1] signal Sensitivity. 1 disabled Disable PDCMQREQn[1] signal Sensitivity. 0 S_PDCMQREQ2 Enable PDCMQREQn[2] signal Sensitivity [18:18] read-write enable Enable PDCMQREQn[2] signal Sensitivity. 1 disabled Disable PDCMQREQn[2] signal Sensitivity. 0 S_PDCMQREQ3 Enable PDCMQREQn[3] signal Sensitivity [19:19] read-write enable Enable PDCMQREQn[3] signal Sensitivity. 1 disabled Disable PDCMQREQn[3] signal Sensitivity. 0 MIN_PWR_STATE Defines the Minimum Power State, when PD_SYS is trying to enter a lower power state. [31:30] read-write PDCM_PD_CPU0_SENSE PDCM PD_CPU0 Sensitivity. 0x204 read-write 0x00000000 S_PD_SYS_ON Enable PD_SYS ON Sensitivity [0:0] read-write enable Keep PD_SYS awake after powered ON 1 S_PD_CPU0_ON Tied to LOW [1:1] read-only S_PD_DEBUG_ON Tied to LOW [13:13] read-only S_PDCMQREQ0 PDCMQREQn[0] Tied to LOW [16:16] read-write S_PDCMQREQ1 PDCMQREQn[1] Tied to LOW [17:17] read-write S_PDCMQREQ2 PDCMQREQn[2] Tied to LOW [18:18] read-write S_PDCMQREQ3 PDCMQREQn[3] Tied to LOW [19:19] read-write PDCM_PD_VMR0_SENSE PDCM PD_VMR0 Sensitivity. 0x214 read-write 0x40000000 S_PD_SYS_ON Enable PD_SYS ON Sensitivity [0:0] read-write enable Keep PD_SYS awake after powered ON 1 S_PD_CPU0_ON Tied to HIGH [1:1] read-only high PD_SYS always tries to stay ON if PD_CPU0CORE is ON 1 S_PD_DEBUG_ON Tied to LOW [13:13] read-only S_PDCMQREQ0 Enable PDCMQREQn[0] signal Sensitivity [16:16] read-write enable Enable PDCMQREQn[0] signal Sensitivity. 1 disabled Disable PDCMQREQn[0] signal Sensitivity. 0 S_PDCMQREQ1 Enable PDCMQREQn[1] signal Sensitivity [17:17] read-write enable Enable PDCMQREQn[1] signal Sensitivity. 1 disabled Disable PDCMQREQn[1] signal Sensitivity. 0 S_PDCMQREQ2 Enable PDCMQREQn[2] signal Sensitivity [18:18] read-write enable Enable PDCMQREQn[2] signal Sensitivity. 1 disabled Disable PDCMQREQn[2] signal Sensitivity. 0 S_PDCMQREQ3 Enable PDCMQREQn[3] signal Sensitivity [19:19] read-write enable Enable PDCMQREQn[3] signal Sensitivity. 1 disabled Disable PDCMQREQn[3] signal Sensitivity. 0 MIN_PWR_STATE Defines the Minimum Power State, when PD_SYS is trying to enter a lower power state. [31:30] read-write PDCM_PD_VMR1_SENSE PDCM PD_VMR1 Sensitivity. 0x218 read-write 0x40000000 S_PD_SYS_ON Enable PD_SYS ON Sensitivity [0:0] read-write enable Keep PD_SYS awake after powered ON 1 S_PD_CPU0_ON Tied to HIGH [1:1] read-only high PD_SYS always tries to stay ON if PD_CPU0CORE is ON 1 S_PD_DEBUG_ON Tied to LOW [13:13] read-only S_PDCMQREQ0 Enable PDCMQREQn[0] signal Sensitivity [16:16] read-write enable Enable PDCMQREQn[0] signal Sensitivity. 1 disabled Disable PDCMQREQn[0] signal Sensitivity. 0 S_PDCMQREQ1 Enable PDCMQREQn[1] signal Sensitivity [17:17] read-write enable Enable PDCMQREQn[1] signal Sensitivity. 1 disabled Disable PDCMQREQn[1] signal Sensitivity. 0 S_PDCMQREQ2 Enable PDCMQREQn[2] signal Sensitivity [18:18] read-write enable Enable PDCMQREQn[2] signal Sensitivity. 1 disabled Disable PDCMQREQn[2] signal Sensitivity. 0 S_PDCMQREQ3 Enable PDCMQREQn[3] signal Sensitivity [19:19] read-write enable Enable PDCMQREQn[3] signal Sensitivity. 1 disabled Disable PDCMQREQn[3] signal Sensitivity. 0 MIN_PWR_STATE Defines the Minimum Power State, when PD_SYS is trying to enter a lower power state. [31:30] read-write PIDR4 Peripheral ID 4 0xFD0 read-only 0x00000004 PIDR0 Peripheral ID 0 0xFE0 read-only 0x00000054 PIDR1 Peripheral ID 1 0xFE4 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 read-only 0x0000001B PIDR3 Peripheral ID 3 0xFEC read-only 0x00000000 CIDR0 Component ID 0 0xFF0 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 read-only 0x00000005 CIDR3 Component ID 3 0xFFC read-only 0x000000B1 SAU 1.0 Security Attribution Unit SAU 0xE000EDD0 32 read-write 0 0x20 registers CTRL Control Register 0x00 ENABLE Enable [0:0] Disable SAU is disabled 0 Enable SAU is enabled 1 ALLNS Security attribution if SAU disabled [1:1] Secure Memory is marked as secure 0 Non_Secure Memory is marked as non-secure 1 TYPE Type Register 0x04 read-only SREGION Number of implemented SAU regions [7:0] RNR Region Number Register 0x08 REGION Currently selected SAU region [7:0] SAU_Region_0 Select SAU Region 0 0 SAU_Region_1 Select SAU Region 1 1 SAU_Region_2 Select SAU Region 2 2 SAU_Region_3 Select SAU Region 3 3 RBAR Region Base Address Register 0x0C BADDR Base Address [31:5] RLAR Region Limit Address Register 0x10 LADDR Limit Address [31:5] NSC Non-Secure Callable [1:1] ENABLE SAU Region enabled [0:0] SFSR Secure Fault Status Register 0x14 LSERR Lazy state error flag [7:7] SFARVALID Secure fault address valid [6:6] LSPERR Lazy state preservation error flag [5:5] INVTRAN Invalid transition flag [4:4] AUVIOL Attribution unit violation flag [3:3] INVER Invalid exception return flag [2:2] INVIS Invalid integrity signature flag [1:1] INVEP Invalid entry pointd [0:0] TIMER0 1.0 Timer 0 Timer 0x48000000 32 read-write 0 0x1000 registers TIMER0 Timer 0 3 CNTPCTLOW Physical Count Register Lower Word. 0x000 read-only 0x00000000 CNTPCTHIGH Physical Count Register Higher Word. 0x004 read-only 0x00000000 CNTFRQ Counter Frequency Register. 0x010 read-write 0x00000000 CNTP_CVAL_LOW Timer Compare Value Lower Word Register. 0x020 read-write 0x00000000 CNTP_CVAL_HIGH Timer Compare Value Higher Word Register. 0x024 read-write 0x00000000 CNTP_TVAL Timer Value register. 0x028 read-write 0x00000000 CNTP_CTL Timer Control register. 0x02C read-write 0x00000000 En Enable Counter [0:0] Off 0 On 1 IMASK Interrupt Mask [1:1] Off 0 On 1 ISTATUS Interrupt Status [2:2] Off 0 On 1 CNTP_AIVAL_LOW AutoIncrValue Lower Word Register. 0x040 read-only 0x00000000 CNTP_AIVAL_HIGH AutoIncrValue Higher Word Register. 0x044 read-only 0x00000000 CNTP_AIVAL_RELOAD AutoIncrValue Reload register. 0x048 read-write 0x00000000 CNTP_AIVAL_CTL AutoIncrValue Control register. 0x04C read-write 0x00000000 En Enable AutoIncrement. [0:0] Off 0 On 1 IRQ_CLR Interrupt Clear [1:1] Nop 0 Clear 1 CNTP_CFG Timer Configuration register. 0x050 read-write 0x00000000 PIDR4 Peripheral ID 4 0xFD0 read-only 0x00000004 PIDR0 Peripheral ID 0 0xFE0 read-only 0x000000B7 PIDR1 Peripheral ID 1 0xFE4 read-only 0x000000B0 PIDR2 Peripheral ID 2 0xFE8 read-only 0x0000000B PIDR3 Peripheral ID 3 0xFEC read-only 0x00000000 CIDR0 Component ID 0 0xFF0 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 read-only 0x00000005 CIDR3 Component ID 3 0xFFC read-only 0x000000B1 TIMER1 Timer 1 Timer 0x48001000 TIMER1 Timer 1 4 TIMER2 Timer 2 Timer 0x48002000 DUALTIMER Timer 2 5 TIMER3 AON Timer 3 Timer 0x48003000 TIMER3 Timer 3 27 SLOWCLK SLOWCLK AON Timer Timer 0x4802F000 0 0x10 registers S32K_TIMER S32K Timer 2 CTRL Control Register 0x000 ENABLE Enable [0:0] Disable Timer is disabled 0 Enable Timer is enabled 1 EXTIN External Input as Enable [1:1] Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 EXTCLK External Clock Enable [2:2] Disable External Clock is disabled 0 Enable External Clock is enabled 1 INTEN Interrupt Enable [3:3] Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 VALUE Current Timer Counter Value 0x004 RELOAD Counter Reload Value 0x008 INTSTATUS Timer Interrupt status register 0x00C read-only INTCLEAR Timer Interrupt clear register INTSTATUS 0x00C write-only oneToClear TIMER0_Secure Timer 0 (Secure) Timer_Secure 0x58000000 TIMER1_Secure Timer 1 (Secure) Timer_Secure 0x58001000 TIMER2_Secure Timer 2 (Secure) Timer_Secure 0x58002000 TIMER3_Secure Timer 3 (Secure) Timer_Secure 0x58003000 SLOWCLK_Secure SLOWCLK AON Timer (Secure) Timer_Secure 0x5802F000 GPIO0 1.0 General-purpose I/O 0 GPIO 0x41100000 32 read-write 0 0x3C registers GPIO0_COMBINED GPIO 0 combined 69 DATA Data Register 0x000 DATAOUT Data Output Register 0x004 OUTENSET Ouptut enable set Register 0x010 OUTENCLR Ouptut enable clear Register 0x014 ALTFUNCSET Alternate function set Register 0x018 ALTFUNCCLR Alternate function clear Register 0x01C INTENSET Interrupt enable set Register 0x020 INTENCLR Interrupt enable clear Register 0x024 INTTYPESET Interrupt type set Register 0x028 INTTYPECLR Interrupt type clear Register 0x02C INTPOLSET Polarity-level, edge interrupt configuration set Register 0x030 INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x034 INTSTATUS Interrupt Status Register 0x038 read-only INTCLEAR Interrupt CLEAR Register INTSTATUS 0x038 write-only oneToClear GPIO1 1.0 General-purpose I/O 1 GPIO 0x41101000 32 read-write GPIO1_COMBINED GPIO 1 combined 70 GPIO2 1.0 General-purpose I/O 2 GPIO 0x41102000 32 read-write GPIO2_COMBINED GPIO 2 combined 71 GPIO3 1.0 General-purpose I/O 3 GPIO 0x41103000 32 read-write GPIO3_COMBINED GPIO 3 combined 72 GPIO0_Secure General-purpose I/O 0 (Secure) GPIO_Secure 0x50100000 GPIO1_Secure General-purpose I/O 1 (Secure) GPIO_Secure 0x50101000 GPIO2_Secure General-purpose I/O 2 (Secure) GPIO_Secure 0x50102000 GPIO3_Secure General-purpose I/O 3 (Secure) GPIO_Secure 0x50103000 DMA0 1.0 Direct Memory Access 0 (PL081) DMA 0x41200000 32 read-write 0 0x14 registers IntStatus Interrupt Status 0x000 1 read-only IntTCStatus Interrupt Terminal Count Status 0x004 2 read-only IntTCClear Interrupt Terminal Count Clear 0x008 2 write-only DMA1 Direct Memory Access 1 DMA 0x41101000 DMA2 Direct Memory Access 2 DMA 0x41202000 DMA3 Direct Memory Access 3 DMA 0x41203000 DMA0_Secure Direct Memory Access 0 (Secure) DMA_Secure 0x51200000 DMA1_Secure Direct Memory Access 1 (Secure) DMA_Secure 0x51201000 DMA2_Secure Direct Memory Access 2 (Secure) DMA_Secure 0x51202000 DMA3_Secure Direct Memory Access 3 (Secure) DMA_Secure 0x51203000 UART0 1.0 UART 0 UART 0x49303000 32 read-write 0 0x14 registers UART0_RX UART 0 RX 33 UART0_TX UART 0 TX 34 UART0_COMBINED UART 0 Combined interrupt 43 DATA Receive and Transmit Data Value 0x000 8 STATE UART Status Register 0x004 RXOV RX Buffer Overun (write 1 to clear) [3:3] oneToClear TXOV TX Buffer Overun (write 1 to clear) [2:2] oneToClear RXBF RX Buffer Full [1:1] read-only TXBF TX Buffer Full [0:0] read-only CTRL UART Control Register 0x008 HSTX High Speed Test Mode for TX only [6:6] Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable [5:5] Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable [4:4] Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable [3:3] Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable [2:2] Disable Disabled 0 Enable Enabled 1 RXEN RX Enable [1:1] Disable Disabled 0 Enable Enabled 1 TXEN TX Enable [0:0] Disable Disabled 0 Enable Enabled 1 INTSTATUS UART Interrupt Status Register 0x00C read-only RXOV RX Overrun Interrupt [3:3] TXOV TX Overrun Interrupt [2:2] RXINT RX Interrupt [1:1] TXINT TX Interrupt [0:0] INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0x00C write-only RXOV RX Overrun Interrupt [3:3] oneToClear TXOV TX Overrun Interrupt [2:2] oneToClear RXINT RX Interrupt [1:1] oneToClear TXINT TX Interrupt [0:0] oneToClear BAUDDIV Baudrate Divider 0x010 UART1 UART 1 UART 0x49304000 UART1_RX UART 1 RX 35 UART1_TX UART 1 TX 36 UART1_COMBINED UART 1 Combined interrupt 44 UART2 UART 2 UART 0x49305000 UART2_RX UART 2 RX 37 UART2_TX UART 2 TX 38 UART2_COMBINED UART 2 Combined interrupt 45 UART3 UART 3 UART 0x49306000 UART3_RX UART 3 RX 39 UART3_TX UART 3 TX 40 UART3_COMBINED UART 3 Combined interrupt 46 UART4 UART 4 UART 0x49307000 UART4_RX UART 4 RX 41 UART4_TX UART 4 TX 42 UART4_COMBINED UART 4 Combined interrupt 47 UART5 UART 5 UART 0x49308000 UART5_RX UART 5 RX 125 UART5_TX UART 5 TX 126 UART5_COMBINED UART 5 Combined interrupt 127 UART_OVERFLOW UART 0 to 5 combined overflow/overrun 48 UART0_Secure UART 0 (Secure) UART_Secure 0x59303000 UART1_Secure UART 1 (Secure) UART_Secure 0x59304000 UART2_Secure UART 2 (Secure) UART_Secure 0x59305000 UART3_Secure UART 3 (Secure) UART_Secure 0x59306000 UART4_Secure UART 4 (Secure) UART_Secure 0x59307000 UART5_Secure UART 5 (Secure) UART_Secure 0x59308000 I2C0 1.0 I2C Touch I2C 0x49200000 32 read-write 0 12 registers TouchScreen 51 CONTROLS Control Set 0x000 write-only SDA Serial data line [1:1] SCL Serial clock line [0:0] CONTROL Control Status CONTROLS 0x000 read-only SDA Serial data line [1:1] SCL Serial clock line [0:0] CONTROLC Control Clear 0x004 SDA Serial data line [1:1] SCL Serial clock line [0:0] I2C1 I2C Audio I2C 0x49201000 I2C0_Secure I2C Touch (Secure) I2C_Secure 0x59200000 I2C1_Secure I2C Audio (Secure) I2C_Secure 0x59201000 SSP0 1.0 SPI 0 SPI 0x49203000 32 read-write 0 0x90 registers SPI0 SPI 0 54 CR0 Control register 0 0x000 SCR Serial clock rate [15:8] SPH SSPCLKOUT phase [7:7] SPO SSPCLKOUT polarity [6:6] FRF Frame format [5:4] Motorola Motorola SPI frame format 0 TI TI synchronous serial frame format 1 NM National Microwire frame format 2 DSS Data Size Select [3:0] 4bit 3 5bit 4 6bit 5 7bit 6 8bit 7 9bit 8 10bit 9 11bit 10 12bit 11 13bit 12 14bit 13 15bit 14 16bit 15 CR1 Control register 1 0x004 SOD Slave-mode output disable [3:3] Enable SSP can drive the SSPTXD output in slave mode 0 Disable SSP must not drive the SSPTXD output in slave mode 1 MS Master or slave mode select [2:2] Master Device configured as master, default 0 Slave Device configured as slave 1 SSE Synchronous serial port enable [1:1] Disabled SSP operation disabled 0 Enabled SSP operation enabled 1 LBM Loop back mode [0:0] Normal Normal serial port operation enabled 0 Loopback Output of transmit serial shifter is connected to input of receive serial shifter internally 1 DR Data register 0x008 Data Transmit/Receive FIFO [15:0] SR Status register 0x00C BSY PrimeCell SSP busy flag [4:4] Idle SSP is idle 0 Busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 RFF Receive FIFO full [3:3] NF Receive FIFO is not full 0 F Receive FIFO is full 1 RNE Receive FIFO not empty [2:2] E Receive FIFO is empty 0 NE Receive FIFO is not empty 1 TNF Transmit FIFO not full [1:1] F Receive FIFO is full 0 NF Receive FIFO is not full 1 TFE Transmit FIFO empty [0:0] NE Receive FIFO is not empty 0 E Receive FIFO is empty 1 CPSR Clock prescale register 0x010 CPSDVSR Clock prescale divisor [7:0] IMSC Interrupt mask set or clear register 0x014 TXIM Transmit FIFO interrupt mask [3:3] Masked Transmit FIFO half empty or less condition interrupt is masked 0 NotMasked Transmit FIFO half empty or less condition interrupt is not masked 1 RXIM Receive FIFO interrupt mask [2:2] Masked Receive FIFO half full or less condition interrupt is masked 0 NotMasked Receive FIFO half full or less condition interrupt is not masked 1 RTIM Receive timeout interrupt mask [1:1] Masked Receive FIFO not empty or no read prior to timeout period interrupt is masked 0 NotMasked Receive FIFO not empty or no read prior to timeout period interrupt is not masked 1 RORIM Receive overrun interrupt mask [0:0] Masked Receive FIFO written to while full condition interrupt is masked 0 NotMasked Receive FIFO written to while full condition interrupt is not masked 1 RIS Raw interrupt status register 0x018 TXRIS transmit FIFO raw interrupt state [3:3] RXRIS receive FIFO raw interrupt state [2:2] RTRIS receive timeout raw interrupt state [1:1] RORRIS receive over run raw interrupt state [0:0] MIS Masked interrupt status register 0x01C TXMIS transmit FIFO masked interrupt state [3:3] RXMIS receive FIFO masked interrupt state [2:2] RTMIS receive timeout masked interrupt state [1:1] RORMIS receive over run masked interrupt state [0:0] ICR Interrupt clear register 0x020 RTIC Clears the SSPRTINTR interrupt [1:1] RORIC Clears the SSPRORINTR interrupt [0:0] DMACR DMA control register 0x024 TXDMAE Transmit DMA Enable [1:1] RXDMAE Receive DMA Enable [0:0] TCR Test control register 0x080 0x0 TESTFIFO Test FIFO enable [1:1] Disabled Normal operation 0 Enabled When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO. 1 ITEN Integration test enable [0:0] Disabled Normal mode 0 Enabled The PrimeCell SSP is placed in integration test mode. 1 ITIP Integration test input register 0x084 0x00 TXDMACLR Value to be driven on the intra-chip input [4:4] RXDDMACLR Value to be driven on the intra-chip input [3:3] CLKIN Return the value of CLKIN primary input [2:2] FSSIN Return the value of FSSIN primary input [1:1] RXD Return the value of RXD primary input [0:0] ITOP Integration test output register 0x088 0x0000 TXDMASREQ Value on the TXDMASREQ line [13:13] TXDMABREQ Value on the TXDMABREQ line [12:12] RXDMASREQ Value on the TXDMASREQ line [11:11] RXDMABREQ Value on the TXDMABREQ line [10:10] INTR Value on the INTR line [9:9] TXINTR Value on the TXINTR line [8:8] RXINTR Value on the RXINTR line [7:7] RTINTR Value on the RTINTR line [6:6] RORINTR Value on the RORINTR line [5:5] OE Value on the OE line [4:4] CTLOE Value on the OE line [3:3] CLKOUT Value on the CLKOUT line [2:2] FSSOUT Value on the FSSOUT line [1:1] TXD Value on the TXD line [0:0] TDR Test data register 0x08C 0x0000 DATA When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO [15:0] SSP1 SPI 1 SPI 0x49204000 SPI1 SPI 1 55 SSP2 SPI 2 SPI 0x49202000 SPI2 SPI 2 53 SSP0_Secure SPI 0 (Secure) SPI_Secure 0x59203000 SSP1_Secure SPI 1 (Secure) SPI_Secure 0x59204000 SSP2_Secure SPI 2 (Secure) SPI_Secure 0x59202000 WATCHDOG Non-secure Watchdog Timer WATCHDOG 0x48040000 0 0x1FD0 registers NONSEC_WATCHDOG_RST_REQ Non-Secure Watchdog reset Request 0 NONSEC_WATCHDOG_IRQ Non-Secure Watchdog Interrupt 1 WCS Watchdog control and Status. 0x000 read-write 0x00000000 WOR Watchdog Offset Register. 0x008 read-write 0x00000000 WCV_LOW Watchdog Compare Value Lower Word. 0x010 read-write 0x00000000 WCV_HIGH Watchdog Compare Value Higher Word. 0x014 read-write 0x00000000 CNT_W_IIDR Control Frame Watchdog Interface Identification Register. 0xFCC read-only 0x0000143B WRR Watchdog Refresh Register. 0x1000 write-only 0x00000000 REF_W_IIDR Refresh Frame Watchdog Interface Identification Register. 0x1FCC read-only 0x0000143B WATCHDOG_Secure Watchdog (Secure) WATCHDOG_Secure 0x58040000 SLOWCLKWATCHDOG SLOWCLK Watchdog (Secure) WATCHDOG_Secure 0x5802E000 FPGAIO FPGA System Control I/O FPGAIO 0x49302000 0 0x100 registers LED LED Connections 0x000 32 0x0 LED0 [0:0] Off LED is off 0 On LED is on 1 LED1 [1:1] Off LED is off 0 On LED is on 1 LED2 [2:2] Off LED is off 0 On LED is on 1 LED3 [3:3] Off LED is off 0 On LED is on 1 LED4 [4:4] Off LED is off 0 On LED is on 1 LED5 [5:5] Off LED is off 0 On LED is on 1 LED6 [6:6] Off LED is off 0 On LED is on 1 LED7 [7:7] Off LED is off 0 On LED is on 1 LED8 [8:8] Off LED is off 0 On LED is on 1 LED9 [9:9] Off LED is off 0 On LED is on 1 BUTTON Button Connections 0x008 32 0x0 BUTTON0 [0:0] Off BUTTON is off 0 On BUTTON is on 1 BUTTON1 [1:1] Off BUTTON is off 0 On BUTTON is on 1 CLK1HZ 1Hz Up Counter 0x010 32 read-only 0x0 CLK100HZ 100Hz Up Counter 0x014 32 read-only 0x0 COUNTER Cycle up counter 0x018 32 read-write 0x0 PRESCALER Reload value for prescaler counter 0x01C 32 read-write 0x0 PSCNTR Prescale Counter 0x020 32 read-write 0x0 SWITCHES User Switches 0x28 32 read-only SW0 [0:0] Off Switch is Off 0 On Switch is On 1 SW1 [1:1] Off Switch is Off 0 On Switch is On 1 SW2 [2:2] Off Switch is Off 0 On Switch is On 1 SW3 [3:3] Off Switch is Off 0 On Switch is On 1 SW4 [4:4] Off Switch is Off 0 On Switch is On 1 SW5 [5:5] Off Switch is Off 0 On Switch is On 1 SW6 [6:6] Off Switch is Off 0 On Switch is On 1 SW7 [7:7] Off Switch is Off 0 On Switch is On 1 MISC Misc. Control 0x04C 32 read-write 0x0 SHIELD1_SPI_nCS [9:9] SHIELD0_SPI_nCS [8:8] ADC_SPI_nCS [7:7] CLCD_BL_CTRL [6:6] CLCD_RD [5:5] CLCD_RS [4:4] CLCD_RESET [3:3] SPI_nSS [1:1] CLCD_CS [0:0] FPGAIO_Secure FPGA System Control I/O (Secure) FPGAIO_Secure 0x59302000 SCC Serial Communication Controller SCC 0x49300000 0 0x1000 registers CFG_REG0 0x000 32 read-write 0x0 REMAP 1 = REMAP Block RAM to ZBT [0:0] CFG_REG1 0x004 32 read-write 0x0 MCC_LED7 MCC LEDs: 0 = OFF 1 = ON [7:7] Off LED is off 0 On LED is on 1 MCC_LED6 MCC LEDs: 0 = OFF 1 = ON [6:6] Off LED is off 0 On LED is on 1 MCC_LED5 MCC LEDs: 0 = OFF 1 = ON [5:5] Off LED is off 0 On LED is on 1 MCC_LED4 MCC LEDs: 0 = OFF 1 = ON [4:4] Off LED is off 0 On LED is on 1 MCC_LED3 MCC LEDs: 0 = OFF 1 = ON [3:3] Off LED is off 0 On LED is on 1 MCC_LED2 MCC LEDs: 0 = OFF 1 = ON [2:2] Off LED is off 0 On LED is on 1 MCC_LED1 MCC LEDs: 0 = OFF 1 = ON [1:1] Off LED is off 0 On LED is on 1 MCC_LED0 MCC LEDs: 0 = OFF 1 = ON [0:0] Off LED is off 0 On LED is on 1 CFG_REG2 0x008 32 read-only 0x0 CFG_REG3 0x00C 32 read-only 0x0 MCC_SWITCH7 MCC SWITCHES: 0 = OFF 1 = ON [7:7] Off Switch is off 0 On Switch is on 1 MCC_SWITCH6 MCC SWITCHES: 0 = OFF 1 = ON [6:6] Off Switch is off 0 On Switch is on 1 MCC_SWITCH5 MCC SWITCHES: 0 = OFF 1 = ON [5:5] Off Switch is off 0 On Switch is on 1 MCC_SWITCH4 MCC SWITCHES: 0 = OFF 1 = ON [4:4] Off Switch is off 0 On Switch is on 1 MCC_SWITCH3 MCC SWITCHES: 0 = OFF 1 = ON [3:3] Off Switch is off 0 On Switch is on 1 MCC_SWITCH2 MCC SWITCHES: 0 = OFF 1 = ON [2:2] Off Switch is off 0 On Switch is on 1 MCC_SWITCH1 MCC SWITCHES: 0 = OFF 1 = ON [1:1] Off Switch is off 0 On Switch is on 1 MCC_SWITCH0 MCC SWITCHES: 0 = OFF 1 = ON [0:0] Off Switch is off 0 On Switch is on 1 CFG_REG4 0x010 32 read-only 0x0 BRDREV Board Revision [3:0] CFG_REG5 0x014 32 read-write 0x0 DEBUG Debug: 0 = Serial Wire Debug 1 = JTAG [5:5] CFG_REG6 0x018 32 read-only 0x0 CFG_REG7 0x01C 32 read-only 0x0 SYS_CFGDATA_RTN 0x0A0 32 read-write 0x0 SYS_CFGDATA_OUT 0x0A4 32 read-write 0x0 SYS_CFGCTRL 0x0A8 32 read-write 0x0 START Start: generates interrupt on write to this bit [31:31] RW_ACCESS Read/Write Access [30:30] RFUNCVAL Function Value [25:20] DEVICE Device (value of 0/1/2 for supported clocks [11:0] SYS_CFGSTAT 0x0AC 32 read-write 0x0 ERROR Error Flag [1:1] COMPLETE Complete Flag [0:0] DLL DLL Lock Register 0x100 32 read-write 0x0 LOCKED_MASKED Error Flag [31:24] LOCK_UNLOCK Complete Flag [23:16] LOCKED Complete Flag [0:0] AID 0xFF8 32 read-only 0x0 FPGA_BUILD FPGA Build Number [31:24] MPS3_REV V2M-MPS3 target Board Revision (A=0,B=1,C=2) [23:20] NUM_CFG_REG Number of SCC configuration register [7:0] ID 0xFFC 32 read-only 0x0 IMPLEMENTER_ID Implementer ID: 0x41 = ARM [31:24] APP_NOTE_VAR Application note IP variant number [23:20] IP_ARCH IP Architecture: 0x4 = AHB [19:16] PRI_NUM Primary Part Number: 521 = AN521 [15:4] APP_REV Application note IP revision number [3:0] SCC_Secure Serial Communication Controller SCC_Secure 0x59300000 SACRB Secure Access Configuration Register Block 0x50080000 0 0x1000 registers PPC PPC Combined 10 MSC MSC Combined 11 BRG Bridge Buffer Error 12 SPCSECTRL Secure Privilege Controller Secure Configuration Control register 0x0 32 read-write 0x0 BUSWAIT Bus Access wait control after reset 0x4 32 read-write SECRESPCFG Security Violation Response Configuration register 0x10 32 read-write 0x0 NSCCFG Non Secure Callable Configuration for IDAU 0x14 32 read-write 0x0 SECMPCINTSTATUS Secure MPC Interrupt Status 0x1C 32 read-only 0x0 SECPPCINTSTAT Secure PPC Interrupt Status 0x20 32 read-only 0x0 SECPPCINTCLR Secure PPC Interrupt Clear 0x24 32 write-only 0x0 SECPPCINTEN Secure PPC Interrupt Enable 0x28 32 read-write 0x0 SECMSCINTSTAT Secure MSC Interrupt Status 0x30 32 read-only 0x0 SECMSCINTCLR Secure MSC Interrupt Clear 0x34 32 read-write 0x0 SECMSCINTEN Secure MSC Interrupt Enable 0x38 32 read-write 0x0 BRGINTSTAT Bridge Buffer Error Interrupt Status 0x40 32 read-only 0x0 BRGINTCLR Bridge Buffer Error Interrupt Clear 0x44 32 write-only 0x0 BRGINTEN Bridge Buffer Error Interrupt Enable 0x48 32 read-write 0x0 AHBNSPPC0 Non-Secure Access AHB slave Peripheral Protection Control 0 0x50 32 read-write 0x0 AHBNSPPCEXP0 Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control 0x60 32 read-write 0x0 AHBNSPPCEXP1 Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control 0x64 32 read-write 0x0 AHBNSPPCEXP2 Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control 0x68 32 read-write 0x0 AHBNSPPCEXP3 Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control 0x6C 32 read-write 0x0 APBNSPPC0 Non-Secure Access APB slave Peripheral Protection Control 0 0x70 32 read-write 0x0 APBNSPPC1 Non-Secure Access APB slave Peripheral Protection Control 1 0x74 32 read-write 0x0 APBNSPPCEXP0 Expansion 0 Non_Secure Access APB slave Peripheral Protection Control 0x80 32 read-write 0x0 APBNSPPCEXP1 Expansion 1 Non_Secure Access APB slave Peripheral Protection Control 0x84 32 read-write 0x0 APBNSPPCEXP2 Expansion 2 Non_Secure Access APB slave Peripheral Protection Control 0x88 32 read-write 0x0 APBNSPPCEXP3 Expansion 3 Non_Secure Access APB slave Peripheral Protection Control 0x8C 32 read-write 0x0 AHBSPPPC0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0 0x90 32 read-only 0x0 AHBSPPPCEXP0 Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write 0x0 AHBSPPPCEXP1 Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write 0x0 AHBSPPPCEXP2 Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write 0x0 AHBSPPPCEXP3 Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write 0x0 APBSPPPC0 Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write 0x0 APBSPPPC1 Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write 0x0 APBSPPPCEXP0 Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write 0x0 APBSPPPCEXP1 Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write 0x0 APBSPPPCEXP2 Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write 0x0 APBSPPPCEXP3 Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write 0x0 NSMSCEXP Expansion MSC Non-Secure Configuration 0xD0 32 read-only 0x0 PID4 Peripheral ID 4 0xFD0 32 read-only 0x00000004 PID0 Peripheral ID 0 0xFE0 32 read-only 0x00000052 PID1 Peripheral ID 1 0xFE4 32 read-only 0x000000B8 PID2 Peripheral ID 2 0xFE8 32 read-only 0x0000000B PID3 Peripheral ID 3 0xFEC 32 read-only 0x0 CIDR0 Component ID 0 0xFF0 32 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 32 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 32 read-only 0x00000005 CIDR3 Component ID 3 0xFFC 32 read-only 0x000000B1 NSACRB Non-secure Access Configuration Register Block 0x40080000 0 0x1000 registers AHBNSPPPC0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0 0x90 32 read-write 0x0 AHBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write 0x0 AHBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write 0x0 AHBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write 0x0 AHBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write 0x0 APBNSPPPC0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write 0x0 APBNSPPPC1 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write 0x0 APBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write 0x0 APBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write 0x0 APBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write 0x0 APBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write 0x0 PIDR4 Peripheral ID 4 0xFD0 32 read-only 0x0 PIDR0 Peripheral ID 0 0xFE0 32 read-only 0x00000053 PIDR1 Peripheral ID 1 0xFE4 32 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 32 read-only 0x0000000B PIDR3 Peripheral ID 3 0xFEC 32 read-only 0x0 CIDR0 Component ID 0 0xFF0 32 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 32 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 32 read-only 0x00000005 CIDR3 Component ID 3 0xFFC 32 read-only 0x000000B1 ISRAM0MPC ISRAM 0 Memory Protection Controller ISRAM_MPC 0x50083000 0 0x1000 registers MPC MPC Combined 9 CTRL MPC Control register 0x00 32 read-write 0x0 CFG_SEC_RESP Security error response configuration 4 1 RAZ_WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 DATA_IF_GATING_REQ Data interface gating request 6 1 DATA_IF_GATING_ACK Data interface gating acknowledge (RO) 7 1 read-only AUTO_INCREMENT Auto-increment 8 1 SEC_LOCKDOWN Security lockdown 31 1 BLK_MAX Maximum value of block based index register 0x10 32 read-only BLK_SIZE Block size 0 4 IN_PROGRESS Initialization in progress 31 1 BLK_CFG Block Configuration 0x14 32 read-only BLK_IDX Index value for accessing block based look up table 0x18 32 read-write 0x0 BLK_LUT Block based gating Look Up Table 0x1C 32 read-write INT_STAT Interrupt state 0x20 32 read-only 0x0 mpc_irq mpc_irq triggered 0 1 INT_CLEAR Interrupt clear 0x24 32 write-only 0x0 mpc_irq mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write 0x0 mpc_irq mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only 0x0 INT_INFO2 Interrupt information 2 0x30 32 read-only hmaster hmaster 0 16 hnonsec hnonsec 16 1 cfg_ns cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only 0x0 mpc_irq mpc_irq set. Debug purpose only 0 1 PIDR4 Peripheral ID 4 0xFD0 32 read-only 0x00000004 jep106_c_code jep106_c_code 0 4 block_count block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only 0x0 part_number Part number 0 4 jep106_id_3_0 jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only 0x0 PIDR7 Peripheral ID 7 0xFDC 32 read-only 0x0 PIDR0 Peripheral ID 0 0xFE0 32 read-only 0x00000060 PIDR1 Peripheral ID 1 0xFE4 32 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 32 read-only 0x0000000B part_number Part number 0 4 jep106_id_3_0 jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only 0x0 customer_mod_number Customer modification number 0 4 evo_rev ECO revision number 4 4 CIDR0 Component ID 0 0xFF0 32 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 32 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 32 read-only 0x00000005 CIDR3 Component ID 3 0xFFC 32 read-only 0x000000B1 ISRAM1MPC ISRAM 1 Memory Protection Controller ISRAM_MPC 0x50084000 Ethernet SMSC LAN9220 0x41400000 0 0x100000 registers Ethernet 49 AudioI2S 0x49301000 0 0x1000 registers AudioI2S 50 CONTROL Control register 0x0 32 read-write TxEnable Enable Transfer Buffer 0 1 TxIRQEnable Enable Interrupt on Transmit Buffer 1 1 RxEnable Enable Receive Buffer 2 1 RxIRQEnable Enable Interrupt on Receive Buffer 3 1 TxBufIRQLevel Transmit Buffer IRQ Water level 8 3 RxBufIRQLevel Receive Buffer IRQ Water level 12 3 FIFOReset FIFO reset 16 1 CodecReset Audio codec reset control 17 1 STATUS Status register 0x4 32 read-only TxBuffAlert Transmit Buffer Alert (Depends on Water level) 0 1 RxBuffAlert Receive Buffer Alert (Depends on Water level) 1 1 TxBuffEmpty Transmit Buffer Empty 2 1 TxBuffFull Transmit Buffer Full 3 1 RxBuffEmpty Receive Buffer Empty 4 1 RxBuffFull Receive Buffer Full 5 1 ERROR Error status register 0x8 32 read-write TxOverrun Transmit buffer ovverrun or underrun. Set this bit to clear. 0 1 RxOverrun Receive buffer ovverrun. Set this bit to clear. 1 1 DIVIDE Clock Divide Ratio register 0xC 32 read-write LRDIV Left/Right. The default value is 0x80 0 10 TXBUF Transmit Buffer FIFO Data register 0x10 32 write-only RightChannel Right channel value 0 16 LeftChannel Left channel value 16 16 RXBUF Receive Buffer FIFO Data register 0x14 32 read-only RightChannel Right channel value 0 16 LeftChannel Left channel value 16 16 ITCR Integration Test Control register 0x300 32 read-write ITCR Integration test control bit 0 1 ITIP1 Integration Test Input register 1 0x304 32 read-write SDIN SDIN pin value 0 1 ITOP1 Integration Test Output register 1 0x308 32 read-write SDOUT SDOUT signal value 0 1 SCLK SLCK signal value 1 1 LRCK LRCK signal value 2 1 IRQOUT IRQOUT signal value 3 1 USB 0x41500000 0 0x100000 registers USB 52