8 16 16 RxDataFifo RX Data FIFO Port 0x00 32 read-only TxDataFifo TX Data FIFO Port 0x20 32 write-only RxStatusFifo RX Status FIFO Port 0x40 32 read-only RxStatusFifoPeek RX Status FIFO PEEK Port 0x44 32 read-only TxStatusFifo TX Status FIFO Port 0x48 32 read-only TxStatusFifoPeek TX Status FIFO PEEK Port 0x4C 32 read-only ID_REV ID and Revision 0x50 32 read-only 0x92200000 REV [15:0] ID [31:16] IRQ_CFG Main Interrupt Configuration 0x54 32 read-write 0x00000000 IRQ_TYPE IRQ Buffer Type [0:0] IRQ_POL IRQ Polarity [4:4] IRQ_EN IRQ Enable [8:8] IRQ_INT Master Interrupt [12:12] read-only INT_DEAS_STS Interrupt Deassertion Status [13:13] read-only INT_DEAS_CLR Interrupt Deassertion Interval Clear [14:14] read-only INT_DEAS Interrupt Deassertion Interval [31:24] INT_STS Interrupt Status Register 0x58 32 read-write 0x00000000 SW_INT Software Interrupt [31:31] TXSTOP_INT TX Stopped [25:25] RXSTOP_INT RX Stopped [24:24] RXDFH_INT RX Dropped Frame Counter Halfway [23:23] TX_IOC TX IOC Interrupt [21:21] RXD_INT RX DMA Interrupt [20:20] GPT_INT GP Timer [19:19] PHY_INT PHY [18:18] PME_INT Power Management Event Interrupt [17:17] TXSO TX Status Fifo Overflow [16:16] RWT Receive Watchdog Time-out [15:15] RXE Receiver Error [14:14] TXE Transmitter Error [13:13] TDFO TX Data FIFO Overrun Interrupt [10:10] TDFA TX Data Available Interrupt [9:9] TSFF TX Status FIFO Full Interrupt [8:8] TSFL TX Status FIFO Level Interrupt [7:7] RXDF_INT RX Dropped Frame Interrupt [6:6] RSFF RX Status FIFO Full Interrupt [4:4] RSFL RX Status FIFO Level Interrupt [3:3] GPIO2_INT [2:2] GPIO1_INT [1:1] GPIO0_INT [0:0] INT_EN Interrupt Enable Register 0x5C 32 read-write 0x00000000 SW_INT_EN Software Interrupt [31:31] TXSTOP_INT_EN TX Stopped Interrupt Enable [25:25] RXSTOP_INT_EN RX Stopped Interrupt Enable [24:24] RXDFH_INT_EN RX Dropped Frame Counter Halfway Interrupt Enable [23:23] TIOC_INT_EN TX IOC Interrupt Enable [21:21] RXD_INT RX DMA Interrupt [20:20] GPT_INT_EN GP Timer [19:19] PHY_INT_EN PHY [18:18] PME_INT_EN Power Management Event Interrupt Enable [17:17] TXSO_EN TX Status FIFO Overflow [16:16] RWT_INT_EN Receive Watchdog Time-out Interrupt [15:15] RXE_INT_EN Receiver Error Interrupt [14:14] TXE_INT_EN Transmitter Error Interrupt [13:13] TDFO_INT_EN TX Data FIFO Overrun Interrupt [10:10] TDFA_INT_EN TX Data FIFO Available Interrupt [9:9] TSFF_INT_EN TX Status FIFO Full Interrupt [8:8] TSFL_INT_EN TX Status FIFO Level Interrupt [7:7] RXDF_INT_EN RX Dropped Frame Interrupt Enable [6:6] RSFF_INT_EN RX Status FIFO Full Interrupt [4:4] RSFL_INT_EN RX Status FIFO Level Interrupt [3:3] GPIO2_INT_EN GPIO 2 Interrupt [2:2] GPIO1_INT_EN GPIO 1 Interrupt [1:1] GPIO0_INT_EN GPIO 0 Interrupt [0:0] TEST_BYTE Byte Order Test Register 0x64 32 read-only 0x87654321 FIFO_INT FIFO Level Interrupt 0x68 32 read-write 0x48000000 TDFL TX Data FIFO Level [31:24] TSFL TX Status FIFO Level [23:16] RSFL RX Status FIFO Level [7:0] RX_CFG Receive Configuration 0x6C 32 read-write 0x00000000 RX_END_ALIGN RX End Alignment [31:30] RX_DMA_CNT RX DMA Count [27:16] RX_DUMP Force RX Discard [15:15] RXDOFF RX Data Offset [12:8] TX_CFG Transmit Configuration 0x70 32 read-write 0x00000000 TXS_DUMP Force TX Status Discard [15:15] TXD_DUMP Force TX Data Discard [14:14] TXSAO TX Status Allow Overun [2:2] TX_ON Transmitter Enable [1:1] STOP_TX Stop Transmitter [0:0] HW_CFG Hardware Configuration 0x74 32 read-write 0x00050000 FPORTEND FIFO Port Endian Ordering [29:29] LE Little Endian 0 BE Big Endian 1 FSELEND Direct FIFO Access Endian Ordering [28:28] LE Little Endian 0 BE Big Endian 1 AMDIX_EN AMDIX_EN Strap state [24:24] MBO Must Be One [20:20] One 1 TX_FIF_SZ TX FIFO Size [19:16] SRST_TO Soft Reset Timeout [1:1] read-only SRST Soft Reset [0:0] RX_DP_CTL RX Datapath Control 0x78 32 read-only 0x00000000 RX_FFWD RX Data FIFO Fast Forward [31:31] RX_FIFO_INF Receive FIFO Configuration 0x7C 32 read-write 0x00000000 RXSUSED RX Status FIFO Used Space [23:16] RDFREE RX Data FIFO Free Space [15:0] TX_FIFO_INF Transmit FIFO Configuration 0x80 32 read-write 0x00001200 TXSUSED TX Status FIFO Used Space [23:16] TDFREE TX Data FIFO Free Space [15:0] PMT_CTRL Power Management Control 0x84 32 read-write 0x00000000 PM_MODE Power Management Mode [13:12] Normal 0 WakeUpOrMagicPacket 1 CanEnergyDetect 2 PHY_RST PHY Reset [10:10] WOL_EN Wake-On-Lan Enable [9:9] ED_EN Energy Detect Enable [8:8] PME_TYPE PME Buffer Type [6:6] WUPS WAKE-UP Status [5:4] NoWakeUp 0 Energy 1 WakeUpOrMagicPacket 2 Multiple 3 PME_IND PME Indication [3:3] PME_POL PME Polarity [2:2] PME_EN PME Enable [1:1] READY Device Ready [0:0] read-only GPIO_CFG General Purpose IO Configuration 0x88 32 read-write 0x00000000 LED2_EN Led Enable [30:30] LED1_EN Led Enable [29:29] LED0_EN Led Enable [28:28] GPIO2_INT_POL GPIO Interrupt Polarity [26:26] GPIO1_INT_POL GPIO Interrupt Polarity [25:25] GPIO0_INT_POL GPIO Interrupt Polarity [24:24] EEPR_EN EEPROM Enable [22:20] EEDIO_EECLK 0 GPO3_GPO4 1 GPO3_RX_DV 3 TX_EN_GPO4 5 TX_EN_RX_DV 6 TX_CLK_RX_CLK 7 GPIOBUF2 GPIO Buffer Type [18:18] GPIOBUF1 GPIO Buffer Type [17:17] GPIOBUF0 GPIO Buffer Type [16:16] GPDIR2 GPIO Direction [10:10] GPDIR1 GPIO Direction [9:9] GPDIR0 GPIO Direction [8:8] GPOD4 GPO Data [4:4] GPOD3 GPO Data [3:3] GPIOD2 GPIO Data [2:2] GPIOD1 GPIO Data [1:1] GPIOD0 GPIO Data [0:0] GPT_CFG General Purpose Timer Configuration 0x8C 32 read-write 0x0000FFFF TIMER_EN GP Timer Enable [29:29] GPT_LOAD General Purpose Timer Pre-Load [15:0] GPT_CNT General Purpose Timer Count 0x90 32 read-only 0x0000FFFF CNT Counter [15:0] WORD_SWAP WORD SWAP Register 0x98 32 read-write 0x00000000 FREE_RUN Free Run Counter 0x9C 32 read-only RX_DROP RX Dropped Frames Counter 0xA0 32 read-only 0x00000000 MAC_CSR_CMD MAC CSR Synchronizer Command 0xA4 32 read-write 0x00000000 BSY CSR Busy [31:31] RnW R/nW [30:30] Address CSR Address [7:0] MAC_CSR_DATA MAC CSR Synchronizer Data 0xA8 32 read-write 0x00000000 AFC_CFG Automatic Flow Control Configuration 0xAC 32 read-write 0x00000000 AFC_HI Automatic Flow Control High Level [23:16] AFC_LO Automatic Flow Control Low Level [15:8] BACK_DUR Backpresure duration [7:4] FCMULT Flow Control on Multicast Frame [3:3] FCBRD Flow Control on Broadcast Frame [2:2] FCADD Flow Control on Address Decode [1:1] FCANY Flow Control on Any Frame [0:0] E2P_CMD EEPROM Command 0xB0 32 read-write 0x00000000 BSY EPC Busy [31:31] CMD EPC Command [30:28] READ 0 EWDS Erase/Write Disable 1 EWEN Erase/Write Enable 2 WRITE 3 WRAL Write All 4 ERASE 5 ERAL Erase All 6 RELOAD MAC Address Reload 7 TIME_OUT EPC Time-out [9:9] MAC_LDR MAC Address Loaded [8:8] Addr EPC Address [7:0] E2P_DATA EEPROM Data 0xB4 32 read-write 0x00000000 Data EEPROM Data [7:0]