2 shapeType DIL Description 4-bit arithmetic logic unit romContent Width 11 In Label Cn pinNumber 7 And And And Inputs 3 And Inputs 3 Not NOr Inputs 3 In Label ~A0 pinNumber 2 NOr And And And Inputs 3 And Inputs 3 NOr Inputs 3 NOr In Label ~A1 pinNumber 23 Not In Label ~A2 pinNumber 21 And And And Inputs 3 And Inputs 3 NOr Inputs 3 NOr In Label ~A3 pinNumber 19 Not In Label ~B0 pinNumber 1 And And And Inputs 3 And Inputs 3 NOr Inputs 3 NOr In Label ~B1 pinNumber 22 Not In Label ~B2 pinNumber 20 In Label ~B3 pinNumber 18 In rotation Label S0 pinNumber 6 In rotation Label S1 pinNumber 5 In rotation Label S2 pinNumber 4 Not And In rotation Label S3 pinNumber 3 In Label M pinNumber 8 And And Inputs 3 XOr NOr XOr Not And And And Inputs 3 And Inputs 4 NOr Inputs 3 XOr Out Label ~G pinNumber 17 Out Label ~P pinNumber 15 And Inputs 4 Out Label ~F0 pinNumber 9 Out Label ~F1 pinNumber 10 And And Inputs 3 And Inputs 4 And Inputs 5 NOr Inputs 4 Not And XOr Out Label ~F2 pinNumber 11 And Not And Inputs 4 And Inputs 3 And NAnd Inputs 4 NAnd Inputs 5 Out Label ~F3 pinNumber 13 NOr Inputs 4 Out Label A=B pinNumber 14 Out Label Cn+4 pinNumber 16 PowerSupply In Label VCC pinNumber 24 InDefault In Label GND pinNumber 12 NAnd Not Testcase Label A (A0000) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # M=0, Cn=1 MEANS ARITHMETIC MODE # A repeat(16) 0 0 0 0 0 1 bits(4,n) X X X X bits(4,n) Testcase Label A OR B (A0001) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A OR B loop(a,16) loop(b,16) 0 0 0 1 0 1 bits(4,a) bits(4,b) bits(4,a|b) end loop end loop Testcase Label A OR !B (A0010) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A OR !B loop(a,16) loop(b,16) 0 0 1 0 0 1 bits(4,a) bits(4,b) bits(4,a|~b) end loop end loop Testcase Label minus 1 (A0011) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # MINUS 1 0 0 1 1 0 1 X X X X X X X X 1 1 1 1 Testcase Label A plus (A AND !B) (A0100) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A plus (A AND !B) #0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 loop(a,16) loop(b,16) 0 1 0 0 0 1 bits(4,a) bits(4,b) bits(4,a+(a&~b)) end loop end loop Text textFontSize 36 Description Arithmetic Tests (M=0, Cn=1) Testcase Label (A OR B) plus (A AND !B) (A0101) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A OR B) plus (A AND !B) loop(a,16) loop(b,16) 0 1 0 1 0 1 bits(4,a) bits(4,b) bits(4,(a|b)+(a&~b)) end loop end loop Testcase Label A minus B minus 1 (A0110) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A minus B minus 1 loop(a,16) loop(b,16) 0 1 1 0 0 1 bits(4,a) bits(4,b) bits(4,a-b-1) end loop end loop Testcase Label (A AND !B) minus 1 (A0111) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A AND !B) minus 1 loop(a,16) loop(b,16) 0 1 1 1 0 1 bits(4,a) bits(4,b) bits(4,(a&~b)-1) end loop end loop Testcase Label A plus (A AND B) (A1000) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A plus (A AND B) 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 loop(a,16) loop(b,16) 1 0 0 0 0 1 bits(4,a) bits(4,b) bits(4,a+(a&b)) end loop end loop Testcase Label A plus B (A1001) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 Cn+4 ~F3 ~F2 ~F1 ~F0 # A plus B loop(a,16) loop(b,16) 1 0 0 1 0 1 bits(4,a) bits(4,b) ((~((a+b)>>4))&1) bits(4,a+b) end loop end loop # A plus B plus 1 loop(a,16) loop(b,16) 1 0 0 1 0 0 bits(4,a) bits(4,b) ((~((a+b+1)>>4))&1) bits(4,a+b+1) end loop end loop Testcase Label (A OR !B) plus (A AND B) (A1010) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A OR !B) plus (A AND B) loop(a,16) loop(b,16) 1 0 1 0 0 1 bits(4,a) bits(4,b) bits(4,(a|~b)+(a&b)) end loop end loop Testcase Label (A AND B) minus 1 (A1011) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A AND B) minus 1 loop(a,16) loop(b,16) 1 0 1 1 0 1 bits(4,a) bits(4,b) bits(4,(a&b)-1) end loop end loop Testcase Label A plus A (A1100) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A plus A loop(a,16) 1 1 0 0 0 1 bits(4,a) X X X X bits(4,a+a) end loop Testcase Label (A OR B) plus A (A1101) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A OR B) plus A loop(a,16) loop(b,16) 1 1 0 1 0 1 bits(4,a) bits(4,b) bits(4,(a|b)+a) end loop end loop Testcase Label (A OR !B) plus A (A1110) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A OR !B) plus A loop(a,16) loop(b,16) 1 1 1 0 0 1 bits(4,a) bits(4,b) bits(4,(a|~b)+a) end loop end loop Testcase Label A minus 1 (A1111) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A minus 1 loop(a,16) 1 1 1 1 0 1 bits(4,a) X X X X bits(4,a-1) end loop Testcase Label !A (L0000) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # M=1, Cn=X MEANS LOGIC MODE # !A loop(a,16) 0 0 0 0 1 0 bits(4,a) X X X X bits(4,~a) end loop Testcase Label !A AND !B (L0001) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # !A AND !B loop(a,16) loop(b,16) 0 0 0 1 1 0 bits(4,a) bits(4,b) bits(4,(~a)&(~b)) end loop end loop Testcase Label !A AND B (L0010) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # !A AND B loop(a,16) loop(b,16) 0 0 1 0 1 0 bits(4,a) bits(4,b) bits(4,~a&b) end loop end loop Testcase Label logic 0 (L0011) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # MINUS 1 0 0 1 1 1 0 X X X X X X X X 0 0 0 0 Testcase Label !(A AND B) (L0100) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # !(A AND B) loop(a,16) loop(b,16) 0 1 0 0 1 0 bits(4,a) bits(4,b) bits(4,~(a&b)) end loop end loop Text textFontSize 36 Description Logic Tests (M=1) Testcase Label !B (L0101) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # !B loop(a,16) loop(b,16) 0 1 0 1 1 0 bits(4,a) bits(4,b) bits(4,~b) end loop end loop Testcase Label A XOR B (L0110) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A XOR B loop(a,16) loop(b,16) 0 1 1 0 1 0 bits(4,a) bits(4,b) bits(4,a^b) end loop end loop Testcase Label A AND !B (L0111) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # (A AND !B) loop(a,16) loop(b,16) 0 1 1 1 1 0 bits(4,a) bits(4,b) bits(4,(a&~b)) end loop end loop Testcase Label !A OR B (L1000) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # !A OR B loop(a,16) loop(b,16) 1 0 0 0 1 1 bits(4,a) bits(4,b) bits(4,~a|b) end loop end loop Testcase Label !(A XOR B) (L1001) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # !(A XOR B) loop(a,16) loop(b,16) 1 0 0 1 1 0 bits(4,a) bits(4,b) bits(4,~(a^b)) end loop end loop Testcase Label B (L1010) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # B loop(a,16) loop(b,16) 1 0 1 0 1 0 bits(4,a) bits(4,b) bits(4,b) end loop end loop Testcase Label A AND B (L1011) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A AND B loop(a,16) loop(b,16) 1 0 1 1 1 0 bits(4,a) bits(4,b) bits(4,a&b) end loop end loop Testcase Label logic 1 (L1100) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A plus A 1 1 0 0 1 0 X X X X X X X X 1 1 1 1 Testcase Label A OR !B (L1101) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A OR !B loop(a,16) loop(b,16) 1 1 0 1 1 0 bits(4,a) bits(4,b) bits(4,a|~b) end loop end loop Testcase Label A OR B (L1110) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A OR B loop(a,16) loop(b,16) 1 1 1 0 1 0 bits(4,a) bits(4,b) bits(4,a|b) end loop end loop Testcase Label A (L1111) Testdata S3 S2 S1 S0 M Cn ~A3 ~A2 ~A1 ~A0 ~B3 ~B2 ~B1 ~B0 ~F3 ~F2 ~F1 ~F0 # A loop(a,16) 1 1 1 1 1 0 bits(4,a) X X X X bits(4,a) end loop NAnd