/* * Generated by Digital. Don't modify this file! * Any changes will be lost if this file is regenerated. */ module DIG_D_FF_1bit #( parameter Default = 0 ) ( input D, input C, output Q, output \~Q ); reg state; assign Q = state; assign \~Q = ~state; always @ (posedge C) begin state <= D; end initial begin state = Default; end endmodule // flip flop part of 74779 module \74779_inc ( input DATA, input LOAD, input \~TOGGLE , input CP, output Q, output \~Q ); wire s0; wire Q_temp; wire \~Q_temp ; assign s0 = ((DATA & LOAD) | (~ LOAD & \~TOGGLE & Q_temp) | (~ LOAD & ~ \~TOGGLE & \~Q_temp )); DIG_D_FF_1bit #( .Default(0) ) DIG_D_FF_1bit_i0 ( .D( s0 ), .C( CP ), .Q( Q_temp ), .\~Q ( \~Q_temp ) ); assign Q = Q_temp; assign \~Q = \~Q_temp ; endmodule module Driver ( input in, input sel, output out ); assign out = (sel == 1'b1)? in : 1'bz; endmodule // 8-Bit Bidirectional Binary Counter with 3-STATE Outputs module \74779 ( input CP, input S0, input S1, input \~OE , inout \I/O0 , inout \I/O1 , inout \I/O2 , inout \I/O3 , inout \I/O4 , inout \I/O5 , inout \I/O6 , inout \I/O7 , input \~CET , input VCC, input GND, output \~TC ); wire s2; wire s3; wire s4; wire s5; wire s6; wire s7; wire s8; wire s9; wire s10; wire s11; wire s12; wire s13; wire s14; wire s15; wire s16; wire s17; wire s18; wire s19; wire s20; wire s21; wire s22; wire s23; wire s24; wire s25; wire s26; wire s27; wire s28; wire s29; wire s30; wire s31; wire s32; wire s33; wire s34; wire s35; wire s36; wire s37; wire s38; wire s39; wire s40; assign s11 = ~ S0; assign s12 = ~ S1; assign s16 = ~ \~OE ; assign s2 = ~ \~CET ; assign s3 = ~ s2; assign s13 = (s11 & s12); assign s14 = (~ s12 & s11); assign s15 = (s12 & ~ s11); \74779_inc \74779_inc_i0 ( .DATA( \I/O0 ), .LOAD( s13 ), .\~TOGGLE ( s3 ), .CP( CP ), .Q( s33 ), .\~Q ( s32 ) ); assign s4 = ~ ((s2 & s33 & s14) | (s32 & s15 & s2)); assign s17 = ~ s32; Driver Driver_i1 ( .in( s17 ), .sel( s16 ), .out( \I/O0 ) ); \74779_inc \74779_inc_i2 ( .DATA( \I/O1 ), .LOAD( s13 ), .\~TOGGLE ( s4 ), .CP( CP ), .Q( s34 ), .\~Q ( s31 ) ); assign s5 = ~ ((s2 & s34 & s33 & s14) | (s31 & s32 & s15 & s2)); assign s18 = ~ s31; Driver Driver_i3 ( .in( s18 ), .sel( s16 ), .out( \I/O1 ) ); \74779_inc \74779_inc_i4 ( .DATA( \I/O2 ), .LOAD( s13 ), .\~TOGGLE ( s5 ), .CP( CP ), .Q( s35 ), .\~Q ( s30 ) ); assign s6 = ~ ((s2 & s35 & s34 & s33 & s14) | (s30 & s31 & s32 & s15 & s2)); assign s19 = ~ s30; Driver Driver_i5 ( .in( s19 ), .sel( s16 ), .out( \I/O2 ) ); \74779_inc \74779_inc_i6 ( .DATA( \I/O3 ), .LOAD( s13 ), .\~TOGGLE ( s6 ), .CP( CP ), .Q( s36 ), .\~Q ( s29 ) ); assign s7 = ~ (((s2 & s36 & s35) & (s34 & s33 & s14)) | ((s29 & s30 & s31) & (s32 & s15 & s2))); assign s20 = ~ s29; Driver Driver_i7 ( .in( s20 ), .sel( s16 ), .out( \I/O3 ) ); \74779_inc \74779_inc_i8 ( .DATA( \I/O4 ), .LOAD( s13 ), .\~TOGGLE ( s7 ), .CP( CP ), .Q( s37 ), .\~Q ( s28 ) ); assign s8 = ~ (((s2 & s37 & s36) & (s35 & s34 & s33 & s14)) | ((s28 & s29 & s30) & (s31 & s32 & s15 & s2))); assign s21 = ~ s28; Driver Driver_i9 ( .in( s21 ), .sel( s16 ), .out( \I/O4 ) ); \74779_inc \74779_inc_i10 ( .DATA( \I/O5 ), .LOAD( s13 ), .\~TOGGLE ( s8 ), .CP( CP ), .Q( s38 ), .\~Q ( s25 ) ); assign s9 = ~ (((s2 & s38 & s37 & s36) & (s35 & s34 & s33 & s14)) | ((s25 & s28 & s29 & s30) & (s31 & s32 & s15 & s2))); assign s22 = ~ s25; Driver Driver_i11 ( .in( s22 ), .sel( s16 ), .out( \I/O5 ) ); \74779_inc \74779_inc_i12 ( .DATA( \I/O6 ), .LOAD( s13 ), .\~TOGGLE ( s9 ), .CP( CP ), .Q( s39 ), .\~Q ( s26 ) ); assign s10 = ~ (((s2 & s39 & s38 & s37) & (s36 & s35 & s34 & s33 & s14)) | ((s26 & s25 & s28 & s29) & (s30 & s31 & s32 & s15 & s2))); assign s23 = ~ s26; Driver Driver_i13 ( .in( s23 ), .sel( s16 ), .out( \I/O6 ) ); \74779_inc \74779_inc_i14 ( .DATA( \I/O7 ), .LOAD( s13 ), .\~TOGGLE ( s10 ), .CP( CP ), .Q( s40 ), .\~Q ( s27 ) ); assign s24 = ~ s27; assign \~TC = ~ (((s40 & s39 & s38 & s37 & s36) & (s35 & s34 & s33 & s14 & s2)) | ((s27 & s26 & s25 & s28 & s29) & (s30 & s31 & s32 & s15 & s2))); Driver Driver_i15 ( .in( s24 ), .sel( s16 ), .out( \I/O7 ) ); endmodule