[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 2048
device_width = 4
BL = 8

[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 243
tRFC4 = 243
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 5
tRRD_L = 5
tWTR_S = 7
tWTR_L = 7
tFAW = 26
tWR = 15
tWR2 = 15
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1

[power]
VDD = 1.35
IDD0 = 62
IPP0 = 0.0
IDD2P = 18
IDD2N = 35
IDD3P = 41
IDD3N = 41
IDD4W = 133
IDD4R = 164
IDD5AB = 242
IDD6x = 20

[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32

[other]
epoch_period = 934579
output_level = 1