[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 1024
device_width = 16
BL = 8

[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 328
tRFC2 = 328
tRFC4 = 328
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 7
tWTR_L = 7
tFAW = 33
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 338
tXP = 6
tRTRS = 1

[power]
VDD = 1.35
IDD0 = 69
IPP0 = 0.0
IDD2P = 11
IDD2N = 38
IDD3P = 38
IDD3N = 53
IDD4W = 195
IDD4R = 195
IDD5AB = 275
IDD6x = 24

[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32

[other]
epoch_period = 934579
output_level = 1