[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8

[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 16
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1

[power]
VDD = 1.2
IDD0 = 40
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 30
IDD3N = 35
IDD4W = 95
IDD4R = 100
IDD5AB = 250
IDD6x = 30

[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32

[other]
epoch_period = 1063829
output_level = 1