[dram_structure]
protocol = HBM
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 64
device_width = 128
BL = 4
num_dies = 4

[timing]
tCK = 2
CL = 7
CWL = 2
tRCDRD = 7
tRCDWR = 7
tRP = 7
tRAS = 17
tRFC = 130
tREFI = 1950
tREFIb = 64
tRPRE = 1
tWPRE = 1
tRRD_S = 2
tRRD_L = 3
tWTR_S = 3
tWTR_L = 4
tFAW = 15
tWR = 8
tCCD_S = 1
tCCD_L = 1
tXS = 134
tCKE = 4
tCKSRE = 5
tXP = 4
tRTP_L = 3
tRTP_S = 2

[power]
VDD = 1.2
IDD0 = 65
IDD2P = 28
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 440
IDD4R = 360
IDD5AB = 250
IDD6x = 31

[system]
channel_size = 512
channels = 8
bus_width = 128
address_mapping = rorabgbachco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = False

[other]
epoch_period = 500000
output_level = 1