[dram_structure]
protocol = HBM
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 64
device_width = 128
BL = 4
num_dies = 4

[timing]
tCK = 1
CL = 14
CWL = 4
tRCDRD = 14
tRCDWR = 14
tRP = 14
tRAS = 34
tRFC = 260
tREFI = 3900
tREFIb = 128
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 6
tWTR_L = 8
tFAW = 30
tWR = 16
tCCD_S = 1
tCCD_L = 2
tXS = 268
tCKE = 8
tCKSRE = 10
tXP = 8
tRTP_L = 6
tRTP_S = 4

[power]
VDD = 1.2
IDD0 = 65
IDD2P = 28
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 500
IDD4R = 390
IDD5AB = 250
IDD6x = 31

[system]
channel_size = 512
channels = 8
bus_width = 128
address_mapping = rorabgbachco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = False

[other]
epoch_period = 1000000
output_level = 1