[dram_structure]
protocol = LPDDR3
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 32
BL = 8

[timing]
tCK = 1.07
AL = 0
CL = 14
CWL = 11
tRCD = 17
tRP = 17
tRAS = 40
tRFC = 196
tRFCb = 85
tRFC2 = 196
tRFC4 = 196
REFI = 3645
tREFIb = 456
tRPRE = 1
tWPRE = 1
tRRD_S = 10
tRRD_L = 10
tWTR_S = 7
tWTR_L = 7
tFAW = 47
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 7
tCKESR = 15
tXS = 206
tXP = 7
tRTRS = 1

[power]
VDD = 1.2
IDD0 = 41.5
IPP0 = 0
IDD2P = 1.3
IDD2N = 21.5
IDD3P = 7
IDD3N = 22.0
IDD4W = 285
IDD4R = 290
IDD5AB = 150
IDD6x = 22.0

[system]
channel_size = 2048
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32

[other]
epoch_period = 934579
output_level = 1