Nordic Semiconductor Nordic nrf9160 nrf91 1 nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n \n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n \n 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n 8 32 32 0x00000000 0xFFFFFFFF CM33 r0p4 little 1 1 3 0 69 0 system_nrf9160 NRF_ 240 FICR_S Factory Information Configuration Registers 0x00FF0000 FICR 0 0x1000 registers FICR 0x20 INFO Device info FICR_INFO read-write 0x200 0x2 0x4 DEVICEID[%s] Description collection: Device identifier 0x004 read-only 0xFFFFFFFF DEVICEID 64 bit unique device identifier 0 31 PART Part code 0x00C read-only 0x00009160 PART Part code 0 31 N9160 nRF9160 0x9160 VARIANT Part Variant, Hardware version and Production configuration 0x010 read-only 0x0FFFFFFF VARIANT Part Variant, Hardware version and Production configuration, encoded as ASCII 0 31 AAAA AAAA 0x41414141 AAA0 AAA0 0x41414130 PACKAGE Package option 0x014 read-only 0x00002000 PACKAGE Package option 0 31 CC CCxx - 236 ball wlCSP 0x2000 RAM RAM variant 0x018 read-only 0x00000100 RAM RAM variant 0 31 K256 256 kByte RAM 0x100 Unspecified Unspecified 0xFFFFFFFF FLASH Flash variant 0x01C read-only 0x00000400 FLASH Flash variant 0 31 K1024 1 MByte FLASH 0x400 CODEPAGESIZE Code memory page size 0x020 read-only 0x00001000 CODEPAGESIZE Code memory page size 0 31 CODESIZE Code memory size 0x024 read-only 0x00000100 CODESIZE Code memory size in number of pages 0 31 DEVICETYPE Device type 0x028 read-only 0xFFFFFFFF DEVICETYPE Device type 0 31 Die Device is an physical DIE 0x0000000 FPGA Device is an FPGA 0xFFFFFFFF 256 0x008 TRIMCNF[%s] Unspecified FICR_TRIMCNF read-write 0x300 ADDR Description cluster: Address 0x000 read-only 0xFFFFFFFF Address Address 0 31 DATA Description cluster: Data 0x004 read-only 0xFFFFFFFF Data Data 0 31 TRNG90B NIST800-90B RNG calibration data FICR_TRNG90B read-write 0xC00 BYTES Amount of bytes for the required entropy bits 0x000 read-only 0xFFFFFFFF BYTES Amount of bytes for the required entropy bits 0 31 RCCUTOFF Repetition counter cutoff 0x004 read-only 0xFFFFFFFF RCCUTOFF Repetition counter cutoff 0 31 APCUTOFF Adaptive proportion cutoff 0x008 read-only 0xFFFFFFFF APCUTOFF Adaptive proportion cutoff 0 31 STARTUP Amount of bytes for the startup tests 0x00C read-only 0x00000210 STARTUP Amount of bytes for the startup tests 0 31 ROSC1 Sample count for ring oscillator 1 0x010 read-only 0xFFFFFFFF ROSC1 Sample count for ring oscillator 1 0 31 ROSC2 Sample count for ring oscillator 2 0x014 read-only 0xFFFFFFFF ROSC2 Sample count for ring oscillator 2 0 31 ROSC3 Sample count for ring oscillator 3 0x018 read-only 0xFFFFFFFF ROSC3 Sample count for ring oscillator 3 0 31 ROSC4 Sample count for ring oscillator 4 0x01C read-only 0xFFFFFFFF ROSC4 Sample count for ring oscillator 4 0 31 UICR_S User information configuration registers User information configuration registers 0x00FF8000 UICR 0 0x1000 registers UICR 0x20 APPROTECT Access port protection 0x000 read-write 0x00000000 PALL Blocks debugger read/write access to all CPU registers and memory mapped addresses 0 31 Unprotected Unprotected 0xFFFFFFFF Protected Protected 0x00000000 XOSC32M Oscillator control 0x014 read-write 0xFFFFFFCF CTRL Pierce current DAC control signals 0 5 HFXOSRC HFXO clock source selection 0x01C read-write 0xFFFFFFFF HFXOSRC HFXO clock source selection 0 0 XTAL 32 MHz crystal oscillator 1 TCXO 32 MHz temperature compensated crystal oscillator (TCXO) 0 HFXOCNT HFXO startup counter 0x020 read-write 0xFFFFFFFF HFXOCNT HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us 0 7 MinDebounceTime Min debounce time = (0*64 us + 0.5 us) 0 MaxDebounceTime Max debounce time = (255*64 us + 0.5 us) 255 SECUREAPPROTECT Secure access port protection 0x02C read-write 0x00000000 PALL Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses 0 31 Unprotected Unprotected 0xFFFFFFFF Protected Protected 0x00000000 ERASEPROTECT Erase protection 0x030 read-write 0x00000000 PALL Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality 0 31 Unprotected Unprotected 0xFFFFFFFF Protected Protected 0x00000000 0xBE 0x4 OTP[%s] Description collection: One time programmable memory 0x108 read-write 0xFFFFFFFF LOWER Lower half word 0 15 read-writeonce UPPER Upper half word 16 31 read-writeonce KEYSLOT Unspecified UICR_KEYSLOT read-write 0x400 128 0x008 CONFIG[%s] Unspecified UICR_KEYSLOT_CONFIG read-write 0x000 DEST Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address MUST match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read! 0x000 read-write 0xFFFFFFFF DEST Secure APB destination address 0 31 PERM Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. 0x004 read-write 0xFFFFFFFF WRITE Write permission for key slot 0 0 Disabled Disable write to the key value registers 0 Enabled Enable write to the key value registers 1 READ Read permission for key slot 1 1 Disabled Disable read from key value registers 0 Enabled Enable read from key value registers 1 PUSH Push permission for key slot 2 2 Disabled Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled 0 Enabled Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! 1 STATE Revocation state for the key slot 16 16 Revoked Key value registers can no longer be read or pushed 0 Active Key value registers are readable (if enabled) and can be pushed (if enabled) 1 128 0x010 KEY[%s] Unspecified UICR_KEYSLOT_KEY read-write 0x400 0x4 0x4 VALUE[%s] Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. 0x000 read-write 0xFFFFFFFF VALUE Define bits [31+o*32:0+o*32] of value assigned to KMU key slot 0 31 TAD_S Trace and debug control 0xE0080000 TAD 0 0x1000 registers TAD 0x20 CLOCKSTART Start all trace and debug clocks. 0x000 write-only START 0 0 Start Start all trace and debug clocks. 1 CLOCKSTOP Stop all trace and debug clocks. 0x004 write-only STOP 0 0 Stop Stop all trace and debug clocks. 1 ENABLE Enable debug domain and aquire selected GPIOs 0x500 read-write ENABLE 0 0 DISABLED Disable debug domain and release selected GPIOs 0 ENABLED Enable debug domain and aquire selected GPIOs 1 PSEL Unspecified TAD_PSEL read-write 0x504 TRACECLK Pin number configuration for TRACECLK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TRACEDATA0 Pin number configuration for TRACEDATA[0] 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TRACEDATA1 Pin number configuration for TRACEDATA[1] 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TRACEDATA2 Pin number configuration for TRACEDATA[2] 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TRACEDATA3 Pin number configuration for TRACEDATA[3] 0x010 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TRACEPORTSPEED Clocking options for the Trace Port debug interface 0x518 read-write 0x00000000 TRACEPORTSPEED Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. 0 1 32MHz 32 MHz Trace Port clock (TRACECLK = 16 MHz) 0 16MHz 16 MHz Trace Port clock (TRACECLK = 8 MHz) 1 8MHz 8 MHz Trace Port clock (TRACECLK = 4 MHz) 2 4MHz 4 MHz Trace Port clock (TRACECLK = 2 MHz) 3 SPU_S System protection unit 0x50003000 SPU 0 0x1000 registers SPU 3 SPU 0x20 EVENTS_RAMACCERR A security violation has been detected for the RAM memory space 0x100 read-write EVENTS_RAMACCERR A security violation has been detected for the RAM memory space 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_FLASHACCERR A security violation has been detected for the flash memory space 0x104 read-write EVENTS_FLASHACCERR A security violation has been detected for the flash memory space 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_PERIPHACCERR A security violation has been detected on one or several peripherals 0x108 read-write EVENTS_PERIPHACCERR A security violation has been detected on one or several peripherals 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_RAMACCERR Publish configuration for event RAMACCERR 0x180 read-write CHIDX Channel that event RAMACCERR will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_FLASHACCERR Publish configuration for event FLASHACCERR 0x184 read-write CHIDX Channel that event FLASHACCERR will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_PERIPHACCERR Publish configuration for event PERIPHACCERR 0x188 read-write CHIDX Channel that event PERIPHACCERR will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write RAMACCERR Enable or disable interrupt for event RAMACCERR 0 0 Disabled Disable 0 Enabled Enable 1 FLASHACCERR Enable or disable interrupt for event FLASHACCERR 1 1 Disabled Disable 0 Enabled Enable 1 PERIPHACCERR Enable or disable interrupt for event PERIPHACCERR 2 2 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write RAMACCERR Write '1' to enable interrupt for event RAMACCERR 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 FLASHACCERR Write '1' to enable interrupt for event FLASHACCERR 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PERIPHACCERR Write '1' to enable interrupt for event PERIPHACCERR 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write RAMACCERR Write '1' to disable interrupt for event RAMACCERR 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 FLASHACCERR Write '1' to disable interrupt for event FLASHACCERR 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PERIPHACCERR Write '1' to disable interrupt for event PERIPHACCERR 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CAP Show implemented features for the current device 0x400 read-only 0x00000001 TZM Show ARM TrustZone status 0 0 NotAvailable ARM TrustZone support not available 0 Enabled ARM TrustZone support is available 1 1 0x004 EXTDOMAIN[%s] Unspecified SPU_EXTDOMAIN read-write 0x440 PERM Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n 0x000 read-write 0x00000000 SECUREMAPPING Define configuration capabilities for TrustZone Cortex-M secure attribute 0 1 NonSecure The bus access from this external domain always have the non-secure attribute set 0 Secure The bus access from this external domain always have the secure attribute set 1 UserSelectable Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register 2 SECATTR Peripheral security mapping 4 4 NonSecure Bus accesses from this domain have the non-secure attribute set 0 Secure Bus accesses from this domain have secure attribute set 1 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 1 0x008 DPPI[%s] Unspecified SPU_DPPI read-write 0x480 PERM Description cluster: Select between secure and non-secure attribute for the DPPI channels. 0x000 read-write 0x0000FFFF CHANNEL0 Select secure attribute. 0 0 Secure Channel0 has its secure attribute set 1 NonSecure Channel0 has its non-secure attribute set 0 CHANNEL1 Select secure attribute. 1 1 Secure Channel1 has its secure attribute set 1 NonSecure Channel1 has its non-secure attribute set 0 CHANNEL2 Select secure attribute. 2 2 Secure Channel2 has its secure attribute set 1 NonSecure Channel2 has its non-secure attribute set 0 CHANNEL3 Select secure attribute. 3 3 Secure Channel3 has its secure attribute set 1 NonSecure Channel3 has its non-secure attribute set 0 CHANNEL4 Select secure attribute. 4 4 Secure Channel4 has its secure attribute set 1 NonSecure Channel4 has its non-secure attribute set 0 CHANNEL5 Select secure attribute. 5 5 Secure Channel5 has its secure attribute set 1 NonSecure Channel5 has its non-secure attribute set 0 CHANNEL6 Select secure attribute. 6 6 Secure Channel6 has its secure attribute set 1 NonSecure Channel6 has its non-secure attribute set 0 CHANNEL7 Select secure attribute. 7 7 Secure Channel7 has its secure attribute set 1 NonSecure Channel7 has its non-secure attribute set 0 CHANNEL8 Select secure attribute. 8 8 Secure Channel8 has its secure attribute set 1 NonSecure Channel8 has its non-secure attribute set 0 CHANNEL9 Select secure attribute. 9 9 Secure Channel9 has its secure attribute set 1 NonSecure Channel9 has its non-secure attribute set 0 CHANNEL10 Select secure attribute. 10 10 Secure Channel10 has its secure attribute set 1 NonSecure Channel10 has its non-secure attribute set 0 CHANNEL11 Select secure attribute. 11 11 Secure Channel11 has its secure attribute set 1 NonSecure Channel11 has its non-secure attribute set 0 CHANNEL12 Select secure attribute. 12 12 Secure Channel12 has its secure attribute set 1 NonSecure Channel12 has its non-secure attribute set 0 CHANNEL13 Select secure attribute. 13 13 Secure Channel13 has its secure attribute set 1 NonSecure Channel13 has its non-secure attribute set 0 CHANNEL14 Select secure attribute. 14 14 Secure Channel14 has its secure attribute set 1 NonSecure Channel14 has its non-secure attribute set 0 CHANNEL15 Select secure attribute. 15 15 Secure Channel15 has its secure attribute set 1 NonSecure Channel15 has its non-secure attribute set 0 LOCK Description cluster: Prevent further modification of the corresponding PERM register 0x004 read-write 0x00000000 LOCK 0 0 Locked DPPI[n].PERM register can't be changed until next reset 1 Unlocked DPPI[n].PERM register content can be changed 0 1 0x008 GPIOPORT[%s] Unspecified SPU_GPIOPORT read-write 0x4C0 PERM Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. 0x000 read-write 0xFFFFFFFF PIN0 Select secure attribute attribute for PIN 0. 0 0 Secure Pin 0 has its secure attribute set 1 NonSecure Pin 0 has its non-secure attribute set 0 PIN1 Select secure attribute attribute for PIN 1. 1 1 Secure Pin 1 has its secure attribute set 1 NonSecure Pin 1 has its non-secure attribute set 0 PIN2 Select secure attribute attribute for PIN 2. 2 2 Secure Pin 2 has its secure attribute set 1 NonSecure Pin 2 has its non-secure attribute set 0 PIN3 Select secure attribute attribute for PIN 3. 3 3 Secure Pin 3 has its secure attribute set 1 NonSecure Pin 3 has its non-secure attribute set 0 PIN4 Select secure attribute attribute for PIN 4. 4 4 Secure Pin 4 has its secure attribute set 1 NonSecure Pin 4 has its non-secure attribute set 0 PIN5 Select secure attribute attribute for PIN 5. 5 5 Secure Pin 5 has its secure attribute set 1 NonSecure Pin 5 has its non-secure attribute set 0 PIN6 Select secure attribute attribute for PIN 6. 6 6 Secure Pin 6 has its secure attribute set 1 NonSecure Pin 6 has its non-secure attribute set 0 PIN7 Select secure attribute attribute for PIN 7. 7 7 Secure Pin 7 has its secure attribute set 1 NonSecure Pin 7 has its non-secure attribute set 0 PIN8 Select secure attribute attribute for PIN 8. 8 8 Secure Pin 8 has its secure attribute set 1 NonSecure Pin 8 has its non-secure attribute set 0 PIN9 Select secure attribute attribute for PIN 9. 9 9 Secure Pin 9 has its secure attribute set 1 NonSecure Pin 9 has its non-secure attribute set 0 PIN10 Select secure attribute attribute for PIN 10. 10 10 Secure Pin 10 has its secure attribute set 1 NonSecure Pin 10 has its non-secure attribute set 0 PIN11 Select secure attribute attribute for PIN 11. 11 11 Secure Pin 11 has its secure attribute set 1 NonSecure Pin 11 has its non-secure attribute set 0 PIN12 Select secure attribute attribute for PIN 12. 12 12 Secure Pin 12 has its secure attribute set 1 NonSecure Pin 12 has its non-secure attribute set 0 PIN13 Select secure attribute attribute for PIN 13. 13 13 Secure Pin 13 has its secure attribute set 1 NonSecure Pin 13 has its non-secure attribute set 0 PIN14 Select secure attribute attribute for PIN 14. 14 14 Secure Pin 14 has its secure attribute set 1 NonSecure Pin 14 has its non-secure attribute set 0 PIN15 Select secure attribute attribute for PIN 15. 15 15 Secure Pin 15 has its secure attribute set 1 NonSecure Pin 15 has its non-secure attribute set 0 PIN16 Select secure attribute attribute for PIN 16. 16 16 Secure Pin 16 has its secure attribute set 1 NonSecure Pin 16 has its non-secure attribute set 0 PIN17 Select secure attribute attribute for PIN 17. 17 17 Secure Pin 17 has its secure attribute set 1 NonSecure Pin 17 has its non-secure attribute set 0 PIN18 Select secure attribute attribute for PIN 18. 18 18 Secure Pin 18 has its secure attribute set 1 NonSecure Pin 18 has its non-secure attribute set 0 PIN19 Select secure attribute attribute for PIN 19. 19 19 Secure Pin 19 has its secure attribute set 1 NonSecure Pin 19 has its non-secure attribute set 0 PIN20 Select secure attribute attribute for PIN 20. 20 20 Secure Pin 20 has its secure attribute set 1 NonSecure Pin 20 has its non-secure attribute set 0 PIN21 Select secure attribute attribute for PIN 21. 21 21 Secure Pin 21 has its secure attribute set 1 NonSecure Pin 21 has its non-secure attribute set 0 PIN22 Select secure attribute attribute for PIN 22. 22 22 Secure Pin 22 has its secure attribute set 1 NonSecure Pin 22 has its non-secure attribute set 0 PIN23 Select secure attribute attribute for PIN 23. 23 23 Secure Pin 23 has its secure attribute set 1 NonSecure Pin 23 has its non-secure attribute set 0 PIN24 Select secure attribute attribute for PIN 24. 24 24 Secure Pin 24 has its secure attribute set 1 NonSecure Pin 24 has its non-secure attribute set 0 PIN25 Select secure attribute attribute for PIN 25. 25 25 Secure Pin 25 has its secure attribute set 1 NonSecure Pin 25 has its non-secure attribute set 0 PIN26 Select secure attribute attribute for PIN 26. 26 26 Secure Pin 26 has its secure attribute set 1 NonSecure Pin 26 has its non-secure attribute set 0 PIN27 Select secure attribute attribute for PIN 27. 27 27 Secure Pin 27 has its secure attribute set 1 NonSecure Pin 27 has its non-secure attribute set 0 PIN28 Select secure attribute attribute for PIN 28. 28 28 Secure Pin 28 has its secure attribute set 1 NonSecure Pin 28 has its non-secure attribute set 0 PIN29 Select secure attribute attribute for PIN 29. 29 29 Secure Pin 29 has its secure attribute set 1 NonSecure Pin 29 has its non-secure attribute set 0 PIN30 Select secure attribute attribute for PIN 30. 30 30 Secure Pin 30 has its secure attribute set 1 NonSecure Pin 30 has its non-secure attribute set 0 PIN31 Select secure attribute attribute for PIN 31. 31 31 Secure Pin 31 has its secure attribute set 1 NonSecure Pin 31 has its non-secure attribute set 0 LOCK Description cluster: Prevent further modification of the corresponding PERM register 0x004 read-write 0x00000000 LOCK 0 0 Locked GPIOPORT[n].PERM register can't be changed until next reset 1 Unlocked GPIOPORT[n].PERM register content can be changed 0 2 0x008 FLASHNSC[%s] Unspecified SPU_FLASHNSC read-write 0x500 REGION Description cluster: Define which flash region can contain the non-secure callable (NSC) region n 0x000 read-write 0x00000000 REGION Region number 0 4 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 SIZE Description cluster: Define the size of the non-secure callable (NSC) region n 0x004 read-write 0x00000000 SIZE Size of the non-secure callable (NSC) region n 0 3 Disabled The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. 0 32 The region n is defined as non-secure callable with a 32-byte size 1 64 The region n is defined as non-secure callable with a 64-byte size 2 128 The region n is defined as non-secure callable with a 128-byte size 3 256 The region n is defined as non-secure callable with a 256-byte size 4 512 The region n is defined as non-secure callable with a 512-byte size 5 1024 The region n is defined as non-secure callable with a 1024-byte size 6 2048 The region n is defined as non-secure callable with a 2048-byte size 7 4096 The region n is defined as non-secure callable with a 4096-byte size 8 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 2 0x008 RAMNSC[%s] Unspecified SPU_RAMNSC read-write 0x540 REGION Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n 0x000 read-write 0x00000000 REGION Region number 0 3 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 SIZE Description cluster: Define the size of the non-secure callable (NSC) region n 0x004 read-write 0x00000000 SIZE Size of the non-secure callable (NSC) region n 0 3 Disabled The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. 0 32 The region n is defined as non-secure callable with a 32-byte size 1 64 The region n is defined as non-secure callable with a 64-byte size 2 128 The region n is defined as non-secure callable with a 128-byte size 3 256 The region n is defined as non-secure callable with a 256-byte size 4 512 The region n is defined as non-secure callable with a 512-byte size 5 1024 The region n is defined as non-secure callable with a 1024-byte size 6 2048 The region n is defined as non-secure callable with a 2048-byte size 7 4096 The region n is defined as non-secure callable with a 4096-byte size 8 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 32 0x004 FLASHREGION[%s] Unspecified SPU_FLASHREGION read-write 0x600 PERM Description cluster: Access permissions for flash region n 0x000 read-write 0x00000017 EXECUTE Configure instruction fetch permissions from flash region n 0 0 Enable Allow instruction fetches from flash region n 1 Disable Block instruction fetches from flash region n 0 WRITE Configure write permission for flash region n 1 1 Enable Allow write operation to region n 1 Disable Block write operation to region n 0 READ Configure read permissions for flash region n 2 2 Enable Allow read operation from flash region n 1 Disable Block read operation from flash region n 0 SECATTR Security attribute for flash region n 4 4 Non_Secure Flash region n security attribute is non-secure 0 Secure Flash region n security attribute is secure 1 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 32 0x004 RAMREGION[%s] Unspecified SPU_RAMREGION read-write 0x700 PERM Description cluster: Access permissions for RAM region n 0x000 read-write 0x00000017 EXECUTE Configure instruction fetch permissions from RAM region n 0 0 Enable Allow instruction fetches from RAM region n 1 Disable Block instruction fetches from RAM region n 0 WRITE Configure write permission for RAM region n 1 1 Enable Allow write operation to RAM region n 1 Disable Block write operation to RAM region n 0 READ Configure read permissions for RAM region n 2 2 Enable Allow read operation from RAM region n 1 Disable Block read operation from RAM region n 0 SECATTR Security attribute for RAM region n 4 4 Non_Secure RAM region n security attribute is non-secure 0 Secure RAM region n security attribute is secure 1 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 67 0x004 PERIPHID[%s] Unspecified SPU_PERIPHID read-write 0x800 PERM Description cluster: List capabilities and access permissions for the peripheral with ID n 0x000 read-write 0x00000012 SECUREMAPPING Define configuration capabilities for TrustZone Cortex-M secure attribute 0 1 read-only NonSecure This peripheral is always accessible as a non-secure peripheral 0 Secure This peripheral is always accessible as a secure peripheral 1 UserSelectable Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register 2 Split This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. 3 DMA Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself 2 3 read-only NoDMA Peripheral has no DMA capability 0 NoSeparateAttribute Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral 1 SeparateAttribute Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral 2 SECATTR Peripheral security mapping 4 4 Secure Peripheral is mapped in secure peripheral address space 1 NonSecure If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. 0 DMASEC Security attribution for the DMA transfer 5 5 Secure DMA transfers initiated by this peripheral have the secure attribute set 1 NonSecure DMA transfers initiated by this peripheral have the non-secure attribute set 0 LOCK 8 8 Unlocked This register can be updated 0 Locked The content of this register can't be changed until the next reset 1 PRESENT Indicate if a peripheral is present with ID n 31 31 read-only NotPresent Peripheral is not present 0 IsPresent Peripheral is present 1 REGULATORS_NS Voltage regulators control 0 0x40004000 REGULATORS 0 0x1000 registers REGULATORS 0x20 SYSTEMOFF System OFF register 0x500 write-only SYSTEMOFF Enable System OFF mode 0 0 Enable Enable System OFF mode 1 DCDCEN Enable DC/DC mode of the main voltage regulator. 0x578 read-write DCDCEN Enable DC/DC converter 0 0 Disabled DC/DC mode is disabled 0 Enabled DC/DC mode is enabled 1 REGULATORS_S Voltage regulators control 1 0x50004000 CLOCK_NS Clock management 0 0x40005000 CLOCK 0 0x1000 registers CLOCK_POWER 5 CLOCK 0x20 TASKS_HFCLKSTART Start HFCLK source 0x000 write-only TASKS_HFCLKSTART Start HFCLK source 0 0 Trigger Trigger task 1 TASKS_HFCLKSTOP Stop HFCLK source 0x004 write-only TASKS_HFCLKSTOP Stop HFCLK source 0 0 Trigger Trigger task 1 TASKS_LFCLKSTART Start LFCLK source 0x008 write-only TASKS_LFCLKSTART Start LFCLK source 0 0 Trigger Trigger task 1 TASKS_LFCLKSTOP Stop LFCLK source 0x00C write-only TASKS_LFCLKSTOP Stop LFCLK source 0 0 Trigger Trigger task 1 SUBSCRIBE_HFCLKSTART Subscribe configuration for task HFCLKSTART 0x080 read-write CHIDX Channel that task HFCLKSTART will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_HFCLKSTOP Subscribe configuration for task HFCLKSTOP 0x084 read-write CHIDX Channel that task HFCLKSTOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_LFCLKSTART Subscribe configuration for task LFCLKSTART 0x088 read-write CHIDX Channel that task LFCLKSTART will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_LFCLKSTOP Subscribe configuration for task LFCLKSTOP 0x08C read-write CHIDX Channel that task LFCLKSTOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_HFCLKSTARTED HFCLK oscillator started 0x100 read-write EVENTS_HFCLKSTARTED HFCLK oscillator started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LFCLKSTARTED LFCLK started 0x104 read-write EVENTS_LFCLKSTARTED LFCLK started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_HFCLKSTARTED Publish configuration for event HFCLKSTARTED 0x180 read-write CHIDX Channel that event HFCLKSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_LFCLKSTARTED Publish configuration for event LFCLKSTARTED 0x184 read-write CHIDX Channel that event LFCLKSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write HFCLKSTARTED Enable or disable interrupt for event HFCLKSTARTED 0 0 Disabled Disable 0 Enabled Enable 1 LFCLKSTARTED Enable or disable interrupt for event LFCLKSTARTED 1 1 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write HFCLKSTARTED Write '1' to enable interrupt for event HFCLKSTARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write HFCLKSTARTED Write '1' to disable interrupt for event HFCLKSTARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 INTPEND Pending interrupts 0x30C read-only HFCLKSTARTED Read pending status of interrupt for event HFCLKSTARTED 0 0 read NotPending Read: Not pending 0 Pending Read: Pending 1 LFCLKSTARTED Read pending status of interrupt for event LFCLKSTARTED 1 1 read NotPending Read: Not pending 0 Pending Read: Pending 1 HFCLKRUN Status indicating that HFCLKSTART task has been triggered 0x408 read-only STATUS HFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0 Triggered Task triggered 1 HFCLKSTAT The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) 0x40C read-only SRC Active clock source 0 0 HFXO HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator 1 STATE HFCLK state 16 16 NotRunning HFXO has not been started or HFCLKSTOP task has been triggered 0 Running HFXO has been started (HFCLKSTARTED event has been generated) 1 LFCLKRUN Status indicating that LFCLKSTART task has been triggered 0x414 read-only STATUS LFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0 Triggered Task triggered 1 LFCLKSTAT The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) 0x418 read-only SRC Active clock source 0 1 RFU Reserved for future use 0 LFRC 32.768 kHz RC oscillator 1 LFXO 32.768 kHz crystal oscillator 2 STATE LFCLK state 16 16 NotRunning Requested LFCLK source has not been started or LFCLKSTOP task has been triggered 0 Running Requested LFCLK source has been started (LFCLKSTARTED event has been generated) 1 LFCLKSRCCOPY Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered 0x41C read-only 0x00000001 SRC Clock source 0 1 RFU Reserved for future use 0 LFRC 32.768 kHz RC oscillator 1 LFXO 32.768 kHz crystal oscillator 2 LFCLKSRC Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. 0x518 read-write 0x00000001 SRC Clock source 0 1 RFU Reserved for future use (equals selecting LFRC) 0 LFRC 32.768 kHz RC oscillator 1 LFXO 32.768 kHz crystal oscillator 2 POWER_NS Power control 0 0x40005000 CLOCK_NS POWER 0 0x1000 registers CLOCK_POWER 5 POWER 0x20 TASKS_CONSTLAT Enable constant latency mode. 0x78 write-only TASKS_CONSTLAT Enable constant latency mode. 0 0 Trigger Trigger task 1 TASKS_LOWPWR Enable low power mode (variable latency) 0x7C write-only TASKS_LOWPWR Enable low power mode (variable latency) 0 0 Trigger Trigger task 1 SUBSCRIBE_CONSTLAT Subscribe configuration for task CONSTLAT 0xF8 read-write CHIDX Channel that task CONSTLAT will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_LOWPWR Subscribe configuration for task LOWPWR 0xFC read-write CHIDX Channel that task LOWPWR will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_POFWARN Power failure warning 0x108 read-write EVENTS_POFWARN Power failure warning 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0x114 read-write EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0x118 read-write EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_POFWARN Publish configuration for event POFWARN 0x188 read-write CHIDX Channel that event POFWARN will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_SLEEPENTER Publish configuration for event SLEEPENTER 0x194 read-write CHIDX Channel that event SLEEPENTER will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_SLEEPEXIT Publish configuration for event SLEEPEXIT 0x198 read-write CHIDX Channel that event SLEEPEXIT will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write POFWARN Enable or disable interrupt for event POFWARN 2 2 Disabled Disable 0 Enabled Enable 1 SLEEPENTER Enable or disable interrupt for event SLEEPENTER 5 5 Disabled Disable 0 Enabled Enable 1 SLEEPEXIT Enable or disable interrupt for event SLEEPEXIT 6 6 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write POFWARN Write '1' to enable interrupt for event POFWARN 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write POFWARN Write '1' to disable interrupt for event POFWARN 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESETREAS Reset reason 0x400 read-write RESETPIN Reset from pin reset detected 0 0 NotDetected Not detected 0 Detected Detected 1 DOG Reset from global watchdog detected 1 1 NotDetected Not detected 0 Detected Detected 1 OFF Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO 2 2 NotDetected Not detected 0 Detected Detected 1 DIF Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode 4 4 NotDetected Not detected 0 Detected Detected 1 SREQ Reset from AIRCR.SYSRESETREQ detected 16 16 NotDetected Not detected 0 Detected Detected 1 LOCKUP Reset from CPU lock-up detected 17 17 NotDetected Not detected 0 Detected Detected 1 CTRLAP Reset triggered through CTRL-AP 18 18 NotDetected Not detected 0 Detected Detected 1 POWERSTATUS Modem domain power status 0x440 read-only LTEMODEM LTE modem domain status 0 0 OFF LTE modem domain is powered off 0 ON LTE modem domain is powered on 1 0x2 0x4 GPREGRET[%s] Description collection: General purpose retention register 0x51C read-write GPREGRET General purpose retention register 0 7 CLOCK_S Clock management 1 0x50005000 CLOCK_POWER 5 POWER_S Power control 1 0x50005000 CLOCK_S CLOCK_POWER 5 CTRL_AP_PERI_S Control access port 0x50006000 CTRLAPPERI 0 0x1000 registers CTRLAPPERI 0x20 MAILBOX Unspecified CTRLAPPERI_MAILBOX read-write 0x400 RXDATA Data sent from the debugger to the CPU 0x000 read-only 0x00000000 RXDATA Data received from debugger 0 31 RXSTATUS Status to indicate if data sent from the debugger to the CPU has been read 0x004 read-only 0x00000000 RXSTATUS Status of data in register RXDATA 0 0 NoDataPending No data pending in register RXDATA 0 DataPending Data pending in register RXDATA 1 TXDATA Data sent from the CPU to the debugger 0x80 read-write 0x00000000 TXDATA Data sent to debugger 0 31 TXSTATUS Status to indicate if data sent from the CPU to the debugger has been read 0x84 read-only 0x00000000 TXSTATUS Status of data in register TXDATA 0 0 NoDataPending No data pending in register TXDATA 0 DataPending Data pending in register TXDATA 1 ERASEPROTECT Unspecified CTRLAPPERI_ERASEPROTECT read-write 0x500 LOCK Lock register ERASEPROTECT.DISABLE from being written until next reset 0x000 read-writeonce 0x00000000 LOCK Lock register ERASEPROTECT.DISABLE from being written until next reset 0 0 Unlocked Register ERASEPROTECT.DISABLE is writeable 0 Locked Register ERASEPROTECT.DISABLE is read-only 1 DISABLE Disable ERASEPROTECT and perform ERASEALL 0x004 read-write 0x00000000 KEY The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side 0 31 SPIM0_NS Serial Peripheral Interface Master with EasyDMA 0 0x40008000 SPIM 0 0x1000 registers UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 SPIM 0x20 TASKS_START Start SPI transaction 0x010 write-only TASKS_START Start SPI transaction 0 0 Trigger Trigger task 1 TASKS_STOP Stop SPI transaction 0x014 write-only TASKS_STOP Stop SPI transaction 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend SPI transaction 0x01C write-only TASKS_SUSPEND Suspend SPI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume SPI transaction 0x020 write-only TASKS_RESUME Resume SPI transaction 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x090 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x094 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_SUSPEND Subscribe configuration for task SUSPEND 0x09C read-write CHIDX Channel that task SUSPEND will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_RESUME Subscribe configuration for task RESUME 0x0A0 read-write CHIDX Channel that task RESUME will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_STOPPED SPI transaction has stopped 0x104 read-write EVENTS_STOPPED SPI transaction has stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_END End of RXD buffer and TXD buffer reached 0x118 read-write EVENTS_END End of RXD buffer and TXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDTX End of TXD buffer reached 0x120 read-write EVENTS_ENDTX End of TXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STARTED Transaction started 0x14C read-write EVENTS_STARTED Transaction started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x190 read-write CHIDX Channel that event ENDRX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_END Publish configuration for event END 0x198 read-write CHIDX Channel that event END will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ENDTX Publish configuration for event ENDTX 0x1A0 read-write CHIDX Channel that event ENDTX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_STARTED Publish configuration for event STARTED 0x1CC read-write CHIDX Channel that event STARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write END_START Shortcut between event END and task START 17 17 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for event END 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STARTED Write '1' to enable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for event END 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STARTED Write '1' to disable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable SPIM 0x500 read-write ENABLE Enable or disable SPIM 0 3 Disabled Disable SPIM 0 Enabled Enable SPIM 7 PSEL Unspecified SPIM_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 RXD RXD EasyDMA channel SPIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 12 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel SPIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 12 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 ORC Over-read character. Character clocked out in case an over-read of the TXD buffer. 0x5C0 read-write ORC Over-read character. Character clocked out in case an over-read of the TXD buffer. 0 7 SPIS0_NS SPI Slave 0 0x40008000 SPIM0_NS SPIS 0 0x1000 registers UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 SPIS 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0x024 write-only TASKS_ACQUIRE Acquire SPI semaphore 0 0 Trigger Trigger task 1 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0x028 write-only TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0 0 Trigger Trigger task 1 SUBSCRIBE_ACQUIRE Subscribe configuration for task ACQUIRE 0x0A4 read-write CHIDX Channel that task ACQUIRE will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_RELEASE Subscribe configuration for task RELEASE 0x0A8 read-write CHIDX Channel that task RELEASE will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_END Granted transaction completed 0x104 read-write EVENTS_END Granted transaction completed 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ACQUIRED Semaphore acquired 0x128 read-write EVENTS_ACQUIRED Semaphore acquired 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_END Publish configuration for event END 0x184 read-write CHIDX Channel that event END will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x190 read-write CHIDX Channel that event ENDRX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ACQUIRED Publish configuration for event ACQUIRED 0x1A8 read-write CHIDX Channel that event ACQUIRED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write END_ACQUIRE Shortcut between event END and task ACQUIRE 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ACQUIRED Write '1' to enable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ACQUIRED Write '1' to disable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEMSTAT Semaphore status register 0x400 read-only 0x00000001 SEMSTAT Semaphore status 0 1 Free Semaphore is free 0 CPU Semaphore is assigned to CPU 1 SPIS Semaphore is assigned to SPI slave 2 CPUPending Semaphore is assigned to SPI but a handover to the CPU is pending 3 STATUS Status from last transaction 0x440 read-write OVERREAD TX buffer over-read detected, and prevented 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 write Clear Write: clear error on writing '1' 1 OVERFLOW RX buffer overflow detected, and prevented 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 write Clear Write: clear error on writing '1' 1 ENABLE Enable SPI slave 0x500 read-write ENABLE Enable or disable SPI slave 0 3 Disabled Disable SPI slave 0 Enabled Enable SPI slave 2 PSEL Unspecified SPIS_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CSN Pin select for CSN signal 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Unspecified SPIS_RXD read-write 0x534 PTR RXD data pointer 0x000 read-write PTR RXD data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 12 AMOUNT Number of bytes received in last granted transaction 0x008 read-only AMOUNT Number of bytes received in the last granted transaction 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD Unspecified SPIS_TXD read-write 0x544 PTR TXD data pointer 0x000 read-write PTR TXD data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 12 AMOUNT Number of bytes transmitted in last granted transaction 0x008 read-only AMOUNT Number of bytes transmitted in last granted transaction 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 DEF Default character. Character clocked out in case of an ignored transaction. 0x55C read-write DEF Default character. Character clocked out in case of an ignored transaction. 0 7 ORC Over-read character 0x5C0 read-write ORC Over-read character. Character clocked out after an over-read of the transmit buffer. 0 7 TWIM0_NS I2C compatible Two-Wire Master Interface with EasyDMA 0 0x40008000 SPIM0_NS TWIM 0 0x1000 registers UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 TWIM 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only TASKS_STARTRX Start TWI receive sequence 0 0 Trigger Trigger task 1 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only TASKS_STARTTX Start TWI transmit sequence 0 0 Trigger Trigger task 1 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0x014 write-only TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 1 SUBSCRIBE_STARTRX Subscribe configuration for task STARTRX 0x080 read-write CHIDX Channel that task STARTRX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STARTTX Subscribe configuration for task STARTTX 0x088 read-write CHIDX Channel that task STARTTX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x094 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_SUSPEND Subscribe configuration for task SUSPEND 0x09C read-write CHIDX Channel that task SUSPEND will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_RESUME Subscribe configuration for task RESUME 0x0A0 read-write CHIDX Channel that task RESUME will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0x15C read-write EVENTS_LASTRX Byte boundary, starting to receive the last byte 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0x160 read-write EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ERROR Publish configuration for event ERROR 0x1A4 read-write CHIDX Channel that event ERROR will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_SUSPENDED Publish configuration for event SUSPENDED 0x1C8 read-write CHIDX Channel that event SUSPENDED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_RXSTARTED Publish configuration for event RXSTARTED 0x1CC read-write CHIDX Channel that event RXSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_TXSTARTED Publish configuration for event TXSTARTED 0x1D0 read-write CHIDX Channel that event TXSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_LASTRX Publish configuration for event LASTRX 0x1DC read-write CHIDX Channel that event LASTRX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_LASTTX Publish configuration for event LASTTX 0x1E0 read-write CHIDX Channel that event LASTTX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write LASTTX_STARTRX Shortcut between event LASTTX and task STARTRX 7 7 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTTX_SUSPEND Shortcut between event LASTTX and task SUSPEND 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTTX_STOP Shortcut between event LASTTX and task STOP 9 9 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_STARTTX Shortcut between event LASTRX and task STARTTX 10 10 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_SUSPEND Shortcut between event LASTRX and task SUSPEND 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_STOP Shortcut between event LASTRX and task STOP 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0 Enabled Enable 1 SUSPENDED Enable or disable interrupt for event SUSPENDED 18 18 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0 Enabled Enable 1 LASTRX Enable or disable interrupt for event LASTRX 23 23 Disabled Disable 0 Enabled Enable 1 LASTTX Enable or disable interrupt for event LASTTX 24 24 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SUSPENDED Write '1' to enable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LASTRX Write '1' to enable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LASTTX Write '1' to enable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SUSPENDED Write '1' to disable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LASTRX Write '1' to disable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LASTTX Write '1' to disable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4C4 read-write oneToClear OVERRUN Overrun error 0 0 NotReceived Error did not occur 0 Received Error occurred 1 ANACK NACK received after sending the address (write '1' to clear) 1 1 NotReceived Error did not occur 0 Received Error occurred 1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 NotReceived Error did not occur 0 Received Error occurred 1 ENABLE Enable TWIM 0x500 read-write ENABLE Enable or disable TWIM 0 3 Disabled Disable TWIM 0 Enabled Enable TWIM 6 PSEL Unspecified TWIM_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps 0x06400000 RXD RXD EasyDMA channel TWIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 12 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel TWIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 12 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 ADDRESS Address used in the TWI transfer 0x588 read-write ADDRESS Address used in the TWI transfer 0 6 TWIS0_NS I2C compatible Two-Wire Slave Interface with EasyDMA 0 0x40008000 SPIM0_NS TWIS 0 0x1000 registers UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 TWIS 0x20 TASKS_STOP Stop TWI transaction 0x014 write-only TASKS_STOP Stop TWI transaction 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 1 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0x030 write-only TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0 0 Trigger Trigger task 1 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0x034 write-only TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0 0 Trigger Trigger task 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x094 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_SUSPEND Subscribe configuration for task SUSPEND 0x09C read-write CHIDX Channel that task SUSPEND will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_RESUME Subscribe configuration for task RESUME 0x0A0 read-write CHIDX Channel that task RESUME will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_PREPARERX Subscribe configuration for task PREPARERX 0x0B0 read-write CHIDX Channel that task PREPARERX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_PREPARETX Subscribe configuration for task PREPARETX 0x0B4 read-write CHIDX Channel that task PREPARETX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_WRITE Write command received 0x164 read-write EVENTS_WRITE Write command received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_READ Read command received 0x168 read-write EVENTS_READ Read command received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ERROR Publish configuration for event ERROR 0x1A4 read-write CHIDX Channel that event ERROR will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_RXSTARTED Publish configuration for event RXSTARTED 0x1CC read-write CHIDX Channel that event RXSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_TXSTARTED Publish configuration for event TXSTARTED 0x1D0 read-write CHIDX Channel that event TXSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_WRITE Publish configuration for event WRITE 0x1E4 read-write CHIDX Channel that event WRITE will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_READ Publish configuration for event READ 0x1E8 read-write CHIDX Channel that event READ will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write WRITE_SUSPEND Shortcut between event WRITE and task SUSPEND 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 READ_SUSPEND Shortcut between event READ and task SUSPEND 14 14 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0 Enabled Enable 1 WRITE Enable or disable interrupt for event WRITE 25 25 Disabled Disable 0 Enabled Enable 1 READ Enable or disable interrupt for event READ 26 26 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 WRITE Write '1' to enable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 READ Write '1' to enable interrupt for event READ 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 WRITE Write '1' to disable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 READ Write '1' to disable interrupt for event READ 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4D0 read-write oneToClear OVERFLOW RX buffer overflow detected, and prevented 0 0 NotDetected Error did not occur 0 Detected Error occurred 1 DNACK NACK sent after receiving a data byte 2 2 NotReceived Error did not occur 0 Received Error occurred 1 OVERREAD TX buffer over-read detected, and prevented 3 3 NotDetected Error did not occur 0 Detected Error occurred 1 MATCH Status register indicating which address had a match 0x4D4 read-only MATCH Which of the addresses in {ADDRESS} matched the incoming address 0 0 ENABLE Enable TWIS 0x500 read-write ENABLE Enable or disable TWIS 0 3 Disabled Disable TWIS 0 Enabled Enable TWIS 9 PSEL Unspecified TWIS_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD EasyDMA channel TWIS_RXD read-write 0x534 PTR RXD Data pointer 0x000 read-write PTR RXD Data pointer 0 31 MAXCNT Maximum number of bytes in RXD buffer 0x004 read-write MAXCNT Maximum number of bytes in RXD buffer 0 12 AMOUNT Number of bytes transferred in the last RXD transaction 0x008 read-only AMOUNT Number of bytes transferred in the last RXD transaction 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel TWIS_TXD read-write 0x544 PTR TXD Data pointer 0x000 read-write PTR TXD Data pointer 0 31 MAXCNT Maximum number of bytes in TXD buffer 0x004 read-write MAXCNT Maximum number of bytes in TXD buffer 0 12 AMOUNT Number of bytes transferred in the last TXD transaction 0x008 read-only AMOUNT Number of bytes transferred in the last TXD transaction 0 12 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 0x2 0x4 ADDRESS[%s] Description collection: TWI slave address n 0x588 read-write ADDRESS TWI slave address 0 6 CONFIG Configuration register for the address match mechanism 0x594 read-write 0x00000001 ADDRESS0 Enable or disable address matching on ADDRESS[0] 0 0 Disabled Disabled 0 Enabled Enabled 1 ADDRESS1 Enable or disable address matching on ADDRESS[1] 1 1 Disabled Disabled 0 Enabled Enabled 1 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0x5C0 read-write ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 7 UARTE0_NS UART with EasyDMA 0 0x40008000 SPIM0_NS UARTE 0 0x1000 registers UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 UARTE 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only TASKS_STARTRX Start UART receiver 0 0 Trigger Trigger task 1 TASKS_STOPRX Stop UART receiver 0x004 write-only TASKS_STOPRX Stop UART receiver 0 0 Trigger Trigger task 1 TASKS_STARTTX Start UART transmitter 0x008 write-only TASKS_STARTTX Start UART transmitter 0 0 Trigger Trigger task 1 TASKS_STOPTX Stop UART transmitter 0x00C write-only TASKS_STOPTX Stop UART transmitter 0 0 Trigger Trigger task 1 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0x02C write-only TASKS_FLUSHRX Flush RX FIFO into RX buffer 0 0 Trigger Trigger task 1 SUBSCRIBE_STARTRX Subscribe configuration for task STARTRX 0x080 read-write CHIDX Channel that task STARTRX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOPRX Subscribe configuration for task STOPRX 0x084 read-write CHIDX Channel that task STOPRX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STARTTX Subscribe configuration for task STARTTX 0x088 read-write CHIDX Channel that task STARTTX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOPTX Subscribe configuration for task STOPTX 0x08C read-write CHIDX Channel that task STOPTX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_FLUSHRX Subscribe configuration for task FLUSHRX 0x0AC read-write CHIDX Channel that task FLUSHRX will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write EVENTS_CTS CTS is activated (set low). Clear To Send. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0x108 read-write EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDRX Receive buffer is filled up 0x110 read-write EVENTS_ENDRX Receive buffer is filled up 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXDRDY Data sent from TXD 0x11C read-write EVENTS_TXDRDY Data sent from TXD 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDTX Last TX byte transmitted 0x120 read-write EVENTS_ENDTX Last TX byte transmitted 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR Error detected 0x124 read-write EVENTS_ERROR Error detected 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXTO Receiver timeout 0x144 read-write EVENTS_RXTO Receiver timeout 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXSTARTED UART receiver has started 0x14C read-write EVENTS_RXSTARTED UART receiver has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTARTED UART transmitter has started 0x150 read-write EVENTS_TXSTARTED UART transmitter has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTOPPED Transmitter stopped 0x158 read-write EVENTS_TXSTOPPED Transmitter stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_CTS Publish configuration for event CTS 0x180 read-write CHIDX Channel that event CTS will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_NCTS Publish configuration for event NCTS 0x184 read-write CHIDX Channel that event NCTS will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_RXDRDY Publish configuration for event RXDRDY 0x188 read-write CHIDX Channel that event RXDRDY will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x190 read-write CHIDX Channel that event ENDRX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_TXDRDY Publish configuration for event TXDRDY 0x19C read-write CHIDX Channel that event TXDRDY will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ENDTX Publish configuration for event ENDTX 0x1A0 read-write CHIDX Channel that event ENDTX will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_ERROR Publish configuration for event ERROR 0x1A4 read-write CHIDX Channel that event ERROR will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_RXTO Publish configuration for event RXTO 0x1C4 read-write CHIDX Channel that event RXTO will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_RXSTARTED Publish configuration for event RXSTARTED 0x1CC read-write CHIDX Channel that event RXSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_TXSTARTED Publish configuration for event TXSTARTED 0x1D0 read-write CHIDX Channel that event TXSTARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_TXSTOPPED Publish configuration for event TXSTOPPED 0x1D8 read-write CHIDX Channel that event TXSTOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write ENDRX_STARTRX Shortcut between event ENDRX and task STARTRX 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ENDRX_STOPRX Shortcut between event ENDRX and task STOPRX 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write CTS Enable or disable interrupt for event CTS 0 0 Disabled Disable 0 Enabled Enable 1 NCTS Enable or disable interrupt for event NCTS 1 1 Disabled Disable 0 Enabled Enable 1 RXDRDY Enable or disable interrupt for event RXDRDY 2 2 Disabled Disable 0 Enabled Enable 1 ENDRX Enable or disable interrupt for event ENDRX 4 4 Disabled Disable 0 Enabled Enable 1 TXDRDY Enable or disable interrupt for event TXDRDY 7 7 Disabled Disable 0 Enabled Enable 1 ENDTX Enable or disable interrupt for event ENDTX 8 8 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0 Enabled Enable 1 RXTO Enable or disable interrupt for event RXTO 17 17 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0 Enabled Enable 1 TXSTOPPED Enable or disable interrupt for event TXSTOPPED 22 22 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write CTS Write '1' to enable interrupt for event CTS 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NCTS Write '1' to enable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDRDY Write '1' to enable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDRDY Write '1' to enable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXTO Write '1' to enable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTOPPED Write '1' to enable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write CTS Write '1' to disable interrupt for event CTS 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NCTS Write '1' to disable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDRDY Write '1' to disable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDRDY Write '1' to disable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXTO Write '1' to disable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTOPPED Write '1' to disable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source Note : this register is read / write one to clear. 0x480 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 PARITY Parity error 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 BREAK Break condition 3 3 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable UART 0x500 read-write ENABLE Enable or disable UARTE 0 3 Disabled Disable UARTE 0 Enabled Enable UARTE 8 PSEL Unspecified UARTE_PSEL read-write 0x508 RTS Pin select for RTS signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TXD Pin select for TXD signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CTS Pin select for CTS signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Pin select for RXD signal 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14401) 0x003AF000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28777) 0x0075C000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38369) 0x009D0000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57554) 0x00EB0000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115108) 0x01D60000 Baud230400 230400 baud (actual rate: 231884) 0x03B00000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 457143) 0x07400000 Baud921600 921600 baud (actual rate: 941176) 0x0F000000 Baud1M 1Mega baud 0x10000000 RXD RXD EasyDMA channel UARTE_RXD read-write 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 12 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 12 TXD TXD EasyDMA channel UARTE_TXD read-write 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 12 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 12 CONFIG Configuration of parity and hardware flow control 0x56C read-write HWFC Hardware flow control 0 0 Disabled Disabled 0 Enabled Enabled 1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include even parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0 Two Two stop bits 1 SPIM0_S Serial Peripheral Interface Master with EasyDMA 1 0x50008000 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 SPIS0_S SPI Slave 1 0x50008000 SPIM0_S UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 TWIM0_S I2C compatible Two-Wire Master Interface with EasyDMA 1 0x50008000 SPIM0_S UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 TWIS0_S I2C compatible Two-Wire Slave Interface with EasyDMA 1 0x50008000 SPIM0_S UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 UARTE0_S UART with EasyDMA 1 0x50008000 SPIM0_S UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 8 SPIM1_NS Serial Peripheral Interface Master with EasyDMA 2 0x40009000 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 SPIS1_NS SPI Slave 2 0x40009000 SPIM1_NS UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 TWIM1_NS I2C compatible Two-Wire Master Interface with EasyDMA 2 0x40009000 SPIM1_NS UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 TWIS1_NS I2C compatible Two-Wire Slave Interface with EasyDMA 2 0x40009000 SPIM1_NS UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 UARTE1_NS UART with EasyDMA 2 0x40009000 SPIM1_NS UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 SPIM1_S Serial Peripheral Interface Master with EasyDMA 3 0x50009000 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 SPIS1_S SPI Slave 3 0x50009000 SPIM1_S UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 TWIM1_S I2C compatible Two-Wire Master Interface with EasyDMA 3 0x50009000 SPIM1_S UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 TWIS1_S I2C compatible Two-Wire Slave Interface with EasyDMA 3 0x50009000 SPIM1_S UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 UARTE1_S UART with EasyDMA 3 0x50009000 SPIM1_S UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 9 SPIM2_NS Serial Peripheral Interface Master with EasyDMA 4 0x4000A000 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 SPIS2_NS SPI Slave 4 0x4000A000 SPIM2_NS UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 TWIM2_NS I2C compatible Two-Wire Master Interface with EasyDMA 4 0x4000A000 SPIM2_NS UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 TWIS2_NS I2C compatible Two-Wire Slave Interface with EasyDMA 4 0x4000A000 SPIM2_NS UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 UARTE2_NS UART with EasyDMA 4 0x4000A000 SPIM2_NS UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 SPIM2_S Serial Peripheral Interface Master with EasyDMA 5 0x5000A000 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 SPIS2_S SPI Slave 5 0x5000A000 SPIM2_S UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 TWIM2_S I2C compatible Two-Wire Master Interface with EasyDMA 5 0x5000A000 SPIM2_S UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 TWIS2_S I2C compatible Two-Wire Slave Interface with EasyDMA 5 0x5000A000 SPIM2_S UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 UARTE2_S UART with EasyDMA 5 0x5000A000 SPIM2_S UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 10 SPIM3_NS Serial Peripheral Interface Master with EasyDMA 6 0x4000B000 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 SPIS3_NS SPI Slave 6 0x4000B000 SPIM3_NS UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 TWIM3_NS I2C compatible Two-Wire Master Interface with EasyDMA 6 0x4000B000 SPIM3_NS UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 TWIS3_NS I2C compatible Two-Wire Slave Interface with EasyDMA 6 0x4000B000 SPIM3_NS UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 UARTE3_NS UART with EasyDMA 6 0x4000B000 SPIM3_NS UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 SPIM3_S Serial Peripheral Interface Master with EasyDMA 7 0x5000B000 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 SPIS3_S SPI Slave 7 0x5000B000 SPIM3_S UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 TWIM3_S I2C compatible Two-Wire Master Interface with EasyDMA 7 0x5000B000 SPIM3_S UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 TWIS3_S I2C compatible Two-Wire Slave Interface with EasyDMA 7 0x5000B000 SPIM3_S UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 UARTE3_S UART with EasyDMA 7 0x5000B000 SPIM3_S UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 11 GPIOTE0_S GPIO Tasks and Events 0 0x5000D000 GPIOTE 0 0x1000 registers GPIOTE0 13 GPIOTE 0x20 0x8 0x4 TASKS_OUT[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only TASKS_OUT Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0 0 Trigger Trigger task 1 0x8 0x4 TASKS_SET[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only TASKS_SET Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0 0 Trigger Trigger task 1 0x8 0x4 TASKS_CLR[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only TASKS_CLR Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0 0 Trigger Trigger task 1 0x8 0x4 SUBSCRIBE_OUT[%s] Description collection: Subscribe configuration for task OUT[n] 0x080 read-write CHIDX Channel that task OUT[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x8 0x4 SUBSCRIBE_SET[%s] Description collection: Subscribe configuration for task SET[n] 0x0B0 read-write CHIDX Channel that task SET[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x8 0x4 SUBSCRIBE_CLR[%s] Description collection: Subscribe configuration for task CLR[n] 0x0E0 read-write CHIDX Channel that task CLR[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x8 0x4 EVENTS_IN[%s] Description collection: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write EVENTS_IN Event generated from pin specified in CONFIG[n].PSEL 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0x17C read-write EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x8 0x4 PUBLISH_IN[%s] Description collection: Publish configuration for event IN[n] 0x180 read-write CHIDX Channel that event IN[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_PORT Publish configuration for event PORT 0x1FC read-write CHIDX Channel that event PORT will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTENSET Enable interrupt 0x304 read-write IN0 Write '1' to enable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN1 Write '1' to enable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN2 Write '1' to enable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN3 Write '1' to enable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN4 Write '1' to enable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN5 Write '1' to enable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN6 Write '1' to enable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN7 Write '1' to enable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PORT Write '1' to enable interrupt for event PORT 31 31 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write IN0 Write '1' to disable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN1 Write '1' to disable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN2 Write '1' to disable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN3 Write '1' to disable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN4 Write '1' to disable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN5 Write '1' to disable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN6 Write '1' to disable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN7 Write '1' to disable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PORT Write '1' to disable interrupt for event PORT 31 31 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 0x8 0x4 CONFIG[%s] Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event 0x510 read-write MODE Mode 0 1 Disabled Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0 Event Event mode 1 Task Task mode 3 PSEL GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event 8 12 POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. 16 17 None Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. 0 LoToHi Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. 1 HiToLo Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. 2 Toggle Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. 3 OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. 20 20 Low Task mode: Initial value of pin before task triggering is low 0 High Task mode: Initial value of pin before task triggering is high 1 SAADC_NS Analog to Digital Converter 0 0x4000E000 SAADC 0 0x1000 registers SAADC 14 SAADC 0x20 TASKS_START Start the ADC and prepare the result buffer in RAM 0x000 write-only TASKS_START Start the ADC and prepare the result buffer in RAM 0 0 Trigger Trigger task 1 TASKS_SAMPLE Take one ADC sample, if scan is enabled all channels are sampled 0x004 write-only TASKS_SAMPLE Take one ADC sample, if scan is enabled all channels are sampled 0 0 Trigger Trigger task 1 TASKS_STOP Stop the ADC and terminate any on-going conversion 0x008 write-only TASKS_STOP Stop the ADC and terminate any on-going conversion 0 0 Trigger Trigger task 1 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0x00C write-only TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_SAMPLE Subscribe configuration for task SAMPLE 0x084 read-write CHIDX Channel that task SAMPLE will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x088 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_CALIBRATEOFFSET Subscribe configuration for task CALIBRATEOFFSET 0x08C read-write CHIDX Channel that task CALIBRATEOFFSET will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_STARTED The ADC has started 0x100 read-write EVENTS_STARTED The ADC has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_END The ADC has filled up the Result buffer 0x104 read-write EVENTS_END The ADC has filled up the Result buffer 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DONE A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write EVENTS_DONE A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RESULTDONE A result is ready to get transferred to RAM. 0x10C read-write EVENTS_RESULTDONE A result is ready to get transferred to RAM. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_CALIBRATEDONE Calibration is complete 0x110 read-write EVENTS_CALIBRATEDONE Calibration is complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STOPPED The ADC has stopped 0x114 read-write EVENTS_STOPPED The ADC has stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 8 0x008 EVENTS_CH[%s] Peripheral events. SAADC_EVENTS_CH read-write 0x118 LIMITH Description cluster: Last results is equal or above CH[n].LIMIT.HIGH 0x000 read-write LIMITH Last results is equal or above CH[n].LIMIT.HIGH 0 0 NotGenerated Event not generated 0 Generated Event generated 1 LIMITL Description cluster: Last results is equal or below CH[n].LIMIT.LOW 0x004 read-write LIMITL Last results is equal or below CH[n].LIMIT.LOW 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_STARTED Publish configuration for event STARTED 0x180 read-write CHIDX Channel that event STARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_END Publish configuration for event END 0x184 read-write CHIDX Channel that event END will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_DONE Publish configuration for event DONE 0x188 read-write CHIDX Channel that event DONE will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_RESULTDONE Publish configuration for event RESULTDONE 0x18C read-write CHIDX Channel that event RESULTDONE will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_CALIBRATEDONE Publish configuration for event CALIBRATEDONE 0x190 read-write CHIDX Channel that event CALIBRATEDONE will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x194 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 8 0x008 PUBLISH_CH[%s] Publish configuration for events SAADC_PUBLISH_CH read-write 0x198 LIMITH Description cluster: Publish configuration for event CH[n].LIMITH 0x000 read-write CHIDX Channel that event CH[n].LIMITH will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 LIMITL Description cluster: Publish configuration for event CH[n].LIMITL 0x004 read-write CHIDX Channel that event CH[n].LIMITL will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0 Enabled Enable 1 END Enable or disable interrupt for event END 1 1 Disabled Disable 0 Enabled Enable 1 DONE Enable or disable interrupt for event DONE 2 2 Disabled Disable 0 Enabled Enable 1 RESULTDONE Enable or disable interrupt for event RESULTDONE 3 3 Disabled Disable 0 Enabled Enable 1 CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE 4 4 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for event STOPPED 5 5 Disabled Disable 0 Enabled Enable 1 CH0LIMITH Enable or disable interrupt for event CH0LIMITH 6 6 Disabled Disable 0 Enabled Enable 1 CH0LIMITL Enable or disable interrupt for event CH0LIMITL 7 7 Disabled Disable 0 Enabled Enable 1 CH1LIMITH Enable or disable interrupt for event CH1LIMITH 8 8 Disabled Disable 0 Enabled Enable 1 CH1LIMITL Enable or disable interrupt for event CH1LIMITL 9 9 Disabled Disable 0 Enabled Enable 1 CH2LIMITH Enable or disable interrupt for event CH2LIMITH 10 10 Disabled Disable 0 Enabled Enable 1 CH2LIMITL Enable or disable interrupt for event CH2LIMITL 11 11 Disabled Disable 0 Enabled Enable 1 CH3LIMITH Enable or disable interrupt for event CH3LIMITH 12 12 Disabled Disable 0 Enabled Enable 1 CH3LIMITL Enable or disable interrupt for event CH3LIMITL 13 13 Disabled Disable 0 Enabled Enable 1 CH4LIMITH Enable or disable interrupt for event CH4LIMITH 14 14 Disabled Disable 0 Enabled Enable 1 CH4LIMITL Enable or disable interrupt for event CH4LIMITL 15 15 Disabled Disable 0 Enabled Enable 1 CH5LIMITH Enable or disable interrupt for event CH5LIMITH 16 16 Disabled Disable 0 Enabled Enable 1 CH5LIMITL Enable or disable interrupt for event CH5LIMITL 17 17 Disabled Disable 0 Enabled Enable 1 CH6LIMITH Enable or disable interrupt for event CH6LIMITH 18 18 Disabled Disable 0 Enabled Enable 1 CH6LIMITL Enable or disable interrupt for event CH6LIMITL 19 19 Disabled Disable 0 Enabled Enable 1 CH7LIMITH Enable or disable interrupt for event CH7LIMITH 20 20 Disabled Disable 0 Enabled Enable 1 CH7LIMITL Enable or disable interrupt for event CH7LIMITL 21 21 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DONE Write '1' to enable interrupt for event DONE 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RESULTDONE Write '1' to enable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH0LIMITL Write '1' to enable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH3LIMITH Write '1' to enable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH6LIMITL Write '1' to enable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DONE Write '1' to disable interrupt for event DONE 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESULTDONE Write '1' to disable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH0LIMITL Write '1' to disable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH3LIMITH Write '1' to disable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH6LIMITL Write '1' to disable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH7LIMITH Write '1' to disable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STATUS Status 0x400 read-only STATUS Status 0 0 Ready ADC is ready. No on-going conversion. 0 Busy ADC is busy. Single conversion in progress. 1 ENABLE Enable or disable ADC 0x500 read-write ENABLE Enable or disable ADC 0 0 Disabled Disable ADC 0 Enabled Enable ADC 1 8 0x010 CH[%s] Unspecified SAADC_CH read-write 0x510 PSELP Description cluster: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 PSELP Analog positive input channel 0 4 NC Not connected 0 AnalogInput0 AIN0 1 AnalogInput1 AIN1 2 AnalogInput2 AIN2 3 AnalogInput3 AIN3 4 AnalogInput4 AIN4 5 AnalogInput5 AIN5 6 AnalogInput6 AIN6 7 AnalogInput7 AIN7 8 VDDGPIO VDD_GPIO 9 PSELN Description cluster: Input negative pin selection for CH[n] 0x004 read-write 0x00000000 PSELN Analog negative input, enables differential channel 0 4 NC Not connected 0 AnalogInput0 AIN0 1 AnalogInput1 AIN1 2 AnalogInput2 AIN2 3 AnalogInput3 AIN3 4 AnalogInput4 AIN4 5 AnalogInput5 AIN5 6 AnalogInput6 AIN6 7 AnalogInput7 AIN7 8 VDD_GPIO VDD_GPIO 9 CONFIG Description cluster: Input configuration for CH[n] 0x008 read-write 0x00020000 RESP Positive channel resistor control 0 1 Bypass Bypass resistor ladder 0 Pulldown Pull-down to GND 1 Pullup Pull-up to VDD_GPIO 2 VDD1_2 Set input at VDD_GPIO/2 3 RESN Negative channel resistor control 4 5 Bypass Bypass resistor ladder 0 Pulldown Pull-down to GND 1 Pullup Pull-up to VDD_GPIO 2 VDD1_2 Set input at VDD_GPIO/2 3 GAIN Gain control 8 10 Gain1_6 1/6 0 Gain1_5 1/5 1 Gain1_4 1/4 2 Gain1_3 1/3 3 Gain1_2 1/2 4 Gain1 1 5 Gain2 2 6 Gain4 4 7 REFSEL Reference control 12 12 Internal Internal reference (0.6 V) 0 VDD1_4 VDD_GPIO/4 as reference 1 TACQ Acquisition time, the time the ADC uses to sample the input voltage 16 18 3us 3 us 0 5us 5 us 1 10us 10 us 2 15us 15 us 3 20us 20 us 4 40us 40 us 5 MODE Enable differential mode 20 20 SE Single ended, PSELN will be ignored, negative input to ADC shorted to GND 0 Diff Differential 1 BURST Enable burst mode 24 24 Disabled Burst mode is disabled (normal operation) 0 Enabled Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 1 LIMIT Description cluster: High/low limits for event monitoring a channel 0x00C read-write 0x7FFF8000 LOW Low level limit 0 15 HIGH High level limit 16 31 RESOLUTION Resolution configuration 0x5F0 read-write 0x00000001 VAL Set the resolution 0 2 8bit 8 bit 0 10bit 10 bit 1 12bit 12 bit 2 14bit 14 bit 3 OVERSAMPLE Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write OVERSAMPLE Oversample control 0 3 Bypass Bypass oversampling 0 Over2x Oversample 2x 1 Over4x Oversample 4x 2 Over8x Oversample 8x 3 Over16x Oversample 16x 4 Over32x Oversample 32x 5 Over64x Oversample 64x 6 Over128x Oversample 128x 7 Over256x Oversample 256x 8 SAMPLERATE Controls normal or continuous sample rate 0x5F8 read-write CC Capture and compare value. Sample rate is 16 MHz/CC 0 10 MODE Select mode for sample rate control 12 12 Task Rate is controlled from SAMPLE task 0 Timers Rate is controlled from local timer (use CC to control the rate) 1 RESULT RESULT EasyDMA channel SAADC_RESULT read-write 0x62C PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of buffer words to transfer 0x004 read-write MAXCNT Maximum number of buffer words to transfer 0 14 AMOUNT Number of buffer words transferred since last START 0x008 read-only AMOUNT Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. 0 14 SAADC_S Analog to Digital Converter 1 0x5000E000 SAADC 14 TIMER0_NS Timer/Counter 0 0x4000F000 TIMER 0 0x1000 registers TIMER0 15 TIMER 0x20 TASKS_START Start Timer 0x000 write-only TASKS_START Start Timer 0 0 Trigger Trigger task 1 TASKS_STOP Stop Timer 0x004 write-only TASKS_STOP Stop Timer 0 0 Trigger Trigger task 1 TASKS_COUNT Increment Timer (Counter mode only) 0x008 write-only TASKS_COUNT Increment Timer (Counter mode only) 0 0 Trigger Trigger task 1 TASKS_CLEAR Clear time 0x00C write-only TASKS_CLEAR Clear time 0 0 Trigger Trigger task 1 TASKS_SHUTDOWN Deprecated register - Shut down timer 0x010 write-only TASKS_SHUTDOWN Deprecated field - Shut down timer 0 0 Trigger Trigger task 1 0x6 0x4 TASKS_CAPTURE[%s] Description collection: Capture Timer value to CC[n] register 0x040 write-only TASKS_CAPTURE Capture Timer value to CC[n] register 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_COUNT Subscribe configuration for task COUNT 0x088 read-write CHIDX Channel that task COUNT will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_CLEAR Subscribe configuration for task CLEAR 0x08C read-write CHIDX Channel that task CLEAR will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_SHUTDOWN Deprecated register - Subscribe configuration for task SHUTDOWN 0x090 read-write CHIDX Channel that task SHUTDOWN will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x6 0x4 SUBSCRIBE_CAPTURE[%s] Description collection: Subscribe configuration for task CAPTURE[n] 0x0C0 read-write CHIDX Channel that task CAPTURE[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x6 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x6 0x4 PUBLISH_COMPARE[%s] Description collection: Publish configuration for event COMPARE[n] 0x1C0 read-write CHIDX Channel that event COMPARE[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write COMPARE0_CLEAR Shortcut between event COMPARE[0] and task CLEAR 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE1_CLEAR Shortcut between event COMPARE[1] and task CLEAR 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE2_CLEAR Shortcut between event COMPARE[2] and task CLEAR 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE3_CLEAR Shortcut between event COMPARE[3] and task CLEAR 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE4_CLEAR Shortcut between event COMPARE[4] and task CLEAR 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE5_CLEAR Shortcut between event COMPARE[5] and task CLEAR 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE0_STOP Shortcut between event COMPARE[0] and task STOP 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE1_STOP Shortcut between event COMPARE[1] and task STOP 9 9 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE2_STOP Shortcut between event COMPARE[2] and task STOP 10 10 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE3_STOP Shortcut between event COMPARE[3] and task STOP 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE4_STOP Shortcut between event COMPARE[4] and task STOP 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE5_STOP Shortcut between event COMPARE[5] and task STOP 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 MODE Timer mode selection 0x504 read-write MODE Timer mode 0 1 Timer Select Timer mode 0 Counter Deprecated enumerator - Select Counter mode 1 LowPowerCounter Select Low Power Counter mode 2 BITMODE Configure the number of bits used by the TIMER 0x508 read-write BITMODE Timer bit width 0 1 16Bit 16 bit timer bit width 0 08Bit 8 bit timer bit width 1 24Bit 24 bit timer bit width 2 32Bit 32 bit timer bit width 3 PRESCALER Timer prescaler register 0x510 read-write 0x00000004 PRESCALER Prescaler value 0 3 0x6 0x4 ONESHOTEN[%s] Description collection: Enable one-shot operation for Capture/Compare channel n 0x514 read-write ONESHOTEN Enable one-shot operation 0 0 Disable Disable one-shot operation 0 Enable Enable one-shot operation 1 0x6 0x4 CC[%s] Description collection: Capture/Compare register n 0x540 read-write CC Capture/Compare value 0 31 TIMER0_S Timer/Counter 1 0x5000F000 TIMER0 15 TIMER1_NS Timer/Counter 2 0x40010000 TIMER1 16 TIMER1_S Timer/Counter 3 0x50010000 TIMER1 16 TIMER2_NS Timer/Counter 4 0x40011000 TIMER2 17 TIMER2_S Timer/Counter 5 0x50011000 TIMER2 17 RTC0_NS Real-time counter 0 0x40014000 RTC 0 0x1000 registers RTC0 20 RTC 0x20 TASKS_START Start RTC counter 0x000 write-only TASKS_START Start RTC counter 0 0 Trigger Trigger task 1 TASKS_STOP Stop RTC counter 0x004 write-only TASKS_STOP Stop RTC counter 0 0 Trigger Trigger task 1 TASKS_CLEAR Clear RTC counter 0x008 write-only TASKS_CLEAR Clear RTC counter 0 0 Trigger Trigger task 1 TASKS_TRIGOVRFLW Set counter to 0xFFFFF0 0x00C write-only TASKS_TRIGOVRFLW Set counter to 0xFFFFF0 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_CLEAR Subscribe configuration for task CLEAR 0x088 read-write CHIDX Channel that task CLEAR will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_TRIGOVRFLW Subscribe configuration for task TRIGOVRFLW 0x08C read-write CHIDX Channel that task TRIGOVRFLW will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_TICK Event on counter increment 0x100 read-write EVENTS_TICK Event on counter increment 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_OVRFLW Event on counter overflow 0x104 read-write EVENTS_OVRFLW Event on counter overflow 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x4 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_TICK Publish configuration for event TICK 0x180 read-write CHIDX Channel that event TICK will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_OVRFLW Publish configuration for event OVRFLW 0x184 read-write CHIDX Channel that event OVRFLW will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 0x4 0x4 PUBLISH_COMPARE[%s] Description collection: Publish configuration for event COMPARE[n] 0x1C0 read-write CHIDX Channel that event COMPARE[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTENSET Enable interrupt 0x304 read-write TICK Write '1' to enable interrupt for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 OVRFLW Write '1' to enable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TICK Write '1' to disable interrupt for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 OVRFLW Write '1' to disable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EVTEN Enable or disable event routing 0x340 read-write TICK Enable or disable event routing for event TICK 0 0 Disabled Disable 0 Enabled Disable 1 OVRFLW Enable or disable event routing for event OVRFLW 1 1 Disabled Disable 0 Enabled Disable 1 COMPARE0 Enable or disable event routing for event COMPARE[0] 16 16 Disabled Disable 0 Enabled Disable 1 COMPARE1 Enable or disable event routing for event COMPARE[1] 17 17 Disabled Disable 0 Enabled Disable 1 COMPARE2 Enable or disable event routing for event COMPARE[2] 18 18 Disabled Disable 0 Enabled Disable 1 COMPARE3 Enable or disable event routing for event COMPARE[3] 19 19 Disabled Disable 0 Enabled Disable 1 EVTENSET Enable event routing 0x344 read-write TICK Write '1' to enable event routing for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 OVRFLW Write '1' to enable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE0 Write '1' to enable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EVTENCLR Disable event routing 0x348 read-write TICK Write '1' to disable event routing for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 OVRFLW Write '1' to disable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE0 Write '1' to disable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COUNTER Current counter value 0x504 read-only COUNTER Counter value 0 23 PRESCALER 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write PRESCALER Prescaler value 0 11 0x4 0x4 CC[%s] Description collection: Compare register n 0x540 read-write COMPARE Compare value 0 23 RTC0_S Real-time counter 1 0x50014000 RTC0 20 RTC1_NS Real-time counter 2 0x40015000 RTC1 21 RTC1_S Real-time counter 3 0x50015000 RTC1 21 DPPIC_NS Distributed Programmable Peripheral Interconnect Controller 0 0x40017000 DPPIC 0 0x1000 registers DPPIC 0x20 6 0x008 TASKS_CHG[%s] Channel group tasks DPPIC_TASKS_CHG write-only 0x000 EN Description cluster: Enable channel group n 0x000 write-only EN Enable channel group n 0 0 Trigger Trigger task 1 DIS Description cluster: Disable channel group n 0x004 write-only DIS Disable channel group n 0 0 Trigger Trigger task 1 6 0x008 SUBSCRIBE_CHG[%s] Subscribe configuration for tasks DPPIC_SUBSCRIBE_CHG read-write 0x080 EN Description cluster: Subscribe configuration for task CHG[n].EN 0x000 read-write CHIDX Channel that task CHG[n].EN will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 DIS Description cluster: Subscribe configuration for task CHG[n].DIS 0x004 read-write CHIDX Channel that task CHG[n].DIS will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 CHEN Channel enable register 0x500 read-write CH0 Enable or disable channel 0 0 0 Disabled Disable channel 0 Enabled Enable channel 1 CH1 Enable or disable channel 1 1 1 Disabled Disable channel 0 Enabled Enable channel 1 CH2 Enable or disable channel 2 2 2 Disabled Disable channel 0 Enabled Enable channel 1 CH3 Enable or disable channel 3 3 3 Disabled Disable channel 0 Enabled Enable channel 1 CH4 Enable or disable channel 4 4 4 Disabled Disable channel 0 Enabled Enable channel 1 CH5 Enable or disable channel 5 5 5 Disabled Disable channel 0 Enabled Enable channel 1 CH6 Enable or disable channel 6 6 6 Disabled Disable channel 0 Enabled Enable channel 1 CH7 Enable or disable channel 7 7 7 Disabled Disable channel 0 Enabled Enable channel 1 CH8 Enable or disable channel 8 8 8 Disabled Disable channel 0 Enabled Enable channel 1 CH9 Enable or disable channel 9 9 9 Disabled Disable channel 0 Enabled Enable channel 1 CH10 Enable or disable channel 10 10 10 Disabled Disable channel 0 Enabled Enable channel 1 CH11 Enable or disable channel 11 11 11 Disabled Disable channel 0 Enabled Enable channel 1 CH12 Enable or disable channel 12 12 12 Disabled Disable channel 0 Enabled Enable channel 1 CH13 Enable or disable channel 13 13 13 Disabled Disable channel 0 Enabled Enable channel 1 CH14 Enable or disable channel 14 14 14 Disabled Disable channel 0 Enabled Enable channel 1 CH15 Enable or disable channel 15 15 15 Disabled Disable channel 0 Enabled Enable channel 1 CHENSET Channel enable set register 0x504 read-write oneToSet CH0 Channel 0 enable set register. Writing '0' has no effect 0 0 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH1 Channel 1 enable set register. Writing '0' has no effect 1 1 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH2 Channel 2 enable set register. Writing '0' has no effect 2 2 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH3 Channel 3 enable set register. Writing '0' has no effect 3 3 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH4 Channel 4 enable set register. Writing '0' has no effect 4 4 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH5 Channel 5 enable set register. Writing '0' has no effect 5 5 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH6 Channel 6 enable set register. Writing '0' has no effect 6 6 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH7 Channel 7 enable set register. Writing '0' has no effect 7 7 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH8 Channel 8 enable set register. Writing '0' has no effect 8 8 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH9 Channel 9 enable set register. Writing '0' has no effect 9 9 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH10 Channel 10 enable set register. Writing '0' has no effect 10 10 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH11 Channel 11 enable set register. Writing '0' has no effect 11 11 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH12 Channel 12 enable set register. Writing '0' has no effect 12 12 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH13 Channel 13 enable set register. Writing '0' has no effect 13 13 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH14 Channel 14 enable set register. Writing '0' has no effect 14 14 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH15 Channel 15 enable set register. Writing '0' has no effect 15 15 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CHENCLR Channel enable clear register 0x508 read-write oneToClear CH0 Channel 0 enable clear register. Writing '0' has no effect 0 0 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH1 Channel 1 enable clear register. Writing '0' has no effect 1 1 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH2 Channel 2 enable clear register. Writing '0' has no effect 2 2 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH3 Channel 3 enable clear register. Writing '0' has no effect 3 3 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH4 Channel 4 enable clear register. Writing '0' has no effect 4 4 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH5 Channel 5 enable clear register. Writing '0' has no effect 5 5 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH6 Channel 6 enable clear register. Writing '0' has no effect 6 6 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH7 Channel 7 enable clear register. Writing '0' has no effect 7 7 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH8 Channel 8 enable clear register. Writing '0' has no effect 8 8 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH9 Channel 9 enable clear register. Writing '0' has no effect 9 9 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH10 Channel 10 enable clear register. Writing '0' has no effect 10 10 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH11 Channel 11 enable clear register. Writing '0' has no effect 11 11 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH12 Channel 12 enable clear register. Writing '0' has no effect 12 12 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH13 Channel 13 enable clear register. Writing '0' has no effect 13 13 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH14 Channel 14 enable clear register. Writing '0' has no effect 14 14 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH15 Channel 15 enable clear register. Writing '0' has no effect 15 15 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 0x6 0x4 CHG[%s] Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. 0x800 read-write CH0 Include or exclude channel 0 0 0 Excluded Exclude 0 Included Include 1 CH1 Include or exclude channel 1 1 1 Excluded Exclude 0 Included Include 1 CH2 Include or exclude channel 2 2 2 Excluded Exclude 0 Included Include 1 CH3 Include or exclude channel 3 3 3 Excluded Exclude 0 Included Include 1 CH4 Include or exclude channel 4 4 4 Excluded Exclude 0 Included Include 1 CH5 Include or exclude channel 5 5 5 Excluded Exclude 0 Included Include 1 CH6 Include or exclude channel 6 6 6 Excluded Exclude 0 Included Include 1 CH7 Include or exclude channel 7 7 7 Excluded Exclude 0 Included Include 1 CH8 Include or exclude channel 8 8 8 Excluded Exclude 0 Included Include 1 CH9 Include or exclude channel 9 9 9 Excluded Exclude 0 Included Include 1 CH10 Include or exclude channel 10 10 10 Excluded Exclude 0 Included Include 1 CH11 Include or exclude channel 11 11 11 Excluded Exclude 0 Included Include 1 CH12 Include or exclude channel 12 12 12 Excluded Exclude 0 Included Include 1 CH13 Include or exclude channel 13 13 13 Excluded Exclude 0 Included Include 1 CH14 Include or exclude channel 14 14 14 Excluded Exclude 0 Included Include 1 CH15 Include or exclude channel 15 15 15 Excluded Exclude 0 Included Include 1 DPPIC_S Distributed Programmable Peripheral Interconnect Controller 1 0x50017000 WDT_NS Watchdog Timer 0 0x40018000 WDT 0 0x1000 registers WDT 24 WDT 0x20 TASKS_START Start the watchdog 0x000 write-only TASKS_START Start the watchdog 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_TIMEOUT Watchdog timeout 0x100 read-write EVENTS_TIMEOUT Watchdog timeout 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_TIMEOUT Publish configuration for event TIMEOUT 0x180 read-write CHIDX Channel that event TIMEOUT will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTENSET Enable interrupt 0x304 read-write TIMEOUT Write '1' to enable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TIMEOUT Write '1' to disable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RUNSTATUS Run status 0x400 read-only RUNSTATUSWDT Indicates whether or not the watchdog is running 0 0 NotRunning Watchdog not running 0 Running Watchdog is running 1 REQSTATUS Request status 0x404 read-only 0x00000001 RR0 Request status for RR[0] register 0 0 DisabledOrRequested RR[0] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[0] register is enabled, and are not yet requesting reload 1 RR1 Request status for RR[1] register 1 1 DisabledOrRequested RR[1] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[1] register is enabled, and are not yet requesting reload 1 RR2 Request status for RR[2] register 2 2 DisabledOrRequested RR[2] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[2] register is enabled, and are not yet requesting reload 1 RR3 Request status for RR[3] register 3 3 DisabledOrRequested RR[3] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[3] register is enabled, and are not yet requesting reload 1 RR4 Request status for RR[4] register 4 4 DisabledOrRequested RR[4] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[4] register is enabled, and are not yet requesting reload 1 RR5 Request status for RR[5] register 5 5 DisabledOrRequested RR[5] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[5] register is enabled, and are not yet requesting reload 1 RR6 Request status for RR[6] register 6 6 DisabledOrRequested RR[6] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[6] register is enabled, and are not yet requesting reload 1 RR7 Request status for RR[7] register 7 7 DisabledOrRequested RR[7] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[7] register is enabled, and are not yet requesting reload 1 CRV Counter reload value 0x504 read-write 0xFFFFFFFF CRV Counter reload value in number of cycles of the 32.768 kHz clock 0 31 RREN Enable register for reload request registers 0x508 read-write 0x00000001 RR0 Enable or disable RR[0] register 0 0 Disabled Disable RR[0] register 0 Enabled Enable RR[0] register 1 RR1 Enable or disable RR[1] register 1 1 Disabled Disable RR[1] register 0 Enabled Enable RR[1] register 1 RR2 Enable or disable RR[2] register 2 2 Disabled Disable RR[2] register 0 Enabled Enable RR[2] register 1 RR3 Enable or disable RR[3] register 3 3 Disabled Disable RR[3] register 0 Enabled Enable RR[3] register 1 RR4 Enable or disable RR[4] register 4 4 Disabled Disable RR[4] register 0 Enabled Enable RR[4] register 1 RR5 Enable or disable RR[5] register 5 5 Disabled Disable RR[5] register 0 Enabled Enable RR[5] register 1 RR6 Enable or disable RR[6] register 6 6 Disabled Disable RR[6] register 0 Enabled Enable RR[6] register 1 RR7 Enable or disable RR[7] register 7 7 Disabled Disable RR[7] register 0 Enabled Enable RR[7] register 1 CONFIG Configuration register 0x50C read-write 0x00000001 SLEEP Configure the watchdog to either be paused, or kept running, while the CPU is sleeping 0 0 Pause Pause watchdog while the CPU is sleeping 0 Run Keep the watchdog running while the CPU is sleeping 1 HALT Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause Pause watchdog while the CPU is halted by the debugger 0 Run Keep the watchdog running while the CPU is halted by the debugger 1 0x8 0x4 RR[%s] Description collection: Reload request n 0x600 write-only RR Reload request register 0 31 Reload Value to request a reload of the watchdog timer 0x6E524635 WDT_S Watchdog Timer 1 0x50018000 WDT 24 EGU0_NS Event generator unit 0 0x4001B000 EGU 0 0x1000 registers EGU0 27 EGU 0x20 0x10 0x4 TASKS_TRIGGER[%s] Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event 0x000 write-only TASKS_TRIGGER Trigger n for triggering the corresponding TRIGGERED[n] event 0 0 Trigger Trigger task 1 0x10 0x4 SUBSCRIBE_TRIGGER[%s] Description collection: Subscribe configuration for task TRIGGER[n] 0x080 read-write CHIDX Channel that task TRIGGER[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x10 0x4 EVENTS_TRIGGERED[%s] Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task 0x100 read-write EVENTS_TRIGGERED Event number n generated by triggering the corresponding TRIGGER[n] task 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x10 0x4 PUBLISH_TRIGGERED[%s] Description collection: Publish configuration for event TRIGGERED[n] 0x180 read-write CHIDX Channel that event TRIGGERED[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write TRIGGERED0 Enable or disable interrupt for event TRIGGERED[0] 0 0 Disabled Disable 0 Enabled Enable 1 TRIGGERED1 Enable or disable interrupt for event TRIGGERED[1] 1 1 Disabled Disable 0 Enabled Enable 1 TRIGGERED2 Enable or disable interrupt for event TRIGGERED[2] 2 2 Disabled Disable 0 Enabled Enable 1 TRIGGERED3 Enable or disable interrupt for event TRIGGERED[3] 3 3 Disabled Disable 0 Enabled Enable 1 TRIGGERED4 Enable or disable interrupt for event TRIGGERED[4] 4 4 Disabled Disable 0 Enabled Enable 1 TRIGGERED5 Enable or disable interrupt for event TRIGGERED[5] 5 5 Disabled Disable 0 Enabled Enable 1 TRIGGERED6 Enable or disable interrupt for event TRIGGERED[6] 6 6 Disabled Disable 0 Enabled Enable 1 TRIGGERED7 Enable or disable interrupt for event TRIGGERED[7] 7 7 Disabled Disable 0 Enabled Enable 1 TRIGGERED8 Enable or disable interrupt for event TRIGGERED[8] 8 8 Disabled Disable 0 Enabled Enable 1 TRIGGERED9 Enable or disable interrupt for event TRIGGERED[9] 9 9 Disabled Disable 0 Enabled Enable 1 TRIGGERED10 Enable or disable interrupt for event TRIGGERED[10] 10 10 Disabled Disable 0 Enabled Enable 1 TRIGGERED11 Enable or disable interrupt for event TRIGGERED[11] 11 11 Disabled Disable 0 Enabled Enable 1 TRIGGERED12 Enable or disable interrupt for event TRIGGERED[12] 12 12 Disabled Disable 0 Enabled Enable 1 TRIGGERED13 Enable or disable interrupt for event TRIGGERED[13] 13 13 Disabled Disable 0 Enabled Enable 1 TRIGGERED14 Enable or disable interrupt for event TRIGGERED[14] 14 14 Disabled Disable 0 Enabled Enable 1 TRIGGERED15 Enable or disable interrupt for event TRIGGERED[15] 15 15 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write TRIGGERED0 Write '1' to enable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED1 Write '1' to enable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED2 Write '1' to enable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED3 Write '1' to enable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED4 Write '1' to enable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED5 Write '1' to enable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED6 Write '1' to enable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED7 Write '1' to enable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED8 Write '1' to enable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED9 Write '1' to enable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED10 Write '1' to enable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED11 Write '1' to enable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED12 Write '1' to enable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED13 Write '1' to enable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED14 Write '1' to enable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED15 Write '1' to enable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TRIGGERED0 Write '1' to disable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED1 Write '1' to disable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED2 Write '1' to disable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED3 Write '1' to disable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED4 Write '1' to disable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED5 Write '1' to disable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED6 Write '1' to disable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED7 Write '1' to disable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED8 Write '1' to disable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED9 Write '1' to disable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED10 Write '1' to disable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED11 Write '1' to disable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED12 Write '1' to disable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED13 Write '1' to disable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED14 Write '1' to disable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED15 Write '1' to disable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EGU0_S Event generator unit 1 0x5001B000 EGU0 27 EGU1_NS Event generator unit 2 0x4001C000 EGU1 28 EGU1_S Event generator unit 3 0x5001C000 EGU1 28 EGU2_NS Event generator unit 4 0x4001D000 EGU2 29 EGU2_S Event generator unit 5 0x5001D000 EGU2 29 EGU3_NS Event generator unit 6 0x4001E000 EGU3 30 EGU3_S Event generator unit 7 0x5001E000 EGU3 30 EGU4_NS Event generator unit 8 0x4001F000 EGU4 31 EGU4_S Event generator unit 9 0x5001F000 EGU4 31 EGU5_NS Event generator unit 10 0x40020000 EGU5 32 EGU5_S Event generator unit 11 0x50020000 EGU5 32 PWM0_NS Pulse width modulation unit 0 0x40021000 PWM 0 0x1000 registers PWM0 33 PWM 0x20 TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0x004 write-only TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0 0 Trigger Trigger task 1 0x2 0x4 TASKS_SEQSTART[%s] Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0x008 write-only TASKS_SEQSTART Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0 0 Trigger Trigger task 1 TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0x010 write-only TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0 0 Trigger Trigger task 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x2 0x4 SUBSCRIBE_SEQSTART[%s] Description collection: Subscribe configuration for task SEQSTART[n] 0x088 read-write CHIDX Channel that task SEQSTART[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_NEXTSTEP Subscribe configuration for task NEXTSTEP 0x090 read-write CHIDX Channel that task NEXTSTEP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0x104 read-write EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x2 0x4 EVENTS_SEQSTARTED[%s] Description collection: First PWM period started on sequence n 0x108 read-write EVENTS_SEQSTARTED First PWM period started on sequence n 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x2 0x4 EVENTS_SEQEND[%s] Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0x110 read-write EVENTS_SEQEND Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0x118 read-write EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0x11C read-write EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 0x2 0x4 PUBLISH_SEQSTARTED[%s] Description collection: Publish configuration for event SEQSTARTED[n] 0x188 read-write CHIDX Channel that event SEQSTARTED[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 0x2 0x4 PUBLISH_SEQEND[%s] Description collection: Publish configuration for event SEQEND[n] 0x190 read-write CHIDX Channel that event SEQEND[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_PWMPERIODEND Publish configuration for event PWMPERIODEND 0x198 read-write CHIDX Channel that event PWMPERIODEND will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_LOOPSDONE Publish configuration for event LOOPSDONE 0x19C read-write CHIDX Channel that event LOOPSDONE will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 SHORTS Shortcuts between local events and tasks 0x200 read-write SEQEND0_STOP Shortcut between event SEQEND[0] and task STOP 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 SEQEND1_STOP Shortcut between event SEQEND[1] and task STOP 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LOOPSDONE_SEQSTART0 Shortcut between event LOOPSDONE and task SEQSTART[0] 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LOOPSDONE_SEQSTART1 Shortcut between event LOOPSDONE and task SEQSTART[1] 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0 Enabled Enable 1 SEQSTARTED0 Enable or disable interrupt for event SEQSTARTED[0] 2 2 Disabled Disable 0 Enabled Enable 1 SEQSTARTED1 Enable or disable interrupt for event SEQSTARTED[1] 3 3 Disabled Disable 0 Enabled Enable 1 SEQEND0 Enable or disable interrupt for event SEQEND[0] 4 4 Disabled Disable 0 Enabled Enable 1 SEQEND1 Enable or disable interrupt for event SEQEND[1] 5 5 Disabled Disable 0 Enabled Enable 1 PWMPERIODEND Enable or disable interrupt for event PWMPERIODEND 6 6 Disabled Disable 0 Enabled Enable 1 LOOPSDONE Enable or disable interrupt for event LOOPSDONE 7 7 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQSTARTED0 Write '1' to enable interrupt for event SEQSTARTED[0] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQSTARTED1 Write '1' to enable interrupt for event SEQSTARTED[1] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQEND0 Write '1' to enable interrupt for event SEQEND[0] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQEND1 Write '1' to enable interrupt for event SEQEND[1] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PWMPERIODEND Write '1' to enable interrupt for event PWMPERIODEND 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LOOPSDONE Write '1' to enable interrupt for event LOOPSDONE 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQSTARTED0 Write '1' to disable interrupt for event SEQSTARTED[0] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQSTARTED1 Write '1' to disable interrupt for event SEQSTARTED[1] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQEND0 Write '1' to disable interrupt for event SEQEND[0] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQEND1 Write '1' to disable interrupt for event SEQEND[1] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PWMPERIODEND Write '1' to disable interrupt for event PWMPERIODEND 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LOOPSDONE Write '1' to disable interrupt for event LOOPSDONE 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE PWM module enable register 0x500 read-write 0x00000000 ENABLE Enable or disable PWM module 0 0 Disabled Disabled 0 Enabled Enable 1 MODE Selects operating mode of the wave counter 0x504 read-write 0x00000000 UPDOWN Selects up mode or up-and-down mode for the counter 0 0 Up Up counter, edge-aligned PWM duty cycle 0 UpAndDown Up and down counter, center-aligned PWM duty cycle 1 COUNTERTOP Value up to which the pulse generator counter counts 0x508 read-write 0x000003FF COUNTERTOP Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 0 14 PRESCALER Configuration for PWM_CLK 0x50C read-write 0x00000000 PRESCALER Prescaler of PWM_CLK 0 2 DIV_1 Divide by 1 (16 MHz) 0 DIV_2 Divide by 2 (8 MHz) 1 DIV_4 Divide by 4 (4 MHz) 2 DIV_8 Divide by 8 (2 MHz) 3 DIV_16 Divide by 16 (1 MHz) 4 DIV_32 Divide by 32 (500 kHz) 5 DIV_64 Divide by 64 (250 kHz) 6 DIV_128 Divide by 128 (125 kHz) 7 DECODER Configuration of the decoder 0x510 read-write 0x00000000 LOAD How a sequence is read from RAM and spread to the compare register 0 1 Common 1st half word (16-bit) used in all PWM channels 0..3 0 Grouped 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 1 Individual 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 2 WaveForm 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP 3 MODE Selects source for advancing the active sequence 8 8 RefreshCount SEQ[n].REFRESH is used to determine loading internal compare registers 0 NextStep NEXTSTEP task causes a new value to be loaded to internal compare registers 1 LOOP Number of playbacks of a loop 0x514 read-write 0x00000000 CNT Number of playbacks of pattern cycles 0 15 Disabled Looping disabled (stop at the end of the sequence) 0 2 0x020 SEQ[%s] Unspecified PWM_SEQ read-write 0x520 PTR Description cluster: Beginning address in RAM of this sequence 0x000 read-write 0x00000000 PTR Beginning address in RAM of this sequence 0 31 CNT Description cluster: Number of values (duty cycles) in this sequence 0x004 read-write 0x00000000 CNT Number of values (duty cycles) in this sequence 0 14 Disabled Sequence is disabled, and shall not be started as it is empty 0 REFRESH Description cluster: Number of additional PWM periods between samples loaded into compare register 0x008 read-write 0x00000001 CNT Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) 0 23 Continuous Update every PWM period 0 ENDDELAY Description cluster: Time added after the sequence 0x00C read-write 0x00000000 CNT Time added after the sequence in PWM periods 0 23 PSEL Unspecified PWM_PSEL read-write 0x560 0x4 0x4 OUT[%s] Description collection: Output pin select for PWM channel n 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 PWM0_S Pulse width modulation unit 1 0x50021000 PWM0 33 PWM1_NS Pulse width modulation unit 2 0x40022000 PWM1 34 PWM1_S Pulse width modulation unit 3 0x50022000 PWM1 34 PWM2_NS Pulse width modulation unit 4 0x40023000 PWM2 35 PWM2_S Pulse width modulation unit 5 0x50023000 PWM2 35 PWM3_NS Pulse width modulation unit 6 0x40024000 PWM3 36 PWM3_S Pulse width modulation unit 7 0x50024000 PWM3 36 PDM_NS Pulse Density Modulation (Digital Microphone) Interface 0 0x40026000 PDM 0 0x1000 registers PDM 38 PDM 0x20 TASKS_START Starts continuous PDM transfer 0x000 write-only TASKS_START Starts continuous PDM transfer 0 0 Trigger Trigger task 1 TASKS_STOP Stops PDM transfer 0x004 write-only TASKS_STOP Stops PDM transfer 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_STARTED PDM transfer has started 0x100 read-write EVENTS_STARTED PDM transfer has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STOPPED PDM transfer has finished 0x104 read-write EVENTS_STOPPED PDM transfer has finished 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0x108 read-write EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_STARTED Publish configuration for event STARTED 0x180 read-write CHIDX Channel that event STARTED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_END Publish configuration for event END 0x188 read-write CHIDX Channel that event END will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0 Enabled Enable 1 END Enable or disable interrupt for event END 2 2 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for event END 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for event END 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE PDM module enable register 0x500 read-write 0x00000000 ENABLE Enable or disable PDM module 0 0 Disabled Disable 0 Enabled Enable 1 PDMCLKCTRL PDM clock generator control 0x504 read-write 0x08400000 FREQ PDM_CLK frequency 0 31 1000K PDM_CLK = 32 MHz / 32 = 1.000 MHz 0x08000000 Default PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. 0x08400000 1067K PDM_CLK = 32 MHz / 30 = 1.067 MHz 0x08800000 1231K PDM_CLK = 32 MHz / 26 = 1.231 MHz 0x09800000 1280K PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. 0x0A000000 1333K PDM_CLK = 32 MHz / 24 = 1.333 MHz 0x0A800000 MODE Defines the routing of the connected PDM microphones' signals 0x508 read-write 0x00000000 OPERATION Mono or stereo operation 0 0 Stereo Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] 0 Mono Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] 1 EDGE Defines on which PDM_CLK edge Left (or mono) is sampled 1 1 LeftFalling Left (or mono) is sampled on falling edge of PDM_CLK 0 LeftRising Left (or mono) is sampled on rising edge of PDM_CLK 1 GAINL Left output gain adjustment 0x518 read-write 0x00000028 GAINL Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust 0 6 MinGain -20dB gain adjustment (minimum) 0x00 DefaultGain 0dB gain adjustment 0x28 MaxGain +20dB gain adjustment (maximum) 0x50 GAINR Right output gain adjustment 0x51C read-write 0x00000028 GAINR Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0 6 MinGain -20dB gain adjustment (minimum) 0x00 DefaultGain 0dB gain adjustment 0x28 MaxGain +20dB gain adjustment (maximum) 0x50 RATIO Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. 0x520 read-write 0x00000000 RATIO Selects the ratio between PDM_CLK and output sample rate 0 0 Ratio64 Ratio of 64 0 Ratio80 Ratio of 80 1 PSEL Unspecified PDM_PSEL read-write 0x540 CLK Pin number configuration for PDM CLK signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 DIN Pin number configuration for PDM DIN signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SAMPLE Unspecified PDM_SAMPLE read-write 0x560 PTR RAM address pointer to write samples to with EasyDMA 0x000 read-write SAMPLEPTR Address to write PDM samples to over DMA 0 31 MAXCNT Number of samples to allocate memory for in EasyDMA mode 0x004 read-write BUFFSIZE Length of DMA RAM allocation in number of samples 0 14 PDM_S Pulse Density Modulation (Digital Microphone) Interface 1 0x50026000 PDM 38 I2S_NS Inter-IC Sound 0 0x40028000 I2S 0 0x1000 registers I2S 40 I2S 0x20 TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0x000 write-only TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0 0 Trigger Trigger task 1 TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0x004 write-only TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0 0 Trigger Trigger task 1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write CHIDX Channel that task START will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write CHIDX Channel that task STOP will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0x104 read-write EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STOPPED I2S transfer stopped. 0x108 read-write EVENTS_STOPPED I2S transfer stopped. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0x114 read-write EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 PUBLISH_RXPTRUPD Publish configuration for event RXPTRUPD 0x184 read-write CHIDX Channel that event RXPTRUPD will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x188 read-write CHIDX Channel that event STOPPED will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 PUBLISH_TXPTRUPD Publish configuration for event TXPTRUPD 0x194 read-write CHIDX Channel that event TXPTRUPD will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write RXPTRUPD Enable or disable interrupt for event RXPTRUPD 1 1 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for event STOPPED 2 2 Disabled Disable 0 Enabled Enable 1 TXPTRUPD Enable or disable interrupt for event TXPTRUPD 5 5 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write RXPTRUPD Write '1' to enable interrupt for event RXPTRUPD 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for event STOPPED 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXPTRUPD Write '1' to enable interrupt for event TXPTRUPD 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write RXPTRUPD Write '1' to disable interrupt for event RXPTRUPD 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for event STOPPED 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXPTRUPD Write '1' to disable interrupt for event TXPTRUPD 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable I2S module. 0x500 read-write 0x00000000 ENABLE Enable I2S module. 0 0 Disabled Disable 0 Enabled Enable 1 CONFIG Unspecified I2S_CONFIG read-write 0x504 MODE I2S mode. 0x000 read-write 0x00000000 MODE I2S mode. 0 0 Master Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. 0 Slave Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 1 RXEN Reception (RX) enable. 0x004 read-write 0x00000000 RXEN Reception (RX) enable. 0 0 Disabled Reception disabled and now data will be written to the RXD.PTR address. 0 Enabled Reception enabled. 1 TXEN Transmission (TX) enable. 0x008 read-write 0x00000001 TXEN Transmission (TX) enable. 0 0 Disabled Transmission disabled and now data will be read from the RXD.TXD address. 0 Enabled Transmission enabled. 1 MCKEN Master clock generator enable. 0x00C read-write 0x00000001 MCKEN Master clock generator enable. 0 0 Disabled Master clock generator disabled and PSEL.MCK not connected(available as GPIO). 0 Enabled Master clock generator running and MCK output on PSEL.MCK. 1 MCKFREQ Master clock generator frequency. 0x010 read-write 0x20000000 MCKFREQ Master clock generator frequency. 0 31 32MDIV8 32 MHz / 8 = 4.0 MHz 0x20000000 32MDIV10 32 MHz / 10 = 3.2 MHz 0x18000000 32MDIV11 32 MHz / 11 = 2.9090909 MHz 0x16000000 32MDIV15 32 MHz / 15 = 2.1333333 MHz 0x11000000 32MDIV16 32 MHz / 16 = 2.0 MHz 0x10000000 32MDIV21 32 MHz / 21 = 1.5238095 0x0C000000 32MDIV23 32 MHz / 23 = 1.3913043 MHz 0x0B000000 32MDIV30 32 MHz / 30 = 1.0666667 MHz 0x08800000 32MDIV31 32 MHz / 31 = 1.0322581 MHz 0x08400000 32MDIV32 32 MHz / 32 = 1.0 MHz 0x08000000 32MDIV42 32 MHz / 42 = 0.7619048 MHz 0x06000000 32MDIV63 32 MHz / 63 = 0.5079365 MHz 0x04100000 32MDIV125 32 MHz / 125 = 0.256 MHz 0x020C0000 RATIO MCK / LRCK ratio. 0x014 read-write 0x00000006 RATIO MCK / LRCK ratio. 0 3 32X LRCK = MCK / 32 0 48X LRCK = MCK / 48 1 64X LRCK = MCK / 64 2 96X LRCK = MCK / 96 3 128X LRCK = MCK / 128 4 192X LRCK = MCK / 192 5 256X LRCK = MCK / 256 6 384X LRCK = MCK / 384 7 512X LRCK = MCK / 512 8 SWIDTH Sample width. 0x018 read-write 0x00000001 SWIDTH Sample width. 0 1 8Bit 8 bit. 0 16Bit 16 bit. 1 24Bit 24 bit. 2 ALIGN Alignment of sample within a frame. 0x01C read-write 0x00000000 ALIGN Alignment of sample within a frame. 0 0 Left Left-aligned. 0 Right Right-aligned. 1 FORMAT Frame format. 0x020 read-write 0x00000000 FORMAT Frame format. 0 0 I2S Original I2S format. 0 Aligned Alternate (left- or right-aligned) format. 1 CHANNELS Enable channels. 0x024 read-write 0x00000000 CHANNELS Enable channels. 0 1 Stereo Stereo. 0 Left Left only. 1 Right Right only. 2 RXD Unspecified I2S_RXD read-write 0x538 PTR Receive buffer RAM start address. 0x000 read-write 0x00000000 PTR Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 0 31 TXD Unspecified I2S_TXD read-write 0x540 PTR Transmit buffer RAM start address. 0x000 read-write 0x00000000 PTR Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. 0 31 RXTXD Unspecified I2S_RXTXD read-write 0x550 MAXCNT Size of RXD and TXD buffers. 0x000 read-write 0x00000000 MAXCNT Size of RXD and TXD buffers in number of 32 bit words. 0 13 PSEL Unspecified I2S_PSEL read-write 0x560 MCK Pin select for MCK signal. 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SCK Pin select for SCK signal. 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 LRCK Pin select for LRCK signal. 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDIN Pin select for SDIN signal. 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDOUT Pin select for SDOUT signal. 0x010 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 I2S_S Inter-IC Sound 1 0x50028000 I2S 40 IPC_NS Inter Processor Communication 0 0x4002A000 IPC 0 0x1000 registers IPC 42 IPC 0x20 0x8 0x4 TASKS_SEND[%s] Description collection: Trigger events on channel enabled in SEND_CNF[n]. 0x000 write-only TASKS_SEND Trigger events on channel enabled in SEND_CNF[n]. 0 0 Trigger Trigger task 1 0x8 0x4 SUBSCRIBE_SEND[%s] Description collection: Subscribe configuration for task SEND[n] 0x080 read-write CHIDX Channel that task SEND[n] will subscribe to 0 3 EN 31 31 Disabled Disable subscription 0 Enabled Enable subscription 1 0x8 0x4 EVENTS_RECEIVE[%s] Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF[n]. 0x100 read-write EVENTS_RECEIVE Event received on one or more of the enabled channels in RECEIVE_CNF[n]. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x8 0x4 PUBLISH_RECEIVE[%s] Description collection: Publish configuration for event RECEIVE[n] 0x180 read-write CHIDX Channel that event RECEIVE[n] will publish to. 0 3 EN 31 31 Disabled Disable publishing 0 Enabled Enable publishing 1 INTEN Enable or disable interrupt 0x300 read-write RECEIVE0 Enable or disable interrupt for event RECEIVE[0] 0 0 Disabled Disable 0 Enabled Enable 1 RECEIVE1 Enable or disable interrupt for event RECEIVE[1] 1 1 Disabled Disable 0 Enabled Enable 1 RECEIVE2 Enable or disable interrupt for event RECEIVE[2] 2 2 Disabled Disable 0 Enabled Enable 1 RECEIVE3 Enable or disable interrupt for event RECEIVE[3] 3 3 Disabled Disable 0 Enabled Enable 1 RECEIVE4 Enable or disable interrupt for event RECEIVE[4] 4 4 Disabled Disable 0 Enabled Enable 1 RECEIVE5 Enable or disable interrupt for event RECEIVE[5] 5 5 Disabled Disable 0 Enabled Enable 1 RECEIVE6 Enable or disable interrupt for event RECEIVE[6] 6 6 Disabled Disable 0 Enabled Enable 1 RECEIVE7 Enable or disable interrupt for event RECEIVE[7] 7 7 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write RECEIVE0 Write '1' to enable interrupt for event RECEIVE[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE1 Write '1' to enable interrupt for event RECEIVE[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE2 Write '1' to enable interrupt for event RECEIVE[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE3 Write '1' to enable interrupt for event RECEIVE[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE4 Write '1' to enable interrupt for event RECEIVE[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE5 Write '1' to enable interrupt for event RECEIVE[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE6 Write '1' to enable interrupt for event RECEIVE[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RECEIVE7 Write '1' to enable interrupt for event RECEIVE[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write RECEIVE0 Write '1' to disable interrupt for event RECEIVE[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE1 Write '1' to disable interrupt for event RECEIVE[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE2 Write '1' to disable interrupt for event RECEIVE[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE3 Write '1' to disable interrupt for event RECEIVE[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE4 Write '1' to disable interrupt for event RECEIVE[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE5 Write '1' to disable interrupt for event RECEIVE[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE6 Write '1' to disable interrupt for event RECEIVE[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RECEIVE7 Write '1' to disable interrupt for event RECEIVE[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 INTPEND Pending interrupts 0x30C read-only RECEIVE0 Read pending status of interrupt for event RECEIVE[0] 0 0 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE1 Read pending status of interrupt for event RECEIVE[1] 1 1 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE2 Read pending status of interrupt for event RECEIVE[2] 2 2 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE3 Read pending status of interrupt for event RECEIVE[3] 3 3 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE4 Read pending status of interrupt for event RECEIVE[4] 4 4 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE5 Read pending status of interrupt for event RECEIVE[5] 5 5 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE6 Read pending status of interrupt for event RECEIVE[6] 6 6 read NotPending Read: Not pending 0 Pending Read: Pending 1 RECEIVE7 Read pending status of interrupt for event RECEIVE[7] 7 7 read NotPending Read: Not pending 0 Pending Read: Pending 1 0x8 0x4 SEND_CNF[%s] Description collection: Send event configuration for TASKS_SEND[n]. 0x510 read-write 0x00000000 CHEN0 Enable broadcasting on channel 0. 0 0 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN1 Enable broadcasting on channel 1. 1 1 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN2 Enable broadcasting on channel 2. 2 2 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN3 Enable broadcasting on channel 3. 3 3 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN4 Enable broadcasting on channel 4. 4 4 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN5 Enable broadcasting on channel 5. 5 5 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN6 Enable broadcasting on channel 6. 6 6 Disable Disable broadcast. 0 Enable Enable broadcast. 1 CHEN7 Enable broadcasting on channel 7. 7 7 Disable Disable broadcast. 0 Enable Enable broadcast. 1 0x8 0x4 RECEIVE_CNF[%s] Description collection: Receive event configuration for EVENTS_RECEIVE[n]. 0x590 read-write 0x00000000 CHEN0 Enable subscription to channel 0. 0 0 Disable Disable events. 0 Enable Enable events. 1 CHEN1 Enable subscription to channel 1. 1 1 Disable Disable events. 0 Enable Enable events. 1 CHEN2 Enable subscription to channel 2. 2 2 Disable Disable events. 0 Enable Enable events. 1 CHEN3 Enable subscription to channel 3. 3 3 Disable Disable events. 0 Enable Enable events. 1 CHEN4 Enable subscription to channel 4. 4 4 Disable Disable events. 0 Enable Enable events. 1 CHEN5 Enable subscription to channel 5. 5 5 Disable Disable events. 0 Enable Enable events. 1 CHEN6 Enable subscription to channel 6. 6 6 Disable Disable events. 0 Enable Enable events. 1 CHEN7 Enable subscription to channel 7. 7 7 Disable Disable events. 0 Enable Enable events. 1 0x4 0x4 GPMEM[%s] Description collection: General purpose memory. 0x610 read-write 0x00000000 GPMEM General purpose memory 0 31 IPC_S Inter Processor Communication 1 0x5002A000 IPC 42 FPU_NS FPU 0 0x4002C000 FPU 0 0x1000 registers FPU 44 FPU 0x20 UNUSED Unused. 0x000 0x00000000 read-only FPU_S FPU 1 0x5002C000 FPU 44 GPIOTE1_NS GPIO Tasks and Events 1 0x40031000 GPIOTE1 49 KMU_NS Key management unit 0 0x40039000 KMU 0 0x1000 registers KMU 57 KMU 0x20 TASKS_PUSH_KEYSLOT Push a key slot over secure APB 0x0000 write-only TASKS_PUSH_KEYSLOT Push a key slot over secure APB 0 0 Trigger Trigger task 1 EVENTS_KEYSLOT_PUSHED Key slot successfully pushed over secure APB 0x100 read-write EVENTS_KEYSLOT_PUSHED Key slot successfully pushed over secure APB 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_KEYSLOT_REVOKED Key slot has been revoked and cannot be tasked for selection 0x104 read-write EVENTS_KEYSLOT_REVOKED Key slot has been revoked and cannot be tasked for selection 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_KEYSLOT_ERROR No key slot selected, no destination address defined, or error during push operation 0x108 read-write EVENTS_KEYSLOT_ERROR No key slot selected, no destination address defined, or error during push operation 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTEN Enable or disable interrupt 0x300 read-write KEYSLOT_PUSHED Enable or disable interrupt for event KEYSLOT_PUSHED 0 0 Disabled Disable 0 Enabled Enable 1 KEYSLOT_REVOKED Enable or disable interrupt for event KEYSLOT_REVOKED 1 1 Disabled Disable 0 Enabled Enable 1 KEYSLOT_ERROR Enable or disable interrupt for event KEYSLOT_ERROR 2 2 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write KEYSLOT_PUSHED Write '1' to enable interrupt for event KEYSLOT_PUSHED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 KEYSLOT_REVOKED Write '1' to enable interrupt for event KEYSLOT_REVOKED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 KEYSLOT_ERROR Write '1' to enable interrupt for event KEYSLOT_ERROR 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write KEYSLOT_PUSHED Write '1' to disable interrupt for event KEYSLOT_PUSHED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 KEYSLOT_REVOKED Write '1' to disable interrupt for event KEYSLOT_REVOKED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 KEYSLOT_ERROR Write '1' to disable interrupt for event KEYSLOT_ERROR 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 INTPEND Pending interrupts 0x30C read-only KEYSLOT_PUSHED Read pending status of interrupt for event KEYSLOT_PUSHED 0 0 read NotPending Read: Not pending 0 Pending Read: Pending 1 KEYSLOT_REVOKED Read pending status of interrupt for event KEYSLOT_REVOKED 1 1 read NotPending Read: Not pending 0 Pending Read: Pending 1 KEYSLOT_ERROR Read pending status of interrupt for event KEYSLOT_ERROR 2 2 read NotPending Read: Not pending 0 Pending Read: Pending 1 STATUS Status bits for KMU operation 0x40C read-only 0x00000000 SELECTED Key slot ID successfully selected by the KMU 0 0 Disabled No key slot ID selected by KMU 0 Enabled Key slot ID successfully selected by KMU 1 BLOCKED Violation status 1 1 Disabled No access violation detected 0 Enabled Access violation detected and blocked 1 SELECTKEYSLOT Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started 0x500 read-write 0x00000000 ID Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1 0 7 NVMC_NS Non-volatile memory controller 0 0x40039000 KMU_NS NVMC 0 0x1000 registers NVMC 0x20 READY Ready flag 0x400 read-only 0x00000001 READY NVMC is ready or busy 0 0 Busy NVMC is busy (on-going write or erase operation) 0 Ready NVMC is ready 1 READYNEXT Ready flag 0x408 read-only 0x00000001 READYNEXT NVMC can accept a new write operation 0 0 Busy NVMC cannot accept any write operation 0 Ready NVMC is ready 1 CONFIG Configuration register 0x504 read-write WEN Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. 0 2 Ren Read only access 0 Wen Write enabled 1 Een Erase enabled 2 PEen Partial erase enabled 4 ERASEALL Register for erasing all non-volatile user memory 0x50C write-only ERASEALL Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. 0 0 NoOperation No operation 0 Erase Start chip erase 1 ERASEPAGEPARTIALCFG Register for partial erase configuration 0x51C read-write 0x0000000A DURATION Duration of the partial erase in milliseconds 0 6 ICACHECNF I-code cache configuration register 0x540 read-write 0x00000000 CACHEEN Cache enable 0 0 Disabled Disable cache. Invalidates all cache entries. 0 Enabled Enable cache 1 CACHEPROFEN Cache profiling enable 8 8 Disabled Disable cache profiling 0 Enabled Enable cache profiling 1 IHIT I-code cache hit counter 0x548 read-write HITS Number of cache hits Write zero to clear 0 31 IMISS I-code cache miss counter 0x54C read-write MISSES Number of cache misses Write zero to clear 0 31 CONFIGNS Unspecified 0x584 read-write WEN Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. 0 1 Ren Read only access 0 Wen Write enabled 1 Een Erase enabled 2 WRITEUICRNS Non-secure APPROTECT enable register 0x588 write-only SET Allow non-secure code to set APPROTECT 0 0 Set Set value 1 KEY Key to write in order to validate the write operation 4 31 Keyvalid Key value 0xAFBE5A7 KMU_S Key management unit 1 0x50039000 KMU 57 NVMC_S Non-volatile memory controller 1 0x50039000 KMU_S VMC_NS Volatile Memory controller 0 0x4003A000 VMC 0 0x1000 registers VMC 0x20 8 0x010 RAM[%s] Unspecified VMC_RAM read-write 0x600 POWER Description cluster: RAMn power control register 0x000 read-write 0x0000FFFF S0POWER Keep RAM section S0 of RAM n on or off in System ON mode 0 0 Off Off 0 On On 1 S1POWER Keep RAM section S1 of RAM n on or off in System ON mode 1 1 Off Off 0 On On 1 S2POWER Keep RAM section S2 of RAM n on or off in System ON mode 2 2 Off Off 0 On On 1 S3POWER Keep RAM section S3 of RAM n on or off in System ON mode 3 3 Off Off 0 On On 1 S0RETENTION Keep retention on RAM section S0 of RAM n when RAM section is switched off 16 16 Off Off 0 On On 1 S1RETENTION Keep retention on RAM section S1 of RAM n when RAM section is switched off 17 17 Off Off 0 On On 1 S2RETENTION Keep retention on RAM section S2 of RAM n when RAM section is switched off 18 18 Off Off 0 On On 1 S3RETENTION Keep retention on RAM section S3 of RAM n when RAM section is switched off 19 19 Off Off 0 On On 1 POWERSET Description cluster: RAMn power control set register 0x004 write-only 0x0000FFFF S0POWER Keep RAM section S0 of RAM n on or off in System ON mode 0 0 On On 1 S1POWER Keep RAM section S1 of RAM n on or off in System ON mode 1 1 On On 1 S2POWER Keep RAM section S2 of RAM n on or off in System ON mode 2 2 On On 1 S3POWER Keep RAM section S3 of RAM n on or off in System ON mode 3 3 On On 1 S0RETENTION Keep retention on RAM section S0 of RAM n when RAM section is switched off 16 16 On On 1 S1RETENTION Keep retention on RAM section S1 of RAM n when RAM section is switched off 17 17 On On 1 S2RETENTION Keep retention on RAM section S2 of RAM n when RAM section is switched off 18 18 On On 1 S3RETENTION Keep retention on RAM section S3 of RAM n when RAM section is switched off 19 19 On On 1 POWERCLR Description cluster: RAMn power control clear register 0x008 write-only 0x0000FFFF S0POWER Keep RAM section S0 of RAM n on or off in System ON mode 0 0 Off Off 1 S1POWER Keep RAM section S1 of RAM n on or off in System ON mode 1 1 Off Off 1 S2POWER Keep RAM section S2 of RAM n on or off in System ON mode 2 2 Off Off 1 S3POWER Keep RAM section S3 of RAM n on or off in System ON mode 3 3 Off Off 1 S0RETENTION Keep retention on RAM section S0 of RAM n when RAM section is switched off 16 16 Off Off 1 S1RETENTION Keep retention on RAM section S1 of RAM n when RAM section is switched off 17 17 Off Off 1 S2RETENTION Keep retention on RAM section S2 of RAM n when RAM section is switched off 18 18 Off Off 1 S3RETENTION Keep retention on RAM section S3 of RAM n when RAM section is switched off 19 19 Off Off 1 VMC_S Volatile Memory controller 1 0x5003A000 CC_HOST_RGF_S CRYPTOCELL HOST_RGF interface 0x50840000 CC_HOST_RGF 0 0x2000 registers CC_HOST_RGF 0x20 HOST_CRYPTOKEY_SEL AES hardware key select 0x1A38 read-write 0x00000000 HOST_CRYPTOKEY_SEL Select the source of the HW key that is used by the AES engine 0 1 K_DR Use device root key K_DR from CRYPTOCELL AO power domain 0 K_PRTL Use hard-coded RTL key K_PRTL 1 Session Use provided session key 2 HOST_IOT_KPRTL_LOCK This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A4C read-write 0x00000000 HOST_IOT_KPRTL_LOCK This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0 0 Disabled K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL 0 Enabled K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. 1 HOST_IOT_KDR0 This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. 0x1A50 read-write 0x00000000 HOST_IOT_KDR0 Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. 0 31 HOST_IOT_KDR1 This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A54 write-only 0x00000000 HOST_IOT_KDR1 K_DR bits 63:32 0 31 HOST_IOT_KDR2 This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A58 write-only 0x00000000 HOST_IOT_KDR2 K_DR bits 95:64 0 31 HOST_IOT_KDR3 This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A5C write-only 0x00000000 HOST_IOT_KDR3 K_DR bits 127:96 0 31 HOST_IOT_LCS Controls lifecycle state (LCS) for CRYPTOCELL subsystem 0x1A60 read-write 0x00000002 LCS Lifecycle state value. This field is write-once per reset. 0 2 Debug CC310 operates in debug mode 0 Secure CC310 operates in secure mode 2 LCS_IS_VALID Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. 8 8 Invalid Valid LCS not yet retained in the CRYPTOCELL AO power domain 0 Valid Valid LCS successfully retained in the CRYPTOCELL AO power domain 1 CRYPTOCELL_S ARM TrustZone CryptoCell register interface 0x50840000 CC_HOST_RGF_S CRYPTOCELL 0 0x2000 registers CRYPTOCELL 64 CRYPTOCELL 0x20 ENABLE Enable CRYPTOCELL subsystem 0x500 read-write 0x00000000 ENABLE Enable or disable the CRYPTOCELL subsystem 0 0 Disabled CRYPTOCELL subsystem disabled 0 Enabled CRYPTOCELL subsystem enabled. 1 P0_NS GPIO Port 0 0x40842500 GPIO 0 0x300 registers GPIO 0x20 OUT Write GPIO port 0x004 read-write PIN0 Pin 0 0 0 Low Pin driver is low 0 High Pin driver is high 1 PIN1 Pin 1 1 1 Low Pin driver is low 0 High Pin driver is high 1 PIN2 Pin 2 2 2 Low Pin driver is low 0 High Pin driver is high 1 PIN3 Pin 3 3 3 Low Pin driver is low 0 High Pin driver is high 1 PIN4 Pin 4 4 4 Low Pin driver is low 0 High Pin driver is high 1 PIN5 Pin 5 5 5 Low Pin driver is low 0 High Pin driver is high 1 PIN6 Pin 6 6 6 Low Pin driver is low 0 High Pin driver is high 1 PIN7 Pin 7 7 7 Low Pin driver is low 0 High Pin driver is high 1 PIN8 Pin 8 8 8 Low Pin driver is low 0 High Pin driver is high 1 PIN9 Pin 9 9 9 Low Pin driver is low 0 High Pin driver is high 1 PIN10 Pin 10 10 10 Low Pin driver is low 0 High Pin driver is high 1 PIN11 Pin 11 11 11 Low Pin driver is low 0 High Pin driver is high 1 PIN12 Pin 12 12 12 Low Pin driver is low 0 High Pin driver is high 1 PIN13 Pin 13 13 13 Low Pin driver is low 0 High Pin driver is high 1 PIN14 Pin 14 14 14 Low Pin driver is low 0 High Pin driver is high 1 PIN15 Pin 15 15 15 Low Pin driver is low 0 High Pin driver is high 1 PIN16 Pin 16 16 16 Low Pin driver is low 0 High Pin driver is high 1 PIN17 Pin 17 17 17 Low Pin driver is low 0 High Pin driver is high 1 PIN18 Pin 18 18 18 Low Pin driver is low 0 High Pin driver is high 1 PIN19 Pin 19 19 19 Low Pin driver is low 0 High Pin driver is high 1 PIN20 Pin 20 20 20 Low Pin driver is low 0 High Pin driver is high 1 PIN21 Pin 21 21 21 Low Pin driver is low 0 High Pin driver is high 1 PIN22 Pin 22 22 22 Low Pin driver is low 0 High Pin driver is high 1 PIN23 Pin 23 23 23 Low Pin driver is low 0 High Pin driver is high 1 PIN24 Pin 24 24 24 Low Pin driver is low 0 High Pin driver is high 1 PIN25 Pin 25 25 25 Low Pin driver is low 0 High Pin driver is high 1 PIN26 Pin 26 26 26 Low Pin driver is low 0 High Pin driver is high 1 PIN27 Pin 27 27 27 Low Pin driver is low 0 High Pin driver is high 1 PIN28 Pin 28 28 28 Low Pin driver is low 0 High Pin driver is high 1 PIN29 Pin 29 29 29 Low Pin driver is low 0 High Pin driver is high 1 PIN30 Pin 30 30 30 Low Pin driver is low 0 High Pin driver is high 1 PIN31 Pin 31 31 31 Low Pin driver is low 0 High Pin driver is high 1 OUTSET Set individual bits in GPIO port 0x008 read-write oneToSet PIN0 Pin 0 0 0 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 OUTCLR Clear individual bits in GPIO port 0x00C read-write oneToClear PIN0 Pin 0 0 0 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 IN Read GPIO port 0x010 read-only PIN0 Pin 0 0 0 Low Pin input is low 0 High Pin input is high 1 PIN1 Pin 1 1 1 Low Pin input is low 0 High Pin input is high 1 PIN2 Pin 2 2 2 Low Pin input is low 0 High Pin input is high 1 PIN3 Pin 3 3 3 Low Pin input is low 0 High Pin input is high 1 PIN4 Pin 4 4 4 Low Pin input is low 0 High Pin input is high 1 PIN5 Pin 5 5 5 Low Pin input is low 0 High Pin input is high 1 PIN6 Pin 6 6 6 Low Pin input is low 0 High Pin input is high 1 PIN7 Pin 7 7 7 Low Pin input is low 0 High Pin input is high 1 PIN8 Pin 8 8 8 Low Pin input is low 0 High Pin input is high 1 PIN9 Pin 9 9 9 Low Pin input is low 0 High Pin input is high 1 PIN10 Pin 10 10 10 Low Pin input is low 0 High Pin input is high 1 PIN11 Pin 11 11 11 Low Pin input is low 0 High Pin input is high 1 PIN12 Pin 12 12 12 Low Pin input is low 0 High Pin input is high 1 PIN13 Pin 13 13 13 Low Pin input is low 0 High Pin input is high 1 PIN14 Pin 14 14 14 Low Pin input is low 0 High Pin input is high 1 PIN15 Pin 15 15 15 Low Pin input is low 0 High Pin input is high 1 PIN16 Pin 16 16 16 Low Pin input is low 0 High Pin input is high 1 PIN17 Pin 17 17 17 Low Pin input is low 0 High Pin input is high 1 PIN18 Pin 18 18 18 Low Pin input is low 0 High Pin input is high 1 PIN19 Pin 19 19 19 Low Pin input is low 0 High Pin input is high 1 PIN20 Pin 20 20 20 Low Pin input is low 0 High Pin input is high 1 PIN21 Pin 21 21 21 Low Pin input is low 0 High Pin input is high 1 PIN22 Pin 22 22 22 Low Pin input is low 0 High Pin input is high 1 PIN23 Pin 23 23 23 Low Pin input is low 0 High Pin input is high 1 PIN24 Pin 24 24 24 Low Pin input is low 0 High Pin input is high 1 PIN25 Pin 25 25 25 Low Pin input is low 0 High Pin input is high 1 PIN26 Pin 26 26 26 Low Pin input is low 0 High Pin input is high 1 PIN27 Pin 27 27 27 Low Pin input is low 0 High Pin input is high 1 PIN28 Pin 28 28 28 Low Pin input is low 0 High Pin input is high 1 PIN29 Pin 29 29 29 Low Pin input is low 0 High Pin input is high 1 PIN30 Pin 30 30 30 Low Pin input is low 0 High Pin input is high 1 PIN31 Pin 31 31 31 Low Pin input is low 0 High Pin input is high 1 DIR Direction of GPIO pins 0x014 read-write PIN0 Pin 0 0 0 Input Pin set as input 0 Output Pin set as output 1 PIN1 Pin 1 1 1 Input Pin set as input 0 Output Pin set as output 1 PIN2 Pin 2 2 2 Input Pin set as input 0 Output Pin set as output 1 PIN3 Pin 3 3 3 Input Pin set as input 0 Output Pin set as output 1 PIN4 Pin 4 4 4 Input Pin set as input 0 Output Pin set as output 1 PIN5 Pin 5 5 5 Input Pin set as input 0 Output Pin set as output 1 PIN6 Pin 6 6 6 Input Pin set as input 0 Output Pin set as output 1 PIN7 Pin 7 7 7 Input Pin set as input 0 Output Pin set as output 1 PIN8 Pin 8 8 8 Input Pin set as input 0 Output Pin set as output 1 PIN9 Pin 9 9 9 Input Pin set as input 0 Output Pin set as output 1 PIN10 Pin 10 10 10 Input Pin set as input 0 Output Pin set as output 1 PIN11 Pin 11 11 11 Input Pin set as input 0 Output Pin set as output 1 PIN12 Pin 12 12 12 Input Pin set as input 0 Output Pin set as output 1 PIN13 Pin 13 13 13 Input Pin set as input 0 Output Pin set as output 1 PIN14 Pin 14 14 14 Input Pin set as input 0 Output Pin set as output 1 PIN15 Pin 15 15 15 Input Pin set as input 0 Output Pin set as output 1 PIN16 Pin 16 16 16 Input Pin set as input 0 Output Pin set as output 1 PIN17 Pin 17 17 17 Input Pin set as input 0 Output Pin set as output 1 PIN18 Pin 18 18 18 Input Pin set as input 0 Output Pin set as output 1 PIN19 Pin 19 19 19 Input Pin set as input 0 Output Pin set as output 1 PIN20 Pin 20 20 20 Input Pin set as input 0 Output Pin set as output 1 PIN21 Pin 21 21 21 Input Pin set as input 0 Output Pin set as output 1 PIN22 Pin 22 22 22 Input Pin set as input 0 Output Pin set as output 1 PIN23 Pin 23 23 23 Input Pin set as input 0 Output Pin set as output 1 PIN24 Pin 24 24 24 Input Pin set as input 0 Output Pin set as output 1 PIN25 Pin 25 25 25 Input Pin set as input 0 Output Pin set as output 1 PIN26 Pin 26 26 26 Input Pin set as input 0 Output Pin set as output 1 PIN27 Pin 27 27 27 Input Pin set as input 0 Output Pin set as output 1 PIN28 Pin 28 28 28 Input Pin set as input 0 Output Pin set as output 1 PIN29 Pin 29 29 29 Input Pin set as input 0 Output Pin set as output 1 PIN30 Pin 30 30 30 Input Pin set as input 0 Output Pin set as output 1 PIN31 Pin 31 31 31 Input Pin set as input 0 Output Pin set as output 1 DIRSET DIR set register 0x018 read-write oneToSet PIN0 Set as output pin 0 0 0 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN1 Set as output pin 1 1 1 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN2 Set as output pin 2 2 2 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN3 Set as output pin 3 3 3 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN4 Set as output pin 4 4 4 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN5 Set as output pin 5 5 5 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN6 Set as output pin 6 6 6 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN7 Set as output pin 7 7 7 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN8 Set as output pin 8 8 8 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN9 Set as output pin 9 9 9 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN10 Set as output pin 10 10 10 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN11 Set as output pin 11 11 11 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN12 Set as output pin 12 12 12 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN13 Set as output pin 13 13 13 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN14 Set as output pin 14 14 14 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN15 Set as output pin 15 15 15 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN16 Set as output pin 16 16 16 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN17 Set as output pin 17 17 17 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN18 Set as output pin 18 18 18 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN19 Set as output pin 19 19 19 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN20 Set as output pin 20 20 20 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN21 Set as output pin 21 21 21 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN22 Set as output pin 22 22 22 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN23 Set as output pin 23 23 23 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN24 Set as output pin 24 24 24 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN25 Set as output pin 25 25 25 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN26 Set as output pin 26 26 26 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN27 Set as output pin 27 27 27 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN28 Set as output pin 28 28 28 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN29 Set as output pin 29 29 29 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN30 Set as output pin 30 30 30 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN31 Set as output pin 31 31 31 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 DIRCLR DIR clear register 0x01C read-write oneToClear PIN0 Set as input pin 0 0 0 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN1 Set as input pin 1 1 1 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN2 Set as input pin 2 2 2 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN3 Set as input pin 3 3 3 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN4 Set as input pin 4 4 4 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN5 Set as input pin 5 5 5 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN6 Set as input pin 6 6 6 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN7 Set as input pin 7 7 7 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN8 Set as input pin 8 8 8 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN9 Set as input pin 9 9 9 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN10 Set as input pin 10 10 10 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN11 Set as input pin 11 11 11 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN12 Set as input pin 12 12 12 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN13 Set as input pin 13 13 13 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN14 Set as input pin 14 14 14 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN15 Set as input pin 15 15 15 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN16 Set as input pin 16 16 16 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN17 Set as input pin 17 17 17 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN18 Set as input pin 18 18 18 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN19 Set as input pin 19 19 19 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN20 Set as input pin 20 20 20 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN21 Set as input pin 21 21 21 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN22 Set as input pin 22 22 22 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN23 Set as input pin 23 23 23 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN24 Set as input pin 24 24 24 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN25 Set as input pin 25 25 25 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN26 Set as input pin 26 26 26 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN27 Set as input pin 27 27 27 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN28 Set as input pin 28 28 28 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN29 Set as input pin 29 29 29 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN30 Set as input pin 30 30 30 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN31 Set as input pin 31 31 31 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 LATCH Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 0x020 read-write PIN0 Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. 0 0 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN1 Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. 1 1 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN2 Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. 2 2 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN3 Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. 3 3 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN4 Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. 4 4 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN5 Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. 5 5 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN6 Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. 6 6 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN7 Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. 7 7 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN8 Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. 8 8 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN9 Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. 9 9 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN10 Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. 10 10 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN11 Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. 11 11 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN12 Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. 12 12 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN13 Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. 13 13 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN14 Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. 14 14 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN15 Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. 15 15 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN16 Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. 16 16 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN17 Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. 17 17 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN18 Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. 18 18 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN19 Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. 19 19 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN20 Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. 20 20 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN21 Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. 21 21 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN22 Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. 22 22 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN23 Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. 23 23 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN24 Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. 24 24 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN25 Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. 25 25 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN26 Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. 26 26 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN27 Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. 27 27 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN28 Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. 28 28 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN29 Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. 29 29 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN30 Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. 30 30 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN31 Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. 31 31 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 DETECTMODE Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) 0x024 read-write DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0 0 Default DETECT directly connected to PIN DETECT signals 0 LDETECT Use the latched LDETECT behavior 1 DETECTMODE_SEC Select between default DETECT signal behavior and LDETECT mode (For secure pin only) 0x028 read-write DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0 0 Default DETECT directly connected to PIN DETECT signals 0 LDETECT Use the latched LDETECT behavior 1 0x20 0x4 PIN_CNF[%s] Description collection: Configuration of GPIO pins 0x200 read-write 0x00000002 DIR Pin direction. Same physical register as DIR register 0 0 Input Configure pin as an input pin 0 Output Configure pin as an output pin 1 INPUT Connect or disconnect input buffer 1 1 Connect Connect input buffer 0 Disconnect Disconnect input buffer 1 PULL Pull configuration 2 3 Disabled No pull 0 Pulldown Pull down on pin 1 Pullup Pull up on pin 3 DRIVE Drive configuration 8 10 S0S1 Standard '0', standard '1' 0 H0S1 High drive '0', standard '1' 1 S0H1 Standard '0', high drive '1' 2 H0H1 High drive '0', high 'drive '1'' 3 D0S1 Disconnect '0', standard '1' (normally used for wired-or connections) 4 D0H1 Disconnect '0', high drive '1' (normally used for wired-or connections) 5 S0D1 Standard '0', disconnect '1' (normally used for wired-and connections) 6 H0D1 High drive '0', disconnect '1' (normally used for wired-and connections) 7 SENSE Pin sensing mechanism 16 17 Disabled Disabled 0 High Sense for high level 2 Low Sense for low level 3 P0_S GPIO Port 1 0x50842500